DS1236S-5N [DALLAS]
Power Supply Management Circuit, Fixed, 2 Channel, PDSO16,;
| 型号： | DS1236S-5N |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Power Supply Management Circuit, Fixed, 2 Channel, PDSO16, 输入元件 光电二极管 |
| 文件： | 总19页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1236
MicroManager Chip
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ Holds microprocessor in check during power
transients
VBAT
VCCO
VCC
GND
PF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RST
RST
PBRST
CEI
ꢀ Halts and restarts an out-of-control
microprocessor
ꢀ Monitors pushbutton for external override
ꢀ Warns microprocessor of an impending power
failure
ꢀ Converts CMOS SRAM into nonvolatile
memory
ꢀ Unconditionally write-protects memory when
power supply is out of tolerance
ꢀ Consumes less than 100 nA of battery current
at 25°C
VBAT
VCCO
VCC
GND
PF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RST
RST
PBRST
CEI
CEO
ST
PF
CEO
ST
NMI
IN
WC/SC
RC
NMI
IN
PF
WC/SC
RCI
16-Pin DIP (300-mil)
See Mech. Drawings Section
16-Pin SOIC (300-mil)
See Mech. Drawings Section
ꢀ Controls external power switch for high
current applications
ꢀ Accurate 10% power supply monitoring
ꢀ Optional 5% power supply monitoring
designated DS1236-5
ꢀ Provides orderly shutdown in nonvolatile
microprocessor applications
ꢀ Supplies necessary control for low-power
“stop mode” in battery operated hand-held
applications
ꢀ Standard 16-pin DIP or space-saving 16-pin
SOIC
ꢀ Optional industrial temperature range -40°C
to +85°C
PIN DESCRIPTION
VBAT
VCCO
VCC
GND
PF
- +3-Volt Battery Input
- Switched SRAM Supply Output
- +5-Volt Power Supply Input
- Ground
- Power-Fail (Active High)
- Power-Fail (Active Low)
- Wake-Up Control (Sleep)
- Reset Control
PF
WC/SC
RC
IN
NMI
- Early Warning Input
- Non-Maskable Interrupt
- Strobe Input
ST
CEO
CEI
- Chip Enable Output
- Chip Enable Input
PBRST
RST
- Pushbutton Reset Input
- Reset Output (Active Low)
- Reset Output (Active High)
RST
DESCRIPTION
The DS1236 MicroManager Chip provides all the necessary functions for power supply monitoring, reset
control, and memory backup in microprocessor-based systems. A precise internal voltage reference and
comparator circuit monitor power supply status. When an out-of-tolerance condition occurs, the
microprocessor reset and power-fail outputs are forced active, and static RAM control unconditionally
write protects external memory. The DS1236 also provides early warning detection of a user-defined
threshold by driving a non-maskable interrupt. External reset control is provided by a pushbutton reset
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111899
DS1236
input which is debounced and activates reset outputs. An internal watchdog timer can also force the reset
outputs to the active state if the strobe input is not driven low prior to watchdog timeout. Reset control
and wake-up/sleep control inputs also provide the necessary signals for orderly shutdown and startup in
battery backup and battery operated applications. A block diagram of the DS1236 is shown in Figure 1.
PIN DESCRIPTION
PIN NAME
DESCRIPTION
+3V battery input provides nonvolatile operation of control functions.
VCC output for nonvolatile SRAM applications.
+5V primary power input.
VBAT
VCCO
VCC
PF
Power-fail indicator, active high, used for external power switching as shown in
Figure 9.
Power-fail indicator, active low.
PF
WC/SC
RC
Wake-up and Sleep control. Invokes low-power mode.
Reset control input. Determines reset output. Normally low for NMOS processors and
high for battery backed CMOS processors.
IN
NMI
ST
Early warning power-fail input. This voltage sense point can be tied (via resistor
divider) to a user-selected voltage.
Non-maskable interrupt. Used in conjunction with the IN pin to indicate an impending
power failure.
Strobe input. A high-to-low transition will reset the watchdog timer, indicating that
software is still in control.
Chip enable output. Used with nonvolatile SRAM applications.
Chip enable input.
CEO
CEI
Pushbutton reset input.
PBRST
RST
Active low reset output.
RST
Active high reset output.
PROCESSOR MODE
A distinction is often made between CMOS and NMOS processor systems. In a CMOS system, power
consumption may be a concern, and nonvolatile operation is possible by battery backing both the SRAM
and the CMOS processor. All resources would be maintained in the absence of VCC. A power-down reset
is not issued since the low-power mode of most CMOS processors (Stop) is terminated with a Reset. A
pulsed interrupt ( NMI ) is issued to allow the CMOS processor to invoke a sleep mode to save power. For
this case, a power-on reset is desirable to wake up and initialize the processor. The CMOS mode is
invoked by connecting RC to VCCO
.
An NMOS processor consumes more power, and consequently may not be battery backed. In this case, it
is desirable to notify the processor of a power-fail, then keep it in reset during the loss of VCC. This avoids
intermittent or aberrant operation. On power-up, the processor will continue to be reset until VCC reaches
an operational level to provide an orderly start. The NMOS mode is invoked by connecting RC to ground.
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DS1236
POWER MONITOR
The DS1236 employs a band gap voltage reference and a precision comparator to monitor the 5-volt
supply (VCC) in microprocessor-based systems. When an out-of-tolerance condition occurs, the RST and
RST outputs are driven to the active state. The VCC trip point (VCCTP) is set for 10% operation so that the
RST and RST outputs will become active as VCC falls below 4.5 volts (4.37 typical). The VCCTP for the
5% operation option (DS1236-5) is set for 4.75 volts (4.62 typical). The RST and RST signals are
excellent for microprocessor reset control, as processing is stopped at the last possible moment of in-
tolerance VCC. On power-up, the RST and RST signals are held active for a minimum of 25 ms (100 ms
typical) after VCCTP is reached to allow the power supply and microprocessor to stabilize. Note: The
operation described above is obtained with the reset control pin (RC) connected to GND (NMOS mode).
Please review the reset control section for more information.
WATCHDOG TIMER
The DS1236 provides a watchdog timer function which forces the RST and RST signals to the active
state when the strobe input (ST ) is not stimulated for a predetermined time period. This time period is 400
ms typically with a maximum time-out of 600 ms. The watchdog time-out period begins as soon as RST
and RST are inactive. If a high-to-low transition occurs at the ST input prior to time-out, the watchdog
timer is reset and begins to time out again. The ST input timing is shown in Figure 2. To guarantee the
watchdog timer does not time out, a high-to-low transition on ST must occur at or less than 100 ms
(minimum time-out) from a reset. If the watchdog timer is allowed to time out, the RST and RST outputs
are driven to the active state for 25 ms minimum. The ST input can be derived from microprocessor
address, data, and/or control signals. Under normal operating conditions, these signals would routinely
reset the watchdog timer prior to time-out. If the watchdog timer is not required, two methods have been
provided to disable it.
Permanently grounding the IN pin in the CMOS mode (RC=1) will disable the watchdog. In normal
operation with RC=1, the watchdog is disabled as soon as the IN pin is below VTP. With IN grounded, an
NMI output will occur only at power-up, or when the ST pin is strobed. As shown in the Figure 3, a
falling edge on ST will generate an NMI when IN is below VTP. This allows the processor to verify that
power is between VTP and VCCTP, as an NMI will be returned immediately after the ST strobe. The
watchdog timer is not affected by the IN pin when in NMOS mode (RC=0).
If the NMI signal is required to monitor supply voltages, the watchdog may also be disabled by leaving
the ST input open. Independent of the state of the RC pin, the watchdog is also disabled as soon as VCC
falls to VCCTP
.
PUSHBUTTON RESET
An input pin is provided on the DS1236 for direct connection to a pushbutton. The pushbutton reset input
requires an active low signal. Internally, this input is pulled high by a 10k resistor whenever VCC is
greater than VBAT. The PBRST pin is also debounced and timed such that the RST and RST outputs are
driven to the active state for 25 ms minimum. This 25 ms delay begins as the pushbutton is released from
a low level. A typical example of the power monitor, watchdog timer, and pushbutton reset connections
are shown in Figure 4. The PBRST input is disabled whenever the IN pin voltage level is less than VTP
and the reset control (RC) is tied high (CMOS mode). The PBRST input is also disabled whenever VCC is
below VBAT. Timing of the PBRST -generated RST is illustrated in Figure 5.
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DS1236
NON-MASKABLE INTERRUPT
The DS1236 generates a non-maskable interrupt NMI for early warning of power failure to a
microprocessor. A precision comparator monitors the voltage level at the IN pin relative to a reference
generated by the internal band gap. The IN pin is a high-impedance input allowing for a user-defined
sense point. An external resistor voltage divider network (Figure 6) is used to interface with high voltage
signals. This sense point may be derived from the regulated 5-volt supply or from a higher DC voltage
level closer to the main system power input. Since the IN trip point VTP is 2.54 volts, the proper values
for R1 and R2 can be determined by the equation as shown in Figure 6. Proper operation of the DS1236
requires that the voltage at the IN pin be limited to VIN. Therefore, the maximum allowable voltage at the
supply being monitored (VMAX) can also be derived as shown in Figure 6. A simple approach to solving
this equation is to select a value for R2 high enough to keep power consumption low, and solve for R1.
The flexibility of the IN input pin allows for detection of power loss at the earliest point in a power
supply system, maximizing the amount of time for microprocessor shutdown between NMI and RST or
RST .
When the supply being monitored decays to the voltage sense point, the DS1236 pulses the NMI output
to the active state for a minimum of 200 µs. The NMI power-fail detection circuitry also has built-in time
domain hysteresis. That is, the monitored supply is sampled periodically at a rate determined by an
internal ring oscillator running at approximately 30 kHz (33 µs/cycle). Three consecutive samplings of
out-of-tolerance supply (below VSENSE) must occur at the IN pin to activate NMI . Therefore, the supply
must be below the voltage sense point for approximately 100 µs or the comparator will reset. In this way,
power supply noise is removed from the monitoring function, preventing false trips. During a power-up,
any IN pin levels below VTP are disabled from reaching the NMI pin until VCC rises to VCCTP. As a result,
any potential NMI pulse will not be initiated until VCC reaches VCCTP
.
Removal of an active low level on the NMI pin is controlled by either an internal time-out (when IN pin
is less than VTP) or by the subsequent rise of the IN pin above VTP. The initiation and removal of the NMI
signal during power-up results in an NMI pulse of from 0 µs minimum to 500 µs maximum, depending
on the relative voltage relationship between VCC and the IN pin voltage. As an example, when the IN pin
is tied to ground during power-up, the internal time-out will result in a pulse of 200 µs minimum to 500
µs maximum. In contrast, if the IN pin is tied to VCCO during power-up, NMI will not produce a pulse on
power-up. Note that a fast slewing power supply may cause the NMI to be virtually nonexistent on
power-up. This is of no consequence, however, since an RST will be active.
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DS1236
DS1236 FUNCTIONAL BLOCK DIAGRAM Figure 1
If the IN pin is connected to VCCO, the NMI output will pulse low as VCC decays to VCCTP in the NMOS
mode (RC=0). In the CMOS mode (RC=VCCO) the power-down of VCC out-of-tolerance at VCCTP will not
produce a pulse on the NMI pin. Given that any NMI pulse has been completed by the time VCC decays
to VCCTP, the NMI pin will remain high. The NMI voltage will follow VCC down until VCC decays to
VBAT. Once VCC decays to VBAT, the NMI pin will either remain at VOHL or enter tri-state mode as
determined by the RC pin (see “Reset Control” section).
MEMORY BACKUP
The DS1236 provides all of the necessary functions required to battery back a static RAM. First, a switch
is provided to direct SRAM power from the incoming 5-volt supply (VCC) or from an external battery
(VBAT), whichever is greater. This switched supply (VCCO) can also be used to battery back a CMOS
microprocessor. For more information about nonvolatile processor applications, review the “Reset
Control” and “Wake Control” sections. Second, the same power-fail detection described in the power
monitor section is used to hold the chip enable output ( CEO ) to within 0.3 volts of VCC or to within 0.7
volts of VBAT. This write protection mechanism occurs as VCC falls below VCCTP as specified. If CEI is
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DS1236
low at the time power-fail detection occurs, CEO is held in its present state until CEI is returned high, or
the period tCE expires. This delay of write protection until the current memory cycle is completed prevents
the corruption of data. If CEO is in an inactive state at the time of VCC fail detection, CEO will be
unconditionally disabled within tCF. During nominal supply conditions CEO will follow CEI with a
maximum propagation delay of 20 ns. Figure 7 shows a typical nonvolatile SRAM application.
FRESHNESS SEAL
In order to conserve battery capacity during storage and/or shipment of an end system, the DS1236
provides a freshness seal to electrically disconnect the battery. Figure 8 depicts the three pulses below
ground on the IN pin required to invoke the freshness seal. The freshness seal will be disconnected and
normal operation will begin when VCC is cycled and reapplied to a level above VBAT
.
To prevent negative pulses associated with noise from setting the freshness mode in system applications,
a series diode and resistor can be used to shunt noise to ground. During manufacturing, the freshness seal
can still be set by holding TP2 at -3 volts while applying the 0 to –3 volts clock to TP1.
POWER SWITCHING
When larger operating currents are required in a battery backed system, the 5-volt supply and battery
supply switches internal to the DS1236 may not be large enough to support the required load through
VCCO with a reasonable voltage drop. For these applications, the PF and PF outputs are provided to gate
external power switching devices. As shown in Figure 9, power to the load is switched from VCC to
battery on power-down, and from battery to VCC on power-up. The DS1336 is designed to use the PF
output to switch between VBAT and VCC. It provides better leakage and switchover performance than
currently available discrete components. The transition threshold for PF and PF is set to the external
battery voltage VBAT, allowing a smooth transition between sources. The load applied to the PF pin from
the external switch will be supplied by the battery. Therefore, if a discrete switch is used, this load should
be taken into consideration when sizing the battery.
RESET CONTROL
As mentioned above, the DS1236 supports two modes of operation. The CMOS mode is used when the
system incorporates a CMOS microprocessor which is battery backed. The NMOS mode is used when a
non-battery backed processor is incorporated. The mode is selected by the RC (Reset Control) pin. The
level of this pin distinguishes timing and level control on RST, RST , and NMI outputs for volatile
processor operation versus nonvolatile battery backup or battery operated processor applications.
ST/INPUT TIMING Figure 2
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DS1236
NMI/FROM ST/INPUT Figure 3
POWER MONITOR, WATCHDOG Figure 4
PUSH BUTTON RESET TIMING Figure 5
NON-MASKABLE INTERRUPT Figure 6
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DS1236
EXAMPLE 1: 5 VOLT SUPPLY, R2 = 10k OHM, VSENSE = 4.80 VOLTS
R1+10k
4.80 =
X 2.54
R1 = 8.9k OHM
10k
EXAMPLE 2: 12 VOLT SUPPLY, R2 = 10k OHM, VSENSE = 9.00 VOLTS
R1+10k
9.00 =
X 2.54
R1 = 25.4k OHM
10k
9.00
2.54
VMAX
=
X 5.00 = 17.7 VOLTS
NONVOLATILE SRAM Figure 7
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DS1236
When the RC pin is tied to ground, the DS1236 is designed to interface with NMOS processors which do
not have the microamp currents required during a battery backed mode. Grounding the RC pin does,
however, continue to support nonvolatile backup of system SRAM memory. Nonvolatile systems
incorporating NMOS processors generally require that only the SRAM memory and/or timekeeping
functions be battery backed. When the processor is not battery backed (RC = 0), all signals connected
from the processor to the DS1236 are disconnected from the backup battery supply, or grounded when
system VCC decays below VBAT. In the NMOS processor system, the principal emphasis is placed on
giving early warnings with NMI , then providing a continuously active RST and RST signal during
power-down while isolating the backup battery from the processor during a loss of VCC.
During power-down, NMI will pulse low for a minimum of 200 µs, and then return high. If RC is tied
low (NMOS mode), the voltage on NMI will follow VCC until VCC supply decays to VBAT, at which point
NMI will enter tri-state (see timing diagram). Also, upon VCC out-of-tolerance at VCCTP, the RST and
RST outputs are driven active and RST will follow VCC as the supply decays. On power-up, RST follows
VCC up, RST is held low, and both remain active for tRST after valid VCC. During a power-up from a VCC
voltage below VBAT, any detected IN pin levels below VTP are disabled from reaching the NMI pin until
VCC rises to VCCTP. As a result, any potential NMI pulse will not be initiated until VCC reaches VCCTP
.
Removal of an active low level on the NMI pin is controlled by either an internal time-out (when the IN
pin is less than VTP), or by the subsequent rise of the IN pin above VTP. The initiation and removal of the
NMI signal results in an NMI pulse of 0 µs minimum to 500 µs maximum during power-up, depending
on the relative voltage relationship between VCC and the IN pin. As an example, when the IN pin is tied to
ground, the internal timeout will result in a pulse of 200 µs minimum to 500 µs maximum. In contrast, if
the IN pin is tied to VCCO, NMI will not produce a pulse on power-up.
Connecting the RC pin to a high (VCCO) invokes CMOS mode and provides nonvolatile support to both
the system SRAM as well as a low power CMOS processor. When using CMOS microprocessors, it is
possible to place the microprocessor into a very low-power mode termed the “stop” or “halt” mode. In
this state the CMOS processor requires only microamp currents and is fully capable of being battery
backed. This mode generally allows the CMOS microprocessor to maintain the contents of internal RAM
as well as state control of I/O ports during battery backup. The processor can subsequently be restarted by
any of several different signals. To maintain this low-power state, the DS1236 issues no NMI and/or reset
signals to the processor until it is time to bring the processor back into full operation. To support the low-
power processor battery backed mode (RC = 1), the DS1236 provides a pulsed NMI for early power
failure warning. Waiting to initiate a Stop mode until after the NMI pin has returned high will guarantee
the processor that no other active NMI or RST/RST will be issued by the DS1236 until one of two
conditions occurs: 1) Voltage on the pin rises above VTP, which activates the watchdog, or 2) VCC cycles
below then above VBAT, which also results in an active RST and RST . If VCC does not fall below VCCTP
,
the processor will be restarted by the reset derived from the watchdog timer as the IN pin rises above VTP.
With the RC pin tied to VCCO, RST and RST are not forced active as VCC collapses to VCCTP. The RST is
held at a high level via the external battery as VCC falls below battery potential. This mode of operation is
intended for applications in which the processor is made nonvolatile with an external source, and allows
the processor to power down into a Stop mode as signaled from NMI at an earlier voltage level. The NMI
output pin will pulse low for tNMI following a low voltage detect at the IN pin of VTP. Following tNMI
,
however, NMI will also be held at a high level (VBAT) by the battery as VCC decays below VBAT. On
power-up, RST and RST are held inactive until VCC reaches VBAT, then RST and RST are driven active
for tRST. If the IN pin falls below VTP during an active reset, the reset outputs will be forced inactive by
the NMI output. In addition, as long as the IN pin is less than VTP, stimulation of the ST pin will result in
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DS1236
additional NMI pulses. In this way, the ST pin can be used to allow the CMOS processor to determine if
the supply voltage, as monitored by the IN pin, is above or below a selected operating value. This is
illustrated in Figure 3. As discussed above, the RC pin determines the timing relationships and levels of
several signals. The following section describes the power-up and power-down timing diagrams in more
detail.
TIMING DIAGRAMS
This section provides a description of the timing diagrams shown in Figure 10, Figure 11, Figure 12, and
Figure 13. These diagrams show the relative timing and levels in both the NMOS and the CMOS mode
for power-up and down. Figure 10 illustrates the relationship for power-down in CMOS mode. As VCC
falls, the IN pin voltage drops below VTP. As a result, the processor is notified of an impending power
failure via an active NMI , which allows it to enter a sleep mode. As the power falls further, VCC crosses
VCCTP, the power monitor trip point. Since the DS1236 is in CMOS mode, no reset is generated. The RST
voltage will follow VCC down, but will fall no further than VBAT. At this time, CEO is brought high to
write protect the RAM. When the VCC reaches VBAT, a power-fail is issued via the PF and PF pins.
Figure 11 illustrates operation of the power-down sequence in NMOS mode. Once again, as power falls,
an NMI is issued. This gives the processor time to save critical data in nonvolatile SRAM. When VCC
reaches VCCTP, an active RST and RST are given. The RST voltage will follow VCC as it falls. CEO , PF,
and PF will operate in a similar manner to CMOS mode. Notice that the NMI will tri-state to prevent a
loss of battery power.
Figure 12 shows the power-up sequence for the NMOS mode. As VCC slews above VBAT, the PF and PF
pins are deactivated. An active reset occurs as well as an NMI . Although the NMI may be short due to
slew rates, reset will be maintained for the standard tRST timeout period. At a later time, if the IN pin falls
below VTP, a new NMI will occur. If the processor does not issue a ST , a watchdog reset will also occur.
The second NMI and RST are provided to illustrate these possibilities.
Figure 13 illustrates the power-up timing for CMOS mode. The principal difference is that the DS1236
issues a reset immediately in the NMOS mode. In CMOS mode, a reset is issued when IN rises above
VTP. Depending on the processor type, the NMI may terminate the Stop mode in the processor.
WAKE CONTROL/SLEEP CONTROL
The Wake/Sleep Control input (WC/SC ) allows the processor to disable all comparators on the DS1236
before entering the Stop mode. This feature allows the DS1236, processor, and static RAM to maintain
nonvolatility in the lowest power mode possible. The processor may invoke the sleep mode in battery
operated applications to conserve battery capacity when an absence of activity is detected. The operation
of this signal is shown in Figure 14. The DS1236 may subsequently be restarted by a high-to-low
transition on the PBRST input through human interface via a keyboard, touchpad, etc. The processor will
then be restarted as the watchdog times out and drives RST and RST active. The DS1236 can also be
started up by forcing the WC/SC pin high from an external source. Also, if the DS1236 is placed in a
sleep mode by the processor and system power is lost, the DS1236 will wake up the next time VCC rises
above VBAT. These possibilities are illustrated in Figure 15.
When the sleep mode is invoked during normal power-valid conditions, all operation on the DS1236 is
disabled, thus leaving the NMI , RST, and RST outputs disabled as well as the ST and IN inputs.
However, a loss of power during a sleep mode will result in an active RST and RST when the RC pin is
grounded (NMOS mode). If the RC pin is tied high, the RST and RST pins will remain inactive during
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DS1236
power-down in a sleep mode. Removal of the sleep mode by the PBRST input is not affected by the IN
pin threshold at VTP when the RC pin is tied high (CMOS mode). Subsequent power-up of the VCC supply
with the RC pin tied high will activate the RST and RST outputs as the main supply rises above VBAT. A
high-to-low transition on the WC/SC pin must follow a high-to-low transition on the ST pin by tWC to
invoke a Sleep mode for the DS1236.
FRESHNESS SEAL Figure 8
NOTE: This series of pulses must be applied during normal +5 volt operation.
POWER SWITCHING Figure 9
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DS1236
CMOS MODE POWER-DOWN (RC = VCCO) Figure 10
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DS1236
NMOS MODE POWER-DOWN (RC = GND) Figure 11
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DS1236
NMOS MODE POWER-UP (RC = GND) Figure 12
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DS1236
CMOS MODE POWER-UP (RC = VCCO) Figure 13
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DS1236
WAKE/SLEEP CONTROL Figure 14
OPTIONS FOR INVOKING WAKEUP Figure 15
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DS1236
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to Ground
Voltage on I/O Relative to Ground
Voltage on IN Pin Relative to Ground
Operating Temperature
-0.5V to +7.0V
-0.5V to VCC + 0.5V
-3.5V to VCC + 0.5V
0°C to 70°C
Operating Temperature (Industrial Version)
Storage Temperature
Soldering Temperature
-40°C to +85°C
-55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0°C to 70°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
5.5
UNITS NOTES
Supply Voltage
VCC
4.5
5.0
V
V
V
V
V
V
1
1
1
1
1
1
Supply Voltage (5% Option)
Input High Level
Input Low Level
IN Input Pin
VCC
4.75
2.0
5.0
5.5
VIH
VCC+0.3
+0.8
VIL
-0.3
-0.3
2.7
VIN
VCC+0.3
4.0
Battery Input
VBAT
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC= 4.5V to 5.5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Supply Current
ICC
ICC
4
mA
2
Sleep Supply Current in Sleep
mode
20
µA
Battery Current
IBAT
0.1
2
3
µA
Supply Output Current
(VCCO=VCC - 0.3V)
ICC01
100
mA
Supply Output Current in Data
ICC02
1
mA
4
Retention (VCC < VBAT
)
Supply Output Voltage
Battery Backup Voltage
Low Level @ RST
VCCO
VCCO
VOL
VOH
VOHL
RPBRST
ILI
VCC-0.3
V
V
1
1, 6
1
VBAT-0.7
0.4
V
VCC-0.5V VCC-0.1V
V
1
Output Voltage @ -500 µA
CEO and PF Output
VBAT-0.7
V
1, 6
10k
-1.0
-1.0
Ohms
PBRST Pull-up Resist
Input Leakage Current
Output Leakage Current
Output Current @ 0.4V
+1.0
+1.0
4.0
18
18
12
µA
µA
mA
ILO
IOL
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DS1236
PARAMETER
SYMBOL
IOH
MIN
-1.0
4.25
4.50
-1.0
2.5
TYP
MAX
UNITS NOTES
Output Current @ 2.4V
Power Sup. Trip Point
Power Supply Trip (5% Option)
IN Input Pin Current
IN Input Trip Point
mA
V
13
1
VCCTP
VCCTP
ICCIN
4.37
4.62
4.50
4.75
+1.0
2.6
V
1
µA
V
VTP
2.54
1
AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC= 4.5V to 5.5V)
PARAMETER
SYMBOL
tRPD
tIPD
MIN
40
TYP
100
100
100
300
MAX
UNITS NOTES
175
µs
µs
VCC Fail Detect to RST, RST
VTP to NMI
40
175
RESET Active Time
NMI Pulse Width
tRST
tNMI
tST
25
150
ms
200
20
500
14
19
µs
ns
ST Pulse Width
tPB
30
ms
PBRST @ VIL
VCC Slew Rate 4.75 to 4.25
Chip Enable Propagation Delay
VCC Fail to Chip Enable High
tF
300
µs
ns
tPD
20
44
tCF
7
12
17
µs
ns
tFPU
tRPU
tFB1
tFB2
tREC
100
150
VCC Valid to RST, RST (RC=1)
VCC Valid to RST & RST
VCC Slew to 4.24 to VBAT
VCC Slew 4.25 to 4.75 VBAT
25
10
100
ms
5
7
8
9
µs
µs
µs
100
.1
Chip Enable Output Recovery
Time
VCC Slew 4.25 to 4.75
Chip Enable Pulse Width
Watchdog Time Delay
ST to WC/SC
tR
0
µs
s
tCE
5
10
tTD
100
0.1
400
100
600
50
ms
µs
µs
ns
ns
tWC
tPPF
tSTN
tNRT
tARST
tBRST
2
7
VBAT Detect to PF, PF
ST to NMI
30
11
30
NMI to RST & RST
VBAT Detect to RST & RST
VCC Valid to RST, RST
200
150
15
16
µs
µs
30
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DS1236
CAPACITANCE
PARAMETER
(tA=25°C)
UNITS NOTES
SYMBOL
CIN
MIN
TYP
MAX
Input Capacitance
Output Capacitance
5
7
pF
pF
COUT
NOTES:
1. All voltages referenced to ground. A 0.1 µF capacitor is recommended between VCC and GND.
2. Measured with VCCO, CEO , PF, ST , PBRST , RST, RST , and NMI pin open. IBAT specified at 25°C.
3. ICCO1 is the maximum average load which the DS1236 can supply at VCC-0.3V through the VCCO pin
during normal 5-volt operation.
4. ICCO2 is the maximum average load which the DS1236 can supply through the VCCO pin during data
retention battery supply operation, with a maximum drop of 0.8 volts.
5. With tR = 5 µs.
6. VCCO is approximately VBAT-0.5V at 1 µA load.
7. Sleep mode is not invoked.
8. Sleep mode is invoked.
9. tREC is the minimum time required before CEI /CEO memory access is allowed.
10. tCE maximum must be met to ensure data integrity on power loss.
11. IN input is less than VTP but VCC greater than VCCTP
.
12. All outputs except RST which is 25 µA maximum.
13. All outputs except RST and NMI which is 25 µA minimum.
14. Pulse width of NMI requires that the IN pin remain below VTP. If the IN pin returns to a level above
VTP for a period longer than tIPD and before the tNMI period has elapsed, the NMI pin will immediately
return to a high.
15. IN pin greater than VTP when VCC supply rises to VBAT. Example: IN tied to GND.
16. IN pin less than VTP when VCC supply rises to VBAT
.
17. CEI low.
18. The WC/SC pin contains an internal latch which drives back on to the pin. This latch requires ±200
µamps to switch states. The ST pin will sink ±50 µamps in normal operation and ±1 µamp in the
sleep mode.
19. ST should be active low before the watchdog is disabled (i.e., before the ST input is tristated).
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