DS1244Y-200 [DALLAS]
256K NV SRAM with Phantom Clock; 256K NV SRAM，带有隐含时钟
| 型号： | DS1244Y-200 |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | 256K NV SRAM with Phantom Clock |
| 文件： | 总12页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1244Y
DS1244Y
256K NV SRAM with Phantom Clock
FEATURES
PIN ASSIGNMENT
• Realtimeclockkeepstrackofhundredthsofseconds,
minutes, hours, days, date of the month, months, and
years
A14/RST
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
2
WE
A13
A8
3
• 32K x 8 NV SRAM directly replaces volatile static
RAM or EEPROM
A6
4
A5
5
A9
• Embedded lithium energy cell maintains calendar op-
eration and retains RAM data
A4
6
A11
OE
A3
7
A2
8
A10
CE
• Watch function is transparent to RAM operation
A1
9
• Monthandyeardeterminethenumberofdaysineach
month; volid up to 1200
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
GND
• Standard 28–pin JEDEC pinout
• Full 10% operating range
• Operating temperature range 0°C to 70°C
• Accuracy is better than ±1 minute/month @ 25°C
28–PIN ENCAPSULATED PACKAGE
740 MIL EXTENDED
PIN DESCRIPTION
• Over 10 years of data retention in the absence of
power
A –A
–
–
–
–
–
–
–
–
–
Address Inputs
Chip Enable
Ground
o
CE
GND
14
• Available in 120, 150 and 200 ns access time
DQ DQ
Data In/Data Out
Power (+5V)
Write Enable
Output Enable
No Connect
Reset
0-
7
ORDERING INFORMATION
V
CC
DS1244Y–XXX
WE
OE
NC
–120
–150
120 ns access
150 ns access
RST
200 ns access
DS1244Y
DESCRIPTION
The DS1244Y 256K NV SRAM with Phantom Clock is a
fully static nonvolatile RAM (organized as 32,768 words
by 8 bits) with a built–in real time clock. The DS1244Y
has a self–contained lithium energy source and control
The Phantom Clock provides timekeeping information
including hundredths of seconds, seconds, minutes,
hours, day, date, month, andyearinformation. Thedate
at the end of the month is automatically adjusted for
months with less than 31 days, including correction for
leap years. The Phantom Clock operates in either
24–hour or 12–hour format with an AM/PM indicator.
circuitry which constantly monitors V for an out–of–
CC
tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent
garbled data in both the memory and real time clock.
ECopyright 1997 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
032697 1/12
DS1244Y
RAM READ MODE
PHANTOM CLOCK OPERATION
The DS1244Y executes a read cycle whenever WE
(WriteEnable) is inactive (high) and CE(ChipEnable)is
active(low). Theuniqueaddressspecifiedbythe15ad-
dressinputs(A0-A14)defineswhichofthe32,768 bytes
of data is to be accessed. Valid data will be available to
Communication with the Phantom Clock is established
by pattern recognition on a serial bit stream of 64 bits
which must be matched by executing 64 consecutive
write cycles containing the proper data on DQ0. All ac-
cesseswhichoccurpriortorecognitionofthe64–bitpat-
tern are directed to memory.
the eight data output drivers within t
(Access Time)
ACC
after the last address input signal is stable, providing
that CE and OE (Output Enable) access times and
states are also satisfied. If OE and CE access times are
not satisfied, then data access must be measured from
the later occurring signal (CE or OE) and the limiting pa-
Afterrecognitionisestablished, thenext64readorwrite
cycles either extract or update data in the Phantom
Clock, and memory access is inhibited.
Datatransfertoandfromthetimekeepingfunctionisac-
complished with a serial bit stream under control of Chip
Enable (CE), Output Enable (OE), and Write Enable
(WE). Initially, a read cycle to any memory location us-
ing the CE and OE control of the Phantom Clock starts
the pattern recognition sequence by moving a pointer to
the first bit of the 64–bit comparison register. Next, 64
consecutivewrite cycles are executed using the CEand
WE control of the SmartWatch. These 64 write cycles
are used only to gain access to the Phantom Clock.
Therefore, any address to the memory in the socket is
acceptable. However, the write cycles generated to
gain access to the Phantom Clock are also writing data
to a location in the mated RAM. The preferred way to
manage this requirement is to set aside just one ad-
dress location in RAM as a Phantom Clock scratch pad.
When the first write cycle is executed, it is compared to
bit 0 of the 64–bit comparison register. If a match is
found, the pointer increments to the next location of the
comparisonregister and awaits the next write cycle. If a
match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle oc-
curs at any time during pattern recognition, the present
sequence is aborted and the comparison register point-
erisreset. Patternrecognitioncontinuesforatotalof64
write cycles as described above until all the bits in the
comparisonregisterhavebeenmatched(thisbitpattern
is shown in Figure 1). With a correct match for 64 bits,
the Phantom Clock is enabled and data transfer to or
from the timekeeping registers can proceed. The next
64cycleswillcausethePhantomClocktoeitherreceive
or transmit data on DQ0, depending on the level of the
OE pin or the WE pin. Cycles to other locations outside
the memory block can be interleaved with CE cycles
without interrupting the pattern recognition sequence or
data transfer sequence to the Phantom Clock.
rameter is either t for CE or t for OE rather than ad-
dress access.
CO
OE
RAM WRITE MODE
The DS1244Y is in the write mode whenever the WE
andCEsignalsareintheactive(low)stateafteraddress
inputsare stable. The latter occurring falling edge of CE
or WE will determine the start of the write cycle. The
write cycle is terminated by the earlier rising edge of CE
or WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (t ) before another cycle can
WR
be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
However, if the output bus has been enabled (CE and
OEactive)thenWEwilldisabletheoutputsint
its falling edge.
from
ODW
DATA RETENTION MODE
The DS1244Y provides full functional capability for V
CC
greater than 4.5 volts and write protects by approxi-
mately 4.0 volts. Data is maintained in the absence of
V
CC
without any additional support circuitry. The non-
volatilestaticRAMconstantlymonitorsV . Shouldthe
CC
supply voltage decay, the RAM automatically write pro-
tects itself. All inputs to the RAM become “don’t care”
and all outputs are high impedance. As V falls below
CC
approximately3.0volts, thepowerswitchingcircuitcon-
nects the lithium energy source to RAM to retain data.
Duringpower–up, whenV risesaboveapproximately
CC
3.0 volts, the power switching circuit connects external
V
CC
to the RAM and disconnects the lithium energy
source. Normal RAM operation can resume after V
exceeds 4.5 volts.
CC
032697 2/12
DS1244Y
in a register could produce erroneous results. These
read/write registers are defined in Figure 2.
PHANTOM CLOCK
REGISTER INFORMATION
The Phantom Clock information is contained in 8 regis-
tersof8bits,eachofwhichissequentiallyaccessedone
bit at a time after the 64–bit pattern recognition se-
quence has been completed. When updating the Phan-
tom Clock registers, each register must be handled in
groupsof 8 bits. Writingandreadingindividualbitswith-
Data contained in the Phantom Clock register is in
binary coded decimal format (BCD). Reading and writ-
ing the registers is always accomplished by stepping
throughall8registers, startingwithbit0ofregister0and
ending with bit 7 of register 7.
PHANTOM CLOCK REGISTER DEFINITION Figure 1
HEX
VALUE
7
1
6
1
5
0
4
0
3
0
2
1
1
0
0
1
BYTE 0
C5
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
BYTE 1
BYTE 2
3A
A3
BYTE 3
BYTE 4
5C
C5
BYTE 5
BYTE 6
BYTE 7
3A
A3
5C
NOTE:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally dupli-
19
cated and causing inadvertent entry to the Phantom Clock is less than 1 in 10 . This pattern is sent to the Phantom
Clock LSB to MSB.
032697 3/12
DS1244Y
PHANTOM CLOCK REGISTER DEFINITION Figure 2
REGISTER
RANGE
(BCD)
7
6
5
4
3
2
1
0
0
00–99
0.1 SEC
0.01 SEC
0
10 SEC
SECONDS
MINUTES
HOUR
1
2
00–59
00–59
0
10 MIN
10
01–12
00–23
12/24
0
0
0
0
HR
3
4
A/P
0
0
0
OSC
RST
0
DAY
01–07
10 DATE
DATE
MONTH
YEAR
5
6
01–31
01–12
10
MONTH
0
10 YEAR
7
00–99
to logic 0, a low input on the RESET pin will cause the
Phantom Clock to abort data transfer without changing
data in the watch registers. Bit 5 controls the oscillator.
When set to logic 1, the oscillator is off. When set to log-
ic 0, the oscillator turns on and the watch becomes op-
erational. These bits are shipped from the factory set to
a logic 1.
AM–PM/12/24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hourmodeselectbit. Whenhigh,the12–hourmode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10–hour bit (20–23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the
RESET and oscillator functions. Bit 4 controls the
RESET(pin1). WhentheRESETbitissettologic1, the
RESET input pin is ignored. When the RESET bit is set
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits
which will always read logic 0. When writing these loca-
tions, either a logic 1 or 0 is acceptable.
032697 4/12
DS1244Y
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
–0.3V to +7.0V
0°C to 70°C
Storage Temperature
–40°C to +70°C
Soldering Temperature
260°C for 10 seconds (See Note 13)
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0°C to 70°C)
PARAMETER
Power Supply Voltage
Input Logic 1
SYMBOL
MIN
4.5
2.2
0.3
TYP
MAX
UNITS
NOTES
V
CC
5.0
5.5
V
V
V
V
IH
V
+0.3
CC
Input Logic 0
V
IL
0.8
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5V ± 10%)
PARAMETER
SYMBOL
MIN
–1.0
–1.0
TYP
MAX
+1.0
+1.0
UNITS
µA
NOTES
Input Leakage Current
I/O Leakage Current
I
IL
12
I
IO
µA
CE ꢀ V ꢁ V
IH
CC
Output Current @ 2.4V
Output Current @ 0.4V
Standby Current CE = 2.2V
I
–1.0
2.0
mA
mA
mA
mA
mA
OH
I
OL
I
I
5.0
3.0
10
5.0
85
CCS1
CCS2
Standby Current CE = V – 0.5V
CC
Operating Current t
= 200 ns
I
CC01
CYC
DC TEST CONDITIONS
Outputsareopen;allvoltagesarereferencedtoground.
CAPACITANCE
(tA = 25°C)
PARAMETER
SYMBOL
MIN
TYP
5
MAX
10
UNITS
pF
NOTES
Input Capacitance
Input/Output Capacitance
C
IN
C
5
10
pF
I/O
032697 5/12
DS1244Y
MEMORY AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0V ± 10%)
DS1244Y-120
DS1244Y-150
DS1244Y-200
PARAMETER
SYMBOL
UNITS NOTES
MIN MAX MIN MAX MIN MAX
Read Cycle Time
t
120
150
200
ns
ns
ns
ns
ns
ns
ns
RC
Access Time
t
120
60
150
70
200
100
200
ACC
OE to Output Valid
t
OE
CO
CE to Output Valid
t
120
150
OE or CE to Output Active
Output High Z from Deselection
t
5
5
5
5
5
5
5
5
COE
t
40
70
100
OD
Output Hold from Address
Change
t
oH
Write Cycle Time
t
120
90
0
150
100
0
200
150
0
ns
ns
ns
ns
ns
ns
ns
ns
WC
Write Pulse Width
t
3
WP
Address Setup Time
Write Recovery Time
Output High Z from WE
Output Active from WE
Data Setup Time
t
AW
WR
t
20
20
20
t
40
70
80
5
5
4
4
ODW
t
5
5
5
OEW
t
50
20
60
20
80
20
DS
DH
Data Hold Time from WE
t
AC TEST CONDITIONS
Output Load:
Input Pulse Levels:
50 pF + 1TTL Gate
0-3V
Timing Measurement Reference Levels
Input:
Output:
1.5V
1.5V
Input Pulse Rise and Fall Times:
5 ns
032697 6/12
DS1244Y
PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 4.5 to 5.5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
ns
NOTES
Read Cycle Time
CE Access Time
OE Access Time
CE to Output Low Z
OE to Output Low Z
CE to Output High Z
OE to Output High Z
Read Recovery
t
120
RC
CO
t
100
100
ns
t
ns
OE
t
10
10
ns
COE
t
ns
OEE
t
40
40
ns
5
5
OD
t
ns
ODO
t
20
120
100
20
ns
RR
Write Cycle Time
Write Pulse Width
Write Recovery
t
ns
WC
t
ns
WP
WR
t
ns
10
11
11
Data Setup Time
Data Hold Time
t
40
ns
DS
DH
CW
t
10
ns
CE Pulse Width
t
100
200
ns
RESET Pulse Width
CE High to Power–Fail
t
ns
RST
t
PF
0
ns
POWER-DOWN/POWER-UP TIMING
PARAMETER
CE at V before Power–Down
SYMBOL
MIN
0
TYP
MAX
UNITS
µs
NOTES
t
IH
PD
V
Slew from 4.5V to 0V
t
F
300
µs
CC
(CE at V
)
IH
V
Slew from 0V to 4.5V
t
R
0
µs
CC
(CE at V
)
IH
CE at V after Power–Up
t
2
ms
IH
REC
(tA = 25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Expected Data Retention Time
t
10
years
9
DR
WARNING:
Undernocircumstancesarenegativeundershoots, ofanyamplitude, allowedwhendeviceisinbatterybackupmode.
032697 7/12
DS1244Y
MEMORY READ CYCLE (NOTE 1)
t
RC
V
V
V
IH
IH
IH
ADDRESSES
V
V
V
IL
IL
IL
t
OH
t
ACC
V
IH
V
IH
t
CO
CE
V
IL
t
OD
V
IH
t
OE
V
IH
OE
V
IL
t
COE
t
OD
t
COE
V
V
OH
OH
OUTPUT
DATA VALID
D
OUT
V
V
OL
OL
MEMORY WRITE CYCLE 1 (NOTES 2, 6, AND 7)
t
WC
V
V
V
IH
IH
IH
ADDRESS
V
V
V
IL
IL
IL
t
AW
CE
V
IL
V
IL
t
t
WR
WP
V
IH
V
IH
WE
t
OEW
t
ODW
HIGH IMPEDANCE
t
DH
t
DQ0–DQ7
DS
V
V
IH
IH
DATA IN
STABLE
V
V
IL
IL
032697 8/12
DS1244Y
MEMORY WRITE CYCLE 2 (NOTES 2 AND 8)
WE = V
IH
t
WC
V
V
V
IH
IH
IH
ADDRESSES
V
V
V
IL
IL
IL
t
AW
t
t
WR
WP
V
IH
V
IH
CE
V
IL
V
IL
t
OEW
WE
V
IL
V
IL
t
ODW
t
COE
t
DH
t
DQ0–DQ7
DS
V
V
IH
IH
DATA IN
STABLE
V
V
IL
IL
RESET FOR PHANTOM CLOCK
t
RST
RST
READ CYCLE TO PHANTOM CLOCK
t
RC
t
RR
t
CO
CE
t
OD
t
OE
OE
t
t
ODO
OEE
t
COE
Q
OUTPUT DATA VALID
032697 9/12
DS1244Y
WRITE CYCLE TO PHANTOM CLOCK
OE = V
t
WC
IH
t
WR
t
WP
WE
t
WR
t
CW
CE
t
DH
t
DS
t
DH
D
DATA IN STABLE
POWER–DOWN/POWER–UP CONDITION
V
CC
4.50V
3.2V
t
F
t
R
t
t
REC
PD
CE
DATA RETENTION TIME
LEAKAGE CURRENT
SUPPLIED FROM LITHIUM
CELL
I
L
t
DR
032697 10/12
DS1244Y
NOTES:
1. WE is high for a read cycle.
2. OE = V or V . If OE = V during write cycle, the output buffers remain in a high impedance state.
IH
IL
IH
3. t
is specified as the logical AND of CE and WE. t
is measured from the latter of CE or WE going low to the
WP
WP
earlier of CE or WE going high.
4. t , t are measured from the earlier of CE or WE going high.
DH DS
5. These parameters are sampled with a 50 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output
buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
in a high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers
remain in a high impedance state during this period.
9. The expected t is defined as accumulative time in the absence of V with the clock oscillator running.
DR
CC
10.t
is a function of the latter occurring edge of WE or CE.
WR
11. t and t are a function of the first occurring edge of WE or CE.
DH
DS
12.RST (Pin1) has an internal pull–up resistor.
13.Real–Time Clock Modules can be successfully processed through conventional wave–soldering techniques as
long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post solder
cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used.
032697 11/12
DS1244Y
DS1244Y 256K NV SRAM WITH PHANTOM CLOCK
PKG
28–PIN
MIN
DIM
MAX
A
IN.
MM
1.520
38.61
1.540
39.12
B
C
D
E
F
IN.
MM
0.720
18.29
0.740
18.80
1
IN.
MM
0.395
10.03
0.415
10.54
A
IN.
MM
0.100
2.54
0.130
3.30
IN.
MM
0.017
0.43
0.030
0.76
C
IN.
MM
0.120
3.05
0.160
4.06
G
H
J
IN.
MM
0.090
2.29
0.110
2.79
F
IN.
MM
0.590
14.99
0.630
16.00
D
K
G
IN.
MM
0.008
0.20
0.012
0.30
K
IN.
MM
0.015
0.38
0.021
0.53
J
E
H
B
032697 12/12
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