DS1250WP-100-IND [DALLAS]
Non-Volatile SRAM, 512KX8, 100ns, CMOS,;
| 型号： | DS1250WP-100-IND |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Non-Volatile SRAM, 512KX8, 100ns, CMOS, 静态存储器 |
| 文件： | 总11页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1250W
3.3V 4096k Nonvolatile SRAM
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
C 10 years minimum data retention in the
absence of external power
A18
A16
A14
A12
A7
VCC
A15
A17
WE
A13
A8
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
3
4
C Data is automatically protected during power
loss
5
C Replaces 512k x 8 volatile static RAM,
EEPROM or Flash memory
A6
6
A5
A9
7
8
9
10
11
12
13
14
15
16
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A4
C Unlimited write cycles
A3
C Low-power CMOS
A2
A1
C Read and write access times as fast as 100ns
C Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
A0
DQ0
DQ1
DQ2
GND
C Optional industrial temperature range of -
40LC to +85LC, designated IND
C JEDEC standard 32-pin DIP package
C PowerCap® Module (PCM) package
– Directly surface-mountable module
– Replaceable snap-on PowerCap provides
lithium backup battery
32-Pin Encapsulated Package
740-Mil Extended
A18
A17
A14
A13
A12
A11
A10
A9
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
1
2
3
NC
A15
A16
NC
4
5
6
7
8
9
– Standardized pinout for all nonvolatile
SRAM products
VCC
E
OE
CE
– Detachment feature on PCM allows easy
removal using a regular screwdriver
A8
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A6
A5
A4
A3
A2
A1
A0
10
11
12
13
14
15
16
17
PowerCap® is a registered trademark of Dallas
Semiconductor.
GND VBAT
DQ2
DQ1
DQ0
GND
34-Pin PowerCap Module (PCM)
(Uses DS9034PC PowerCap)
PIN DESCRIPTION
A0 - A18
DQ0 - DQ7
CE
WE
OE
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Power (+3.3V)
- Ground
VCC
GND
NC
- No Connect
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103102
DS1250W
DESCRIPTION
The DS1250W 3.3V 4096k Nonvolatile SRAM is a 4,194,304-bit, fully static, nonvolatile SRAM
organized as 524,288 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
control circuitry, which constantly monitors VCC for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1250W devices can be used in place of existing 512k
x 8 static RAMs directly conforming to the popular bytewide 32-pin DIP standard. DS1250W devices in
the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODE
The DS1250W executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs
(A0 - A18) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1250W executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR
)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE
will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1250W provides full functional capability for VCC greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile
static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As VCC
falls below approximately 2.5 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when VCC rises above approximately 2.5 volts, the power
switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal
RAM operation can resume after VCC exceeds 3.0 volts.
FRESHNESS SEAL
Each DS1250W device is shipped from Dallas Semiconductor with its lithium energy source
disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than 3.0
volts, the lithium energy source is enabled for battery back-up operation.
PACKAGES
The DS1250W is available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-
pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
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DS1250W
memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1250W PCM
device to be surface mounted without subjecting its lithium backup battery to destructive high-
temperature reflow soldering. After a DS1250W module base is reflow soldered, a DS9034PC PowerCap
is snapped on top of the base to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to
prevent improper attachment. DS1250W module bases and DS9034PC PowerCaps are ordered separately
and shipped in separate containers. See the DS9034PC data sheet for further information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-0.3V to +4.6V
0°C to 70°C, -40°C to +85°C for IND parts
-40°C to +70°C, -40°C to +85°C for IND parts
260°C for 10 seconds
Storage Temperature
Soldering Temperature
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(tA: See Note 10)
PARAMETER
Power Supply Voltage
Logic 1
SYMBOL MIN
TYP
3.3
MAX
3.6
VCC
+0.4
UNITS NOTES
VCC
VIH
VIL
3.0
2.2
0.0
V
V
V
Logic 0
DC ELECTRICAL CHARACTERISTICS
(tA: See Note 10) (VCC=3.3V Mꢀ0.3V)
PARAMETER
SYMBOL MIN
TYP
MAX
+1.0
UNITS NOTES
Input Leakage Current
IIL
-1.0
-1.0
-1.0
2.0
ꢀA
ꢀA
mA
mA
ꢀA
ꢀA
mA
V
IIO
IOH
+1.0
I/O Leakage Current CE O VIH ? VCC
Output Current @ 2.2V
Output Current @ 0.4V
IOL
ICCS1
ICCS2
ICCO1
VTP
50
30
250
150
50
Standby Current CE =2.2V
Standby Current CE =VCC-0.2V
Operating Current
Write Protection Voltage
2.8
2.9
3.0
CAPACITANCE
PARAMETER
Input Capacitance
(tA=25LC)
SYMBOL MIN
TYP
5
5
MAX
10
10
UNITS NOTES
CIN
CI/O
pF
pF
Input/Output Capacitance
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DS1250W
(tA: See Note 10) (VCC=3.3V Mꢀ0.3V)
DS1250W-100 DS1250W-150
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Read Cycle Time
Access Time
OE to Output Valid
SYMBOL
tRC
MIN
100
MAX MIN MAX UNITS NOTES
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tACC
tOE
tCO
tCOE
tOD
tOH
tWC
tWP
tAW
100
50
100
150
70
150
CE to Output Valid
5
5
5
5
OE or CE to Output Active
Output High Z from Deselection
Output Hold from Address Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
35
35
5
100
75
0
5
20
5
150
100
0
3
tWR1
5
12
13
5
5
4
tWR2
20
tODW
tOEW
tDS
35
35
ns
ns
ns
ns
Output High Z from WE
Output Active from WE
Data Setup Time
5
40
0
5
60
0
Data Hold Time
tDH1
12
13
tDH2
20
20
READ CYCLE
SEE NOTE 1
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DS1250W
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, AND 12
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DS1250W
POWER-DOWN/POWER-UP CONDITION
POWER-DOWN/POWER-UP TIMING
(tA: See Note 10)
PARAMETER
SYMBOL MIN
TYP
TYP
MAX
1.5
UNITS NOTES
tPD
tF
tR
11
VCC Fail Detect to CE and WE Inactive
VCC slew from VTP to 0V
VCC slew from 0V to VTP
ꢀs
ꢀs
150
150
ꢀs
ms
ms
tPU
tREC
2
125
VCC Valid to CE and WE Inactive
VCC Valid to End of Write Protection
(tA=25LC)
PARAMETER
Expected Data Retention Time
SYMBOL MIN
tDR 10
MAX
UNITS NOTES
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDH, tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
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DS1250W
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1250W has a built-in switch that disconnects the lithium source until VCC is first applied by
the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the
time power is first applied by the user.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0LC to 70LC. For industrial products (IND), this range is -40LC to
+85LC.
11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12. tWR1 and tDH1 are measured from WE going high.
13. tWR2 and tDH2 are measured from CE going high.
14. DS1250 modules are recognized by Underwriters Laboratory (U.L.®) under file E99151.
DC TEST CONDITIONS
Outputs Open
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 to 2.7V
Timing Measurement Reference Levels
Input: 1.5V
Cycle = 200ns for operating current
All voltages are referenced to ground
Output: 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
DS1250 W P - SSS - III
Operating Temperature Range
blank: 0L to 70LC
IND: -40L to +85LC
Access Speed
100: 100ns
150: 150ns
Package Type
blank: 32-pin 600-mil DIP
P:
34-pin PowerCap Module
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DS1250W
DS1250W NONVOLATILE SRAM, 32-PIN 740 MIL EXTENDED DIP MODULE
PKG
DIM
32-PIN
MIN
MAX
A IN.
MM
1.680
42.67
1.700
43.18
B IN.
MM
0.720
18.29
0.740
18.80
C IN.
MM
0.355
9.02
0.375
9.52
D IN.
MM
0.080
2.03
0.110
2.79
E IN.
MM
0.015
0.38
0.025
0.63
F IN.
MM
0.120
3.05
0.160
4.06
G IN.
MM
0.090
2.29
0.110
2.79
H IN.
MM
0.590
14.99
0.630
16.00
J IN.
MM
0.008
0.20
0.012
0.30
K IN.
MM
0.015
0.38
0.021
0.53
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DS1250W
DS1250W NONVOLATILE SRAM, 34-PIN POWERCAP MODULE
INCHES
PKG
DIM
MIN
0.920
0.980
-
0.052
0.048
0.015
0.020
NOM
0.925
0.985
-
0.055
0.050
0.020
0.025
MAX
A
B
C
D
E
F
0.930
0.990
0.080
0.058
0.052
0.025
0.030
G
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DS1250W
DS1250W NONVOLATILE SRAM, 34-PIN POWERCAP MODULE WITH
POWERCAP
INCHES
NOM
PKG
DIM
MIN
MAX
A
B
C
D
E
F
0.920
0.955
0.240
0.052
0.048
0.015
0.020
0.925
0.960
0.245
0.055
0.050
0.020
0.025
0.930
0.965
0.250
0.058
0.052
0.025
0.030
G
ASSEMBLY AND USE
Reflow soldering
Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented label-side up (live-bug).
Hand soldering and touch-up
Do not touch soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the
lead frame pad and apply solder. To remove part, apply flux, heat pad until solder reflows, and use a
solder wick.
LPM replacement in a socket
To replace a Low Profile Module in a 68-pin PLCC socket, attach a DS9034PC PowerCap to a module
base then insert the complete module into the socket one row of leads at a time, pushing only on the
corners of the cap. Never apply force to the center of the device. To remove from a socket, use a PLCC
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DS1250W
extraction tool and ensure that it does not hit or damage any of the module IC components. Do not use
any other tool for extraction.
RECOMMENDED POWERCAP MODULE LAND PATTERN
INCHES
NOM
PKG
DIM
MIN
MAX
A
B
C
D
E
-
-
-
-
-
1.050
0.826
0.050
0.030
0.112
-
-
-
-
-
RECOMMENDED POWERCAP MODULE SOLDER STENCIL
INCHES
PKG
DIM
MIN
NOM
1.050
0.890
0.050
0.030
0.080
MAX
A
B
C
D
E
-
-
-
-
-
-
-
-
-
-
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相关型号：
DS1250Y-100-IND
Non-Volatile SRAM Module, 512KX8, 100ns, CMOS, 0.740 INCH, EXTENDED MODULE, DIP-32
DALLAS
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