DS1350W-IND [DALLAS]
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| 型号： | DS1350W-IND |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | 暂无描述 电池 静态存储器 监控 |
| 文件： | 总12页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1350Y/AB
4096k Nonvolatile SRAM
with Battery Monitor
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ 10 years minimum data retention in the
absence of external power
A18
A17
A14
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
BW
A15
A16
ꢀ
Data is automatically protected during power loss
A13
A12
A11
A10
A9
ꢀ Power supply monitor resets processor when
VCC power loss occurs and holds processor in
reset during VCC ramp-up
ꢀ Battery monitor checks remaining capacity
daily
ꢀ Read and write access times as fast as 70 ns
ꢀ Unlimited write cycle endurance
ꢀ Typical standby current 50 µA
ꢀ Upgrade for 512k x 8 SRAM, EEPROM or
Flash
RST
VCC
WE
OE
CE
A8
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A6
A5
A4
A3
A2
A1
A0
GND VBAT
DQ2
DQ1
DQ0
GND
34-Pin POWERCAP MODULE (PCM)
(USES DS9034PC POWERCAP)
ꢀ Lithium battery is electrically disconnected to
retain freshness until power is applied for the
first time
ꢀ Full ±10% VCC operating range (DS1350Y)
or optional ±5% VCC operating range
(DS1350AB)
ꢀ Optional industrial temperature range of
-40°C to +85°C, designated IND
ꢀ New PowerCap Module (PCM) package
PIN DESCRIPTION
A0 - A18
DQ0 - DQ7
CE
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Reset Output
- Battery Warning
- Power (+5V)
- Ground
WE
OE
RST
-
-
Directly surface-mountable module
Replaceable snap-on PowerCap provides
lithium backup battery
BW
VCC
GND
NC
-
-
Standardized pinout for all nonvolatile
SRAM products
Detachment feature on PowerCap allows
easy removal using a regular screwdriver
- No Connect
DESCRIPTION
The DS1350 4096k Nonvolatile SRAMs are 4,194,304-bit, fully static, nonvolatile SRAMs organized as
524,288 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry
which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. Additionally, the DS1350 devices have dedicated circuitry for monitoring the
status of VCC and the status of the internal lithium battery. DS1350 devices in the PowerCap Module
package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a
complete Nonvolatile SRAM module. The devices can be used in place of 512k x 8 SRAM, EEPROM or
Flash components.
1 of 12
111999
DS1350Y/AB
READ MODE
The DS1350 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs
(A0 -A18) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1350 devices execute a write cycle whenever the WE and CE signals are in the active (low) state
after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of
the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1350AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1350Y provides full functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As VCC falls below approximately 2.7 volts, the power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 2.7 volts,
the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1350AB and 4.5 volts for the
DS1350Y.
SYSTEM POWER MONITORING
DS1350 devices have the ability to monitor the external VCC power supply. When an out-of-tolerance
power supply condition is detected, the NV SRAMs warn a processor-based system of impending power
failure by asserting RST . On power-up, RST is held active for 200 ms nominal to prevent system
operation during power-on transients and to allow tREC to elapse. RST has an open drain output driver.
BATTERY MONITORING
The DS1350 devices automatically perform periodic battery voltage monitoring on a 24-hour time
interval. Such monitoring begins within tREC after VCC rises above VTP and is suspended when power
failure occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1MΩ=test resistor for one
second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output BW is asserted. Once asserted, BW remains active until the module is replaced.
The battery is still retested after each VCC power-up, however, even if BW is active. If the battery voltage
is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing
resumes. BW has an open drain output driver.
2 of 12
DS1350Y/AB
FRESHNESS SEAL
Each DS1350 is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium
energy source is enabled for battery backup operation.
PACKAGES
The 34-pin PowerCap Module integrates SRAM memory and nonvolatile control along with contacts for
connection to the lithium battery in the DS9034PC PowerCap. The PowerCap Module package design
allows a DS1350 PCM device to be surface mounted without subjecting its lithium backup battery to
destructive high-temperature reflow soldering. After a DS1350 PCM is reflow soldered, a DS9034PC is
snapped on top of the PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to
prevent improper attachment. DS1350 PowerCap Modules and DS9034PC PowerCaps are ordered
separately and shipped in separate containers. See the DS9034PC data sheet for further information.
3 of 12
DS1350Y/AB
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
-0.3V to +7.0V
0°C to 70°C, -40°C to +85°C for IND parts
-40°C to +70°C, -40°C to +85°C for IND parts
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(tA: See Note 10)
PARAMETER
SYMBOL MIN
TYP
5.0
MAX
5.25
5.5
UNITS NOTES
DS1350AB Power Supply Voltage
DS1350Y Power Supply Voltage
Logic 1
VCC
VCC
VIH
VIL
4.75
4.5
2.2
0.0
V
V
V
V
5.0
VCC
0.8
Logic 0
DC ELECTRICAL
CHARACTERISTICS
PARAMETER
(VCC=5V ±=5% for DS1350AB)
(tA: See Note 10) (VCC=5V ±=10% for DS1350Y)
SYMBOL MIN
TYP
MAX
UNITS NOTES
Input Leakage Current
IIL
IIO
-1.0
-1.0
-1.0
2.0
+1.0
µA
µA
+1.0
I/O Leakage Current CE ≥ VIH ≤ VCC
Output Current @ 2.4V
IOH
mA
mA
µA
µA
mA
V
14
14
Output Current @ 0.4V
IOL
ICCS1
ICCS2
ICCO1
VTP
VTP
200
50
600
150
85
Standby Current CE =2.2V
Standby Current CE =VCC-0.5V
Operating Current
Write Protection Voltage (DS1350AB)
Write Protection Voltage (DS1350Y)
4.50
4.25
4.62
4.37
4.75
4.5
V
CAPACITANCE
PARAMETER
(tA=25°C)
UNITS NOTES
SYMBOL MIN
TYP
MAX
10
Input Capacitance
CIN
5
5
pF
pF
Input/Output Capacitance
CI/O
10
4 of 12
DS1350Y/AB
(VCC=5V ±=5% for DS1350AB)
AC ELECTRICAL
CHARACTERISTICS
(tA: See Note 10) (VCC=5V ±=10% for DS1350Y)
DS1350AB-70 DS1350AB-100
DS1350Y-70
DS1330Y-100
PARAMETER
SYMBOL MIN MAX MIN
MAX UNITS NOTES
Read Cycle Time
tRC
tACC
tOE
70
100
ns
Access Time
70
35
70
100
50
ns
ns
ns
ns
ns
ns
OE to Output Valid
CE to Output Valid
OE or CE to Output Active
Output High Z from Deselection
tCO
100
tCOE
tOD
tOH
5
5
5
5
5
5
25
35
Output Hold from Address
Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
tWC
tWP
tAW
70
55
0
100
75
0
ns
ns
ns
ns
3
tWR1
tWR2
5
12
5
12
12
13
tODW
tOEW
tDS
25
35
ns
ns
ns
ns
5
5
4
Output High Z from WE
Output Active from WE
Data Setup Time
5
5
30
40
Data Hold Time
tDH1
tDH2
0
7
0
7
12
13
READ CYCLE
SEE NOTE 1
5 of 12
DS1350Y/AB
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
6 of 12
DS1350Y/AB
POWER-DOWN/POWER-UP CONDITION
BATTERY WARNING DETECTION
SEE NOTE 14
7 of 12
DS1350Y/AB
(tA: See Note 10)
UNITS NOTES
POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL MIN
tPD
tF
tRPD
tR
TYP
MAX
1.5
11
VCC Fail Detect to CE and WE Inactive
VCC slew from VTP to 0V
µs
µs
µs
µs
ms
ms
ms
s
150
150
15
14
VCC Fail Detect to RST Active
VCC slew from 0V to VTP
tPU
2
VCC Valid to CE and WE Inactive
VCC Valid to End of Write Protection
VCC Valid to RST Inactive
tREC
tRPU
tBPU
125
350
1
150
200
14
14
VCC Valid to BW Valid
BATTERY WARNING TIMING
PARAMETER
(tA: See Note 10)
SYMBOL MIN
TYP
MAX
UNITS NOTES
Battery Test Cycle
tBTC
tBTPW
tBW
24
hr
s
Battery Test Pulse Width
1
1
s
Battery Test to BW Active
(tA=25°C)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
Expected Data Retention Time
tDR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
8 of 12
DS1350Y/AB
9. Each DS1230Y has a built-in switch that disconnects the lithium source until VCC is first applied by
the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the
time power is first applied by the user.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12. tWR1 and tDH1 are measured from WE going high.
13. tWR2 and tDH2 are measured from CE going high.
14. RST and BW are open drain outputs and cannot source current. External pullup resistors should be
connected to these pins for proper operation. Both pins will sink 10 mA.
DC TEST CONDITIONS
Outputs Open
Cycle = 200 ns for operating current
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
ORDERING INFORMATION
DS1350 TTP - SSS - III
Operating Temperature Range
blank: 0° to 70°
IND: -40° to +85°C
Access Speed
70:
70 ns
100: 100 ns
Package Type
P:
34-pin PowerCap Module
VCC Tolerance
AB: ±5%
Y: ±10%
9 of 12
DS1350Y/AB
DS1350Y/AB NONVOLATILE SRAM, 34-PIN POWERCAP MODULE
INCHES
PKG
DIM
MIN
0.920
0.980
-
NOM
0.925
0.985
-
MAX
0.930
0.990
0.080
0.058
0.052
0.025
0.030
A
B
C
D
E
F
0.052
0.048
0.015
0.020
0.055
0.050
0.020
0.025
G
10 of 12
DS1350Y/AB
DS1350Y/AB NONVOLATILE SRAM, 34-PIN POWERCAP MODULE WITH
POWERCAP
INCHES
NOM
PKG
DIM
MIN
MAX
0.930
0.965
0.250
0.058
0.052
0.025
0.030
A
B
C
D
E
F
0.920
0.955
0.240
0.052
0.048
0.015
0.020
0.925
0.960
0.245
0.055
0.050
0.020
0.025
G
ASSEMBLY AND USE
Reflow soldering
Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented label-side up (live-bug).
Hand soldering and touch-up
Do not touch soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the
lead frame pad and apply solder. To remove part, apply flux, heat pad until solder reflows, and use a
solder wick.
LPM replacement in a socket
To replace a Low Profile Module in a 68-pin PLCC socket, attach a DS9034PC PowerCap to a module
base then insert the complete module into the socket one row of leads at a time, pushing only on the
corners of the cap. Never apply force to the center of the device. To remove from a socket, use a PLCC
extraction tool and ensure that it does not hit or damage any of the module IC components. Do not use
any other tool for extraction.
11 of 12
DS1350Y/AB
RECOMMENDED POWERCAP MODULE LAND PATTERN
INCHES
NOM
PKG
DIM
MIN
MAX
A
B
C
D
E
-
-
-
-
-
1.050
0.826
0.050
0.030
0.112
-
-
-
-
-
RECOMMENDED POWERCAP MODULE SOLDER STENCIL
INCHES
PKG
DIM
MIN
NOM
1.050
0.890
0.050
0.030
0.080
MAX
A
B
C
D
E
-
-
-
-
-
-
-
-
-
-
12 of 12
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