DS14285Q [DALLAS]
Real Time Clock with NV RAM Control; 实时时钟，带有非易失RAM控制器
| 型号： | DS14285Q |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Real Time Clock with NV RAM Control |
| 文件： | 总25页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS14285/DS14287
Real Time Clock with NV RAM Control
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ Direct replacement for IBM AT computer
clock/calendar
VCCO
VCC
SQW
1
24
23
X1
X2
AD0
AD1
AD2
2
3
4
ꢀ Functionally compatible with the
DS1285/DS1287
ꢀ Available as chip (DS14285, DS14285S, or
DS14285Q) or stand-alone module with
embedded lithium battery and crystal
(DS14287)
ꢀ Automatic backup supply and write
protection to make external SRAM
nonvolatile
22
21
CEO
CEI
VBAT
IRQ
RESET
DS
GND
R/W
AS
5
6
20
19
AD3
AD4
7
8
18
17
AD5
AD6
AD7
9
10
16
15
11
12
14
13
GND
CS
DS14285 24-Pin DIP
ꢀ Counts seconds, minutes, hours, days, day of
the week, date, month, and year with leap
year compensation valid up to 2100
ꢀ Binary or BCD representation of time,
calendar, and alarm
DS14285S 24-Pin SOIC
ꢀ 12- or 24-hour clock with AM and PM in
12-hour mode
ꢀ Daylight Savings Time option
ꢀ Multiplex bus for pin efficiency
ꢀ Interfaced with software as 128 RAM
locations
4
3
2
1
28 27 26
25
5
6
7
8
AD0
AD1
AD2
AD3
AD4
AD5
NC
CEI
VBAT
IRQ
RESET
DS
GND
R/W
24
23
22
21
20
19
9
10
11
12 13 14 15 16 17 18
– 14 bytes of clock and control registers
– 114 bytes of general purpose RAM
ꢀ Programmable square wave output signal
DS14285Q 28-Pin PLCC
ꢀ Bus-compatible interrupt signals ( IRQ )
ꢀ Three interrupts are separately software-
maskable and testable
VCC
VCCO
NC
NC
1
24
23
– Time-of-day alarm once/second to
once/day
– Periodic rates from 122 µs to 500 ms
– End of clock update cycle
SQW
CEO
CEI
2
3
4
22
21
AD0
AD1
AD2
NC
5
6
20
19
IRQ
RESET
DS
NC
R/W
AS
AD3
AD4
7
8
18
17
ꢀ Optional industrial temperature version
available DS14285 DIP, SOIC, and PLCC
AD5
AD6
AD7
9
10
16
15
11
12
14
13
GND
CS
DS14287 24-Pin
Encapsulated Package
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080400
DS14285/DS14287
ORDERING INFORMATION
DS14285
RTC Chip; 24-pin DIP
DS14285N
DS14285S
DS14285SN
DS14285Q
DS14285QN
DS14287
RTC Chip; 24-pin DIP; Industrial Temp Range
RTC Chip; 24-pin SOIC
RTC Chip; 24-pin SOIC; Industrial Temp Range
RTC Chip; 28-pin PLCC
RTC Chip; 28-pin PLCC; Industrial Temp Range
RTC Module; 24-pin DIP
PIN DESCRIPTION
AD0-AD7
NC
- Multiplexed Address/Data Bus
- No Connection
MOT
- Bus Type Select (DS14285Q only)
CS
- Chip Select
AS
- Address Strobe
R/ W
DS
- Read/Write Input
- Data Strobe
RESET
- Reset Input
IRQ
- Interrupt Request Output
- Square Wave Output
- +5V Supply
SQW
VCC
GND
VCCO
- Ground
- RAM Power Supply Output
CEI
- RAM Chip Enable In
CEO
X1, X2
VBAT
- RAM Chip Enable Out
- 32.768 kHz Crystal Connections
- +3V Battery Input
DESCRIPTION
The DS14285/DS14287 Real Time Clock with NVRAM Control provides the industry standard DS1287
clock function with the additional feature of providing nonvolatile control for an external SRAM.
Functions include a nonvolatile time-of-day clock, alarm, 100-year calendar, programmable interrupt,
square wave generator, and 114 bytes of nonvolatile static RAM. For the DS14287 a lithium energy
source, quartz crystal, and write protection circuitry are contained within a 24-pin dual in-line package.
The DS14285 requires an external quartz crystal connected to the X1 and X2 pins as well as an external
energy source connected to the VBAT pin. A standard 32.768 kHz quartz crystal can be directly connected
to the DS14285 via pins 1 and 2 (X1, X2). The crystal selected for use should have a specified load
capacitance (CL) of 6 pF. For more information on crystal selection and crystal layout considerations,
please consult Application Note 58, “Crystal Considerations with Dallas Real-time Clocks.”
The DS14285/DS14287 uses its backup energy source and battery-backup controller to make a standard
CMOS static RAM nonvolatile during power-fail conditions. During power fail, the DS14285/DS14287
automatically write-protects the external SRAM and provides a VCC output sourced from its internal
battery.
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DS14285/DS14287
For the DS14287 the internal lithium cell is electrically isolated from the clock and memory when
shipped from the factory. This isolation is removed after the first application of VCC, allowing the lithium
cell to provide data retention to the clock, internal RAM, VCCO and CEO on subsequent power-downs.
Care must be taken after this isolation has been broken to avoid inadvertently discharging the lithium cell
through the VCCO and CEO pins.
OPERATION
The block diagram in Figure 1 shows the pin connections with the major internal functions of the
DS14285/DS14287. The following paragraphs describe the function of each pin.
SIGNAL DESCRIPTIONS
GND, VCC - DC power is provided to the device on these pins. VCC is the +5 volt input.
SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15
internal divider stages of the real time clock. The frequency of the SQW pin can be changed by
programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE
bit in Register B. The SQW signal is not available when VCC is less than 4.25 volts typical.
AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because
address information and data information time-share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the second
portion of the cycle. Address/data multiplexing does not slow the access time of the DS14285/DS14287
since the bus change from address to data occurs during the internal RAM access time. Addresses must be
valid prior to the falling edge of AS/ALE, at which time the DS14285/DS14287 latches the address from
AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or WR
pulses. In a read cycle the DS14285/DS14287 outputs 8 bits of data during the latter portion of the DS or
RD pulses. The read cycle is terminated and the bus returns to a high impedance state as DS transitions
low in the case of Motorola timing or as RD transitions high in the case of Intel timing.
MOT (Mode Select) - The MOT pin offers the flexibility to choose between to bus types. When
connected to VCC, Motorola bus timing is selected. When connected to GND or left disconnected, Intel
bus timing is selected. The pin has an internal pull-down resistance of approximately 20 KΩ. This pin is
on the DS14285Q only.
AS (Address Strobe Input) - A positive going address strobe pulse serves to demultiplex the bus. The
falling edge of AS/ALE causes the address to be latched within the DS14285/DS14287.
DS (Data Strobe or Read Input) - For the DS14285Q the DS/ RD pin has two modes of operation
depending on the level of the MOT pin. When the MOT pin is connected to VCC, Motorola bus timing is
selected. In this mode DS is a positive pulse during the latter portion of the bus cycle and is called Data
Strobe. During read cycles, DS signifies the time that the DS14285Q is to drive the bidirectional bus. In
write cycles the trailing edge of DS causes the DS14285Q to latch the written data. When the MOT pin is
connected to GND, Intel bus timing is selected. In this mode the DS pin is called Read(RD ). RD identifies
the time period when the DS14285Q drives the bus with read data. The RD signal is the same definition
as the Output Enable (OE ) signal on a typical memory.
The DS14285, DS14285S and DS14287 do not have a MOT pin and therefore operate only in Intel bus
timing mode.
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DS14285/DS14287
R/ W (Read/Write Input) - The R/ W pin also has two modes of operation. When the MOT pin is
connected to VCC for Motorola timing, R/ W is at a level which indicates whether the current cycle is a
read or write. A read cycle is indicated with a high level on R/ W while DS is high. A write cycle is
indicated when R/ W is low during DS.
When the MOT pin is connected to GND for Intel timing, the R/ W signal is an active low signal called
WR . In this mode the R/ W pin has the same meaning as the Write Enable signal ( WE ) on generic
RAMs.
CS (Chip Select Input) - The Chip Select signal must be asserted low for a bus cycle in the
DS14285/DS14287 to be accessed. CS must be kept in the active state during DS for Motorola timing
and during RD and WR for Intel timing. Bus cycles which take place without asserting CS will latch
addresses but no access will occur. When VCC is below 4.25 volts, the DS14285/DS14287 internally
inhibits access cycles by internally disabling the CS input. This action protects both the real time clock
data and RAM data during power outages.
IRQ (Interrupt Request Output) - The IRQ pin is an active low output of the DS14285/DS14287 that
can be used as an interrupt input to a processor. The IRQ output remains low as long as the status bit
causing the interrupt is present and the corresponding interrupt-enable bit is set. To clear the IRQ pin the
processor program normally reads the C register. The RESET pin also clears pending interrupts.
When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple
interrupting devices can be connected to an IRQ bus. The IRQ bus is an open drain output and requires an
external pull-up resistor.
RESET (Reset Input) - The RESET pin has no effect on the clock, calendar, or RAM. On power-up the
RESET pin can be held low for a time in order to allow the power supply to stabilize. The amount of time
that RESET is held low is dependent on the application. However, if RESET is used on power-up, the
time RESET is low should exceed 200 ms to make sure that the internal timer that controls the
DS14285/DS14287 on power-up has timed out. When RESET is low and VCC is above 4.25 volts, the
following occurs:
A. Periodic Interrupt Enable (PEI) bit is cleared to 0.
B. Alarm Interrupt Enable (AIE) bit is cleared to 0.
C. Update Ended Interrupt Flag (UF) bit is cleared to 0.
D. Interrupt Request Status Flag (IRQF) bit is cleared to 0.
E. Periodic Interrupt Flag (PF) bit is cleared to 0.
F. The device is not accessible until RESET is returned high.
G. Alarm Interrupt Flag (AF) bit is cleared to 0.
H. IRQ pin is in the high impedance state.
I. Square Wave Output Enable (SQWE ) bit is cleared to 0.
J. Update Ended Interrupt Enable (UIE) is cleared to 0.
K. CEO is driven high.
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DS14285/DS14287
In a typical application RESET can be connected to VCC. This connection will allow the DS14287 to go in
and out of power fail without affecting any of the control registers.
CEI (External RAM Chip Enable Input, active low) - CEI should be driven low to enable the external
RAM. CEI is internally pulled up with a 50kΩ resistor.
CEO (External RAM Chip Enable Output, active low) - When VCC is greater than 4.25 volts (typical),
CEO will reflect CEI provided the RESET is at a logic high. When VCC is less than 4.25 volts (typical),
CEO will be forced to an inactive level regardless of CEI .
VCCO (External RAM Power Supply Output) - VCCO provides the higher of VCC or VBAT through an
internal switch to power an external RAM.
DS14285 Only
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (CL) of 6 pF. The crystal is
connected directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1
and X2 are very high impedance nodes. It is recommended that they and the crystal be guard–ringed with
ground and that high frequency signals be kept away from the crystal area. For more information on
crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal
Considerations with Dallas Real Time Clocks.”
VBAT – Battery input for any standard 3-volt lithium cell or other energy source. See the Power-Up/Down
section for considerations in selecting the size of the external energy source
The battery should be connected directly to the VBAT pin. A diode must not be placed in series with the
battery to the VBAT pin. Furthermore, a diode is not necessary because reverse charging current
protection circuitry is provided internal to the device and has passed the requirements of Underwriters
Laboratories for UL listing.
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DS14285/DS14287
DS14285/DS14287 BLOCK DIAGRAM Figure 1
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DS14285/DS14287
POWER-DOWN/POWER-UP CONSIDERATIONS
The real time clock function will continue to operate and all of the RAM, time, calendar, and alarm
memory locations remain nonvolatile regardless of the level of the VCC input. When VCC is applied to the
DS14285/DS14287 and reaches a level of greater than 4.25 volts (typical), the device becomes accessible
after 200 ms, provided that the oscillator is running and the oscillator countdown chain is not in reset (see
Register A). This time period allows the system to stabilize after power is applied. When VCC falls below
4.25 volts (typical), the chip select input is internally forced to an inactive level regardless of the value of
CS at the input pin. The DS14285/DS14287 is, therefore, write-protected. When the DS14285/DS14287
is in a write-protected state, all inputs are ignored and all outputs are in a high impedance state. When
VCC falls below a level of approximately 3 volts, the external VCC supply is switched off and an internal
lithium energy source supplies power to the Real-time Clock and the RAM memory.
An external SRAM can be made nonvolatile by using the VCCO and SRAM chip enable pins (see Figure
1). Nonvolatile control of the external SRAM is analogous to that of the real time clock registers. When
VCC slews down during a power fail, CEO is driven to an inactive level regardless CEI . This write
protection occurs when VCC is less than 4.25 volts (typical).
During power up, when VCC reaches a level of greater than 4.25 volts (typical), CEO will reflect CEI
after 200 ms. During power-valid operation, the CEI input is passed to the CEO output with a
propagation delay of less than 10 ns.
When VCC is above a level of approximately 3V, the external SRAM will be powered by VCC through the
VCCO pin. When VCC is below a level of approximately 3V, the external SRAM will be powered by the
internal lithium cell through the VCCO pin. An internal comparator and switch determine whether VCCO is
powered by VCC or the internal lithium cell.
When the device is in battery backup mode, the energy source connected to the VBAT pin in the case of
the DS14285, or the internal lithium cell in the case of the DS14287 can power an external SRAM for an
extended period of time. The amount of time that the lithium cell can supply power to the external SRAM
is a function of the data retention current of the SRAM. The capacity of the lithium cell that is
encapsulated within the DS14287 module is 130 mAh. If an SRAM with a data retention current of less
than 1 µA is used and the oscillator current is 300 nA (typical), the cumulative data retention time is
calculated at more than 11 years.
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DS14285/DS14287
RTC ADDRESS MAP
The address map of the DS14285/DS14287 is shown in Figure 2. The address map consists of 114 bytes
of user RAM, 10 bytes of RAM that contain the RTC time, calendar, and alarm data, and 4 bytes which
are used for control and status. All 128 bytes can be directly written or read except for the following:
1. Registers C and D are read-only.
2. Bit 7 of Register A is read-only.
3. The high order bit of the seconds byte is read-only.
The contents of four registers (A,B,C, and D) are described in the “Registers” section.
DS14285/DS14287 ADDRESS MAP Figure 2
TIME, CALENDAR AND ALARM LOCATIONS
The time and calendar information is obtained by reading the appropriate memory bytes. The time,
calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the 10
time, calendar, and alarm bytes can be either Binary or Binary-Coded Decimal (BCD) format. Before
writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a
logic 1 to prevent updates from occurring while access is being attempted. In addition to writing the 10
time, calendar, and alarm registers in a selected format (binary or BCD), the data mode bit (DM) of
Register B must be set to the appropriate logic level. All 10 time, calendar, and alarm bytes must use the
same data mode. The set bit in Register B should be cleared after the data mode bit has been written to
allow the real-time clock to update the time and calendar bytes. Once initialized, the real-time clock
makes all updates in the selected mode. The data mode cannot be changed without reinitializing the 10
data bytes. Table 1 shows the binary and BCD formats of the ten time, calendar, and alarm locations. The
24-12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is
selected, the high order bit of the hours byte represents PM when it is a logic one. The time, calendar,
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DS14285/DS14287
and alarm bytes are always accessible because they are double buffered. Once per second the 10 bytes are
advanced by 1 second and checked for an alarm condition. If a read of the time and calendar data occurs
during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. The probability
of reading incorrect time and calendar data is low. Several methods of avoiding any possible incorrect
time and calendar reads are covered later in this text.
The three alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate
hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day
if the alarm enable bit is high. The second use condition is to insert a “don’t care” state in one or more of
the 3 alarm bytes. The “don’t care” code is any hexadecimal value from C0 to FF. The 2 most significant
bits of each byte set the “don’t care” condition when at logic 1. An alarm will be generated each hour
when the “don’t care” bits are set in the hours byte. Similarly, an alarm is generated every minute with
“don’t care” codes in the hours and minute alarm bytes. The “don’t care” codes in all three alarm bytes
create an interrupt every second.
TIME, CALENDAR AND ALARM DATA MODES Table 1
RANGE
ADDRESS
DECIMAL
RANGE
0-59
FUNCTION
LOCATION
BINARY DATA MODE BCD DATA MODE
00-3B
00-3B
00-3B
00-3B
01-0C AM, 81-8C PM
0
1
2
3
4
Seconds
Seconds Alarm
Minutes
Minutes Alarm
Hours-12-hr Mode
Hours-24-hr Mode
Hours Alarm-12-hr
Hours Alarm-24-hr
Day of the Week
Sunday = 1
00-59
00-59
00-59
00-59
01-12AM, 81-92PM
00-23
01-12AM, 81-92PM
00-23
0-59
0-59
0-59
1-12
0-23
00-17
5
6
1-12
0-23
1-7
01-0C AM, 81-8C PM
00-17
01-07
01-07
7
8
9
Date of the Month
Month
Year
1-31
1-12
0-99
01-1F
01-0C
00-63
01-31
01-12
00-99
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DS14285/DS14287
CONTROL REGISTERS
The DS14285/DS14287 has four control registers which are accessible at all times, even during the
update cycle.
REGISTER A
MSB
LSB
BIT 0
RS0
BIT 7
UIP
BIT 6
DV2
BIT 5
DV1
BIT 4
DV0
BIT 3
RS3
BIT 2
RS2
BIT 1
RS1
UIP - The Update In Progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1, the
update transfer will soon occur. When UIP is a 0, the update transfer will not occur for at least 244 µs.
The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The
UIP bit is read-only and is not affected by RESET . Writing the SET bit in Register B to a 1 inhibits any
update transfer and clears the UIP status bit.
DV0, DV1, DV2 - These 3 bits are used to turn the oscillator on or off and to reset the countdown chain.
A pattern of 010 is the only combination of bits that will turn the oscillator on and allow the RTC to keep
time. A pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next update
will occur at 500 ms after a pattern of 010 is written to DV0, DV1, and DV2.
RS3, RS2, RS1, RS0 - These four rate-selection bits select one of the 13 taps on the 15-stage divider or
disable the divider output. The tap selected can be used to generate an output square wave (SQW pin)
and/or a periodic interrupt. The user can do one of the following:
1. Enable the interrupt with the PIE bit;
2. Enable the SQW output pin with the SQWE bit;
3. Enable both at the same time and the same rate; or
4. Enable neither.
Table 2 lists the periodic interrupt rates and the square wave frequencies that can be chosen with the RS
bits. These 4 read/write bits are not affected by RESET .
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DS14285/DS14287
REGISTER B
MSB
LSB
BIT 0
DSE
BIT 7
SET
BIT 6
PIE
BIT 5
AIE
BIT 4
UIE
BIT 3
SQWE
BIT 2
DM
BIT 1
24/12
SET - When the SET bit is a 0, the update transfer functions normally by advancing the counts once per
second. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize
the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be
executed in a similar manner. SET is a read/write bit that is not modified by RESET or internal functions
of the DS14285/DS14287.
PIE - The periodic interrupt enable PIE bit is a read/write bit which allows the Periodic Interrupt Flag
(PF) bit in Register C to drive the IRQ pin low. When the PIE bit is set to 1, periodic interrupts are
generated by driving the IRQ pin low at a rate specified by the RS3-RS0 bits of Register A. A 0 in the
PIE bit blocks the IRQ output from being driven by a periodic interrupt, but the Periodic Flag (PF) bit is
still set at the periodic rate. PIE is not modified by any internal DS14285/DS14287 functions, but is
cleared to 0 on RESET .
AIE - The Alarm Interrupt Enable (AIE) bit is a read/write bit which, when set to a 1, permits the Alarm
Flag (AF) bit in register C to assert IRQ . An alarm interrupt occurs for each second that the 3 time bytes
equal the 3 alarm bytes including a “don’t care” alarm code of binary 11XXXXXX. When the AIE bit is
set to 0, the AF bit does not initiate the IRQ signal. The RESET pin clears AIE to 0. The internal
functions of the DS14285/DS14287 do not affect the AIE bit.
UIE - The Update Ended Interrupt Enable (UIE) bit is a read/write that enables the Update End Flag (UF)
bit in Register C to assert IRQ . The RESET pin going low or the SET bit going high clears to UIE bit.
SQWE - When the Square Wave Enable (SQWE) bit is set to a 1, a square wave signal at the frequency
set by the rate-selection bits RS3 through RS0 is driven out on a SQW pin. When the SQWE bit is set to
0, the SQW pin is held low; the state of SQWE is cleared by the RESET pin. SQWE is a read/write bit.
DM - The Data Mode (DM) bit indicates whether time and calendar information is in binary or BCD
format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is
not modified by internal functions or RESET . A one in DM signifies binary data while a 0 in DM
specifies Binary Coded Decimal (BCD) data.
24/12 - The 24/12 control bit establishes the format of the hours byte. A 1 indicates the 24-hour mode and
a 0 indicates the 12-hour mode. This bit is read/write and is not affected by internal functions of RESET .
DSE - The Daylight Savings Enable (DSE) bit is a read/write bit which enables two special updates when
DSE is set to 1. On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On
the last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These
special updates do not occur when the DSE bit is a 0. This bit is not affected by internal functions or
RESET .
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DS14285/DS14287
REGISTER C
MSB
LSB
BIT 0
0
BIT 7
IRQF
BIT 6
PF
BIT 5
AF
BIT 4
UF
BIT 3
0
BIT 2
0
BIT 1
0
IRQF - The Interrupt Request Flag (IRQF) bit is set to a 1 when one or more of the following are true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
That is, IRQF = PF •=PIE + AF •=AIE + UF •=UIE.
Any time the IRQF bit is a 1, the IRQ pin is driven low. All flag bits are cleared after Register C is read
by the program or when the RESET pin is low.
PF - The Periodic Interrupt Flag (PF) is a read-only bit which is set to a 1 when an edge is detected on the
selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a 1
independent of the state of the PIE bit. When both PF and PIE are 1s, the IRQ signal is active and will set
the IRQF bit. The PF bit is cleared by a RESET or a software read of Register C.
AF - A 1 in the Alarm Interrupt Flag (AF) bit indicates that the current time has matched the alarm time.
If the AIE bit is also a 1, the IRQ pin will go low and a one will appear in the IRQF bit. A RESET or a
read of Register C will clear AF.
UF - The Update Ended Interrupt Flag (UF) bit is set after each update cycle. When the UIE bit is set to
1, the 1 in UF causes the IRQF bit to be a 1 which will assert the IRQ pin. UF is cleared by reading
Register C or a RESET .
BIT 0 THROUGH BIT 3 - These are unused bits of the status Register C. These bits always read 0 and
cannot be written.
REGISTER D
MSB
LSB
BIT 0
BIT 7
VRT
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
0
VRT - The Valid RAM and Time (VRT) bit indicates the condition of the internal battery (the battery
connected to the VBAT pin in the case of the DS14285S, DS14285, and the DS14285Q). This bit is not
writable and should always be a 1 when read. If a 0 is ever present, an exhausted internal lithium energy
source is indicated and both the contents of the RTC data and RAM data are questionable. This bit is
unaffected by RESET .
BIT 6 THROUGH BIT 0 - The remaining bits of Register D are not usable. They cannot be written and,
when read, they will always read 0.
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DS14285/DS14287
NONVOLATILE RAM
The 114 general purpose nonvolatile RAM bytes are not dedicated to any special function within the
DS14285/DS14287. They can be used by the processor program as nonvolatile memory and are fully
available during the update cycle.
The DS14285/DS14287 can also provide additional nonvolatile RAM. This is accomplished through the
use of its internal lithium cell in the case of the DS14287 (or the energy source connected to the VBAT pin
in the case of the DS14285) and battery-backup controller to make a standard CMOS SRAM nonvolatile
during power-fail conditions. During power-fail, the DS14285/DS14287 automatically write-protects the
external SRAM and provides a VCC output sourced from the internal lithium cell. The interface between
the DS14285/DS14287 and an external SRAM is illustrated in Figure 3.
EXTERNAL SRAM INTERFACE TO THE DS14285/DS14287 RTC Figure 3
INTERRUPTS
The RTC plus RAM includes three separate, fully automatic sources of interrupt for a processor. The
alarm interrupt can be programmed to occur at rates from once per second to once per day. The periodic
interrupt can be selected for rates from 500 ms to 122 µs. The update-ended interrupt can be used to
indicate to the program that an update cycle is complete. Each of these independent interrupt conditions is
described in greater detail in other sections of this text.
The processor program can select which interrupts, if any, are going to be used. Three bits in Register B
enable the interrupts. Writing a logic 1 to an interrupt-enable bit permits that interrupt to be initiated when
the event occurs. A 0 in an interrupt-enable bit prohibits the IRQ pin from being asserted from that
interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is immediately set
at an active level, although the interrupt initiating the event may have occurred much earlier. As a result,
there are cases where the program should clear such earlier initiated interrupts before first enabling new
interrupts. When an interrupt event occurs, the relating flag bit is set to logic 1 in Register C. These flag
bits are set independent of the state of the corresponding enable bit in Register B. The flag bit can be used
in a polling mode without enabling the corresponding enable bits. The interrupt flag bit is a status bit
which software can interrogate as necessary. When a flag is set, an indication is given to software that an
interrupt event has occurred since the flag bit was last read; however, care should be taken when using the
flag bits as they are cleared each time Register C is read. Double latching is included with Register C so
13 of 25
DS14285/DS14287
that bits which are set remain stable throughout the read cycle. All bits which are set (high) are cleared
when read and new interrupts which are pending during the read cycle are held until after the cycle is
completed. One, 2, or 3 bits can be set when reading Register C. Each utilized flag bit should be
examined when read to ensure that no interrupts are lost.
The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is set and the
corresponding interrupt enable bit is also set, the IRQ pin is asserted low. IRQ is asserted as long as at
least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is
a one whenever the IRQ pin is being driven low. Determination that the RTC initiated an interrupt is
accomplished by reading Register C. A logic one in bit 7 (IRQF bit) indicates that one or more interrupts
have been initiated by the DS14285/DS14287. The act of reading Register C clears all active flag bits and
the IRQF bit.
PERIODIC INTERRUPT SELECTION
The periodic interrupt will cause the IRQ pin to go to an active state from once every 500 ms to once
every 122 µs. This function is separate from the alarm interrupt which can be output from once per
second to once per day. The periodic interrupt rate is selected using the same Register A bits which select
the square wave frequency (see Table 2). Changing the Register A bits affects both the square wave
frequency and the periodic interrupt output. However, each function has a separate enable bit in Register
B. The SQWE bit controls the square wave output. Similarly, the periodic interrupt is enabled by the PIE
bit in Register B. The periodic interrupt can be used with software counters to measure inputs, create
output intervals, or await the next needed software function.
OSCILLATOR CONTROL BITS
When the DS14287 is shipped from the factory, the internal oscillator is turned off. This feature prevents
the lithium energy cell from being used until it is installed in a system. A pattern of 010 in bits 4 through
6 of Register A will turn the oscillator on and enable the countdown chain. A pattern of 11X will turn the
oscillator on, but holds the countdown chain of the oscillator in reset. All other combinations of bits 4
through 6 keep the oscillator off.
SQUARE WAVE OUTPUT SELECTION
Thirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the block diagram of
Figure 1. The first purpose of selecting a divider tap is to generate a square wave output signal on the
SQW pin. The RS0-RS3 bits in Register A establish the square wave output frequency. These
frequencies are listed in Table 2. The SQW frequency selection shares its 1-of-15 selector with the
periodic interrupt generator. Once the frequency is selected, the output of the SQW pin can be turned on
and off under program control with the square wave enable bit (SQWE).
14 of 25
DS14285/DS14287
PERIODIC INTERRUPT RATE AND
SQUARE WAVE OUTPUT FREQUENCY Table 2
SELECT BITS REGISTER A
tPI PERIODIC
INTERRUPT RATE
None
SQW OUTPUT
FREQUENCY
None
RS3
0
RS2
0
RS1
0
RS0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
3.90625 ms
7.8125 ms
122.070 µs
244.141 µs
488.281 µs
976.5625 µs
1.953125 ms
3.90625 ms
7.8125 ms
15.625 ms
31.25 ms
256 Hz
128 Hz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
512 Hz
256 Hz
128 Hz
64 Hz
1
1
1
0
0
0
0
1
1
1
0
1
32 Hz
1
1
0
0
62.5 ms
16 Hz
1
1
0
1
125 ms
8 Hz
1
1
1
0
250 ms
4 Hz
1
1
1
1
500 ms
2 Hz
UPDATE CYCLE
The DS14285/DS14287 executes an update cycle once per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar, and
alarm bytes is frozen and will not update as the time increments. However, the time countdown chain
continues to update the internal copy of the buffer. This feature allows time to maintain accuracy
independent of reading or writing the time, calendar, and alarm buffers and also guarantees that time and
calendar information is consistent. The update cycle also compares each alarm byte with the
corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all three
positions.
There are three methods that can handle access of the real-time clock that avoid any possibility of
accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If
enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read
valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared
before leaving the interrupt routine.
A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in
progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs
244 µs later. If a low is read on the UIP bit, the user has at least 244 µs before the time/calendar data will
be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed
to read valid time/calendar data to exceed 244 µs.
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (see Figure 4). Periodic interrupts
that occur at a rate of greater than tBUC allow valid time and date information to be reached at each
occurrence of the periodic interrupt. The reads should be complete within 1 (tPI/ + tBUC) to ensure that
2
data is not read during the update cycle.
15 of 25
DS14285/DS14287
UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 4
16 of 25
DS14285/DS14287
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Storage Temperature
-0.5V to +7.0V
-40°C to +85°C
Soldering Temperature
DIP: 260°C for 10 seconds (See Note 12)
See IPC/JEDEC Standard J-STD-020A for Surface Mount
Devices
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
Operating Range
Range
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
Vcc
5V ±10%
5V ±10%
RECOMMENDED DC OPERATING CONDITIONS Over the operating range
PARAMETER
Power Supply Voltage
Battery Voltage
Input Logic 1
SYMBOL
VCC
MIN
4.5
2.5
2.2
-0.3
TYP
5.0
MAX
5.5
3.6
VCC+0.3
+0.8
UNITS NOTES
V
V
V
V
1
1
1
1
Vbat
VIH
VIL
Input Logic 0
DC ELECTRICAL CHARACTERISTICS Over the operating range
PARAMETER
Power Supply Current
Oscillator Current
Input Leakage
SYMBOL
ICC1
MIN
TYP
7
300
MAX
15
500
+1.0
+1.0
+500
200
UNITS NOTES
mA
nA
µA
µA
µA
µA
2
IOSC
IIL
-1.0
-1.0
-1.0
-1.0
3
5
3
4
I/O Leakage
ILO
MOT Input Current
IMOT
I
CEI
CEI Input Current
ZCE
60
11
Ω
CEI to CEO Impedance
Output @ 2.4V
Output @ 0.4V
Write-Protect Voltage
VCCO Voltage
VCCO Voltage
IOH
IOL
VTP
VCCO1
VCCO2
-1.0
mA
mA
V
V
V
1, 6
1
4.0
4.5
4.0
VCC-0.3V
VBAT-0.3V
4.25
7
8
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
(tA = 25°C)
SYMBOL
CIN
MIN
TYP
MAX
UNITS NOTES
5
7
pF
pF
COUT
17 of 25
DS14285/DS14287
AC ELECTRICAL CHARACTERISTICS Over the operating range
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
Cycle
tCYC
PWEL
225
115
DC
ns
ns
Pulse Width, DS/E Low or RD/ WR
High
PWEH
80
ns
Pulse Width, DS/E Low or RD/ WR
Low
Input Rise and Fall Time
tR, tF
tRWH
30
50
ns
ns
10
10
20
R/ W Hold Time
tRWS
tCS
ns
ns
R/ W Setup Time Before DS/E
Chip Select Setup Time Before DS,
WR , or RD
Chip Select Hold Time
Read Data Hold Time
Write Data Hold Time
Muxed Address Valid Time to AS/ALE
Fall
tCH
tDHR
tDHW
tASL
0
10
0
ns
ns
ns
ns
30
Muxed Address Hold Time
Delay Time DS/E to AS/ALE Rise
Pulse Width AS/ALE High
Delay Time, AS/ALE to DS/E Rise
Output Data Delay Time From DS/E or
tAHL
tASD
PWASH
tASED
tDDR
10
20
60
35
10
ns
ns
ns
ns
75
ns
9
RD
Data Setup Time
Reset Pulse Width
tDSW
tRWL
tIRDS
60
5
ns
µs
µs
2
2
IRQ Release from DS
tIRR
µs
IRQ Release from RESET
AC TEST CONDITIONS
Input Pulse Level: 0 to 3.0V
Input Rise/Fall Times: 5 ns
Input and Output Timing Reference Levels: 1.5V
OUTPUT LOAD Figure 5
18 of 25
DS14285/DS14287
DS14285 BUS TIMING FOR MOTOROLA INTERFACE
DS14285/DS14287 BUS TIMING FOR INTEL INTERFACE WRITE CYCLE
19 of 25
DS14285/DS14287
DS14285/DS14287 BUS TIMING FOR INTEL INTERFACE READ CYCLE
DS14285/DS14287 IRQ RELEASE DELAY TIMING
20 of 25
DS14285/DS14287
POWER-DOWN/POWER-UP TIMING
POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
tPD
0
µs
CS at VIH before Power-Down
VCC slew from 4.5V to 0V (CS at VIH)
VCC slew from 0V to 4.5V (CS at VIH)
tF
300
100
20
µs
µs
ms
ns
tR
tREC
tCED
200
10
CS at VIH after Power-Up
Chip Enable Propagation Delay to
External SRAM
(tA = 25°C)
PARAMETER
Expected Data Retention for DS14287
SYMBOL MIN
tDR 10
TYP
MAX
UNITS NOTES
years
10
NOTE:
The real-time clock will keep time to an accuracy of+1 minute per month during data retention time for
the period of tDR.
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
21 of 25
DS14285/DS14287
NOTES:
1. All voltages are referenced to ground.
2. All outputs are open.
3. The MOT pin has an internal pull-down of 20 kΩ.
4. The CEI pin has an internal pull-up of 50 kΩ.
5. Applies to the AD0-AD7 pins, the IRQ pin, and the SQW pin when each is in the high impedance
state.
6. The IRQ pin is open drain. The interrupt and the internal clock continue to run regardless of the level
of VCC. However, it is important to insure that the pullup resistor used with the interrupt pin is never
pulled up to a value which is greater than VCC + 0.3V. As VCC falls below approximately 3.0 volts,
a power switching circuit turns the lithium energy source on to maintain the clock and timer data
functionality.
7. ICCO =100 mA, VCC > VBAT
.
8. ICCO =100 µA, VCC < VBAT
.
9. Measured with a load as shown in Figure 5.
10. Expected data retention is based on using an external SRAM with a data retention current of less than
1 µA at 25°C.
11. ZCE is an average input-to-output impedance as the input is swept from ground to VCCI and less than 4
mA is forced through ZCE.
12. Real-Time Clock Modules such as the DS14287 can be successfully processed through conventional
wave-soldering techniques as long as temperature exposure to the lithium energy source contained
within does not exceed +85°C. Post-solder cleaning with water washing techniques is acceptable,
provided that ultrasonic vibration is not used.
22 of 25
DS14285/DS14287
DS14285 24-PIN DIP
PKG
DIM
24-PIN
MIN
MAX
A IN.
MM
B IN.
MM
C IN.
MM
1.245
31.62
0.530
13.46
0.140
3.56
1.270
32.25
0.550
13.97
0.160
4.06
D IN.
MM
E IN.
MM
F IN.
MM
0.600
15.24
0.015
0.380
0.120
3.05
0.625
15.88
0.050
1.27
0.145
3.68
G IN.
MM
0.090
2.29
0.110
2.79
H IN.
MM
J IN.
MM
0.625
15.88
0.008
0.20
0.675
17.15
0.012
0.30
K IN.
MM
0.015
0.38
0.022
0.56
DS14285 24-PIN SOIC
PKG
DIM
24-PIN
MIN
MAX
A IN.
MM
B IN.
MM
0.602
15.29
0.290
7.37
0.612
15.54
0.300
7.65
C IN.
MM
0.089
2.26
0.095
2.41
E IN.
MM
F IN.
MM
0.004
0.102
0.094
2.38
0.012
0.30
0.105
2.68
G IN.
MM
0.050 BSC
1.27 BSC
H IN.
MM
J IN.
MM
K IN.
MM
0.398
0.416
10.57
0.013
0.33
0.019
0.48
10.11
0.009
0.229
0.013
0.33
L IN.
MM
0.016
0.406
0.040
1.02
phi
0°
8°
23 of 25
DS14285/DS14287
DS14285Q 28-PIN PLCC
PKG
DIM
A
A1
A2
B
B1
C
D
D1
D2
E
E1
E2
L1
N
28-PIN
MIN
MAX
0.180
0.120
-
0.165
0.090
0.020
0.026
0.013
0.009
0.485
0.450
0.390
0.485
0.450
0.390
0.060
28
0.033
0.021
0.012
0.495
0.456
0.430
0.495
0.456
0.430
-
-
e1
CH1
0.050 BSC
0.042
0.048
24 of 25
DS14285/DS14287
DS14287 REAL-TIME CLOCK PLUS RAM
PKG
DIM
24-PIN
NOTE:
PINS 2, 3, 16, AND 20 ARE MISSING BY DESIGN.
MIN
MAX
A IN.
MM
B IN.
MM
C IN.
MM
1.320
33.53
0.720
18.29
0.345
8.76
1.335
33.91
0.740
18.80
0.370
9.40
D IN.
MM
0.100
2.54
0.130
3.30
E IN.
MM
0.015
0.38
0.030
0.76
F IN.
MM
0.110
2.79
0.140
3.56
G IN.
MM
0.090
2.29
0.110
2.79
H IN.
MM
J IN.
MM
0.590
14.99
0.008
0.20
0.630
16.00
0.012
0.30
K IN.
MM
0.015
0.38
0.021
0.53
25 of 25
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