DS1682_13 [DALLAS]
Total-Elapsed-Time Recorder with Alarm; 总-经过时间记录与报警
| 型号： | DS1682_13 |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Total-Elapsed-Time Recorder with Alarm |
| 文件： | 总14页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1682
Total-Elapsed-Time Recorder
with Alarm
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS1682 is an integrated elapsed-time recorder
.
Records the Total Time that the Event Input has
Been Active and the Number of Events that have
Occurred
containing
a
factory-calibrated, temperature-
compensated RC time base that eliminates the need
for an external crystal. Using EEPROM technology
to maintain data in the absence of power, the DS1682
requires no backup power source. The DS1682
detects and records the number of events on the
EVENT pin and the total cumulative event time since
the DS1682 was last reset to 0. The ALARM pin
alerts the user when the total time accumulated
equals the user-programmed alarm value. The
polarity of the open-drain ALARM pin can be
programmed to either drive low or to become high
impedance upon an alarm condition. The DS1682 is
ideal for applications that monitor the total amount of
time that a device has been in operation and/or the
number of uses since inception of service, repair, or
the last calibration.
.
32-Bit, Nonvolatile, Elapsed Time Counter
(ETC) Monitors Event Duration with Quarter-
Second Resolution and Provides 34 Years of
Total Time Accumulation
.
.
Programmable Elapsed Time ALARM Output
Nonvolatile 17-Bit Event Counter Records the
Total Number of Times an Event has Occurred
.
Calibrated, Temperature-Compensated RC Time
Base Accurate to 2% Typical
.
.
10 Bytes of EEPROM User Memory
Write Disable Function to Prevent the Memory
from Being Changed or Erased
.
.
.
2-Wire Serial Communication
APPLICATIONS
High-Temp, Rugged, Industrial Applications Where
Vibration or Shock Could Damage a Quartz
Crystal
Wide 2.5V to 5.5V Power-Supply Range
Useful in Time-of-Use Warranty, Calibration,
Repair, and Maintenance Applications
Any System Where Time-of-Use is Important
(Warranty Tracking)
PIN CONFIGURATION
TOP VIEW
ORDERING INFORMATION
TOP
1
EVENT
N.C.
8
7
VCC
PART*
PIN-PACKAGE
MARK†
DS1682
DS1682
DS1682
DS1682
DS1682
N.C.
2
3
4
DS1682S
DS1682S+
DS1682S/T&R
DS1682S+T&R
8 SO
8 SO
8 SO (Tape and Reel)
8 SO (Tape and Reel)
6
5
SDA
SCL
ALARM
GND
SO
(150 mils)
* All devices are specified over the -40°C to +85°C operating
range.
† A “‘+” anywhere on the top mark denotes a lead(Pb)-free device.
+ Denotes a lead(Pb)-free/RoHS-compliant device.
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REV: 081005
DS1682 Total-Elapsed-Time Recorder with Alarm
Figure 1. DS1682 Block Diagram
SCL
SDA
SERIAL
INTERFACE
Dallas
Semiconductor
USER, CONTROL, AND
CONFIGURATION
REGISTERS
OSCILLATOR
AND
DIVIDER
ELAPSED TIME
COUNTER (ETC)
EEPROM ARRAY
ALARM REGS
AND
COMPARE LOGIC
VCC
CONTROL
LOGIC
AND
EVENT
ALARM
EVENT
GLITCH
FILTER
EVENT COUNTER
PIN DESCRIPTION
PIN
NAME
FUNCTION
Event Input. The EVENT pin is the input the DS1682 monitors to determine when
an event occurs. When the pin is pulled high, the contents of the EEPROM are
transferred to the ETC and the oscillator starts. The ETC begins to count in quarter-
second increments. When the EVENT pin falls to logic 0, the event counter
increments, and the event counter, ETC, and user-memory data are stored in the
EEPROM array. When the EVENT pin changes states, the 2-wire bus is
unavailable for communications for tEW (falling) and tER (rising). The EVENT input
is also deglitched (tG) to prevent short noise spikes from triggering an event.
1
EVENT
2, 7
3
N.C.
No Connect. This pin is not connected internally.
Active-Low Alarm Output. The DS1682 monitors the values in the ETC for the
programmed value in the alarm register. When the ETC matches the alarm value,
ALARM the alarm flag (AF) is set. Once set, the alarm flag cannot be reset. See the
operating descriptions for the AOS and AP bits for details about the operation of
the ALARM pin.
4
5
GND
Ground
2-Wire Serial-Clock Input. The SCL pin is the serial-clock input for the 2-wire
synchronous communications channel. The SCL pin is an input that requires an
external pullup resistor.
SCL
2-Wire Input/Output. The SDA pin is the data input/output signal for the 2-wire
synchronous communications channel. The SDA pin is an open-drain I/O, which
requires an external pullup resistor.
6
8
SDA
VCC
+2.5V to +5.5V Input Supply
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DS1682 Total-Elapsed-Time Recorder with Alarm
OPERATION
The block diagram in Figure 1 shows the relationship between the major functional blocks, the serial
interface, and the EEPROM memory section of the DS1682. Upon power-up, the DS1682 transfers the
contents of the EEPROM into the counters and memory registers where the data can be read and written
through the serial interface. The content of the counters and memory registers are written into the
EEPROM memory when the EVENT pin transitions from a logic high to a logic low.
The DS1682 uses a calibrated, temperature-compensated RC time base to increment an ETC while an
event is active. When the event becomes active, the contents of the nonvolatile EEPROM are transferred
to the ETC and event counter and the oscillator starts. As the event continues, the ETC is incremented in
quarter-second increments. When the event becomes inactive, the event counter is incremented and the
contents of the ETC and event counter are written to the nonvolatile EEPROM.
The ALARM output can be used to indicate when the ETC has matched the value in the alarm register.
The DS1682 can be configured to prevent clearing the alarm and the elapsed time and event counters.
The user memory can be separately write-protected.
User-modified data is not stored in EEPROM until an event becomes inactive.
Figure 2 shows the DS1682 measuring total run time and operating from a battery with the alarm tied to
an LED and a pushbutton switch to trigger the alarm output.
Figure 2. Total Run Time
Figure 3 shows the DS1682 in a total time-of-use application where power may be removed at the same
time as the end of the event. The VCC slew rate at power-down is fast with respect to tEW. A capacitor
maintains VCC on the DS1682 above 2.5V until the EEPROM write completes. A Schottky diode blocks
current from the capacitor to other devices connected to VCC.
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DS1682 Total-Elapsed-Time Recorder with Alarm
The VCC holding capacitor value of 30μF is calculated using the maximum EEPROM write current and
EEPROM write time. This assumes that the VCC slew rate allows time from EVENT trip point to VCC at
2.5V on the DS1682 is at least tEW.
Figure 4 shows the DS1682 in a total time-of-use application with power that can be removed at the same
time as the end of the event. In this application, the VCC slew rate at power-down is slow with respect to
tEW. The external RST IC ends the event as VCC begins to drop. VCC must remain above 2.5V until the
end of tEW.
Figure 3. Total Time-of-Use Application with Fast VCC Slew Rate
Figure 4. Total Time-of-Use Application with Slow VCC Slew Rate
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DS1682 Total-Elapsed-Time Recorder with Alarm
Table 1. Memory Map
ADDR BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2 BIT 1
RE AP
BIT 0
FUNCTION
Configuration
Register
00
0
AF
WDF
WMDF
AOS
ECMSB
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Low Byte
Low-Middle Byte
High-Middle Byte
High Byte
Low Byte
Low-Middle Byte
High-Middle Byte
High Byte
Low Byte
High Byte
Byte 1
Alarm Register
Elapsed Time
Counter (ETC)
Event Counter
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
User Memory
Byte 10
Not Used (reads 00h)
Not Used
Reset Command
Write Disable
Write Memory Disable
Reset Command
Write Disable
Memory Disable
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DS1682 Total-Elapsed-Time Recorder with Alarm
EVENT LOGGING
When the DS1682 is powered up, the event time and count values recorded in the EEPROM are
transferred to the ETC and event counter, and the device waits for an event. When an event triggers the
input by transitioning the EVENT pin from a low to a high level, the following occurs:
1) The RC oscillator starts.
2) The alarm, ETC, and event counter are transferred from EEPROM to RAM.
3) Note: Reading the RAM during the transfer results in invalid data.
4) After tES, the ETC increments. An event greater than tG but less than tES increments the event counter
but not the ETC (zero-length event).
5) The ETC increments every TEI. The ETC holds time in quarter-second resolution.
6) When the EVENT pin goes low, the event counter increments, the oscillator stops, and the ETC and
event counter are transferred to EEPROM. The 2-wire bus is not available for tEW.
The ETC stops counting and does not roll over once FFFFFFFFh, or approximately 34 years, is reached.
See Figure 5 for timing.
Figure 5. Event Input Timing
DEVICE SETUP
Once installed in a system, the DS1682 can be programmed to record events as required by the
application, and can be tested by generating events and monitoring the results. Afterwards, it can be
“locked” to prevent alteration of the event and alarm registers and the alarm condition.
The following is a typical sequence:
1) Write the configuration register, alarm registers, and user memory to the desired values.
2) Write-protect the alarm, ETC, and event counter registers with the write disable command if needed.
3) Write-protect the user memory with the write-memory-disable command, if needed.
4) Issue a reset (described in the Reset Command section).
The alarm, ETC and event counter registers, and user memory, once locked, cannot be changed.
Upon reset, the ETC and event counter registers are cleared. The device clears the RE bit, and the
configuration register becomes read-only. Additional resets are ignored.
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DS1682 Total-Elapsed-Time Recorder with Alarm
ALARM
The alarm register is a 32-bit register that holds time in quarter-second resolution. When a nonzero
number is programmed into the alarm register, the ALARM function is enabled and the DS1682 monitors
the values in the ETC for the programmed value in the alarm register. When the ETC matches the alarm
value, the alarm flag is set.
EEPROM ARRAY
When power is applied, the contents of the EEPROM are transferred to the configuration register, alarm
register, ETC, event counter, and user memory. When the event pin goes low, VCC must remain above
VCC minimum for tEW to ensure the EEPROM is properly written.
The EEPROM array for the ETC and the event counter is made up of three banks. Each bank can be
written a maximum of 50k times. The device switches between banks based upon the value in the event
counter. Resetting the event counter before the counter reaches 50,000 will cause additional writes to the
first bank, which can allow writes in excess of 50k. If the event counter is set to greater than 50k or 100k
prior to reset, the device stays on the selected bank. This could result in writes in excess of 50k to one
bank.
The configuration and alarm registers and the user memory are held in one bank of EEPROM. Writes at
the end of an event only occur if the data has changed in one or more of those registers.
User-modified data in any of the registers is stored in EEPROM only if the data was written while an
event was active and is stored when the event ends.
EVENT COUNTER REGISTER
This 17-bit event counter register set provides the total number of data samples logged during the life of
the product up to 131,072 separate events. The event counter consists of 2 bytes of memory in the
memory map plus the event counter MSB bit (ECMSB) in the configuration register. Once the event
counter reaches 1FFFFh, event counting stops.
RESET COMMAND
If RE is set to a 1, a reset occurs when a reset command is sent through the 2-wire bus. A reset command
is issued by writing 55h twice into memory location 1Dh. The writes need not be consecutive. Cycling
power on VCC prior to the second write terminates the reset sequence.
Upon reset, the ETC and event counter registers are cleared. The AF, RE, and ECMSB bits are cleared by
the device, and the configuration register becomes read-only. The data are written to the EEPROM, and
additional resets are ignored.
When a reset command is issued, no additional command should be issued during the EEPROM write
time (tEW).
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DS1682 Total-Elapsed-Time Recorder with Alarm
CONFIGURATION REGISTER
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
AF
WDF
WMDF
AOS
RE
AP
ECMSB
Note: The configuration register is not stored in EEPROM until an event becomes inactive. RE does not need to be
stored in EEPROM to reset the device.
Bit 6: Alarm Flag (AF). The alarm flag is set to a 1 when the ETC value matches the alarm register.
Once the AF bit is set to a 1, it cannot be set to a 0. This bit is read-only.
Bit 5: Write Disable Flag (WDF). When the write disable command is written to AAh twice at memory
location 1Eh, the WDF is set to a 1 and cannot be cleared or reset. When WDF is set to a 1, the alarm,
ETC, and event counter registers are read-only. This bit is read-only. The writes need not be consecutive.
Cycling power on VCC prior to the second write terminates the reset sequence.
Bit 4: Write-Memory-Disable Flag (WMDF). When the write-memory-disable command is written to
F0h twice at memory location 1Fh, the WMDF is set to a 1 and cannot be reset or cleared. Once the
WMDF is set to a 1, the 10-byte user memory becomes read-only. This bit is read-only. The writes need
not be consecutive. Cycling power on VCC prior to the second write terminates the reset sequence.
Bit 3: Alarm Output Select (AOS). If AOS is 0 and AF is true, the DS1682 activates the ALARM
output during an event when AF becomes true. The DS1682 also activates the ALARM output by pulling
the pin low four times at power-up, at the start and end of an event, or when the ALARM pin is pulled
low and released. This output mode can be used to flash an LED or to communicate with another device
to indicate that an alarm has occurred. AP has no affect on the output when AOS is 0.
If AOS is a 1 and AF is true, the ALARM output is constant when the alarm is active. AP determines the
polarity of the output.
Bit 2: Reset Enable (RE). The reset enable bit allows the device to be reset by enabling the reset
command. The sections of the DS1682 that are reset are then dependent on the value in the WDF. With
the WDF set to 0 and the reset enable bit set to a 1, the reset command clears the ETC, EEPROM, and
event counter. When the reset enable bit is set to a 0, the reset command is disabled.
Bit 1: Alarm Polarity (AP). When the alarm polarity bit in the configuration register is set to 0, the
ALARM output is high impedance during the period that the value in the ETC is less than the alarm
register value. When the ETC matches the alarm value, the ALARM pin is driven low. If the AP bit is set
to a 1, the ALARM output is driven low during the period that the ETC is less than the alarm value.
When the ETC matches the alarm value, the ALARM pin becomes high impedance. The AP bit has no
affect if AOS is set to a 0.
Bit 0: Event Counter MSB (ECMSB). This bit is read-only.
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DS1682 Total-Elapsed-Time Recorder with Alarm
USER MEMORY
There are 10 bytes of user-programmable, EEPROM memory. Once the write-memory disable flag is set
to 1, the memory becomes read-only. User memory is not stored in EEPROM until an event becomes
inactive.
2-WIRE SERIAL DATA BUS
The DS1682 supports a bidirectional, 2-wire bus and data-transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device receiving data, a receiver. The device that controls
the message is called a master, and the devices controlled by the master are slaves. A master device that
generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions
must control the bus. The DS1682 operates as a slave on the 2-wire bus. Connections to the bus are made
through the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 6):
.
.
Data transfer can be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy: Both data and clock lines remain high.
Start Data Transfer: A change in the state of the data line, from high to low, while the clock is high,
defines a START condition.
Stop Data Transfer: A change in the state of the data line, from low to high, while the clock line is high,
defines the STOP condition.
Data Valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the high period of the clock signal. The data on the line must be changed
during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions are not limited, and are
determined by the master device. The information is transferred byte-wise and each receiver
acknowledges with a ninth bit. Within the bus specifications a standard mode (100kHz clock rate) and a
fast mode (400kHz clock rate) are defined.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after it
receives each byte. The master device must generate an extra clock pulse, which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of
course, setup and hold times must be considered. A master must signal an end-of-data to the slave by not
9 of 14
DS1682 Total-Elapsed-Time Recorder with Alarm
generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the
slave must leave the data line high to enable the master to generate the STOP condition.
Depending upon the state of the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each
received byte.
Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the
slave address). The slave then returns an acknowledge bit. Next follows a number of data bytes
transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes
other than the last byte. A “not acknowledge” is returned at the end of the last received byte.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus is not released.
Figure 6. Timing Diagram: Data Transfer on 2-Wire Serial Bus
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DS1682 Total-Elapsed-Time Recorder with Alarm
The DS1682 can operate in the following two modes:
Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After
each byte is received, the receiver transmits an acknowledge bit. START and STOP conditions are
recognized as the beginning and end of a serial transfer. The slave address byte is the first byte received
after the master generates a START condition. The address byte contains the 7-bit DS1682 address,
which is 1101011, followed by the direction bit (R/W). The second byte from the master is the register
address. This sets the register pointer. The master then transmits each byte of data, with the DS1682
acknowledging each byte received. The register pointer increments after each byte is written. The master
generates a STOP condition to terminate the data write (Figure 7).
Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver
mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data
is transmitted on SDA by the DS1682 while the serial clock is input on SCL. The slave address byte is the
first byte received after the master generates a START condition. The address byte contains the 7-bit
DS1682 address, followed by the direction bit (R/W). After receiving a valid slave address byte and
direction bit, the DS1682 generates an acknowledge on the SDA line. The DS1682 begins to transmit
data on each SCL pulse starting with the register address pointed to by the register pointer. As the master
reads each byte, it must generate an acknowledge. The register pointer increments after each byte is read.
The DS1682 must receive a “not acknowledge” on the last byte to end a read (Figure 8).
Figure 7. Data Write—Slave Receiver Mode
SLAVE
ADDRESS
R/W
REGISTER
ADDRESS
DATA (n + x)
DATA (n)
DATA (n + 1)
1101011
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
S
0 A
A
A
A
P
DATA TRANSFERRED
S–START
(X + 1 BYTES + ACKNOWLEDGE)
A –ACKNOWLEDGE
P– STOP
R/W –READ/WRITE OR DIRECTION BIT
Figure 8. Data Read—Slave Transmitter Mode
SLAVE
ADDRESS
DATA (n + 2)
DATA (n + x)
DATA (n + 1)
DATA (n)
R/W
1101011
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX /A
S
1 A
A
A
A
DATA TRANSFERRED
S—START
(X + 1 BYTES + ACKNOWLEDGE)
A—- ACKNOWLEDGE
P—- STOP
/A — NOT ACKNOWLEDGE
R/W — READ/WRITE OR DIRECTION BIT
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DS1682 Total-Elapsed-Time Recorder with Alarm
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground…….…………………………………………-0.3V to +6V
Operating Temperature Range……………………………………………….……………..-40°C to +85°C
Storage Temperature Range…………………………………………………..…………...-55°C to +125°C
Soldering Temperature………………………………………….See IPC/JEDEC J-STD-020 Specification
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in
the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods of time can affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Power-Supply Voltage
VCC
2.5
5.5
V
V
%
0.3 x
VCC
1% of
VCC
0.5 x
VCC
0.7 x
VCC
Input Trip Point
VETP
VHYS
Event Trip-Point Hysteresis
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.5V to 5.5V, TA = -40C to +85C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Input Leakage
ILI
-1
+1
0.8
0.8
A
V
ALARM Output (IOL = 10mA)
VOL
VOL
SDA Output (IOL = 4mA)
V
Active Supply Current
(Event Active)
ICCA
(Note 1)
120
300
A
VCC = 5.5V
VCC = 3.0V
(Note 1)
6
2
15
4
Standby Current
(Event Inactive) (Note 1)
ICCS
IEE
A
A
EEPROM Write Current
150
300
EVENT TIMING
(VCC = 2.5V to 5.5V, TA = -40C to +85C.)
PARAMETER
Time Event Minimum
Time Event Start
SYMBOL
CONDITIONS
MIN
10
TYP
35
MAX UNITS
tG
tES
tEI
(Note 1)
70
137
262.5
34
ms
ms
(Note 1)
(Note 1)
112
125
250
Time Event Increment
Time Event Max
237.5
ms
tEM
years
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DS1682 Total-Elapsed-Time Recorder with Alarm
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.5V to 5.5V, TA = -40°C to +85°C.)
PARAMETER
EEPROM Endurance
EEPROM Write Time
EEPROM Transfer to RAM
SYMBOL
CONDITIONS
(Note 2)
(Notes 1, 3, 4)
(Notes 1, 5)
MIN
TYP
MAX
50k
300
UNITS
writes
ms
EE
tEW
tER
150
1
ms
ALARM Output Active-
Low Pulse Width
tSL
tSH
tSPL
fSCL
(Note 1)
(Note 1)
(Note 1)
62.5
437.5
500
ms
ms
ALARM Output Active-
High Pulse Width
ALARM Input Pulled Low
and Released Pulse Width
ms
Fast mode
Standard mode
Fast mode
400
100
SCL Clock Frequency
kHz
Bus Free Time Between a
STOP and START
Condition
1.3
4.7
tBUF
s
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
0.6
4.0
1.3
4.7
0.6
4.0
0.6
Hold Time (Repeated)
START Condition (Note 6)
tHD:STA
tLOW
s
s
s
s
s
ns
LOW Period of SCL
HIGH Period of SCL
tHIGH
Standard mode
Fast mode
Setup Time for a Repeated
START
tSU:STA
tHD:DAT
tSU:DAT
Standard mode
Fast mode
Standard mode
Fast mode
4.7
0
0
100
250
Data Hold Time (Notes 7, 8)
Data Setup Time (Note 9)
Standard mode
20 +
0.1CB
20 +
0.1CB
20 +
0.1CB
20 +
0.1CB
Fast Mode
300
1000
300
Rise Time of SDA and SCL
Signals (Note 10)
tR
ns
ns
Standard mode
Fast mode
Fall Time of SDA and SCL
Signals (Note 10)
tF
Standard mode
300
Fast mode
Standard mode
0.6
4.0
Setup Time for STOP
tSU:STO
CI/O
s
pF
pF
Input Capacitance (Note 1)
Capacitive Load for Each
Bus Line (Note 10)
10
CB
400
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DS1682 Total-Elapsed-Time Recorder with Alarm
TIMING DIAGRAM
Note 1: Typical values are at +25°C, VCC = 4.0V.
Note 2:
The elapsed time and event counters are backed by three EEPROM arrays, which are used
sequentially, allowing up to 3 x EE. The configuration register, alarm trip-point register and user
memory use a single array, limiting them to one EE.
Note 3:
A decoupling capacitor to supply high instantaneous currents during EEPROM writes is recommended.
A typical value is 0.01μF. VCC must be maintained above VCC minimum, including transients, during
EEPROM writes.
Note 4:
Note 5:
Note 6:
Note 7:
VCC must be at or above 2.5V for tEW after the end of an event to ensure data transfer to the EEPROM.
Reading data while the contents of EEPROM are transferred to RAM results in incorrect reads.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 8:
Note 9:
The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL
signal.
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must
be met. This is automatically the case if the device does not stretch the tLOW. If such a device does
stretch tLOW, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 10: CB—total capacitance of one bus line in pF.
CHIP INFORMATION
TRANSISTOR COUNT: 26,032
PROCESS: CMOS
PACKAGE INFORMATION
For the latest package information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
8 SO
S8+5
21-0041
14 of 14
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