DS1706L [DALLAS]
3.3 and 5.0 Volt MicroMonitor; 3.3和5.0伏MicroMonitor
| 型号： | DS1706L |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | 3.3 and 5.0 Volt MicroMonitor |
| 文件： | 总10页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DSDS1705/DS1706
DS1705/DS1706
3.3 and 5.0 Volt MicroMonitor
FEATURES
PIN ASSIGNMENT
• Halts and restarts an out–of–control microprocessor
PBRST
1
2
3
4
8
7
6
5
WDS
RST
ST
• Holds microprocessor in check during power tran-
sients
V
CC
GND
IN
NMI
• Automatically restarts microprocessor after power
failure
8–PIN DIP
(300 MIL)
• Monitors pushbutton for external override
PBRST
1
2
3
4
8
7
6
5
WDS
• Accurate 5%, 10% or 20% resets for 3.3 systems and
5% or 10% resets for 5.0 volt systems
V
RST (*RST)
ST
CC
GND
IN
NMI
• Eliminates the need for discrete components
8–PIN SOIC
(150 MIL)
• 3.3 volt 20% tolerance for use with 3.0 volt systems
• Pin compatible with the MAXIM MAX705/MAX706 in
PBRST
VCC
GND
IN
1
2
3
4
8
7
6
5
WDS
8–pin DIP and 8–pin SOIC
RST (*RST)
ST
• 8–pin DIP, 8–pin SOIC and 8–pin µ–SOP packages
• Industrial temperature range –40°C to +85°C
NMI
8–PIN µ–SOP
(118 MIL)
See Mech. Drawings
Section
DS1705 and DS1706_/R/S/T (*DS1706L and DS1706P)
PIN DESCRIPTION
PBRST
–
–
–
–
–
–
–
–
Pushbutton Reset Input
Power Supply
Ground
V
CC
GND
IN
NMI
ST
RST
*RST
Input
Non–maskable Interrupt
Strobe Input
Active Low Reset Output
Active High Reset Output
(DS1706P and DS1706L only)
Watchdog Status Output
WDS
–
DESCRIPTION
TheDS1705/DS17063.3or5.0VoltMicroMonitormoni-
tors three vital conditions for a microprocessor: power
supply, software execution, and external override. A
precision temperature compensated reference and
condition a non–maskable interrupt is generated. As
the voltage at the device degrades an internal power fail
signal is generated which forces the reset to an active
state. When V returns to an in–tolerance condition,
CC
comparator circuit monitors the status of V
device and at an upstream point for maximum protec-
tion. When the sense input detects an out–of–tolerance
at the
the reset signal is kept in the active state for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
CC
ECopyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
011296 1/10
DS1705/DS1706
The second function the DS1705/DS1706 performs is
DS1705/DS1706 requires that the voltage at the IN pin
be limited to V . Therefore, the maximum allowable
pushbutton reset control.
The DS1705/DS1706
CC
debounces the pushbutton input and guarantees an
active reset pulse width of 130 ms minimum.
voltage at the supply being monitored (V
) can also
MAX
be derived as shown in Figure 5. A simple approach to
solving the equation is to select a value for R2 high
enough to keep power consumption low, and solve for
R1. The flexibility of the IN input pin allows for detection
of power loss at the earliest point in a power supply sys-
tem, maximizing the amount of time for system shut–
down between NMI and RST (or RST).
The third function is
a
watchdog timer.
The
DS1705/DS1706 has an internal timer that forces the
WDO signal to the active state if the strobe input is not
driven low prior to time–out.
OPERATION
When the supply being monitored decays to the voltage
sense point, the DS1705/DS1706 pulses the NMI out-
put to the active state for a minimum 200 µs. The NMI
power fail detection circuitry also has built–in hysteresis
of 100 µV. The supply must be below the voltage sense
point for approximately 5 µs before a low NMI will be
generated. In this way, power supply noise is removed
from the monitoring function, preventing false inter-
rupts. During a power–up, any detected IN pin levels
Power Monitor
The DS1705/DS1706 detects out–of–tolerance power
supply conditions and warns a processor–based sys-
tem of impending power failure. When V falls below
the minimum V tolerance, a comparator outputs the
RST (or RST) signal. RST (or RST) is an excellent con-
trol signal for a microprocessor, as processing is
CC
CC
stopped at the last possible moment of valid V . On
CC
power–up, RST (or RST) are kept active for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
below V by the comparator are disabled from gener-
TP
ating an interrupt until V rises to V
. As a result,
CCTP
CC
any potential NMI pulse will not be initiated until V
CC
reaches V
.
CCTP
Pushbutton Reset
Connecting NMI to PBRST would allow non–maskable
interrupt to generate an automatic reset when an out–
of–tolerance condition occurred in a monitored supply.
An example is shown in Figure 3.
The DS1705/DS1706 provides an input pin for direct
connection to a push–button reset (see Figure 2). The
pushbutton reset input requires an active low signal.
Internally, this input is debounced and timed such that a
RST (or RST) signal of at least 130 ms minimum will be
generated. The 130 ms delay commences as the push-
button reset input is released from the low level. The
push–button can be initiated by connecting the WDS or
NMI outputs to the PBRST input as shown in Figure 3.
Watchdog Timer
The watchdog timer function forces WDS signals active
when the ST input is not clocked within the 1 second
time out period. Timeout of the watchdog starts when
RST(orRST)becomesinactive. Ifahigh–to–lowtransi-
tion occurs on the ST input pin prior to time–out, the
watchdog timer is reset and begins to time–out again. If
the watchdog timer is allowed to time out, the WDS sig-
nal is driven active (low) for a minimum of 130 ms. The
ST input can be derived from many microprocessor out-
puts. The typical signals used are the microprocessors
address signals, data signals, or control signals. When
the microprocessor functions normally, these signals
would, as a matter of routine, cause the watchdog to be
reset prior to time–out. To guarantee that the watchdog
timer does not time–out, a high–to–low transition must
occur at or less than the minimum watchdog time–out of
1 second. A typicalcircuitexampleisshowninFigure6.
Non–Maskable Interrupt
TheDS1705/DS1706 generates a non–maskable inter-
rupt (NMI) for early warning of a power failure. A preci-
sion comparator monitors the voltage level at the IN pin
relative to an on–chip reference generated by an inter-
nal band gap. The IN pin is a high impedance input
allowing for a user–defined sense point. An external
resistor voltage divider network (Figure 5) is used to
interface with high voltage signals. This sense point
may be derived from a regulated supply or from ahigher
DC voltage level closer to the main system power input.
Since the IN trip point V is 1.25 volts, the proper val-
uesforR1andR2canbedeterminedbytheequationas
TP
shown in Figure 5.
Proper operation of the
011296 2/10
DS1705/DS1706
MICROMONITOR BLOCK DIAGRAM Figure 1
IN
–
DIGITAL
SAMPLER
NMI
+
T.C.
REFERENCE
–
DIGITAL
SAMPLER
DIGITAL
DELAY
RST
DS1706_/A/R/S/T
+
V
CC
RST
DS1706L/DS1706P
LEVEL SENSE
AND
DEBOUNCE
PBRST
ST
WATCHDOG
STATUS
LATCH
WDS
PUSH–BUTTON RESET Figure 2
8051
µP
PBRST
WDS
RST
V
CC
RST
ALE
DS1706P
ST
GND
IN
NMI
PUSH–BUTTON RESET CONTROLLED BY NMI AND WDS Figure 3
µP
WDS
RST
ST
PBRST
V
CC
RST
ALE
UPSTREAM
SUPPLY
VOLTAGE
DS1706
GND
IN
NMI
011296 3/10
DS1705/DS1706
TIMING DIAGRAM: PUSHBUTTON RESET Figure 4
t
PDLY
PBRST
t
PB
V
IH
V
IL
t
RST
RST
RST
V
V
OH
OL
NON–MASKABLE INTERRUPT CIRCUIT EXAMPLE Figure 5
PBRST
WDS
RST
V
CC
V
SENSE
DS1706
ST
GND
IN
TO µP
R1
R2
NMI
VSENSE
R1 ) R2
VSENSE
+
x 1.25
VMAX
+
x VCC
R2
VTP
Example:
V
= 4.50 volts at the trip point
= 3.3 volts
SENSE
V
CC
10KΩ = R2
4.50
1.25
x 3.3 + 12.4 volts maximum
Therefore:
R1 ) 10K
4.5 +
x 1.25
R1 + 26KW
10K
011296 4/10
DS1705/DS1706
WATCHDOG TIMER Figure 6
Z80
µP
WDS
RST
ST
PBRST
V
CC
RST
MREQ
DS1706
GND
IN
DECODER
NMI
ADDRESS
BUS
TIMING DIAGRAM: STROBE INPUT Figure 7
INVALID
STROBE
VALID
STROBE
INDETERMINATE
STROBE
ST
MIN.
MAX.
t
TD
WDS
RST
RESET INITIATED
BY PUSHBUTTON
TIMING DIAGRAM: NON–MASKABLE INTERRUPT Figure 8
V
> 1.25V
IN
V
V
TP(MAX)
TP(MAX)
V
V
TP
TP
V
V
TP(MIN)
TP(MIN)
t
t
IPD
IPD
NMI
V
OH
V
OL
011296 5/10
DS1705/DS1706
TIMING DIAGRAM: POWER DOWN Figure 9
t
F
V
CC
V
CCTP(MAX)
V
CCTP
V
CCTP(MIN)
t
RPD
RST
(DS1705 AND DS1706_/R/S/T)
RST SLEWS WITH V
CC
V
OH
V
RST
OL
(DS1706L AND DS1706P ONLY)
WDS
WDS SLEWS WITH V
CC
011296 6/10
DS1705/DS1706
TIMING DIAGRAM: POWER UP Figure 10
V
CCTP(MAX)
V
CCTP
V
CCTP(MIN)
V
CC
t
RPU
RST
RST
(DS1705 AND DS1706_/R/S/T)
V
V
OH
OL
RST
RST
(DS1706L AND DS1706P ONLY)
WDS
011296 7/10
DS1705/DS1706
ABSOLUTE MAXIMUM RATINGS*
Voltage on V Pin Relative to Ground
–0.5V to +7.0V
CC
Voltage on I/O Relative to Ground
Operating Temperature
Storage Temperature
–0.5V to V + 0.5V
–40°C to +85°C
–55°C to +125°C
CC
Soldering Temperature
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(–40°C to +85°C)
PARAMETER
SYMBOL
MIN
1.0
TYP
MAX
UNITS
NOTES
Supply Voltage
V
CC
5.5
V
V
1
ST and PBRST Input High Level
V
IH
2.0
V
+0.3
1, 3
1, 4
CC
V
–0.5
CC
ST and PBRST Input Low Level
V
IL
–0.03
+0.5
V
1
DC ELECTRICAL CHARACTERISTICS
(–40°C to +85°C; VCC=1.2V to 5.5V)
PARAMETER
SYMBOL
MIN
4.50
4.25
3.00
2.85
2.55
–1.0
TYP
4.65
4.40
3.08
2.93
2.63
MAX
4.75
4.50
3.15
3.00
2.70
+1.0
UNITS
V
NOTES
V
CC
V
CC
V
CC
V
CC
V
CC
Trip Point DS1705/DS1706L
Trip Point DS1706
V
CCTP
V
CCTP
V
CCTP
V
CCTP
V
CCTP
1
1
1
1
1
2
3
3
3
V
Trip Point DS1706T
V
Trip Point DS1706S
V
Trip Point DS1706P or R
V
Input Leakage
I
IL
µA
µA
mA
V
Output Current @ 2.4 volts
Output Current @ 0.4 volts
Output Voltage @ –500 µA
Operating Current
I
350
OH
I
OL
10
V
OH
V
+–0.3
V
–0.1
CC
CC
I
60
µA
5
@ V < 5.5 volts
CC
CC
Operating Current
I
50
µA
5
1
@ V < 3.6 volts
CC
CC
IN Input Trip Point
V
1.20
1.25
1.30
V
TP
CAPACITANCE
PARAMETER
(tA=25°C)
SYMBOL
MIN
TYP
MAX
UNITS
pF
NOTES
Input Capacitance
Output Capacitance
C
5
7
IN
C
pF
OUT
011296 8/10
DS1705/DS1706
AC ELECTRICAL CHARACTERISTICS
(–40°C to +85°C; VCC=1.2V to 5.5V)
PARAMETER
PBRST = V
SYMBOL
MIN
150
130
10
TYP
205
5
MAX
285
8
UNITS
ns
NOTES
t
PB
IL
Reset Active Time
ST Pulse Width
t
ms
ns
RST
t
ST
6
9
V
CC
V
CC
V
CC
V
CC
Detect to RST and RST
Slew Rate
t
t
µs
RPD
t
F
20
130
0
µs
Detect to RST and RST
Slew Rate
205
285
250
ms
ns
7
RPU
t
R
PBRST Stable Low to RST and
RST
t
ns
PDLY
Watchdog Timeout
VIN Detect to NMI
t
1.0
1.6
5
2.2
8
s
8
9
TD
t
µs
IPD
NOTES:
1. All voltages are referenced to ground.
2. PBRST is internally pulled up to V with an internal impedance of 40KΩ typical and the ST input is internally
CC
pulled up to V with an internal impedance of 180KΩ typical.
CC
3. V ꢀ 2.4 volts
CC
4. V < 2.4 volts
CC
5. Measured with outputs open and all inputs at V or ground.
CC
6. Must not exceed t minimum.
TD
7. t = 5 µs
R
8. Minimum watchdog timeout tested at 2.7 volts for the 3.3 volt devices and 4.5 volts for the 5.0 volt devices.
9. Noise immunity – pulses < 2 µs at V
minimum will not cause a reset.
CCTP
011296 9/10
DS1705/DS1706
PART MARKING CODES
8
1
7
6
5
4
ABCD
WWY
2
3
8–PIN µ–SOP
(118 MIL)
A, B, C and D represents the device type and tolerance.
ABCD
705_
706_
706L
706P
706R
706S
706T
–
–
–
–
–
–
–
DS1705
DS1706
DS1706L
DS1706P
DS1706R
DS1706S
DS1706T
WWY represents the device manufacturing Work
Week, Year.
011296 10/10
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