DS1993L-F5 [DALLAS]
1kbit/4kbit Memory iButtonTM DS1994 4-kbit Plus Time Memory iButtonTM; 的1K位/ 4k位内存iButtonTM DS1994 4千位加时记忆iButtonTM
| 型号： | DS1993L-F5 |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | 1kbit/4kbit Memory iButtonTM DS1994 4-kbit Plus Time Memory iButtonTM |
| 文件： | 总17页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1992/DS1993
1kb/4kb Memory iButton
www.iButton.com
SPECIAL FEATURES
C 4096 bits of Read/Write Nonvolatile
Memory (DS1993)
C Easily Affixed with Self-Stick Adhesive
Backing, Latched by its Flange, or Locked
with a Ring Pressed onto its Rim
C 1024 bits of Read/Write Nonvolatile
Memory (DS1992)
C Presence Detector Acknowledges When
Reader First Applies Voltage
C 256-bit Scratchpad Ensures Integrity of Data
Transfer
C Meets UL#913 (4th Edit.); Intrinsically Safe
Apparatus, Approved under Entity Concept
for use in Class I, Division 1, Group A, B, C
and D Locations
C Memory Partitioned into 256-bit Pages for
Packetizing Data
C Data Integrity Assured with Strict
Read/Write Protocols
C Operating Temperature Range from -40°C to
+70°C
F5 MICROCAN
5.89
C Over 10 years of data retention
0.36
0.51
© 1993
16.25
17.35
COMMON iButton FEATURES
C Unique, Factory-Lasered and Tested 64-bit
Registration Number (8-bit Family Code +
48-bit Serial Number + 8-bit CRC Tester)
Assures Absolute Traceability Because No
Two Parts are Alike
YYWW REGISTERED RR
06
000000FBD804
DD
IO
C Multidrop Controller for MicroLAN
C Digital Identification and Information by
Momentary Contact
GND
All dimensions shown in millimeters.
C Chip-Based Data Carrier Compactly Stores
Information
ORDERING INFORMATION
C Data Can be Accessed While Affixed to
Object
DS1992L-F5
DS1993L-F5
F5 MicroCan
F5 MicroCan
C Economically Communicates to Bus Master
with a Single Digital Signal at 16.3kbps
C Standard 16mm Diameter and 1-Wire®
Protocol Ensure Compatibility with iButton®
Family
EXAMPLES OF ACCESSORIES
DS9096P Self-Stick Adhesive Pad
DS9101 Multipurpose Clip
C Button Shape is Self-Aligning with Cup-
Shaped Probes
DS9093RA Mounting Lock Ring
DS9093F Snap-In Fob
C Durable Stainless Steel Case Engraved with
Registration Number Withstands Harsh
Environments
DS9092 iButton Probe
1-Wire and iButton are registered trademarks of Dallas Semiconductor.
1 of 17
021604
DS1992/DS1993
iButton DESCRIPTION
The DS1992/DS1993 memory iButtons (hereafter referred to as DS199_) are rugged read/write data
carriers that act as a localized database, easily accessible with minimal hardware. The nonvolatile
memory and optional timekeeping capability offer a simple solution to storing and retrieving vital
information pertaining to the object to which the iButton is attached. Data is transferred serially through
the 1-Wire protocol that requires only a single data lead and a ground return.
The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to
the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command
transfers the data to memory. This process ensures data integrity when modifying the memory. A 48-bit
serial number is factory lasered into each DS199_ to provide a guaranteed unique identity that allows for
absolute traceability. The durable MicroCan package is highly resistant to environmental hazards such as
dirt, moisture, and shock. Its compact coin-shaped profile is self-aligning with mating receptacles,
allowing the DS199_ to be easily used by human operators. Accessories permit the DS199_ to be
mounted on almost any surface including plastic key fobs, photo–ID badges, and PC boards.
Applications include access control, work-in-progress tracking, electronic travelers, storage of calibration
constants, and debit tokens.
OPERATION
The DS199_ have three main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad, and 3)
1024-bit (DS1992) or 4096-bit (DS1993) SRAM. All data is read and written least significant bit first.
The memory functions are not available until the ROM function protocol has been established. This
protocol is described in the ROM functions flow chart (Figure 9). The master must first provide one of
four ROM function commands: 1) read ROM, 2) match ROM, 3) search ROM, or 4) skip ROM. After a
ROM function sequence has been successfully executed, the memory functions are accessible and the
master can then provide any one of the four memory function commands (Figure 6).
PARASITE POWER
The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry steals power whenever
the data input is high. The data line provides sufficient power as long as the specified timing and voltage
requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input,
lithium is conserved, and 2) if the lithium is exhausted for any reason, the ROM can still be read
normally.
64-bit LASERED ROM
Each DS199_ contain a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 2.)
The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates
as shown in Figure 3. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-Wire
Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards. The shift register bits
are initialized to zero. Then starting with the least significant bit of the family code, 1 bit at a time is
shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After
the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in
the 8 bits of CRC should return the shift register to all zeros.
2of 2
DS1992/DS1993
Figure 1. DS199_ BLOCK DIAGRAM
PARASITE-
POWERED
CIRCUITRY
ROM
64-BIT
LASERED
ROM
1-WIRE
FUNCTION
1-W
PORT
CONTROL
MEMORY
FUNCTION
CONTROL
256-BIT
SCRATCHPAD
SRAM
16 PAGES of 256-
BITs (1993)
4 PAGES of 256-
BITs (1992)
3V LITHIUM
Figure 2. 64-BIT LASERED ROM
MSB
LSB
8-Bit Family Code
8-Bit CRC Code
48-Bit Serial Number
(06h)1993
(08h)1992
MSB
LSB MSB
LSB MSB
LSB
Figure 3. 1-WIRE CRC CODE
Polynomial = X8 + X5 + X4 + 1
1st
2nd
3rd
4th
5th
6th
7th
8th
STAGE STAGE
X1
STAGE STAGE
X3
STAGE
STAGE STAGE STAGE
X0
X2
X4
X5
X6
X7
X8
INPUT DATA
3of 3
DS1992/DS1993
Figure 4a. DS1993 MEMORY MAP
NOTE: Each page is 32 bytes (256 bits). The hex values
represent the starting address for each page or register.
SCRATCHPAD
PAGE
PAGE 0
PAGE 1
0000h
0020h
PAGE 2
PAGE 3
PAGE 4
0040h
0060h
0080h
PAGE 5
00A0h
00C0h
00E0h
PAGE 6
PAGE 7
PAGE 8
MEMORY
0100h
PAGE 9
0120h
0140h
0160h
PAGE 10
PAGE 11
PAGE 12
PAGE 13
PAGE 14
PAGE 15
0180h
01A0h
01C0h
01E0h
Figure 4b. DS1992 MEMORY MAP
NOTE: Each page is 32 bytes (256 bits). The hex values
represent the starting address for each page or register.
SCRATCHPAD
PAGE
PAGE 0
PAGE 1
0000h
0020h
MEMORY
PAGE 2
PAGE 3
0040h
0060h
4of 4
DS1992/DS1993
MEMORY
The memory map in Figure 4 shows a 32-Byte page called the scratchpad, and additional 32-Byte pages
called memory. The DS1992 contains pages 0 though 3 that make up the 1024-bit SRAM. The DS1993
contain pages 0 through 15 that make up the 4096-bit SRAM.
The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to
the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command
transfers the data to memory. This process ensures data integrity when modifying the memory.
MEMORY FUNCTION COMMANDS
The Memory Function Flow Chart (Figure 6) describes the protocols necessary for accessing the memory.
An example follows the flow chart. Three address registers are provided as shown in Figure 5. The first
two registers represent a 16-bit target address (TA1, TA2). The third register is the ending offset/data
status byte (E/S).
The target address points to a unique Byte location in memory. The first 5 bits of the target address
(T4:T0) represent the Byte offset within a page. This Byte offset points to one of 32 possible Byte
locations within a given page. For instance, 00000b points to the first Byte of a page where as 11111b
would point to the last Byte of a page.
The third register (E/S) is a read only register. The first 5 bits (E4: E0) of this register are called the
ending offset. The ending offset is a Byte offset within a page (1 of 32 Bytes). Bit 5 (PF) is the partial
Byte flag. Bit 6 (OF) is the overflow flag. Bit 7 (AA) is the authorization accepted flag.
Figure 5. ADDRESS REGISTERS
7
6
5
4
3
2
1
0
TARGET ADDRESS (TA1)
TARGET ADDRESS (TA2)
T7
T6
T5
T4
T3
T2
T1
T0
T15 T14 T13 T12 T11 T10
AA OF PF E4 E3 E2
T9
E1
T8
E0
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
Write Scratchpad Command [0Fh]
After issuing the write scratchpad command, the user must first provide the 2-Byte target address,
followed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the
byte offset (T4:T0). The ending offset (E4:E0) is the Byte offset at which the host stops writing data. The
maximum ending offset is 11111b (31d). If the host attempts to write data past this maximum offset, the
overflow flag (OF) is set and the remaining data is ignored. If the user writes an incomplete Byte and an
overflow has not occurred, the partial Byte flag (PF) is set.
Read Scratchpad Command [AAh]
This command can be used to verify scratchpad data and target address. After issuing the read scratchpad
command, the user can begin reading. The first two Bytes are the target address. The next Byte is the
ending offset/data status Byte (E/S) followed by the scratchpad data beginning at the Byte offset (T4: T0).
The user can read data until the end of the scratchpad, after which the data read is all logic 1’s.
5of 5
DS1992/DS1993
Copy Scratchpad [55h]
This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad
command, the user must provide a 3-byte authorization pattern. This pattern must exactly match the data
contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA
(Authorization Accepted) flag is set and the copy begins. A logic 0 is transmitted after the data has been
copied until the user issues a reset pulse. Any attempt to reset the part is ignored while the copy is in
progress. Copy typically takes 30ꢀs.
The data to be copied is determined by the three address registers. The scratchpad data from the
beginning offset through the ending offset is copied to memory, starting at the target address. Anywhere
from 1 to 32 Bytes can be copied to memory with this command. Whole Bytes are copied even if only
partially written. The AA flag is cleared only by executing a write scratchpad command.
Read Memory [F0h]
The read memory command can be used to read the entire memory. After issuing the command, the user
must provide the 2-Byte target address. After the two Bytes, the user reads data beginning from the target
address and may continue until the end of memory, at which point logic 1’s are read. It is important to
realize that the target address registers contains the address provided. The ending offset/data status Byte
is unaffected.
The hardware of the DS1992/DS1993 provides a means to accomplish error-free writing to the memory
section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data
transfers, it is recommended to packetize data into data packets of the size of one memory page each.
Such a packet would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data
transfers that eliminate having to read a page multiple times to determine if the received data is correct or
not. (See Application Note 114 for the recommended file structure to be used with the 1-Wire
environment.)
6of 6
DS1992/DS1993
Figure 6. MEMORY FUNCTIONS FLOW CHART
Master TX Memory
Function Command
0FH
AAH
To Figure 6
Second Part
N
Write
Read
Scratchpad
Scratchpad
?
?
Y
Y
Bus Master RX
Bus Master TX
TA1 (T7:T0)
TA1 (T7:T0)
Bus Master RX
TA2 (T15:T8)
Bus Master TX
TA2 (T15:T8)
Master RX Ending
Offset with Data
Status (E/S)
DS199X sets Scratchpad
Offset = (T4:T0) and
Clears (PF, OF, AA)
DS199X Sets
Scratchpad
Master TX Data Byte
To Scratchpad Offset
Offset=(T4:T0)
DS199X sets (E4:E0)
= Scratchpad Offset
Master RX Data
Byte From
Scratchpad Offset
Y
Bus Master
TX Reset
?
Y
Bus Master
TX Reset
?
DS199X Increments
Scratchpad Offset
N
DS199X Increments
N
Scratch-
pad Offset =
11111b ?
N
Scratchpad Offset
Scratch-
pad Offset =
11111b ?
N
Y
Partial
Byte Written
?
Y
Y
Y
Bus Master
TX Data
Bus Master
N
PF = 1
RX "1"s
?
N
OF = 1
N
Bus Master
TX Reset
?
Y
From Figure 6
Second Part
DS199X TX
Presence Pulse
(See Figure 9)
7of 7
DS1992/DS1993
Figure 6. MEMORY FUNCTIONS FLOW CHART (Continued)
From Figure 6
First Part
55H
Copy
F0H
Y
N
Read Memory
Scratchpad
?
?
N
Y
Bus Master TX
TA1 (T7:T0)
Bus Master TX
TA1 (T7:T0)
Bus Master TX
TA2 (T15:T8)
Bus Master TX
TA2 (T15:T8)
Bus Master TX
E/S Byte
DS199X sets Memory
Address = (T15:T0)
Auth-
rization
N
Code Match
?
Master RX Data
Byte From
Y
AA = 1
Memory Address
DS199X TX "1"s
DS199X
Increments
Address Counter
Y
DS199X Copies
Scratchpad Data
To Memory
Bus Master
TX Reset
?
N
DS199X TX "0"s
N
Memory
Address
= 21Dh ?
N
Bus Master
Y
TX Reset
Bus Master
?
N
RX "1"s
Y
Bus Master
TX Reset
?
Y
To Figure 6
First Part
8of 8
DS1992/DS1993
MEMORY FUNCTION EXAMPLES
Example: Write two data Bytes to memory locations 0026h and 0027h (the seventh and eighth Bytes of
page 1). Read entire memory.
MASTER MODE
DATA (LSB FIRST)
COMMENTS
TX
RX
TX
TX
TX
TX
TX
TX
RX
TX
TX
RX
RX
RX
RX
TX
RX
TX
TX
TX
Reset
Presence
CCh
Reset pulse (480ꢀs to 960ꢀs)
Presence pulse
Issue skip ROM command
Issue write scratchpad command
TA1, beginning offset = 6
TA2, address = 0026h
Write 2 Bytes of data to scratchpad
Reset pulse
0Fh
26h
00h
<2 data Bytes>
Reset
Presence
CCh
Presence pulse
Issue skip ROM command
Issue read scratchpad command
Read TA1, beginning offset = 6
Read TA2, address = 0026h
Read E/S, ending offset = 7, flags = 0
Read scratchpad data and verify
Reset pulse
Aah
26h
00h
07h
<2 data Bytes>
Reset
Presence
CCh
Presence pulse
Issue skip ROM command
Issue copy scratchpad command
TA1
55h
26h
TA2 AUTHORIZATION CODE
E/S
TX
00h
TX
07h
TX
RX
TX
TX
TX
TX
Reset
Reset pulse
Presence pulse
Presence
CCh
Issue skip ROM command
Issue read memory command
TA1, beginning offset = 6
TA2, address = 0000h
F0h
00h
00h
<128 Bytes (DS1992)>
<512 Bytes (DS1993)>
Reset
RX
Read entire memory
TX
RX
Reset pulse
Presence pulse, done
Presence
9of 9
DS1992/DS1993
1-WIRE BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the
DS199_ is a slave device. The bus master is typically a microcontroller or PC. For small configurations
the 1-Wire communication signals can be generated under software control using a single port pin. For
multisensor networks, the DS2480B 1-Wire line driver chip or serial port adapters based on this chip
(DS9097U series) are recommended. This simplifies the hardware design and frees the microprocessor
from responding in real-time.
The discussion of this bus system is broken down into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in
terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from
the bus master. For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton
Standards.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-wire bus must have open-
drain or three-state outputs. The 1-Wire port of the DS199_ is open drain with an internal circuit
equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves
attached. The 1-Wire bus has a maximum data rate of 16.3kbps and requires a pullup resistor of
approximately 5kꢁ. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be
suspended, the bus must be left in the idle state if the transaction is to resume. If this does not occur and
the bus is left low for more than 120ꢀs, one or more of the devices on the bus may be reset.
Figure 8. HARDWARE CONFIGURATION
VPUP
BUS MASTER
DS199X 1-Wire PORT
RPU
RX
TX
DATA
RX
TX
5 µA
Typ.
RX = RECEIVE
TX = TRANSMIT
100 ꢀ
Open Drain
Port Pin
MOSFET
TRANSACTION SEQUENCE
The protocol for accessing the DS199_ through the 1-Wire port is as follows:
C Initialization
C ROM Function Command
C Memory Function Command
C Transaction/Data
INITIALIZATION
All transactions on the 1-wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
10of 10
DS1992/DS1993
slave(s). The presence pulse lets the bus master know that the DS199_ is on the bus and is ready to
operate. For more details, see the 1-Wire Signaling section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the four ROM function commands. All
ROM function commands are 8 bits long. A list of these commands follows (see the flow chart in Figure
9).
Read ROM [33h]
This command allows the bus master to read the DS199_’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command should only be used if there is a single DS199_ on the bus. If
more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the
same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number
usually result in a mismatch of the CRC.
Match ROM [55h]
The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific DS199_ on a multidrop bus. Only the DS199_ that exactly matches the 64-bit ROM sequence
will respond to the following memory function command. All slaves that do not match the 64-bit ROM
sequence wait for a reset pulse. This command can be used with single or multiple devices on the bus.
Skip ROM [CCh]
This command can save time in a single drop bus system by allowing the bus master to access the
memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus
and, for example, a read command is issued following the Skip ROM command, data collision will occur
on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND
result).
Search ROM [F0h]
When a system is initially brought up, the bus master may not know the number of devices on the 1-Wire
bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of
elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is
the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired
value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM. After one
complete pass, the bus master knows the 64-bit ROM code of one device. Additional passes will identify
the ROM codes of the remaining devices. See Chapter 5 of the Book of DS19xx iButton Standards for a
comprehensive discussion of a search ROM, including an actual example.
1-WIRE SIGNALING
The DS199_ require strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, and read data.
The bus master initiates all these signals except presence pulse. The initialization sequence required to
begin any communication with the DS199_ is shown in Figure 10. A reset pulse followed by a presence
pulse indicates the DS199_ is ready to send or receive data given the correct ROM command and
memory function command. The bus master transmits (Tx) a reset pulse (tRSTL, minimum 480ꢀs). The bus
master then releases the line and goes into receive mode (Rx). The 1-Wire bus is pulled to a high state
through the pullup resistor. After detecting the rising edge on the data line, the DS199_ waits (tPDH, 15ꢀs
to 60ꢀs) and then transmits the presence pulse (tPDL, 60ꢀs to 240ꢀs).
11of 11
DS1992/DS1993
12of 12
DS1992/DS1993
Figure 9. ROM FUNCTIONS FLOW CHART
Master TX
Reset Pulse
DS199X TX
Presence Pulse
Master TX ROM
Function Com m and
N
33H
Read ROM
Com m and
?
F0H
55H
Match ROM
Com m and
?
CCH
N
N
N
Search ROM
Com m and
?
Skip ROM
Com m and
?
Y
Y
Y
Y
DS199X TX Bit 0
DS199X TX Bit 0
Master TX Bit 0
DS199X TX
Fam ily Code
1 Byte
Master TX Bit 0
N
N
N
Bit 0
Bit 0
Match ?
Match ?
Y
Y
DS199X TX Bit 1
DS199X TX Bit 1
Master TX Bit 1
DS199X TX
Serial Num ber
Master TX Bit 1
6 Bytes
N
Bit 1
Bit 1
Match ?
Match ?
Y
Y
DS199X TX Bit 63
DS199X TX Bit 63
Master TX Bit 63
DS199X TX
CRC Byte
Master TX Bit 63
N
N
Bit 63
Bit 63
Match ?
Match ?
Y
Y
Master TX Mem ory
Function Com m and
13of 13
DS1992/DS1993
Figure 10. INITIALIZATION PROCEDURE RESET AND PRESENCE PULSE
MASTER TX
MASTER RX "PRESENCE PULSE"
"RESET PULSE"
tRSTH
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
tR
tRSTL
tPDH
tPDL
* In order not to mask interrup signaling
by other devices on the 10Wire bus tRSTL
+ tR should always be less than 960 us
?
480 µs tRSTL
?
A
<
<
*
RESISTOR
MASTER
A
480 µs tRSTH
**
** Includes recovery time
?
15 µs tPDH < 60 µs
DS199X
?
60 tPDL < 240 µs
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 11. The master driving the data line
low initiates all time slots. The falling edge of the data line synchronizes the DS199_ to the master by
triggering a delay circuit in the DS199_. During write time slots, the delay circuit determines when the
DS199_ samples the data line. For a read data time slot, if a 0 is to be transmitted, the delay circuit
determines how long the DS199_ holds the data line low overriding the 1 generated by the master. If the
data bit is a 1, the iButton leaves the read data time slot unchanged.
Figure 11. READ/WRITE TIMING DIAGRAM
Write-One Time Slot
tSLOT
tREC
VPULLUP
VPULLUP MIN
VIH MIN
DS199X
Sampling Window
VIL MAX
0V
tLOW1
15µs
60µs
?
60 µs tSLOT < 120 µs
1 µs tLOW1 < 15 µs
RESISTOR
MASTER
?
?
A
1 µs tREC
<
14of 14
DS1992/DS1993
Figure 11. READ/WRITE TIMING DIAGRAM (continued)
Write-Zero Time Slot
tREC
tSLOT
VPULLUP
VPULLUP MIN
VIH MIN
DS199X
Sampling Window
VIL MAX
0V
15µs
60µs
tLOW0
?
60 µs tLOW0 < tSLOT < 120 µs
RESISTOR
MASTER
?
1 µs tREC
A
<
Read-Data Time Slot
tSLOT
tREC
VPULLUP
VPULLUP MIN
VIH MIN
Master
Sampling Window
VIL MAX
0V
tSU
tLOWR
tRELEASE
tRDV
RESISTOR
MASTER
DS199X
?
60 µs tSLOT < 120 µs
?
1 µs tLOWR < 15 µs
?
1 µs tREC
tRDV = 15 µs
tSU < 1 µs
A
<
?
0
tRELEASE < 45 µs
15of 15
DS1992/DS1993
PHYSICAL SPECIFICATIONS
Size
See mechanical drawing
3.3 grams (F5 package)
10 years at +25LC
Weight
Expected Service Life
Safety
Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus,
Approved under Entity Concept for use in Class I,
Division 1, Group A, B, C and D Locations
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground
Operating Temperature Range
-0.5V to +7.0V
-40LC to +70LC
-40LC to +70LC
Storage Temperature Range
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS (VPUP = 2.8V to 6.0V; -40°C to +70°C.)
PARAMETER
Logic 1 (Notes 1, 2)
Logic 0 (Note 1)
SYMBOL MIN
TYP
MAX
UNITS
VIH
VIL
2.2
V
V
-0.3
+0.8
0.4
Output Logic Low at 4mA
(Note 1)
VOL
V
Output Logic High (Notes 1,
3)
Input Load Current (Note 4)
VOH
IL
VPUP
5
V
ꢀA
CAPACITANCE
PARAMETER
(TA = +25°C)
SYMBOL MIN
TYP
MAX
UNITS
I/O (1-Wire) (Notes 5, 6)
CIN/OUT
100
800
pF
AC ELECTRICAL CHARACTERISTICS (VPUP = 2.8V to 6.0V; -40°C to +70°C.)
PARAMETER
SYMBOL MIN
TYP
MAX
120
15
UNITS
ꢀs
Time Slot
tSLOT
tLOW1
tLOW0
tRDV
60
1
Write 1 Low Time
Write 0 Low Time
Read Data Valid
Release Time
Read Data Setup (Note 7)
Recovery Time
Reset Time High (Note 8)
Reset Time Low (Note 9)
Presence Detect High
Presence Detect Low
ꢀs
60
120
ꢀs
exactly 15
15
ꢀs
tRELEASE
0
45
1
ꢀs
tSU
tREC
ꢀs
1
ꢀs
tRSTH
tRSTL
tPDH
480
480
15
ꢀs
960
60
240
ꢀs
ꢀs
tPDL
60
ꢀs
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DS1992/DS1993
Note 1: All voltages are referenced to ground.
Note 2: VIH is a function of the external pullup resistor and the VCC power supply.
Note 3: VPUP = external pullup voltage.
Note 4: Input load is to ground.
Note 5: Capacitance on the data line could be 800pF when power is first applied. If a 5kꢁꢂresistor is used
to pull up the data line to VPUP, 5ꢀs after power has been applied, the parasite capacitance does
not affect normal communications.
Note 6: Guaranteed by design, not production tested.
Note 7: Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1ꢀs of this falling edge, and remains valid for 14ꢀs minimum.
(15ꢀs total from falling edge on 1-Wire bus.)
Note 8: An additional reset or communication sequence cannot begin until the reset high time has
expired.
Note 9: The reset low time (tRSTL) should be restricted to a maximum of 960ꢀs, to allow interrupt
signaling; otherwise it could mask or conceal interrupt pulses.
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