DS2415P [DALLAS]
1-Wire Time Chip; 1 -Wire时钟芯片
| 型号： | DS2415P |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | 1-Wire Time Chip |
| 文件： | 总20页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1385/DS1387
DS1385/DS1387
RAMified Real Time Clock 4K x 8
FEATURES
PIN ASSIGNMENT
• Upgraded IBM AT computer clock/calendar with
4K x 8 extended RAM
OER
X1
1
24
23
22
21
20
19
18
17
16
15
14
13
V
OER
NC
1
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CC
2
SQW
AS0
AS1
2
SQW
AS0
AS1
NC
• Totally nonvolatile with over 10 years of operation in
the absence of power
X2
3
NC
3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
4
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
4
5
V
5
BAT
• Counts seconds, minutes, hours, day of the week,
date, month and year with leap year compensation
6
IRQ
WER
RD
6
IRQ
WER
RD
7
7
8
8
• Binary or BCD representations of time, calendar and
alarm
9
GND
WR
ALE
CS
9
NC
10
11
12
10
11
12
WR
ALE
CS
• 12– or 24–hour clock with AM and PM in 12–hour
mode
DS1385 24–PIN DIP
(600 MIL)
DS1387 24–PIN
ENCAPSULATED PACKAGE
(740 MIL FLUSH)
• Daylight Savings Time option
• Multiplex bus for pin efficiency
• Interfaced with software as 64 user RAM locations
plus 4K x 8 of static RAM
–
–
–
14–bytes of clock and control registers
50–bytes of general purpose RAM
OER
X1
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
2
SQW
NC
X2
3
4K x 8 SRAM accessible by using separate con-
trol pins
NC
4
AS0
AS1
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
NC
5
6
V
• Programmable square wave output signal
• Bus–compatible interrupt signals (IRQ)
BAT
7
IRQ
WER
RD
8
9
• Three interrupts are separately software–maskable
and testable:
10
11
12
13
14
BGND
WR
ALE
CS
–
–
–
Time–of–day alarm once/second to once/day
Periodic rates from 122 µs to 500 ms
End–of–clock update cycle
GND
NC
DS1385S 28–PIN SOIC
(330 MIL)
• Available as chip (DS1385 or DS1385S) or stand
alone module with embedded lithium battery and
crystal (DS1387)
ORDERING INFORMATION
DS1385
DS1385S
DS1387
RTC Chip; 24–pin DIP
RTC Chip; 28–pin SOIC
RTC Module; 24–pin DIP
ECopyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
012496 1/20
DS1385/DS1387
PIN DESCRIPTION
SIGNAL DESCRIPTIONS
GND, V
– DC power is provided to the device on
CC
OER
X1
X2
AD0-AD7
CS
ALE
WR
RD
WER
IRQ
–
–
–
–
–
–
–
–
–
–
RAM Output Enable
Crystal Input
Crystal Output
Mux’ed Address/Data Bus
RTC Chip Select Input
RTC Address Strobe
RTC Write Data Strobe
RTC Read Data Strobe
RAM Write Data Strobe
Interrupt Request Output (open
these pins. V is the +5 volt input. When 5 volts are
CC
applied within normal limits, the device is fully accessi-
ble and data can be written and read. When V is be-
low 4.25 volts typical, reads and writes are inhibited.
However, the timekeeping function continues unaf-
fected by the lower input voltage. As V falls below 3
volts typical, the RAM and timekeeper are switched
over to the energy source connected to the V
the case of the DS1385, or to the internal battery in the
case of the DS1387. The timekeeping function main-
tains an accuracy of ±1 minute per month at 25°C re-
CC
CC
pin in
BAT
drain)
AS1
AS0
SQW
–
–
–
–
–
–
–
–
RAM Upper Address Strobe
RAM Lower Address Strobe
Square Wave Output
+5V Supply
Ground
Battery + Supply
Battery Ground
gardless of the voltage input on the V pin.
CC
SQW (Square Wave Output) – The SQW pin can output
a signal from one of 13 taps provided by the 15 internal
divider stages of the real time clock. The frequency of the
SQW pin can be changed by programming Register A as
shown in Table 2. The SQW signal can be turned on and
off using the SQWE bit in Register B. The SQW signal is
V
CC
GND
V
BAT
BGND
NC
No Connection
not available when V is less than 4.25 volts typical.
CC
DESCRIPTION
The DS1385/DS1387 RAMified Real Time Clocks
(RTCs) are upward–compatible successors to the in-
dustrystandardDS1285/DS1287RTC’s for PCapplica-
tions. In addition to the basic DS1285/DS1287 RTC
functions, 4K bytes of on–chip nonvolatile RAM have
been added.
AD0–AD7(MultiplexedBi–directionalAddress/Data
Bus) – Multiplexed buses save pins because address
information and data information time share the same
signal paths. The addresses are present during the first
portion of the bus cycle and the same pins and signal
paths are used for data in the second portion of the
cycle. Address/data multiplexing does not slow the ac-
cess time of the DS1385/DS1387 since the bus change
fromaddress to data occurs during the internal RAM ac-
cess time. Addresses must be valid prior to the latter
portion of ALE, AS0, or AS1, at which time the
DS1385/DS1387latches the address from AD0 to AD7.
Valid write data must be present and held stable during
the latter portion of the WR or WER pulses. In a read
cycle, the DS1385/DS1387 outputs eight bits of data
during the latter portion of the RD or OER pulses. The
readcycleisterminatedandthebusreturnstoahighim-
pedance state as RD or OER transitions high.
The RTC functions include a time–of–day clock, a one-
hundred year calendar, time–of–day interrupt, periodic
interrupts, and an end–of–clock update cycle interrupt.
Inaddition, 50–bytesofuserNVRAMareprovidedwith-
in this basic RTC function which can be used to store
configuration data. The clock and user RAM are main-
tainedintheabsenceofsystemV byalithiumbattery.
CC
The 4K x 8 additional NV RAM is provided to store a
muchlargeramountofsystemconfigurationdatathanis
possible within the original 50–byte area. This RAM is
accessed via control signals separate from the RTC,
and is also maintained as nonvolatile storage from the
lithium battery.
ALE (RTC Address Strobe Input) – A positive going
address strobe pulse serves to demultiplex the bus.
The falling edge of ALE causes the RTC address to be
latched within the DS1385/DS1387.
OPERATION
The block diagram in Figure 1 shows the pin connec-
tions with the major internal functions of the
DS1385/DS1387. The following paragraphs describe
the function of each pin.
RD (RTC Read Input) – RD identifies the time period
when the DS1385/DS1387 drives the bus with RTC
read data. The RD signal is an enable signal for the out-
put buffers of the clock.
012496 2/20
DS1385/DS1387
DS1385/DS1387 BLOCK DIAGRAM Figure 1
X1
X2
OSC
ꢀ8
ꢀ64
ꢀ64
CS
POWER
SWITCH
AND
V
CC
PERIODIC INTERRUPT/SQUARE WAVE
SELECTOR
V
CC
WRITE
POK
PROTECT
SQUARE
WAVE OUT
SQW
V
BAT
+
+3V
–
BUFFER
ENABLE
IRQ
CONTROL
REGISTERS A, B, C, D
ALE
RD
DOUBLE
BUFFERED
WR
CS
CLOCK, CALENDAR,
AND ALARM
CLOCK/
CALENDAR
UPDATE
BUS
INTERFACE
AD0-AD7
AS1
AS0
WER
OER
BCD/BINARY
INCREMENT
USER RAM
50 BYTES
ADDRESS HIGH
BYTE LATCH
ADDRESS LOW
BYTE LATCH
NONVOLATILE RAM
4K X 8
DATA LATCH
012496 3/20
DS1385/DS1387
WR (RTC Write Input) –The WR signal is an active low
signal. The WR signal defines the time period during
which data is written to the addressed clock register.
nals be kept away from the crystal area. For more
information on crystal selection and crystal layout con-
siderations, please consult Application Note 58, “Crys-
tal Considerations with Dallas Real Time Clocks”.
CS (RTC Chip Select Input) – The Chip Select signal
must be asserted low during a bus cycle for the RTC
portion of the DS1385/DS1387 to be accessed. CS
must be kept in the active state during RD and WR tim-
ing. Bus cycles which take place without asserting CS
will latch addresses but no access will occur.
V
, BGND – Battery input for any standard 3 volt lithi-
BAT
um cell or other energy source. Battery voltage must be
heldbetween2.5and3.7voltsforproperoperation. The
nominalwriteprotecttrippointvoltageissetbytheinter-
nalcircuitryand is4.25voltstypical. Amaximumloadof
1 µA at 25°C and 3.0V on V
should in the absence of
BAT
IRQ (Interrupt Request Output) – The IRQ pin is an
active low output of the DS1385/DS1387 that can be
tiedto an interrupt input on a processor. The IRQoutput
remains low as long as the status bit causing the inter-
rupt is present and the corresponding interrupt–enable
bit is set. To clear the IRQ pin, the application program
normally reads the C register.
power be used to size the external energy source.
The battery should be connected directly to the V
pin.
BAT
A diode must not be placed in series with the battery to
the V pin. Furthermore, a diode is not necessary
BAT
because reverse charging current protection circuitry is
provided internal to the device and has passed the
requirements of Underwriters Laboratories for UL listing
(E99151).
When no interrupt conditions are present, the IRQ level
is in the high impedance state. Multiple interrupting de-
vices can be connected to an IRQ bus. The IRQ bus is
an open drain output and requires an external pull–up
resistor.
ADDRESS MAP
The address map of the DS1385/DS1387 is shown in
Figure 2. The address map consists of the RTC and the
4K X 8 NV SRAM section. The RTC section contains
50–bytes of user RAM, 10–bytes of RAM that contain
the RTC time, calendar, and alarm data, and 4–bytes
which are used for control and status. All 64–bytes can
be directly written or read except for the following:
AS0 (RAM Address Strobe Zero) – The rising edge of
AS0 latches the lower eight bits of the 4K x 8 RAM ad-
dress.
AS1 (RAM Address Strobe One) – The rising edge of
AS1 latches the upper four bits of the 4K x 8 RAM ad-
dress.
1. Registers C and D are read-only.
2. Bit–7 of Register A is read-only.
OER (RAM Output Enable) – OER is active low and
identifies the time period when the DS1385/DS1387
drives the bus with RAM read data.
3. The high order bit of the seconds byte is read-only.
RTC (REAL TIME CLOCK)
TheRTCfunctionis thesameastheDS1287RealTime
Clock. Access to the RTC is accomplished with four
controls: ALE, RD, WR and CS. The RTC is the same in
the DS1287 with the following exceptions:
WER (RAM Write Enable) – WER is an active low sig-
nal and is used to perform writes to the 4K x 8 RAM por-
tion of the DS1385/DS1387.
(DS1385 ONLY)
1. The MOT pin on the DS1285/DS1287 is not present
ontheDS1385/DS1387. Thebusselectioncapabili-
tyoftheDS1285/DS1287hasbeeneliminated. Only
the Intel bus interface timing is applicable.
X1, X2 – Connections for a standard 32.768 KHz quartz
crystal. When ordering, request a load capacitance of 6
pF. Theinternaloscillatorcircuitryisdesignedforopera-
tion with a crystal having a specified load capacitance
(CL) of 6 pF. The crystal is connected directly to the X1
and X2 pins. There is no need for external capacitors or
resistors. Note: X1 and X2 are very high impedance
nodes. It is recommended that they and the crystal be
guard–ringed with ground and that high frequency sig-
2. The RESET pin on the DS1285/DS1287 is not pres-
ent on the DS1385/DS1387. The DS1385/DS1387
will operate the same as the DS1285/DS1287 with
RESET tied to V
.
CC
012496 4/20
DS1385/DS1387
ADDRESS MAP DS1385/DS1387 Figure 2
0
00
0
1
2
3
4
5
6
7
8
9
SECONDS
SECONDS ALARM
MINUTES
14–BYTES
13
14
0D
0E
MINUTES ALARM
HOURS
50–BYTES
USER RAM
63
0
3F
HOURS ALARM
DAY OF THE WEEK
DAY OF THE MONTH
MONTH
000
4K X 8
NV SRAM
YEAR
10
REGISTER A
REGISTER B
REGISTER C
REGISTER D
11
12
13
4096
FFF
the high order bit of the hours byte represents PM when
it is a logic one. The time, calendar and alarm bytes are
always accessible because they are double buffered.
Once per second the 10–bytes are advanced by one
second and checked for an alarm condition. If a read of
the time and calendar data occurs during an update, a
problem exists where seconds, minutes, hours, etc.
may not correlate. The probability of reading incorrect
time and calendar data is low. Several methods of
avoidinganypossibleincorrecttimeandcalendarreads
are covered later in this text.
TIME, CALENDAR AND ALARM LOCATIONS
The time and calendar information is obtained by read-
ing the appropriate register bytes shown in Table 1. The
time, calendar and alarm are set or initialized by writing
theappropriate register bytes. The contents of the time,
calendar and alarm registers can be either Binary or
Binary–Coded Decimal (BCD) format. Table 1 shows
the binary and BCD formats of the twelve time, calendar
and alarm locations.
Beforewriting the internal time, calendar and alarm reg-
isters, the SET bit in Register B should be written to a
logic one to prevent updates from occurring while ac-
cess is being attempted. Also at this time, the data for-
mat (binary or BCD), should be set via the data mode bit
(DM) of Register B. All time, calendar and alarm regis-
ters must use the same data mode. The set bit in Regis-
ter B should be cleared after the data mode bit has been
written to allow the real–time clock to update the time
and calendar bytes.
The three alarm bytes can be used in two ways. First,
when the alarm time is written in the appropriate hours,
minutes and seconds alarm locations, the alarm inter-
ruptisinitiatedatthespecifiedtimeeachdayifthealarm
enable bit is high. The second method is to insert a
“don’tcare”stateinoneormoreofthethreealarmbytes.
The “don’t care” code is any hexadecimal value from C0
to FF. The two most significant bits of each byte set the
“don’t care” condition when at logic 1. An alarm will be
generatedeachhourwhenthe“don’tcare”bitsaresetin
the hours byte. Similarly, an alarm is generated every
minute with “don’t care” codes in the hours and minute
alarm bytes. The “don’t care” codes in all three alarm
bytes create an interrupt every second.
Once initialized, the real–time clock makes all updates
in the selected mode. The data mode cannot be
changed without reinitializing the ten data bytes. The
24/12 bit cannot be changed without reinitializing the
hour locations. When the 12–hour format is selected,
012496 5/20
DS1385/DS1387
TIME, CALENDAR AND ALARM DATA MODES Table 1
RANGE
BINARY DATA MODE
ADDRESS
LOCATION
DECIMAL
RANGE
FUNCTION
BCD DATA MODE
00–59
0
1
2
3
4
Seconds
0–59
0–59
0–59
0–59
1–12
0–23
1–12
0–23
1–7
00–3B
Seconds Alarm
Minutes
00–3B
00–59
00–3B
00–59
Minutes Alarm
00–3B
00–59
Hours–12–hr Mode
Hours–24–hr Mode
Hours Alarm–12–hr
Hours Alarm–24–hr
01–0C AM, 81–8C PM
00–17
01–12AM, 81–92PM
00–23
5
6
01–0C AM, 81–8C PM
00–17
01–12AM, 81–92PM
00–23
Day of the Week
Sunday = 1
01–07
01–07
7
8
9
Date of the Month
Month
1–31
1–12
0–99
01–1F
01–0C
00–63
01–31
01–12
00–99
Year
condition. If an interrupt flag is already set when an in-
terrupt is enabled, IRQ is immediately set at an active
level, although the interrupt initiating the event may
haveoccurredmuchearlier. Asaresult, therearecases
where the program should clear such earlier initiated in-
terrupts before first enabling new interrupts.
USER NONVOLATILE RAM – RTC
The 50 user nonvolatile RAM bytes are not dedicated to
any special function within the DS1385/DS1387. They
can be used by the application program as nonvolatile
memory and are fully available during the update cycle.
This memory is directly accessible in the RTC section.
When an interrupt event occurs, the relating flag bit is
set to logic 1 in Register C. These flag bits are set inde-
pendent of the state of the corresponding enable bit in
Register B. The flag bit can be used in a polling mode
withoutenablingthecorrespondingenablebits. Whena
flagisset, anindicationisgiventosoftwarethataninter-
rupt event has occurred since the flag bit was last read.
However, care should be taken when using the flag bits
as they are cleared each time Register C is read.
Double latching is included with Register C so that bits
which are set remain stable throughout the read cycle.
All bits which are set (high) are cleared when read and
new interrupts which are pending during the read cycle
are held until after the cycle is completed. One, two or
threebits can be set when reading Register C. Each uti-
lized flag bit should be examined when read to ensure
that no interrupts are lost.
INTERRUPTS
The RTC plus RAM includes three separate, fully auto-
matic sources of interrupt for a processor. The alarm in-
terrupt can be programmed to occur at rates from once
per second to once per day. The periodic interrupt can
be selected for rates from 500 ms to 122 µs. The
update–ended interrupt can be used to indicate to the
program that an update cycle is complete. Each of
these independent interrupt conditions is described in
greater detail in other sections of this text.
The application program can select which interrupts, if
any, are going to be used. Three bits in Register B en-
able the interrupts. Writing a logic 1 to an interrupt–en-
able bit permits that interrupt to be initiated when the
eventoccurs. Alogic0inaninterrupt–enablebitprohib-
its the IRQ pin from being asserted from that interrupt
012496 6/20
DS1385/DS1387
The alternative flag bit usage method is with fully en-
abledinterrupts. Whenaninterruptflagbitissetandthe
corresponding interrupt enable bit is also set, the IRQ
pin is asserted low. IRQ is asserted as long as at least
oneofthethreeinterruptsourceshasitsflagandenable
bits both set. The IRQF bit in Register C is a one when-
ever the IRQ pin is being driven low. Determination that
the RTC initiated an interrupt is accomplished by read-
ing Register C. A logic one in bit–7 (IRQF bit) indicates
that one or more interrupts have been initiated. The act
of reading Register C clears all active flag bits and the
IRQF bit.
will turn the oscillator on and enable the countdown
chain. A pattern of 11X will turn the oscillator on, but
holds the countdown chain of the oscillator in reset. All
other combinations of bits 6 through 4 keep the oscilla-
tor off.
SQUARE WAVE OUTPUT SELECTION
Thirteen of the 15 divider taps are made available to a
1–of–15 selector, as shown in the block diagram of Fig-
ure 1. The first purpose of selecting a divider tap is to
generate a square wave output signal on the SQW pin.
The RS3–RS0 bits in Register A establish the square
wave output frequency. These frequencies are listed in
Table 2. The SQW frequency selection shares its
1–of–15 selector with the periodic interrupt generator.
Once the frequency is selected, the output of the SQW
pin can be turned on and off under program control with
the square wave enable bit (SQWE).
OSCILLATOR CONTROL BITS
When the DS1385/DS1387 is shipped from the factory,
the internal oscillator is turned off. This feature prevents
thelithium battery from being used until it is installed in a
system. A pattern of 010 in bits 6 through 4 of Register A
PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 2
SELECT BITS REGISTER A
t
PERIODIC
SQW OUTPUT
FREQUENCY
PI
INTERRUPT RATE
RS3
0
RS2
0
RS1
0
RS0
0
None
None
0
0
0
1
3.90625 ms
7.8125 ms
122.070 µs
244.141 µs
488.281 µs
976.5625 µs
1.953125 ms
3.90625 ms
7.8125 ms
15.625 ms
31.25 ms
62.5 ms
256 Hz
128 Hz
8.192 KHz
4.096 KHz
2.048 KHz
1.024 KHz
512 Hz
256 Hz
128 Hz
64 Hz
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
32 Hz
1
1
0
0
16 Hz
1
1
0
1
125 ms
8 Hz
1
1
1
0
250 ms
4 Hz
1
1
1
1
500 ms
2 Hz
012496 7/20
DS1385/DS1387
There are three methods that can handle access of the
real–time clock that avoid any possibility of accessing
inconsistent time and calendar data. The first method
uses the update–ended interrupt. If enabled, an inter-
rupt occurs after every up date cycle that indicates that
over 999 ms are available to read valid time and date in-
formation. If this interrupt is used, the IRQF bit in Regis-
ter C should be cleared before leaving the interrupt rou-
tine.
PERIODIC INTERRUPT SELECTION
The periodic interrupt will cause the IRQ pin to go to an
active state from once every 500 ms to once every
122 µs. This function is separate from the alarm inter-
rupt which can be output from once per second to once
per day. The periodic interrupt rate is selected using the
same Register A bits which select the square wave fre-
quency (see Table 1). Changing the Register A bits af-
fects both the square wave frequency and the periodic
interruptoutput. However, eachfunctionhasaseparate
enable bit in Register B. The SQWE bit controls the
square wave output. Similarly, the periodic interrupt is
enabled by the PIE bit in Register B. The periodic inter-
rupt can be used with software counters to measure in-
puts, create output intervals or await the next needed
software function.
A second method uses the update–in–progress bit
(UIP) in Register A to determine if the update cycle is in
progress. The UIP bit will pulse once per second. After
the UIP bit goes high, the update transfer occurs 244 µs
later. If a low is read on the UIP bit, the user has at least
244 µs before the time/calendar data will be changed.
Therefore, the user should avoid interrupt service rou-
tines that would cause the time needed to read valid
time/calendar data to exceed 244 µs.
UPDATE CYCLE
The DS1385/DS1387 executes an update cycle once
per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to one, the user
copyofthedoublebufferedtime,calendarandalarmby-
tes is frozen and will not update as the time increments.
However,thetimecountdownchaincontinuestoupdate
theinternalcopyofthebuffer. Thisfeatureallowstimeto
maintainaccuracy independent of reading or writing the
time, calendar and alarm buffers and also guarantees
thattimeandcalendarinformationisconsistent.Theup-
date cycle also compares each alarm byte with the cor-
respondingtime byte and issues an alarm if a match or if
a “don’t care” code is present in all three positions.
The third method uses a periodic interrupt to determine
if an update cycle is in progress. The UIP bit in Register
A is set high between the setting of the PF bit in Register
C (see Figure 3). Periodic interrupts that occur at a rate
of greater than t
allow valid time and date informa-
BUC
tion to be reached at each occurrence of the periodic in-
terrupt. The reads should be complete within
(t /2+t
)toensurethatdataisnotreadduringtheup-
PI
BUC
date cycle.
UPDATE–ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 3
UIP BIT IN
REGISTER A
t
BUC
UF BIT IN
REGISTER C
t
t
PI/2
PI/2
PF BIT IN
REGISTER C
t
PI
t
t
= Periodic interrupt time interval per Table 1.
PI
= Delay time before update cycle = 244 µs.
BUC
012496 8/20
DS1385/DS1387
the midst of initializing. Read cycles can be executed in
asimilarmanner. SET is a read/write bit that is not modi-
fied by internal functions of the DS1385/DS1387.
REGISTERS
The DS1385/DS1387 has four control registers which
are accessible at all times, even during the update
cycle.
PIE – The Periodic Interrupt Enable bit is a read/write bit
which allows the Periodic Interrupt Flag (PF) bit in Reg-
isterCtodrivetheIRQpin low. WhenthePIEbitissetto
one, periodic interrupts are generated by driving the
IRQ pin low at a rate specified by the RS3-RS0 bits of
Register A. A zero in the PIE bit blocks the IRQ output
from being driven by a periodic interrupt, but the Period-
ic Flag (PF) bit is still set at the periodic rate. PIE is not
modified by any internal DS1385/DS1387 functions.
REGISTER A
MSB
LSB
BIT 0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
UIP
DV2
DV1
DV0
RS3
RS2
RS1
RS0
UIP – The Update In Progress (UIP) bit is a status flag
that can be monitored. When the UIP bit is a one, the
update transfer will soon occur. When UIP is a zero, the
update transfer will not occur for at least 244 µs. The
time, calendar and alarm information in RAM is fully
available for access when the UIP bit is zero. The UIP
bitisreadonly. WritingtheSETbitinRegisterBtoaone
inhibits any update transfer and clears the UIP status
bit.
AIE – The Alarm Interrupt Enable (AIE) bit is a read/
write bit which, when set to a one, permits the Alarm
Flag (AF) bit in register C to assert IRQ. An alarm inter-
rupt occurs for each second that the three time bytes
equal the three alarm bytes including a don’t care alarm
code of binary 11XXXXXX. When the AIE bit is set to
zero, the AF bit does not initiate the IRQ signal. The in-
ternalfunctionsoftheDS1385/DS1387donotaffectthe
AIE bit.
DV2, DV1, DV0 – These three bits are used to turn the
oscillator on or off and to reset the countdown chain. A
patternof010istheonlycombinationofbitsthatwillturn
the oscillator on and allow the RTC to keep time. A pat-
tern of 11X will enable the oscillator but holds the count-
down chain in reset. The next update will occur at 500
ms after a pattern of 010 is written to DV2, DV1, and
DV0.
UIE – The Update Ended Interrupt Enable (UIE) bit is a
read/write bit that enables the Update End Flag (UF) bit
in Register C to assert IRQ. The SET bit going high
clears the UIE bit.
SQWE – When the Square Wave Enable (SQWE) bit is
set to a one, a square wave signal at the frequency set
by the rate–selection bits RS3 through RS0 is driven out
on a SQW pin. When the SQWE bit is set to zero, the
SQW pin is held low. SQWE is a read/write bit.
RS3, RS2, RS1, RS0 – These four rate–selection bits
select one of the 13 taps on the 15–stage divider or dis-
able the divider output. The tap selected can be used to
generateanoutputsquarewave(SQWpin)and/orape-
riodic interrupt. The user can do one of the following:
1. Enable the interrupt with the PIE bit;
2. Enable the SQW output pin with the SQWE bit;
3. Enable both at the same time and the same rate; or
4. Enable neither.
DM – The Data Mode (DM) bit indicates whether time
and calendar information is in binary or BCD format.
The DM bit is set by the program to the appropriate for-
matandcanbereadasrequired. Thisbitisnotmodified
by internal functions. A one in DM signifies binary data
while a zero in DM specifies Binary Coded Decimal
(BCD) data.
Table 2 lists the periodic interrupt rates and the square
wave frequencies that can be chosen with the RS bits.
REGISTER B
MSB
24/12 – The 24/12 control bit establishes the format of
thehoursbyte. Aoneindicatesthe24–hourmodeanda
zero indicates the 12–hour mode. This bit is read/write.
LSB
BIT 1 BIT 0
BIT 7 BIT 6 BIT 5
BIT 4
BIT 3
BIT 2
SET
PIE
AIE
UIE
SQWE
DM
24/12
DSE
DSE – The Daylight Savings Enable (DSE) bit is a read/
write bit which enables two special updates when DSE
is set to one. On the first Sunday in April the time incre-
ments from 1:59:59 AM to 3:00:00 AM. On the last
Sunday in October when the time first reaches 1:59:59
SET – When the SET bit is a zero, the update transfer
functions normally by advancing the counts once per
second.WhentheSETbitiswrittentoaone, anyupdate
transfer is inhibited and the program can initialize the
time and calendar bytes without an update occurring in
012496 9/20
DS1385/DS1387
AMitchangesto1:00:00AM. Thesespecialupdatesdo
not occur when the DSE bit is a zero. This bit is not af-
fected by internal functions.
internal lithium energy source is indicated and both the
contents of the RTC data and RAM data are question-
able.
REGISTER C
MSB
BIT 6 THROUGH BIT 0 –TheremainingbitsofRegister
D are reserved and not usable. They cannot be written
and, when read, they will always read zero.
LSB
BIT 0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
IRQF
PF
AF
UF
0
0
0
0
4K X 8 RAM
IRQF - The Interrupt Request Flag (IRQF) bit is set to a
one when one or more of the following are true:
TheDS1385/DS1387 provides 4K x 8 of on–chip SRAM
which is controlled as nonvolatile storage sustained
from a lithium battery. On power–up, the RAM is taken
out of write–protect status by the internal power OK sig-
nal (POK) generated from the write protect circuitry.
The POK signal becomes active at 4.25 volts (typical).
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
i.e., IRQF = (PF • PIE) + (AF • AIE) + (UF • UIE)
Any time the IRQF bit is a one, the IRQ pin is driven low.
All flag bits are cleared after Register C is read by the
program.
The on–chip 4K x 8 nonvolatile SRAM is accessed via
theeightmultiplexed address/data lines AD7–AD0. Ac-
cess to the SRAM is controlled by three on–chip latch
registers. Two registers are used to hold the SRAM ad-
dress and the third register is used to hold read/write
data. The SRAM address space is from 000H to FFFH.
PF – The Periodic Interrupt Flag (PF) is a read–only bit
which is set to a one when an edge is detected on the
selected tap of the divider chain. The RS3 through RS0
bits establish the periodic rate. PF is set to a one inde-
pendent of the state of the PIE bit. When both PF and
PIE are ones, the IRQ signal is active and will set the
IRQF bit. The PF bit is cleared by a software read of
Register C.
Four control signals, AS0, AS1, OER, and WER, are
used to access the 4K x 8 SRAM. The address latches
areloaded from the address/data bus in response to ris-
ing edge signals applied to the Address Strobe 0 (AS0)
and Address Strobe 1 (AS1) signals. AS0 is used to
latch the lower 8–bits of address, and AS1 is used to
latch the upper 4–bits of address. It is necessary to
meet the setup and hold times given in the Electrical
Specifications with valid address information in order to
properly latch the address. If the upper or lower order
address is correct from a prior cycle, it is not necessary
to repeat the address latching sequence.
AF – A one in the Alarm Interrupt Flag (AF) bit indicates
that the current time has matched the alarm time. If the
AIEbitisalsoaone, theIRQpinwillgolowandaonewill
appear in the IRQF bit. A read of Register C will clear
AF.
UF – The Update Ended Interrupt Flag (UF) bit is set af-
tereachupdatecycle. WhentheUIEbitissettoone,the
one in UF causes the IRQF bit to be a one which will as-
sert the IRQ pin. UF is cleared by reading Register C.
A write operation requires valid data to be placed on the
bus (AD7–AD0) followed by the activation of the Write
Enable RAM (WER) line. Data on the bus will be written
to the RAM provided that the write timing specifications
are met. During a read cycle, the Output Enable RAM
(OER) signal is driven active. Data from the RAM will
becomevalidonthebusprovidedthattheRAMreadac-
cess timing specifications are met. The WER and OER
signalsshouldneverbeactiveatthesametime. Inaddi-
tion, access to the clock/calendar registers and user
RAM (via CS) must not be attempted when the 4K x 8
RAM is being accessed. The RAM is enabled when ei-
ther WER or OER is active. CS is only used for the ac-
cess of the clock calendar registers (including the ex-
tended Dallas registers) and the 50–bytes of user RAM.
BIT 3 THROUGH BIT 0 – These are reserved bits of the
statusRegisterC. Thesebitsalwaysreadzeroandcan-
not be written.
REGISTER D
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
VRT
0
0
0
0
0
0
0
VRT – The Valid RAM and Time (VRT) bit is set to the
one state by Dallas Semiconductor Corporation prior to
shipment. Thisbitisnotwritableandshouldalwaysbea
one when read. If a zero is ever present, an exhausted
012496 10/20
DS1385/DS1387
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground
Operating Temperature
–0.3V to +7.0V
0°C to 70°C
Storage Temperature
DS1387: –40°C to +70°C
DS1385: –55°C to +125°C
260°C for 10 seconds
Soldering Temperature
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0°C to 70°C)
PARAMETER
Power Supply Voltage
Input Logic 1
SYMBOL
MIN
4.5
TYP
MAX
UNITS
NOTES
V
CC
5.0
5.5
V
V
V
V
1
1
1
9
V
IH
2.2
V
+0.3
CC
Input Logic 0
V
IL
–0.3
2.5
+0.8
Battery Voltage
V
BAT
3.7
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C)
PARAMETER
SYMBOL
MIN
TYP
35
1
MAX
50
UNITS
mA
NOTES
Power Supply Current
Standby Current CS, OER and
I
I
2
6
CC1
CC2
5.0
mA
WER = V –0.3 volt
CC
Input Leakage
I
–1.0
–1.0
–1.0
+1.0
+1.0
µA
µA
3
3
IL
I/O Leakage
I
LO
Output @ 2.4 volts
Output @ 0.4 volts
I
mA
mA
1, 4
1
OH
I
OL
2.0
012496 11/20
DS1385/DS1387
RTC AC TIMING CHARACTERISTICS
(0°C to 70°C; VCC = 4.5V to 5.5V)
PARAMETER
SYMBOL
MIN
305
125
150
TYP
MAX
UNITS
ns
NOTES
Cycle Time
t
DC
CYC
Pulse Width, RD/WR Low
Pulse Width, RD/WR High
Input Rise and Fall Time
PW
ns
EH
PW
ns
EL
t , t
R
30
80
ns
F
Chip Select Setup Time Before
WR or RD
t
20
ns
CS
Chip Select Hold Time
Read Data Hold Time
Write Data Hold Time
t
0
10
0
ns
ns
ns
ns
CH
t
DHR
t
DHW
Muxed Address Valid Time to
ALE Fall
t
30
ASL
AHL
ASD
Muxed Address Hold Time from
ALE Fall
t
10
25
ns
ns
RD or WR High Setup to ALE
Rise
t
Pulse Width ALE High
PW
60
40
ns
ns
ns
ns
µs
ASH
ALE Low Setup to RD or WR Fall
Output Data Delay Time from RD
Data Setup Time to Write
IRQ Release from RD
t
ASED
t
20
120
2
5
DDR
t
100
DSW
t
IRD
012496 12/20
DS1385/DS1387
DS1385/DS1387 BUS TIMING FOR WRITE CYCLE TO RTC
t
CYC
PW
ASH
ALE
WR
t
ASED
t
t
ASD
PW
EH
PW
EL
ASD
RD
CS
t
CH
t
t
DSW
CS
t
AHL
t
DHW
t
ASL
AD0–AD7
DS1385/DS1387 BUS TIMING FOR READ CYCLE TO RTC
t
CYC
PW
ASH
ALE
RD
t
ASED
t
t
ASD
PW
EH
PW
EL
ASD
WR
CS
t
CH
t
DDR
t
CS
t
AHL
t
DHR
t
ASL
AD0–AD7
t
IRD
IRQ
012496 13/20
DS1385/DS1387
4K X 8 AC TIMING CHARACTERISTICS
(0°C to 70°C; VCC = 5V + 10%)
PARAMETER
SYMBOL
MIN
55
0
TYP
MAX
UNITS
ns
NOTES
Address Setup Time
Address Hold Time
Data Setup Time
t
AS
AH
DS
DH
t
t
ns
75
0
ns
Data Hold Time
t
ns
Output Enable Access Time
Write Pulse Width
t
200
50
ns
7
OEA
t
200
200
ns
WP
OER Pulse Width
t
ns
RP
OER to Output in High Z
AS0, AS1 Pulse Width
AS0, AS1 High to OER Low
AS0, AS1 High to WER Low
t
ns
OEZ
ASP
ASO
t
75
20
20
ns
t
ns
t
ns
ASW
BUS TIMING FOR READ CYCLE TO 4K X 8 NV SRAM
t
ASP
WER = V
AS0
IH
t
ASP
AS1
t
ASO
t
RP
OER
t
AH
t
OEA
t
AS
t
t
t
AH
OEZ
AS
DATA OUT
VALID
LOW ADDRESS VALID
UPPER ADDRESS VALID
AD0–AD7
012496 14/20
DS1385/DS1387
BUS TIMING FOR WRITE CYCLE TO 4K X 8 SRAM
t
OER = V
ASP
IH
AS0
t
ASP
AS1
t
ASW
t
WP
WER
t
t
AH
AH
t
t
t
t
DH
AS
AS
DS
AD0–AD7
LOW ADDRESS VALID
UPPER ADDRESS VALID
DATA IN VALID
POWER–UP CONDITION
CE
V
IH
t
REC
4.5V
4.25V
4.0V
V
CC
t
R
POWER FAIL
012496 15/20
DS1385/DS1387
POWER–DOWN CONDITION
CE
V
IH
t
PF
t
F
V
CC
4.5V
4.25V
4.0V
V
t
DR
BAT
t
FB
POWER FAIL
POWER–UP POWER–DOWN TIMING
(tA = 25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
ns
NOTES
CE High to Power Fail
Recovery at Power Up
t
PF
0
t
150
ms
REC
V
CC
V
CC
V
CC
Slew Rate Power Down
Slew Rate Power Down
Slew Rate Power Up
t
300
10
0
µs
F
4.0 <V < 4.5V
CC
t
FB
µs
µs
3.0 <V < 4.0V
CC
t
R
4.5V>V >4.0V
CC
Expected Data Retention
t
10
years
8
DR
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery back–up
mode.
CAPACITANCE
PARAMETER
(tA = 25°C)
SYMBOL
MIN
TYP
MAX
12
UNITS
pF
NOTES
Input Capacitance
Output Capacitance
C
IN
C
12
pF
OUT
012496 16/20
DS1385/DS1387
NOTES:
1. All voltages are referenced to ground.
2. All outputs are open.
3. Applies to the AD0–AD7 pins and the SQW pin when each is in the high impedance state.
4. The IRQ pin is open drain.
5. Measured with a load as shown in Figure 4.
6. All other inputs at CMOS levels.
7. Measured with a load as shown in Figure 4.
8. The real–time clock will keep time to an accuracy of ±1 minute per month during data retention time for the
period of t
.
DR
9. Applies to DS1385 and DS1385S only.
OUTPUT LOAD Figure 4
+5 VOLTS
1.1KΩ
D.U.T.
50 pF
680W
012496 17/20
DS1385/DS1387
DS1385 24–PIN DIP
PKG
DIM
24–PIN
MIN
MAX
B
D
A IN.
MM
1.245
31.62
1.270
32.26
B IN.
MM
0.530
13.46
0.550
13.97
1
C IN.
MM
0.140
3.56
0.160
4.06
A
D IN.
MM
0.600
15.24
0.625
15.88
E IN.
MM
0.015
0.38
0.050
1.27
F IN.
MM
0.120
3.05
0.145
3.68
G IN.
MM
0.090
2.29
0.110
2.79
C
F
H IN.
MM
0.625
15.88
0.675
17.15
J IN.
MM
0.008
0.20
0.012
0.30
E
K
G
K IN.
MM
0.015
0.38
0.022
0.56
J
H
012496 18/20
DS1385/DS1387
DS1385S 28–PIN SOIC
K
G
PKG
DIM
28–PIN
MIN
MAX
A IN.
MM
0.706
17.93
0.728
18.49
B IN.
MM
0.338
8.58
0.350
8.89
C IN.
MM
0.086
2.18
0.110
2.79
D IN.
MM
0.020
0.58
0.050
1.27
E IN.
MM
0.002
0.05
0.014
0.36
F IN.
MM
0.090
2.29
0.124
3.15
C
0.050
1.27
BSC
G IN.
MM
A
H IN.
MM
0.460
11.68
0.480
12.19
E
J IN.
MM
0.006
0.15
0.013
0.33
K IN.
MM
0.014
0.36
0.020
0.51
B
H
F
0–8 deg. typ.
J
D
012496 19/20
DS1385/DS1387
DS1387 24–PIN 740 MIL FLUSH ENCAPSULATED
13
24
PKG
DIM
24–PIN
MIN
MAX
A IN.
MM
1.320
33.53
1.335
33.91
1
12
A
B IN.
MM
0.720
18.29
0.740
18.80
C IN.
MM
0.345
8.76
0.370
9.40
D IN.
MM
0.100
2.54
0.130
3.30
E IN.
MM
0.015
0.38
0.030
0.89
C
E
F IN.
MM
0.110
2.79
0.140
3.56
F
G IN.
MM
0.090
2.29
0.110
2.79
D
K
G
H IN.
MM
0.590
14.99
0.630
16.00
11 EQUAL SPACES AT
.100 .010 TNA
±
J IN.
MM
0.008
0.20
0.012
0.30
K IN.
MM
0.015
0.38
0.021
0.53
NOTE:
PINS 2, 3, 16, AND 20 ARE MISSING BY DESIGN.
J
H
B
012496 20/20
相关型号：
©2020 ICPDF网 联系我们和版权申明