DS4000GW/BGA [DALLAS]
Oscillator, 10MHz Min, 19.44MHz Max, 16.8MHz Nom,;
| 型号： | DS4000GW/BGA |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Oscillator, 10MHz Min, 19.44MHz Max, 16.8MHz Nom, |
| 文件： | 总14页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS4000
Digitally Controlled (DC)-TCXO
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT (Top View)
C Aging ≤1.0ppm per year
C Frequency stability ±1.0ppm from -40°C to
+85°C
6
5
4
3
2
1
F2
SCL
V
F1
C Frequency versus supply stability of ±1.0ppm
per volt
A0
VOSC
GND
GND
GNDOSC
N.C.
ꢀ Base frequency is digitally tunable by
±6.0ppm
GND
ꢀ One fixed-frequency output and one
(n + 1) or 2(n + 1) division of the base
frequency output.
BGA
PIN DESCRIPTION
C Temperature measurements from -40CL to
+85LC with 10-bit/+0.25°C resolution and
±3°C accuracy
VCC
- Power Supply
GND
VOSC
GNDOSC
SDA
SCL
- Ground
- Oscillator Power Supply
- Oscillator Ground
C 2-wire serial interface
- 2-Wire Serial-Data Input/Output
- 2-Wire Serial Clock
APPLICATIONS
C Reference Oscillators in PLL Circuits
C Global Positioning Systems
C SATCOM
A0
- 2-Wire Serial-Address Input
- DC-TCXO Outputs
F2, F1
N.C.
- No Connection (do not connect)
C Telecom
C Wireless Base Stations
ORDERING INFORMATION
PIN-
FREQUENCY
PART
TOP MARK
PACKAGE
12 BGA
12 BGA
12 BGA
12 BGA
12 BGA
12 BGA
12 BGA
12 BGA
DESIGNATOR (MHz)
10.00000
DS4000A0/BGA
DS4000CW/BGA
DS4000D0BGA
DS4000EC/BGA
DS4000G0/BGA
DS4000GF/BGA
DS4000GW/BGA
DS4000KI/BGA
DS4000A0
DS4000CW
DS4000D0
DS4000EC
DS4000G0
DS4000GF
DS4000GW
DS4000KI
12.80000
13.00000
14.31818
16.00000
16.38400
16.80000
19.44000
DESCRIPTION
The DS4000 digitally controlled temperature-compensated crystal oscillator (DC-TCXO) features a
digital temperature sensor, one fixed-frequency temperature-compensated square-wave output (F1), one
programmable temperature-compensated square-wave output (F2), and digital communication for
frequency tuning (SDA, SCL).
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: http://www.maxim-ic.com/errata.
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072402
DS4000
SIGNAL DESCRIPTIONS
VCC, GND – DC power is provided to the device on these pins.
VOSC, GNDOSC – DC power is provided to the oscillator on these pins.
SDA (Serial-Data Input/Output) – SDA is the input/output pin for the 2-wire serial interface. The SDA
pin is open drain and requires an external pullup resistor.
SCL (Serial-Clock Input) – SCL is used to synchronize data movement on the serial interface. The SCL
pin is open drain and requires an external pullup resistor.
A0 – 2-wire slave address input. This pin is used to configure the slave address.
F2, F1 – DC-TCXO frequency outputs.
N.C. – Do not connect.
Figure 1. BLOCK DIAGRAM
VOSC
VCC
TEMPERATURE-
F2
F1
COMPENSATED
CRYSTAL
OSCILLATOR
SDA
SCL
A0
2-WIRE
SERIAL
INTERFACE
DIGITAL
TEMPERATURE
SENSOR
DS4000
GND
GNDOSC
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DS4000
TEMPERATURE-COMPENSATED CRYSTAL OSCILLATOR
The DS4000 can either function as a standalone TCXO or as a digitally controlled TCXO. When used as
a standalone TCXO, the only requirements needed to function properly are power, ground, and an output.
However, the 2-wire interface must be used to tune (push and pull) the crystal.
The DS4000 is capable of supplying two different outputs, F1 and F2.
1) F1 is the base frequency of the crystal unit inside of the device. The output type is a CMOS square
wave.
2) F2 is a programmable frequency output. The frequency select register can program this output to an
integer division of the base (F1) frequency. The duty cycle (DC) bit determines if the output is an
n + 1 or a 2(n + 1) division of F1.
F2 FREQUENCY SELECT REGISTER (FSR) (5Dh)
BIT 7
D7
BIT 6
D6
BIT 5
D5
BIT 4
D4
BIT 3
D3
BIT 2
D2
BIT 1
D1
BIT 0
D0
F2 = F1 / (FSR value + 1); with DC = 0
F2 = F1 / [2 x (FSR value + 1)]; with DC = 1
TCXO CONTROL REGISTER (60h)
BIT 7
X
BIT 6
X
BIT 5
X
BIT 4
X
BIT 3
F2OE
BIT 2
F1OE
BIT 1
FT
BIT 0
DC
DC – Duty Cycle Bit. If 50% duty cycle is desired, then this bit must be set to logic 1. The default
condition at power-up is logic 0.
FT – This bit must be programmed by the user to a 0.
F1OE – F1 Output Enable Bit. This bit allows the user to disable/enable the F1 output.
F2OE – F2 Output Enable Bit. This bit allows the user to disable/enable the F2 output.
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DS4000
Digital Tuning the Base Crystal Frequency
When using the 2-wire interface for tuning the base frequency, the frequency tuning register is used. The
frequency tuning register contains two’s complement data. The data is used to add or subtract an offset
from the crystal loading register. When the tuning register is programmed with a value, the next
temperature-update cycle sums the programmed value with the factory-compensated value. This allows
the user/system to digitally control the base frequency by a microcontroller using the 2-wire protocol.
FREQUENCY TUNING REGISTER (66h)
BIT 7
SIGN
BIT 6
FO6
BIT 5
FO5
BIT 4
FO4
BIT 3
FO3
BIT 2
FO2
BIT 1
FO1
BIT 0
FO0
FOS[6:0] – Frequency Offset. These bits are used to tune the base crystal frequency. Each bit represents
approximately 0.05ppm and, therefore, for a value of 07FH, pushes or pulls the base frequency by
approximately 6.35ppm.
SIGN – Sign Bit. This bit is used to determine whether to add or subtract the frequency offset from the
crystal loading.
Table 1. FREQUENCY TUNING RELATIONSHIP
CALCULATED
DIGITAL DATA
(Binary)
DIGITAL DATA
(hex)
FREQUENCY OFFSET
(ppm)
+6.35
+5.0
+3.3
+1.2
+0.05
0.0
0111 1111
0110 0100
0100 0010
0001 0111
0000 0001
0000 0000
1111 1111
1110 1000
1011 0011
1001 1100
1000 0000
7Fh
64h
42h
17h
01h
00h
FFh
E8h
B3h
9Ch
80h
-0.05
-1.2
-3.3
-5.0
-6.35
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DS4000
DIGITAL TEMPERATURE SENSOR
The digital temperature sensor provides 10-bit temperature readings that indicate the temperature of the
device. Temperature readings are communicated from the DS4000 over a 2-wire serial interface. No
additional components are required. The DS4000 has an external address bit that allows a user to choose
the slave address from two possible values.
Overview
The factory-calibrated temperature sensor requires no external components. Upon power-up, the DS4000
starts performing temperature conversions with a resolution of 10 bits (+0.25°C resolution). Following an
8-bit command protocol, temperature data can be read over the 2-wire interface. The host can periodically
read the value in the temperature register, which contains the last completed conversion. As conversions
are performed in the background, reading the temperature register does not affect the conversion in
progress.
Reading Temperature
The DS4000 measures temperature through the use of an on-chip temperature-measurement technique
with an operation range from -40°C to +85°C. The device performs continuous conversions with the most
recent result being stored in the temperature register. The digital temperature is retrieved from the
temperature register using the READ TEMPERATURE command, as described in detail in the following
paragraphs.
Table 2 describes the exact relationship of output data to measured temperature. The data is transmitted
serially over the 2-wire serial interface, MSB first. The MSB of the temperature register contains the
“sign” (S) bit, denoting whether the temperature is positive or negative. For Fahrenheit usage, a lookup
table or conversion routine must be used.
TEMPERATURE/DATA RELATIONSHIP (UNIT = LC)
MSB (64h)
BIT 7
S
BIT 6
26
BIT 5
25
BIT 4
24
BIT 3
23
BIT 2
22
BIT 1
21
BIT 0
20
LSB (65h)
BIT 7
BIT 6
2-2
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
2-1
Table 2. TEMPERATURE/DATA RELATIONSHIP
TEMPERATURE
DIGITAL OUTPUT
DIGITALOUTPUT
(°C)
+85
+75
+0.5
0
-0.5
-20
-40
(Binary)
(hex)
0101 0101 0000 0000
0100 1011 0000 0000
0000 0000 1000 0000
0000 0000 0000 0000
1111 1111 1000 0000
1110 1100 0000 0000
1101 1000 0000 0000
5500h
4B00h
0080h
0000h
FF80h
EC00h
D800h
Note: Internal power dissipation raises the temperature above the ambient. The delta between ambient and the die temperature depends on
power consumption, PC board layout, and airflow.
5 of 14
DS4000
Read Temperature
This command reads the last temperature conversion result from the temperature register in the format
described in the Reading Temperature section. If an application can accept temperature resolutions of
+1.0°C, then the master can read the first data byte and follow with a NACK and STOP. For higher
resolution, both bytes must be read.
Table 3. COMMAND SET
2-WIRE BUS DATA
INSTRUCTION
FUNCTION
PROTOCOL
AFTER ISSUING
PROTOCOL
Read or write 1 data
byte
NOTES
Frequency Select
Register
Defines F2 output frequency
5Dh
60h
64h
66h
2
2
TCXO Control
Register
Enables/disables F1 and F2;
sets duty cycle of F2
Read or write 1 data
byte
Read Temperature
Reads 10-bit temperature register
Read 1 or 2 data bytes
1, 2
2
Frequency Tuning
Register
Digitally adds/subtracts an offset
from oscillator
Read or write 1 data
byte
NOTES:
1) If the user only desires 8-bit thermometer readings, the master can read one data byte, and follow with
a NACK and STOP. If higher resolution is required, both bytes must be read.
2) The slave does not increment the internal address pointer between instructions. The address pointer
must be reinitialized after each access.
6 of 14
DS4000
2-WIRE SERIAL INTERFACE
The DS4000 supports a bidirectional 2-wire serial bus and data transmission protocol. The bus must be
controlled by a master device, which generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS4000 operates as a slave on the
2-wire bus. The DS4000 works in a regular mode (100kHz clock rate) and a fast mode (400kHz clock
rate), which are defined within the bus specifications. Connections to the bus are made by the open-drain
I/O signals SDA and SCL.
The following bus protocol has been defined (Figure 1):
C Data transfer can be initiated only when the bus is not busy.
C During data transfer, the data signal must remain stable whenever the clock signal is HIGH. Changes
in the data signal while the clock signal is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy: Both data and clock signals remain HIGH.
Start Data Transfer: A change in the state of the data signal, from HIGH to LOW, while the clock line
is HIGH, defines the START condition.
Stop Data Transfer: A change in the state of the data signal, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data Valid: The state of the data signal represents valid data when, after a START condition, the data
signal is stable for the duration of the HIGH period of the clock signal. The data on the line must be
changed during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit.
Acknowledge: Each receiving device, when addressed, is required to generate an acknowledge after
reception of each byte. The master device must generate an extra clock pulse that is associated with this
acknowledge bit.
A device that acknowledges must pull down the serial data (SDA) signal during the acknowledge clock
pulse in such a way that the SDA signal is stable LOW during the HIGH period of the acknowledge-
related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an
end-of-data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of
the slave. In this case, the slave must leave the data signal HIGH to enable the master to generate the
STOP condition.
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DS4000
Figure 1. DATA TRANSFER ON 2-WIRE SERIAL BUS
SDA
MSB
SLAVE
ADDRESS
3-5
R/W BIT
8
ACKNOWLEDGEMENT
SIGNAL FROM
RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM
RECEIVER
SCL
1
2
6
7
9
1
2
3-7
8
9
ACK
ACK
REPEATED IF
START
MORE BYTES ARE
TRANSFERRED
STOP CONDITION
CONDITION
OR REPEATED
START CONDITION
Data Transfer
Figures 2 and 3 detail how data transfer is accomplished on the 2-wire bus.
Depending on the R/ W bit in the transmission protocols as shown, two types of data transfer are possible:
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte. Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte
(the slave address). The slave then returns an acknowledge bit. Next follows a number of data bytes
transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes
other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The
master device generates all of the serial clock pulses and the START and STOP conditions. A transfer
is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus is not released.
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DS4000
Slave Address
The slave address is the first byte received following the START condition generated by the master
device. The address byte consists of a 7-bit slave address and the R/ W direction bit. The DS4000 slave
address is set to 100010A0, where A0 is externally hardwired to a HIGH or LOW state. This allows design
flexibility to set the slave’s address to one of two possible address locations. The last bit following the
slave address is the direction bit (R/ W ) and defines the operation to be performed by the master, transmit
data (R/ W = 0), or receive data (R/ W = 1). Following the START condition, the DS4000 monitors the
SDA bus by checking the slave address being transmitted. Upon receiving the proper slave address and
R/ W bit, the slave device outputs an acknowledge signal on the SDA line regardless of the operation
mode.
The DS4000 can operate in the following two modes:
1) Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by the hardware after
reception of the slave address and direction bit (Figure 2).
2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is
transmitted on SDA by the DS4000 while the serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer (Figure 3).
Figure 2. DATA WRITE: SLAVE RECEIVER MODE
<SLAVE ADDRESS>
<DATA ADDRESS>
<DATA (n)>
R/W
S
100010A0
0
A
XXXXXXXX
A
XXXXXXXX
A
P
S = START
A = ACKNOWLEDGE
P = STOP
Figure 3. DATA READ: SLAVE TRANSMITTER MODE
<SLAVE ADDRESS>
R/W
<DATA (n)>
<DATA (n + 1)>
<DATA (n + 2)>
<DATA (n + X)>
S
100010A0
1
A
XXXXXXXX
A
XXXXXXXX
A
XXXXXXXX
A
XXXXXXXX
A
P
S = START
A = ACKNOWLEDGE
P = STOP
A = NOT ACKNOWLEDGE
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DS4000
ABSOLUTE MAXIMUM RATINGS*
Voltage Range on Any Pin Relative to Ground
Operating Temperature Range
-0.3V to +6.0V
-40LC to +85LC
-55LC to +85LC
Storage Temperature Range
Soldering Temperature Range
See IPC/JEDEC J-STD-020A (2x max)
* This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40LC to +85LC)
PARAMETER
SYMBOL
MIN
4.75
4.75
2.2
TYP
MAX
5.25
UNITS NOTES
Supply Voltage
VCC
5.0
V
V
V
V
1, 2
1, 2
1
Oscillator Supply Voltage
Input Logic High
VOSC
VIH
5.0
5.25
VCC + 0.3
+0.8
Input Logic Low
VIL
-0.3
1
DC ELECTRICAL CHARACTERISTICS
(VCC = 4.75 to 5.25V, TA = -40LC to +85LC)
PARAMETER
Active Supply Current
Active Oscillator Supply Current
Output Logic High 2.4V
Output Logic Low 0.4V
Input Leakage
SYMBOL
MIN
TYP
1.5
MAX
2
UNITS NOTES
ICC
mA
mA
mA
mA
ꢁA
ꢁA
ms
3, 4
3, 4
1
IOSC
3.5
5.5
IOH
-1
IOL
4
1
1
ILI
I/O Leakage
ILO
1
Temperature Conversion Time
tCONVT
250
300
3
10 of 14
DS4000
TCXO AC ELECTRICAL CHARACTERISTICS
(VCC = 4.75 to 5.25V, TA = -40LC to +85LC)
PARAMETER
SYMBOL CONDITION MIN TYP MAX UNITS NOTES
F1
Output Frequency
CMOS
10
20
MHz
5
F2
Frequency Stability vs.
Temperature
ppm
ppm/V
ppm/Yr
ꢂF/TA
ꢂF/V
ꢂF/Yr
-1.0
+1.0
Voltage
Aging
F1, F2 Rise and Fall
tR, tF
4
ns
Time, 10% to 90%
Max Output Capacitive
Load
CL
10
60
pF
%
Duty Cycle
tW / t
40
50
Phase Noise F1 Output,
10kHz
-130
dBc/Hz
6
ꢃ
N
11 of 14
DS4000
2-WIRE SERIAL INTERFACE
AC ELECTRICAL CHARACTERISTICS
(VCC = 4.75 to 5.25V, TA = -40LC to +85LC)
PARAMETER
SYMBOL
CONDITION
MIN
TYP MAX UNITS NOTES
Fast mode
Standard mode
400
SCL Clock Frequency
fSCL
0
kHz
100
Bus Free Time
Fast mode
1.3
4.7
0.6
Between a STOP and
START Condition
tBUF
ꢁs
Standard mode
Fast mode
Hold Time (Repeated)
START Condition
tHD:STA
7
ꢁs
ꢁs
ꢁs
Standard mode
Fast mode
4.0
1.3
4.7
Low Period of SCL
Clock
tLOW
Standard mode
Fast mode
0.6
4.0
0.6
High Period of SCL
Clock
tHIGH
Standard mode
Fast mode
Setup Time for a
Repeated START
Condition
tSU:STA
tHD:DAT
tSU:DAT
ꢁs
ꢁs
ns
Standard mode
4.7
0
Fast mode
Standard mode
Data Hold Time
0.9
8
9
Fast mode
100
250
Data Setup Time
Standard mode
Fast mode
300
1000
300
Rise Time of Both
SDA and SCL
20 + 0.1CB
20 + 0.1CB
tR
tF
ns
ns
ꢁs
9
Standard mode
Fast mode
Fall Time of Both
SDA and SCL
10
Standard mode
Fast mode
1000
0.6
4.0
Setup Time for STOP
Condition
tSU:STO
Standard mode
Capacitive Load for
Each Bus Line
CB
CI
400
pF
pF
10
Input Capacitance
5
12 of 14
DS4000
Figure 4. TIMING DIAGRAM
NOTES:
1) All voltages are referenced to ground.
2) For ±10% operating range, contact factory.
3) Typical values are at +25LC and nominal supplies.
4) These parameters are measured with the outputs disabled.
5) F1 is the base frequency as defined by the package markings. F2 is a programmable frequency output.
The output frequency of F2 is derived from the base frequency, F1, by programming the F2 frequency
select register and duty cycle (DC) bit in the TCXO control register. The minimum output frequency
is F1 / (28 + 1) with DC = 0 and F1 / [2 x (28 + 1)] with DC = 1.
6) 10MHz, 5V, +25°C with one of the two outputs enabled.
7) After this period, the first clock pulse is generated.
8) The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
9) A fast-mode device can be used in a standard mode system, but the requirement tSU:DAT >250ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line tRMAX + tSU:DAT (1000 + 250 = 1250ns) before the SCL line is released.
10) CB: Total capacitance of one bus line in pF.
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DS4000
DS4000 BGA PACKAGE DRAWING
Note: The BGA is solder-masked defined.
14 of 14
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