DS87C530-KCL_技术文档

DS87C530

PRELIMINARY

DS87C530

EPROM Micro with Real Time Clock

FEATURES

PACKAGE OUTLINE

7

1

47

• 80C52 Compatible

–

8051 Instruction set

8

46

Four 8–bit I/O ports

Three 16–bit timer/counters

256 bytes scratchpad RAM

• Large On–chip Memory

–

16KB EPROM (OTP)

1KB extra on–chip SRAM for MOVX

DALLAS

DS87C530

TM

• ROMSIZE

Feature

–

Selects effective on–chip ROM size from

0 to 16KB

20

34

–

Allows access to entire external memory map

Dynamically adjustable by software

21

33

52–PIN PLCC

52–PIN CER QUAD

Useful as boot block for external Flash

39

27

• Nonvolatile Functions

40

26

–

On–chip Real Time Clock w/ Alarm Interrupt

Battery backup support of 1KB SRAM

• High–Speed Architecture

DALLAS

DS87C530

–

4 clocks/machine cycle (8051 = 12)

Runs DC to 33 MHz clock rates

Single–cycle instruction in 121 ns

Dual data pointer

14

52

Optional variable length MOVX to access

fast/slow RAM /peripherals

13

52–PIN TQFP OUTLINE

• Power Management Mode

–

Programmable clock source saves power

DESCRIPTION

The DS87C530 is an 8051 compatible microcontroller

basedontheDallasHighSpeedcore. Itusesfourclocks

per instruction cycle instead of 12 used by the standard

8051. It also provides a unique mix of peripherals not

widely available on other processors. They include an

on–chip Real Time Clock (RTC) and battery back up

support for an on–chip 1K x 8 SRAM. The new Power

Management Mode allows software to select reduced

power operation while still processing.

Runs from (crystal/64) or (crystal/1024)

Provides automatic hardware and software exit

• EMI Reduction Mode disables ALE

• High integration controller includes:

–

Power–fail reset

Early–warning power–fail interrupt

Programmable Watchdog timer

• Two full–duplex hardware serial ports

• 14 total interrupt sources with 6 external

patents and other intellectual property rights, please refer to

Dallas Semiconductor data books.

022197 1/40

DS87C530

A combination of high performance microcontroller

core, real time clock, battery backed SRAM, and power

management makes the DS87C530 ideal for instru-

ments and portable applications. It also provides sev-

eral peripherals found on other Dallas High–Speed

Microcontrollers. These include two independent serial

ports, two data pointers, on–chip power monitor with

brown–out detection and a watchdog timer.

four clocks per machine cycle, the PMM runs the pro-

cessor at 64 or 1024 clocks per cycle. There is a corre-

sponding drop in power consumption when the proces-

sor slows.

Note: The DS87C530 is a monolithic device. A user

must supply an external battery or super–cap and a

32.768 KHz timekeeping crystal to have permanently

powered timekeeping or nonvolatile RAM. The

DS87C530 provides all the support and switching cir-

cuitry needed to manage these resources.

Power Management Mode (PMM) allows software to

select a slower CPU clock. While default operation uses

ORDERING INFORMATION

PART NUMBER

DS87C530–QCL

DS87C530–QNL

DS87C530–KCL

DS87C530–ECL

DS87C530–ENL

PACKAGE

52–pin PLCC

MAX. CLOCK SPEED

33 MHz

TEMPERATURE RANGE

0°C to 70°C

52–pin PLCC

33 MHz

–40°C to +85°C

0°C to 70°C

52–pin windowed CERQUAD

52–PIN TQFP

33 MHz

0°C to 70°C

52–PIN TQFP

33 MHz

–40°C to +85°C

DS87C530 BLOCK DIAGRAM Figure 1

RTCX1 RTCX2 GND

V

CC2

V

BAT

V

BATTERY

CONTROL

REAL TIME

CLOCK

CC

1K X 8

SRAM

ACCUMULATOR

ALU REG. 1

PSW

B REGISTER

ALU REG. 2

16K X 8

OTP

ROM

STACK POINTER

ALU

DPTR1

PC ADDR. REG.

BUFFER

INTERRUPT

LOGIC

ADDRESS BUS

256 BYTES

SFR 8 RAM

PC INCREMENT

PROG. COUNTER

DPTR0

INTERRUPT REG.

INSTRUCTION

DECODE

POWER CONTROL REG.

WATCHDOG REG.

CLOCKS AND

MEMORY CONTROL

RESET

V

POWER MONITOR

CC

CONTROL

OSCILLATOR

WATCHDOG TIMER

022197 2/40

DS87C530

PIN DESCRIPTION Table 1

PLCC

TQFP

SIGNAL

NAME

DESCRIPTION

– +5V. Processor power supply.

52

1,25

29

45

18, 46

22

V

CC

V

CC

GND

GND – Processor digital circuit ground.

V – +5V Real Time Clock supply.

CC2

V

CC2

26

19

GND2

RST

GND2 – Real Time Clock circuit ground.

12

5

RST – Input. The RST input pin contains a Schmitt voltage input to recognize

external active high Reset inputs. The pin also employs an internal pull–down

resistor to allow for a combination of wired OR external Reset sources. An RC

isnotrequiredforpower–up,astheDS87C530providesthisfunctioninternally.

23

24

16

17

XTAL2

XTAL1

XTAL1, XTAL2 – The crystal oscillator pins XTAL1 and XTAL2 provide support

for parallel resonant, AT cut crystals. XTAL1 acts also as an input if there is an

external clock source in place of a crystal. XTAL2 serves as the output of the

crystal amplifier.

38

39

31

32

PSEN

ALE

PSEN – Output. The Program Store Enable output. This signal is commonly

connected to optional external ROM memory as a chip enable. PSEN will pro-

vide an active low pulse and is driven high when external ROM is not being

accessed.

ALE – Output. The Address Latch Enable output functions as a clock to latch

the external address LSB from the multiplexed address/data bus on Port 0.

Thissignaliscommonlyconnectedtothelatchenableofanexternal373family

transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles and a period of

four XTAL1 cycles. ALE is forced high when the DS87C530 is in a Reset condi-

tion. ALE can be disabled by writing ALEOFF=1 (PMR.Z). When ALEOFF=1,

ALE is forced high. ALE operates independently of ALEOFF during external

memory accesses.

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

P0.0 (AD0) Port 0 (AD0–7) – I/O. Port 0 is an open–drain 8–bit bi–directional I/O port. As

P0.1 (AD1) an alternate function Port 0 can function as the multiplexed address/data bus

P0.2 (AD2) to access off–chip memory. During the time when ALE is high, the LSB of a

P0.3 (AD3) memory address is presented. When ALE falls to a logic 0, the port transitions

P0.4 (AD4) to a bi–directional data bus. This bus is used to read external ROM and read/

P0.5 (AD5) write external RAM memory or peripherals. When used as a memory bus, the

P0.6 (AD6) port provides active high drivers. The reset condition of Port 0 is tri–state.

P0.7 (AD7) Pull–up resistors are required when using Port 0 as an I/O port.

3–10

48–52, P1.0 – P1.7 Port 1 – I/O. Port 1 functions as both an 8–bit bi–directional I/O port and an

1–3

alternate functional interface for Timer 2 I/O, new External Interrupts, and new

SerialPort1. TheresetconditionofPort1iswithallbitsatalogic1. Inthisstate,

a weak pull–up holds the port high. This condition also serves as an input

mode, since any external circuit that writes to the port will overcome the weak

pull–up. When software writes a 0 to any port pin, the DS87C530 will activate

a strong pull–down that remains on until either a 1 is written or a reset occurs.

Writing a 1 after the port has been at 0 will cause a strong transition driver to

turn on, followed by a weaker sustaining pull–up. Once the momentary strong

driver turns off, the port again becomes the output high (and input) state. The

alternate modes of Port 1 are outlined as follows.

022197 3/40

DS87C530

PLCC

TQFP

SIGNAL

NAME

DESCRIPTION

Port

Alternate Function

3

4

5

6

7

8

9

10

48

49

50

51

52

1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

T2

External I/O for Timer/Counter 2

Timer/Counter 2 Capture/Reload Trigger

Serial Port 1 Input

T2EX

RXD1

TXD1

INT2

INT3

INT4

INT5

Serial Port 1 Output

External Interrupt 2 (Positive Edge Detect)

External Interrupt 3 (Negative Edge Detect)

External Interrupt 4 (Postive Edge Detect)

External Interrupt 5 (Negative Edge Detect)

2

3

30

31

32

33

34

35

36

37

23

24

25

P2.0 (AD8) Port 2 (A8–15) – I/O. Port 2 is a bi–directional I/O port. The reset condition

P2.1 (AD9) of Port 2 is logic high. In this state, a weak pull–up holds the port high. This

P2.2

(AD10)

P2.3

(AD11)

P2.4

(AD12)

P2.5

(AD13)

P2.6

condition also serves as an input mode, since any external circuit that writes

totheportwillovercometheweakpull–up. Whensoftwarewritesa0toanyport

pin, the DS87C530 will activate a strong pull–down that remains on until either

a 1 is written or a reset occurs. Writinga 1 after the port has been at 0 will cause

a strong transition driver to turn on, followed by a weaker sustaining pull–up.

Once the momentary strong driver turns off, the port again becomes both the

outputhighandinputstate. AsanalternatefunctionPort2canfunctionasMSB

of the external address bus. This bus can be used to read external ROM and

read/write external RAM memory or peripherals.

26

27

28

29

30

(AD14)

P2.7

(AD15)

15–22

8–15

P3.0 – P3.7 Port 3 – I/O. Port 3 functions as both an 8–bit bi–directional I/O port and an

alternate functional interface for External Interrupts, Serial Port 0, Timer 0 and

1 Inputs, and RD and WR strobes. The reset condition of Port 3 is with all bits

at a logic 1. In this state, a weak pull–up holds the port high. This condition also

serves as an input mode, since any external circuit that writes to the port will

overcome the weak pull–up. When software writes a 0 to any port pin, the

DS87C530 will activate a strong pull–down that remains on until either a 1 is

written or a reset occurs. Writing a 1 after the port has been at 0 will cause a

strong transition driver to turn on, followed by a weaker sustaining pull–up.

Once the momentary strong driver turns off, the port again becomes both the

output high and input state. The alternate modes of Port 3 are outlined below.

Port

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

Alternate Mode

15

16

17

18

19

20

21

22

8

9

RXD0

TXD0

INT0

INT1

T0

Serial Port 0 Input

Serial Port 0 Output

External Interrupt 0

External Interrupt 1

Timer 0 External Input

Timer 1 External Input

10

11

12

13

14

15

T1

WR

RD

External Data Memory Write Strobe

External Data Memory Read Strobe

42

35

EA

EA–Input. ConnecttogroundtoforcetheDS87C530touseanexternalROM.

TheinternalRAMisstillaccessibleasdeterminedbyregistersettings.Connect

EA to V to use internal ROM.

CC

51

44

V

BAT

V

– Input. Connect to the power source that maintains SRAM and RTC

BAT

when V < V . May be connected to a 3V lithium battery or a super–cap.

CC

BAT

See the electrical specifications for details.

022197 4/40

DS87C530

PLCC

TQFP

SIGNAL

NAME

DESCRIPTION

27, 28

20, 21

RTCX2,

RTCX1

RTCX2, RTCX1 – Timekeeping crystal. Connect a 32.768 KHz crystal

between RTCX2 and RTCX1 to supply the time–base for the real time clock.

The DS87C530 supports both 6 pF and 12.5 pF load capacitance crystals as

selected by an SFR bit described below. To prevent noise from affecting the

RTC, the RTCX2 and RTCX1 pin should be guard–ringed with GND2.

2, 11,

13, 14, 33, 34,

40, 41 47

4, 6, 7,

NC

NC – Reserved. These pins should not be connected. They are reserved for

use with future devices in the family.

areidentical instructions. The majority of instructions on

COMPATIBILITY

The DS87C530 is a fully static CMOS 8051 compatible

microcontroller designed for high performance. While

remaining familiar to 8051 users, it has many new fea-

tures. In general, software written for existing 8051

based systems works without modification on the

DS87C530. The exception is critical timing since the

High Speed Micro performs its instructions much faster

than the original for any given crystal selection. The

DS87C530 runs the standard 8051 instruction set. It is

not pin compatible with other 8051s due to the time-

keeping crystal.

the DS87C530 will see the full 3 to 1 speed improve-

ment. Some instructions will get between 1.5 and 2.4 to

1 improvement. All instructions are faster than the origi-

nal 8051.

The numerical average of all opcodes gives approxi-

mately a 2.5 to 1 speed improvement. Improvement of

individual programs will depend on the actual instruc-

tions used. Speed sensitive applications would make

the most use of instructions that are three times faster.

However, the sheer number of 3 to 1 improved opcodes

makes dramatic speed improvements likely for any

code. These architecture improvements and 0.8 µm

CMOS produce a peak instruction cycle in 121 ns (8.25

MIPs). The Dual Data Pointer feature also allows the

user to eliminate wasted instructions when moving

blocks of memory.

The DS87C530 provides three 16–bit timer/counters,

full–duplex serial port (2), 256 bytes of direct RAM plus

1KB of extra MOVX RAM. I/O ports have the same

operation as a standard 8051 product. Timers will

default to a 12 clock per cycle operation to keep their

timingcompatible with original 8051 systems. However,

timersareindividuallyprogrammabletorunatthenew4

clocks per cycle if desired. The PCA is not supported.

INSTRUCTION SET SUMMARY

All instructions in the DS87C530 perform the same

functions as their 8051 counterparts. Their effect on

bits, flags, and other status functions is identical. How-

ever, the timing of each instruction is different. This

applies both in absolute and relative number of clocks.

The DS87C530 provides several new hardware fea-

tures implemented by new Special Function Registers.

A summary of these SFRs is provided below.

For absolute timing of real–time events, the timing of

software loops can be calculated using a table in the

High–Speed Microcontroller User’s Guide. However,

counter/timers default to run at the older 12 clocks per

increment. In this way, timer–based events occur at the

standard intervals with software executing at higher

speed. Timers optionally can run at 4 clocks per incre-

ment to take advantage of faster processor operation.

PERFORMANCE OVERVIEW

The DS87C530 features a high speed 8051 compatible

core. Higher speed comes not just from increasing the

clock frequency, but from a newer, more efficient

design.

This updated core does not have the dummy memory

cycles that are present in a standard 8051. A conven-

tional 8051 generates machine cycles using the clock

frequency divided by 12. In the DS87C530, the same

machine cycle takes four clocks. Thus the fastest

instruction, 1 machine cycle, executes three times

faster for the same crystal frequency. Note that these

The relative time of two instructions might be different in

the new architecture than it was previously. For exam-

ple, in the original architecture, the “MOVX A, @DPTR”

instruction and the “MOV direct, direct” instruction used

022197 5/40

DS87C530

two machine cycles or 24 oscillator cycles. Therefore,

they required the same amount of time. In the

DS87C530, the MOVX instruction takes as little as two

machine cycles or eight oscillator cycles but the “MOV

direct, direct” uses three machine cycles or 12 oscillator

cycles. While both are faster than their original counter-

parts, they now have different execution times. This is

because the DS87C530 usually uses one instruction

cycle for each instruction byte. The user concerned with

precise program timing should examine the timing of

each instruction for familiarity with the changes. Note

that a machine cycle now requires just four clocks, and

provides one ALE pulse per cycle. Many instructions

requireonly one cycle, but some require five. In the orig-

inal architecture, all were one or two cycles except for

MUL and DIV. Refer to the High–Speed Microcontroller

User’s Guide for details and individual instruction tim-

ing.

SPECIAL FUNCTION REGISTER LOCATIONS Table 2

* Functions not present in the 80C52 are in bold

REGISTER

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

P0.3

BIT 2

P0.2

BIT 1

P0.1

BIT 0

P0.0

ADDRESS

P0

P0.7

P0.6

P0.5

P0.4

80h

SP

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

90h

91h

96h

98h

99h

A0h

A8h

A9h

AAh

B0h

B8h

B9h

DPL

DPH

DPL1

DPH1

DPS

0

SEL

IDLE

IT0

PCON

TCON

TMOD

TL0

SMOD_0 SMOD0

–

GF1

IE1

GF0

IT1

C/T

STOP

IE0

M1

TF1

TR1

C/T

TF0

M1

TR0

M0

GATE

M0

TL1

TH0

TH1

CKCON

P1

WD1

P1.7

WD0

P1.6

T2M

T1M

T0M

MD2

MD1

MD0

P1.0

BGS

TRM0

RI_0

P1.5

P1.4

P1.3

P1.2

P1.1

EXIF

TRIM

SCON0

SBUF0

P2

IE5

IE4

IE3

IE2

XT/RG

TRM1

TB8_0

RGMD

TRM1

RB8_0

RGSL

TRM0

TI_0

E4K

X12/6

SM1_0

TRM2

SM2_0

TRM2

REN_0

SM0/FE_0

P2.7

EA

P2.6

ES1

P2.5

ET2

P2.4

ES0

P2.3

ET1

P2.2

EX1

P2.1

ET0

P2.0

EX0

IE

SADDR0

SADDR1

P3

P3.7

–

P3.6

PS1

P3.5

PT2

P3.4

PS0

P3.3

PT1

P3.2

PX1

P3.1

PT0

P3.0

PX0

IP

SADEN0

022197 6/40

DS87C530

REGISTER

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ADDRESS

SADEN1

BAh

SM0/FE_1

SCON1

SBUF1

ROMSIZE

PMR

SM1_1

SM2_1

REN_1

TB8_1

RB8_1

TI_1

RI_1

C0h

C1h

C2h

C4h

C5h

C7h

C8h

C9h

CAh

CBh

CCh

CDh

D0h

D8h

E0h

E8h

F0h

F2h

F3h

F4h

F5h

F8h

F9h

FAh

FBh

FCh

FDh

FEh

FFh

–

RMS2

RMS1

RMS0

DME0

SPRA0

CD1

PIP

CD0

HIP

SWB

LIP

–

XTOFF

SPTA1

ALEOFF DME1

STATUS

TA

XTUP

SPRA1

SPTA0

T2CON

T2MOD

RCAP2L

RCAP2H

TL2

TF2

–

EXF2

–

RCLK

–

TCLK

–

EXEN2

–

TR2

–

C/T2

CP/RL2

DCEN

T2OE

TH2

PSW

CY

AC

F0

RS1

RS0

OV

FL

P

WDCON

ACC

SMOD_1 POR

EPFI

PFI

WDIF

WTRF

EWT

RWT

EIE

–

ERTCI

EWDI

EX5

EX4

EX3

EX2

B

RTASS

RTAS

RTAM

RTAH

EIP

0

–

PRTCI

MCE

PWDI

HCE

PX5

PX4

PX3

PX2

RTCC

RTCSS

RTCS

RTCM

RTCH

RTCD0

RTCD1

SSCE

SCE

RTCRE

RTCWE

RTCIF

RTCE

0

022197 7/40

DS87C530

The RTC features a programmable alarm condition. A

user selects the alarm time. When the RTC reaches the

selected value, it sets a flag. This will cause an interrupt

if enabled, even in Stop mode. The alarm consists of a

comparator that matches the user value against the

RTC actual value. A user can select a match for one or

more of the sub–seconds, seconds, minutes, or hours.

This allows an interrupt automatically to occur once per

second, once per minute, once per hour, or once per

day. Enabling interrupts with no match will generate an

interrupt 256 times per second.

NONVOLATILE FUNCTIONS

The DS87C530 provides two functions that are perma-

nently powered if a user supplies an external energy

source. These are an on–chip real time clock and anon-

volatile SRAM. The chip contains all related functions

and controls. The user must supply a backup source

and a 32.768 KHz timekeeping crystal.

REAL TIME CLOCK

The on–chip Real Time Clock (RTC) keeps time of day

and calendar functions. Its timebase is a 32.768 KHz

crystal between pins RTCX1 and RTCX2. The RTC

maintainstimeto1/256ofasecond. Italsoallowsauser

to read (and write) seconds, minutes, hours, day of the

week, and date. The clock organization is shown in Fig-

ure 2.

Software enables the timekeeper oscillator using the

RTC Enable bit in the RTC Control register (F9h). This

starts the clock. It can disable the oscillator to preserve

the life of the backup energy–source if unneeded. Val-

ues in the RTC Control register are maintained by the

backup source through power failure. Once enabled,

the RTC maintains time for the life of the backup source

Timekeeping registers allow easy access to commonly

needed time values. For example, software can simply

check the elapsed number of minutes by reading one

register. Alternately, it can read the complete time of

day, including subseconds, in only four registers. The

calendar stores its data in binary form. While this

requires software translation, it allows complete flexibil-

ity as to the exact value. A user can start the calendar

with a variety of selections since it is simply a 16–bit

binarynumberofdays. Thisnumberallowsatotalrange

of 179 years beginning from 0000.

even when V is removed.

CC

The RTC will maintain an accuracy of ±2 minutes per

month at 25°C. Under no circumstances are negative

voltages, of any amplitude, allowed on any pin while the

deviceisindataretentionmode(V < V

). Negative

BAT

CC

voltages will shorten battery life, possibly corrupting the

contents of internal SRAM and the RTC.

REAL TIME CLOCK Figure 2

RTCX2

ꢀ 128

ꢀ 256

ꢀ 60

ꢀ 24

RTCX1

SUB–SECONDS

SECONDS

6–BITS

MINUTES

6–BITS

HOURS

5–BITS

DAY OF WEEK

3–BITS

DAYS

16–BITS

8–BITS

SUB–SECONDS

REGISTER

SECONDS

REGISTER

MINUTES

REGISTER

HOURS

REGISTER

CALENDAR

REGISTERS

RTC CONTROL

REGISTER

MATCH COMPARATOR

RTCIF

SUB–SECONDS

ALARM REG.

SECONDS

ALARM REG.

MINUTES

ALARM REG.

HOURS

ALARM REG.

022197 8/40

DS87C530

Trimregister(TRIM;96h)mustbeprogrammedtospec-

ify the crystal type for the oscillator. When TRIM.6 = 1,

thecircuit expectsa12.5pFcrystal. WhenTRIM.6=0, it

expects a 6 pF crystal. As mentioned above, this bit will

be nonvolatile so these choices will remain while the

backup source is present. A guard ring (connected to

theRealTimeClockground)shouldencircletheRTCX1

and RTCX2 pins.

NONVOLATILE RAM

The 1K x 8 on–chip SRAM can be nonvolatile. An exter-

nal backup energy–source will maintain the SRAM con-

tents through power failure. This allows the DS87C530

to log data or to store configuration settings. Internal

switching circuits will detect the loss of V and switch

SRAM power to the backup source on the V

CC

pin. The

BAT

256 bytes of direct RAM are not affected by this circuit

and are volatile.

Backup Energy Source

The DS87C530 uses an external energy source to

CRYSTAL AND BACKUP SOURCES

To use the unique functions of the DS87C530, two

external components are needed. These are a 32.768

KHz timekeeping crystal and a backup energy–source.

The following describes guidelines for choosing these

devices.

maintaintimekeepingandSRAMdatawithoutV .This

CC

source can be either a battery or 0.47 F super cap and

should be connected to the V

pin. The nominal bat-

BAT

tery voltage is 3V. The V

pin will not source current.

BAT

Therefore,a super cap requires an external resistor and

diode to supply charge.

Timekeeping Crystal

The backup lifetime is a function of the battery capacity

and the data retention current drain. This drain is speci-

fied in the electrical specifications. The circuit loads the

The DS87C530 can use a standard 32.768 KHz crystal

as the RTC time base. There are two versions of stan-

dard crystals available, with 6 pF and 12.5 pF load

capacitance. The tradeoff is that the 6 pF uses less

V

BAT

only when V

has fallen below V . Thus the

CC BAT

actual lifetime depends not only on the current and bat-

tery capacity, but also on the portion of time without

power. A very small lithium cell provides a lifetime of

more than 10 years.

power, givinglongerlifewhileV isoff, butismoresen-

CC

sitive to noise and board layout. The 12.5 pF crystal

uses more power, giving a shorter battery backed life,

but produces a more robust oscillator. Bit 6 in the RTC

022197 9/40

DS87C530

INTERNAL BACKUP CIRCUIT Figure 3

1.5KΩ

V

BAT

–

+

V

CC

V

(SRAM AND RTC)

CC

IMPORTANT APPLICATION NOTE

The pins on the DS87C530 are generally as resilient as other CMOS circuits. They have no unusual susceptibility to

electrostatic discharge (ESD) or other electrical transients. However, no pin on the DS87C530 should ever be tak-

en to a voltage below ground. Negative voltages on any pin can turn on internal parasitic diodes that draw current

directly from the battery. If a device pin is connected to the “outside world” where it may be handled or come in contact

with electrical noise, protection should be added to prevent the device pin from going below -0.3V. Some power sup-

plies can give a small undershoot on power up, which should be prevented. Application Note 93, “Design Guidelines

for Microcontrollers Incorporating NVRAM”, discusses how to protect the DS87C530 against these conditions.

022197 10/40

DS87C530

MEMORY RESOURCES

Maximum on–chip

ROM Address

Like the 8051, the DS87C530 uses three memory

areas. These are program (ROM), data (RAM), and

scratchpad RAM (registers). The DS87C530 contains

on–chip quantities of all three areas.

RMS2 RMS1 RMS0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0KB

1KB

2KB

4KB

The total memory configuration of the DS87C530 is

16KB of ROM, 1KB of data SRAM and 256 bytes of

scratchpad or direct RAM. The 1KB of data space

SRAM is read/write accessible and is memory mapped.

This on–chip SRAM is reached by the MOVX instruc-

tion. It is not used for executable memory. The scratch-

pad area is 256 bytes of register mapped RAM and is

identical to the RAM found on the 80C52. There is no

conflict or overlap among the 256 bytes and the 1KB as

they use different addressing modes and separate

instructions.

8KB

16KB (default)

Invalid – reserved

The reset default condition is a maximum on–chip ROM

address of 16KB. Thus no action is required if this fea-

ture is not used. When accessing external program

memory, the first 16KB would be inaccessible. To select

a smaller effective ROM size, software must alter bits

RMS2–RMS0. Altering these bits requires a Timed

Access procedure as explained below.

OPERATIONAL CONSIDERATION

Care should be taken so that changing the ROMSIZE

registerdoesnotcorruptprogramexecution. Forexam-

ple, assume that a DS87C520 is executing instructions

from internal program memory near the 12KB boundary

(~3000h) and that the ROMSIZE register is currently

configured for a 16KB internal program space. If soft-

ware reconfigures the ROMSIZE register to 4KB

(0000h–0FFFh) in the current state, the device will

immediately jump to external program execution

because program code from 4KB to 16KB

(1000h–3FFFh) is no longer located on–chip. This

could result in code misalignment and execution of an

invalid instruction. The recommended method is to

modifytheROMSIZEregisterfromalocationinmemory

thatwillbeinternal(orexternal)bothbeforeandafterthe

operation. In the above example, the instruction which

modifies the ROMSIZE register should be located

below the 4KB (1000h) boundary, so that it will be unaf-

fected by the memory modification. The same precau-

tion should be applied if the internal program memory

size is modified while executing from external program

memory.

The erasure window should be covered without regard

to the programmed/unprogrammed state of the

EPROM. Otherwise, the device may not meet the AC

and DC parameters listed in the datasheet.

PROGRAM MEMORY ACCESS

On–chip ROM begins at address 0000h and is contigu-

ous through 3FFFh (16KB). Exceeding the maximum

address of on–chip ROM will cause the DS87C530 to

access off–chip memory. However, the maximum on–

chip decoded address is selectable by software using

the ROMSIZE^TMfeature. Software can cause the

DS87C530 to behave like a device with less on–chip

memory. This is beneficial when overlapping external

memory, such as Flash, is used.

The maximum memory size is dynamically variable.

Thus a portion of memory can be removed from the

memory map to access off–chip memory, then restored

to access on–chip memory. In fact, all of the on–chip

memory can be removed from the memory map allow-

ing the full 64KB memory space to be addressed from

off–chip memory. ROM addresses that are larger than

the selected maximum are automatically fetched from

outside the part via Ports 0 and 2. A depiction of the

ROM memory map is shown in Figure 4.

Off–chip memory is accessed using the multiplexed

address/data bus on P0 and the MSB address on P2.

While serving as a memory bus, these pins are not I/O

ports. This convention follows the standard 8051

method of expanding on–chip memory. Off–chip ROM

access also occurs if the EA pin is a logic 0. EA over-

ridesallbitsettings. ThePSENsignalwillgoactive(low)

to serve as a chip enable or output enable when Ports 0

and 2 fetch from external ROM.

The ROMSIZE register is used to select the maximum

on–chip decoded address for ROM. Bits RMS2, RMS1,

RMS0 have the following affect:

022197 11/40

DS87C530

ROM MEMORY MAP Figure 4

ROM SIZE ADJUSTABLE

DEFAULT = 16K BYTES

ROM SIZE IGNORED

EA=0

EA=1

FFFFh

64K

16K

FFFFh

64K

OFF CHIP

3FFFh

USER

SELECTABLE

ON CHIP

0000h

When disabled, the 1KB memory area is transparent to

the system memory map. Any MOVX directed to the

spacebetween0000handFFFFhgoestotheexpanded

bus on Ports 0 and 2. This also is the default condition.

This default allows the DS87C530 to drop into an exist-

ing system that uses these addresses for other hard-

ware and still have full compatibility.

DATA MEMORY ACCESS

Unlike many 8051 derivatives, the DS87C530 contains

on–chip data memory. It also contains the standard 256

bytes of RAM accessed by direct instructions. These

areas are separate. The MOVX instruction accesses

the on–chip data memory. Although physically on–chip,

software treats this area as though it was located off–

chip. The 1KB of SRAM is between address 0000h and

03FFh.

The on–chip data area is software selectable using two

bits in the Power Management Register at location C4h.

This selection is dynamically programmable. Thus

access to the on–chip area becomes transparent to

reachoff–chipdevicesatthesameaddresses. Thecon-

trol bits are DME1 (PMR.1) and DME0 (PMR.0). They

have the following operation:

Access to the on–chip data RAM is optional under soft-

ware control. When enabled by software, the data

SRAM is between 0000h and 03FFh. Any MOVX

instructionthatusesthisareawillgototheon–chipRAM

while enabled. MOVX addresses greater than 03FFh

automatically go to external memory through Ports 0

and 2.

DATA MEMORY ACCESS CONTROL Table 3

DME1

DME0

DATA MEMORY ADDRESS

MEMORY FUNCTION

0

1

0000h – FFFFh

External Data Memory *Default condition

0000h – 03FFh

0400h – FFFFh

Internal SRAM Data Memory

External Data Memory

1

0

1

Reserved

0000h – 03FFh

0400h – FFFBh

FFFCh

Internal SRAM Data Memory

Reserved – no external access

Read access to the status of lock bits

Reserved – no external access

FFFDh–FFFh

NotesonthestatusbytereadatFFFChwithDME1,0=1,1:Bits2–0reflecttheprogrammedstatusofthesecuritylock

bits LB2–LB0. They are individually set to a logic 1 to correspond to a security lock bit that has been programmed.

Thesestatusbitsallowsoftwaretoverifythattheparthasbeenlockedbeforerunningifdesired.Thebitsarereadonly.

Note:After internal MOVX SRAM has been initialized, changing bits DEM0/1 will have no affect on the contents of the

SRAM.

022197 12/40

DS87C530

fore, off–chip RAM access is not at full speed. This is a

convenience to existing designs that may not have fast

RAM in place. Internal SRAM access is always at full

speed regardless of the Stretch setting. When desiring

maximumspeed, softwareshouldselectaStretchvalue

of zero. When using very slow RAM or peripherals,

select a larger Stretch value. Note that this affects data

memory only and the only way to slow programmemory

(ROM) access is to use a slower crystal.

STRETCH MEMORY CYCLE

The DS87C530 allows software to adjust the speed of

off–chip data memory access. The micro is capable of

performing the MOVX in as few as two instruction

cycles. The on–chip SRAM uses this speed and any

MOVX instruction directed internally uses two cycles.

However, the time can be stretched for interface to

external devices. This allows access to both fast

memory and slow memory or peripherals with no glue

logic. Eveninhigh–speedsystems, itmaynotbeneces-

sary or desirable to perform off–chip data memory

access at full speed. In addition, there are a variety of

memory mapped peripherals such as LCDs or UARTs

that are slow.

Using a Stretch value between one and seven causes

the microcontroller to stretch the read/write strobe and

all related timing. Also, setup and hold times are

increased by 1 clock when using any Stretch greater

than 0. This results in a wider read/write strobe and

relaxed interface timing, allowing more time for

memory/peripherals to respond. The timing of the vari-

able speed MOVX is in the Electrical Specifications.

Table 4 shows the resulting strobe widths for each

Stretchvalue. The memory Stretch uses the ClockCon-

trol Special Function Register at SFR location 8Eh. The

Stretch value is selected using bits CKCON.2–0. In the

table, these bits are referred to as M2 through M0. The

first Stretch (default) allows the use of common 120 ns

RAMs without dramatically lengthening the memory

access.

The Stretch MOVX is controlled by the Clock Control

Register at SFR location 8Eh as described below. It

allows the user to select a Stretch value between zero

and seven. A Stretch of zero will result in a two machine

cycle MOVX. A Stretch of seven will result in a MOVX of

nine machine cycles. Software can dynamically change

this value depending on the particular memory or

peripheral.

On reset, the Stretch value will default to a one resulting

in a three cycle MOVX for any external access. There-

DATA MEMORY CYCLE STRETCH VALUES Table 4

CKCON.2–0

M2 M1 M0

RD OR WR STROBE

WIDTH IN CLOCKS

STROBE WIDTH TIME

@ 33 MHz

MEMORY CYCLES

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2 (forced internal)

3 (default external)

2

4

8

12

16

20

24

28

60 ns

121 ns

242 ns

364 ns

485 ns

606 ns

727 ns

848 ns

4

5

6

7

8

9

effect and are 0. The user switches between data point-

ers by toggling the lsb of register 86h. The increment

(INC) instruction is the fastest way to accomplish this.

All DPTR–related instructions use the currently

selected DPTR for any activity. Therefore it takes only

one instruction to switch from a source to a destination

address. Using the Dual Data Pointer saves code from

needing to save source and destination addresses

whendoingablockmove. Thesoftwaresimplyswitches

between DPTR and 1 once software loads them. The

relevant register locations are as follows.

DUAL DATA POINTER

The timing of block moves of data memory is faster

using the DS87C530 Dual Data Pointer (DPTR). The

standard 8051 DPTR is a 16–bit value that is used to

address off–chip data RAM or peripherals. In the

DS87C530, the standard data pointer is called DPTR,

located at SFR addresses 82h and 83h. These are the

standard locations. Using DPTR requires no modifica-

tion of standard code. The new DPTR at SFR 84h and

85h is called DPTR1. The DPTR Select bit (DPS)

chooses the active pointer. Its location is the lsb of the

SFRlocation86h. Nootherbitsinregister86h haveany

022197 13/40

DS87C530

DPL

82h

83h

84h

85h

86h

Low byte original DPTR

High byte original DPTR

Low byte new DPTR

High byte new DPTR

DPTR Select (lsb)

continues to operate but uses an internally divided ver-

sion of the clock source. This creates a lower power

state without external components. It offers a choice of

two reduced instruction cycle speeds (and two clock

sources – discussed below). The speeds are(Clock/64)

and (Clock/1024).

DPH

DPL1

DPH1

DPS

POWER MANAGEMENT

Software is the only mechanism to invoke the PMM.

Table 5 illustrates the instruction cycle rate in PMM for

several common crystal frequencies. Since power con-

sumption is a direct function of operating speed, PMM 1

eliminates most of the power consumption while still

allowingareasonablespeedofprocessing. PMM2runs

very slowly and provides the lowest power consumption

without stopping the CPU. This is illustrated in Table 6.

Along with the standard Idle and power down (Stop)

modes of the standard 80C52, the DS87C530 provides

a new Power Management Mode. This mode allows the

processor to continue functioning, yet to save power

compared with full operation. The DS87C530 also fea-

tures several enhancements to Stop mode that make it

more useful.

Note that PMM provides a lower power condition than

Idle mode. This is because in Idle, all clocked functions

such as timers run at a rate of crystal divided by 4. Since

wake–up from PMM is as fast as or faster than from Idle

and PMM allows the CPU to operate (even if doing

NOPs), there is little reason to use Idle mode in new

designs.

POWER MANAGEMENT MODE (PMM)

Power Management Mode offers a complete scheme of

reducedinternal clock speeds that allow the CPU to run

software but to use substantially less power. During

default operation, the DS87C530 uses four clocks per

machine cycle. Thus the instruction cycle rate is

(Clock/4). At 33 MHz crystal speed, the instruction cycle

speed is 8.25 MHz (33/4). In PMM, the microcontroller

INSTRUCTION CYCLE RATE Table 5

FULL OPERATION

PMM 1

(64 CLOCKS)

PMM 2

(1024 CLOCKS)

CRYSTAL SPEED

1.8432 MHz

11.0592 MHz

22 MHz

(4 CLOCKS)

460.8 KHz

2.765 MHz

5.53 MHz

6.25 MHz

8.25 MHz

28.8 KHz

172.8 KHz

345.6 KHz

390.6 KHz

515.6 KHz

1.8 KHz

10.8 KHz

21.6 KHz

24.4 KHz

32.2 KHz

25 MHz

33 MHz

OPERATING CURRENT ESTIMATES IN PMM Table 6

FULL OPERATION

PMM 1

(64 CLOCKS)

PMM 2

(1024 CLOCKS)

CRYSTAL SPEED

1.8432 MHz

3.57 MHz

11.0592 MHz

16 MHz

(4 CLOCKS)

3.1 mA

1.2 mA

1.6 mA

4.8 mA

7.1 mA

8.3 mA

9.7 mA

12.0 mA

1.0 mA

1.1 mA

4.0 mA

6.0 mA

6.5 mA

8.0 mA

10.0 mA

5.3 mA

15.5 mA

21 mA

22 MHz

25.5 mA

31 mA

25 MHz

33 MHz

36 mA

022197 14/40

DS87C530

The selection of instruction cycle rate will take effect

after a delay of one instruction cycle. Note that the clock

divider choice applies to all functions including timers.

Sincebaud rates are altered, it will be difficult to conduct

serial communication while in PMM. There are minor

restrictions on accessing the clock selection bits. The

processor must be running in a 4 clock state to select

either 64 (PMM1) or 1024 (PMM2) clocks. This means

softwarecannot go directly from PMM1 to PMM2 or visa

versa. It must return to a 4 clock rate first.

CRYSTALESS PMM

A major component of power consumption in PMM is

the crystal amplifier circuit. The DS87C530 allows the

user to switch CPU operation to an internal ring oscilla-

torandturnoffthecrystalamplifier. TheCPUwouldthen

have a clock source of approximately 2–4 MHz, divided

by either 4, 64, or 1024. The ring is not accurate, so soft-

ware can not perform precision timing. However, this

mode allows an additional saving of between 0.5 and

6.0 mA depending on the actual crystal frequency.

While this saving is of little use when running at 4 clocks

perinstructioncycle, itmakesamajorcontributionwhen

running in PMM1 or PMM2.

Switchback

To return to a 4 clock rate from PMM, software can sim-

ply select the CD1 and CD0 clock control bits to the 4

clocks per cycle state. However, the DS87C530 pro-

vides several hardware alternatives for automatic

Switchback. If Switchback is enabled, then the

DS87C530 will automatically return to a 4 clock per

cycle speed when an interrupt occurs from an enabled,

valid external interrupt source. A Switchback will also

occur when a UART detects the beginning of a serial

start bit if the serial receiver is enabled (REN=1). Note

the beginning of a start bit does not generate an inter-

rupt; this occurs on reception of a complete serial word.

The automatic Switchback on detection of a start bit

allows hardware to correct baud rates in time for a

proper serial reception. A switchback will also occur

when a byte is written to the SBUF0 or SBUF1 for trans-

mission.

PMM OPERATION

Software invokes the PMM by setting the appropriate

bits in the SFR area. The basic choices are divider

speed and clock source. There are three speeds (4, 64,

and1024)andtwoclocksources(crystal, ring). Boththe

decisions and the controls are separate. Software will

typicallyselect the clock speed first. Then, it willperform

the switch to ring operation if desired. Lastly, software

can disable the crystal amplifier if desired.

There are two ways of exiting PMM. Software can

remove the condition by reversing the procedure that

invokedPMM or hardware can (optionally) remove it. To

resume operation at a divide by 4 rate under software

control, simply select 4 clocks per cycle, then crystal

based operation if relevant. When disabling the crystal

as the time base in favor of the ring oscillator, there are

timing restrictions associated with restarting the crystal

operation. Details are described below.

Switchback is enabled by setting the SWB bit (PMR.5)

to a 1 in software. For an external interrupt, Switchback

will occur only if the interrupt source could really gener-

atetheinterrupt. Forexample, ifINT0 isenabledbuthas

a low priority setting, then Switchback will not occur on

INT0 if the CPU is servicing a high priority interrupt.

There are three registers containing bits that are con-

cerned with PMM functions. They are Power Manage-

ment Register (PMR; C4h), Status (STATUS; C5h), and

External Interrupt Flag (EXIF; 91h)

Status

Information in the Status register assists decisions

about switching into PMM. This register contains

information about the level of active interrupts and the

activity on the serial ports.

Clock Divider

Software can select the instruction cycle rate by select-

ing bits CD1 (PMR.7) and CD0 (PMR.6) as follows:

The DS87C530 supports three levels of interrupt prior-

ity. These levels are Power–fail, High, and Low. Bits

STATUS.7–5 indicate the service status of each level. If

PIP (Power–fail Interrupt Priority; STATUS.7) is a 1,

then the processor is servicing this level. If either HIP

CD1

CD0

Cycle rate

Reserved

4 clocks (default)

64 clocks

1024 clocks

0

1

0

1

0

1

022197 15/40

DS87C530

(HighInterruptPriority;STATUS.6)orLIP(LowInterrupt

Priority; STATUS.5) is high, then the corresponding

level is in service.

ting XT/RG = 0 selects the ring. The RGMD (EXIF.2) bit

serves as a status bit by indicating the active clock

source. RGMD = 0 indicates the CPU is running from

the crystal. RGMD = 1 indicates it is running from the

ring. When operating from the ring, disable the crystal

amplifier by setting the XTOFF bit (PMR.3) to a 1. This

can only be done when XT/RG = 0.

Software should not rely on a lower priority level inter-

rupt source to remove PMM (Switchback) when a

higher level is in service. Check the current priority ser-

vice level before entering PMM. If the current service

level locks out a desired Switchback source, then it

would be advisable to wait until this condition clears

before entering PMM.

When changing the clock source, the selection will take

effect after a one instruction cycle delay. This applies to

changes from crystal to ring and vise versa. However,

this assumes that the crystal amplifier is running. In

most cases, when the ring is active, software previously

disabled the crystal to save power. If ring operation is

beingusedandthesystemmustswitchtocrystalopera-

tion, the crystal must first be enabled. Set the XTOFF bit

to a 0. At this time, the crystal oscillation will begin. The

DS87C530thenprovidesawarm–updelaytomakecer-

tain that the frequency is stable. Hardware will set the

XTUP bit (STATUS.4) to a 1 when the crystal is ready for

use. Then software should write XT/RG to a 1 to begin

operating from the crystal. Hardware prevents writing

XT/RG to a 1 before XTUP = 1. The delay between

XTOFF=0andXTUP=1willbe65,536crystalclocksin

addition to the crystal cycle startup time.

Alternately, software can prevent anundesiredexitfrom

PMM by entering a low priority interrupt service level

beforeentering PMM. This will prevent other low priority

interrupts from causing a Switchback.

Status also contains information about the state of the

serial ports. Serial Port Zero Receive Activity (SPRA0;

STATUS.0) indicates a serial word is being received on

Serial Port 0 when this bit is set to a 1. Serial Port Zero

Transmit Activity (SPTA0; STATUS.1) indicates that the

serial port is still shifting out a serial transmission. STA-

TUS.2 and STATUS.3 provide the same information for

Serial Port 1, respectively. These bits should be

interrogated before entering PMM1 or PMM2 to ensure

that no serial port operations are in progress. Changing

the clock divisor rate during a serial transmission or

reception will corrupt the operation.

Switchback has no effect on the clock source. If soft-

ware selects a reduced clock divider and enables the

ring, a Switchback will only restore the divider speed.

Theringwillremainasthetimebaseuntilalteredbysoft-

ware. If there is serial activity, Switchback usually

occurs with enough time to create proper baud rates.

This is not true if the crystal is off and the CPU isrunning

from the ring. If sending a serial character that wakes

the system from crystaless PMM, then it should be a

dummy character of no importance with a subsequent

delay for crystal startup.

Crystal/Ring Operation

The DS87C530 allows software to choose the clock

source as an independent selection from the instruction

cycle rate. The user can select crystal–based or ring

oscillator–based operation under software control.

Power–on reset default is the crystal (or external clock)

source. The ring may save power depending on the

actual crystal speed. To save still more power, software

can then disable the crystal amplifier. This process

requirestwo steps. Reversing the process also requires

two steps.

The following table is a summary of the bits relating to

PMM and its operation. The flow chart below illustrates

a typical decision set associated with PMM.

The XT/RG bit (EXIF.3) selects the crystal or ring as the

clocksource. SettingXT/RG = 1 selects the crystal. Set-

022197 16/40

DS87C530

PMM CONTROL AND STATUS BIT SUMMARY Table 7

BIT NAME LOCATION

FUNCTION

RESET

WRITE ACCESS

XT/RG

EXIF.3

EXIF.2

Control. XT/RG=1, runs from crystal or

external clock; XT/RG=0, runs from

internal ring oscillator.

X

0 to 1 only when XTUP=1

and XTOFF=0

RGMD

CD1, CD0

SWB

Status. RGMD=1, CPU clock = ring;

RGMD=0, CPU clock = crystal.

0

0, 1

0

None

PMR.7,

PMR.6

Control. CD1,0=01, 4 clocks;

CS1,0=10, PMM1; CD1,0=11, PMM2.

Write CD1,0=10 or 11 only

from CD1,0=01

PMR.5

Control. SWB=1, hardware invokes

switchback to 4 clocks, SWB=0, no

hardware switchback.

Unrestricted

XTOFF

PIP

PMR.3

Control. Disables crystal operation after

ring is selected.

0

1

1 only when XT/RG=0

STATUS.7

STATUS.6

STATUS.5

STATUS.4

Status. 1 indicates a power–fail interrupt

in service.

None

HIP

Status. 1 indicates high priority interrupt

in service.

LIP

Status. 1 indicates low priority interrupt

in service.

XTUP

Status. 1 indicates that the crystal has

stabilized.

SPTA1

SPRA1

STATUS.3

STATUS.2

Status. Serial transmission on serial port 1.

0

None

Status. Serial word reception on serial

port 1.

SPTA0

SPRA0

STATUS.1

STATUS.0

Status. Serial transmission on serial port

0.

0

None

Status. Serial word reception on serial

port 0.

022197 17/40

DS87C530

INVOKING AND CLEARING PMM Figure 3

ENTER POWER MANAGEMENT MODE

EXITING POWER MANAGEMENT MODE

ALLOW

N

HARDWARE TO CAUSE

A SWITCHBACK

?

SOFTWARE DECIDES

SWB=1 AND EXTERNAL

ACTIVITY OCCURS

TO EXIT

Y

HARDWARE AUTOMATICALLY

SWITCHES CD1, CD0

CD1, CD0 = 01 FOR 4

SET SWB=1

CHECK

STATUS=0

N

CHECK

STATUS=0

N

CHECK AND CLEAR

IMPENDING ACTIVITY

Y

DONE

Y

INVOKE PMM

CLOCK SPEED=64 OR 1024

CD1, CD0=10 FOR 64

CD1, CD0=11 FOR 1024

N

XTOFF = 1

?

XT/RG=1

DONE

Y

OPERATE

WITHOUT CRYSTAL

?

N

XTOFF = 0

DONE

Y

XT/RG=0

XTUP = 1

?

N

DISABLE CRYSTAL?

(NO FAST SWITCH

TO XTAL)

XT/RG=1

DONE

Y

XTOFF = 1

LOWEST POWER OPERATING STATE

022197 18/40

DS87C530

enabled during Stop mode. The default or reset condi-

tion is with the bit at a logic 0. This results in the band–

gapbeing off during Stop mode. Note that this bit has no

control of the reference during full power, PMM, or Idle

modes.

IDLE MODE

Setting thelsbof the Power Control register (PCON; 87h)

invokes the Idle mode. Idle will leave internal clocks,

serial ports and timers running. Power consumption

drops because the CPU is not active. Since clocks are

running, the Idle power consumption is a function of crys-

tal frequency. It should be approximately 1/2 of the opera-

tional power at a given frequency. The CPU can exit the

Idle state with any interrupt or a reset. Idle is available for

backward software compatibility. The system can now

reduce power consumption to below Idle levels by using

PMM1 or PMM2 and running NOPs.

The second feature allows an additional power saving

option while also making Stop easier to use. This is the

ability to start instantly when exiting Stop mode. It is the

internal ring oscillator that provides this feature. This

ring can be a clock source when exiting Stop mode in

response to an interrupt. The benefit of the ring oscilla-

tor is as follows.

STOP MODE ENHANCEMENTS

Using Stop mode turns off the crystal oscillator and all

internal clocks to save power. This requires that the

oscillator be restarted when exiting Stop mode. Actual

start–up time is crystal dependent, but is normally at

least 4 ms. A common recommendation is 10 ms. In an

applicationthatwillwake–up, performashortoperation,

then return to sleep, the crystal start–up can be longer

than the real transaction. However, the ring oscillator

will start instantly. Running from the ring, the user can

perform a simple operation and return to sleep before

the crystal has even started. If a user selects the ring to

provide the start–up clock and the processor remains

running, hardware will automatically switch to the crys-

tal once a power–on reset interval (65536 clocks) has

expired. Hardware uses this value to assure proper

crystal start even though power is not being cycled.

Setting bit 1 of the Power Control register (PCON; 87h)

invokes the Stop mode. Stop mode is the lowest power

state since it turns off all internal clocking. The I of a

CC

standard Stop mode is approximately 1 µA but is speci-

fied in the Electrical Specifications. The CPU will exit

Stop mode from an external interrupt or a reset condi-

tion. Internally generated interrupts (timer, serial port,

watchdog) are not useful since they require clocking

activity. One exception is that a real time clock interrupt

can cause the device to exit Stop mode. This provides a

very power efficient way of performing infrequent yet

periodic tasks.

TheDS87C530providestwoenhancementstotheStop

mode. As documented below, the DS87C530 provides

aband–gapreferencetodeterminePower–failInterrupt

and Reset thresholds. The default state is that the

band–gap reference is off while in Stop mode. This

allows the extremely low power state mentioned above.

A user can optionally choose to have the band–gap

enabled during Stop mode. With the band–gap refer-

ence enabled, PFI and Power–fail reset are functional

and are a valid means for leaving Stop mode. This

allows software to detect and compensate for a brown–

out or power supply sag, even when in Stop mode.

The ring oscillator runs at approximately 2–4 MHz but

will not be a precise value. Do not conduct real–time

precision operations (including serial communication)

during this ring period. Figure 4 shows how the opera-

tion would compare when using the ring, and when

starting up normally. The default state is to exit Stop

mode without using the ring oscillator.

The RGSL – Ring Select bit at EXIF.1 (EXIF; 91h) con-

trols this function. When RGSL = 1, the CPU will use the

ring oscillator to exit Stop mode quickly. As mentioned

above, the processor will automatically switch from the

ring to the crystal after a delay of 65,536 crystal clocks.

For a 3.57 MHz crystal, thisisapproximately18ms. The

processor sets a flag called RGMD– Ring Mode,

located at EXIF.2, that tells software that the ring is

being used. The bit will be a logic 1 when the ring is in

use. Attempt no serial communication or precision tim-

ing while this bit is set, since the operating frequency is

not precise.

In Stop mode with the band–gap enabled, I

will be

CC

approximately 50 µA compared with 1 µA with the

band–gap off. If a user does not require a Power–fail

Reset or Interrupt while in Stop mode, the band–gap

can remain disabled. Only the most power sensitive

applications should turn off the band–gap, as this

results in an uncontrolled power down condition.

The control of the band–gap reference is located in the

Extended Interrupt Flag register (EXIF; 91h). Setting

BGS (EXIF.0) to a 1 will keep the band–gap reference

022197 19/40

DS87C530

RING OSCILLATOR EXIT FROM STOP MODE Figure 4

STOP MODE WITHOUT RING STARTUP

4–10 ms

uC OPERATING

CRYSTAL

OSCILLATION

uC ENTERS

STOP MODE

INTERRUPT;

CLOCK STARTS

CLOCK

STABLE

uC ENTERS

STOP MODE

POWER

STOP MODE WITH RING STARTUP

uC OPERATING

CRYSTAL

OSCILLATION

uC OPERATING

RING

OSCILLATION

uC ENTERS

STOP MODE

INTERRUPT;

RING STARTS

uC ENTERS

STOP MODE

POWER SAVED

POWER

Note: Diagram assumes that the operation following Stop requires less than 18 ms to complete.

below, and more details are available in the High–

EMI REDUCTION

The DS87C530 allows software to reduce EMI. One of

the major contributors to radiated noise in an 8051

based system is the toggling of ALE. The DS87C530

allowssoftwaretodisableALEwhennotusedbysetting

the ALEOFF (PMR.2) bit to a 1. When ALEOFF = 1,

ALE will still toggle during an off–chip MOVX. However,

ALE will remain in a static when performing on–chip

memory access. The default state of ALEOFF = 0 so

ALE toggles with every instruction cycle.

Speed Microcontroller User’s Guide.

SERIAL PORTS

The DS87C530 provides a serial port (UART) that is

identical to the 80C52. In addition it includes a second

hardware serial port that is a full duplicate of the stan-

dard one. This port optionally uses pins P1.2 (RXD1)

and P1.3 (TXD1). It has duplicate control functions

included in new SFR locations.

Both ports can operate simultaneously but can be at dif-

ferent baud rates or even in different modes. The second

serial port has similar control registers (SCON1; C0h,

SBUF1; C1h) to the original. The new serial port can only

use Timer 1 for timer generated baud rates.

PERIPHERAL OVERVIEW

The DS87C530 provides several of the most commonly

needed peripheral functions in microcomputer–based

systems. These new functions include a second serial

port, Power–fail Reset, Power–fail Interrupt, and a pro-

grammable Watchdog Timer. These are described

022197 20/40

DS87C530

D8h). Setting WDCON.5 to a logic 1 will enable the PFI.

Application software can also read the PFI flag at

WDCON.4. APFIconditionsetsthisbittoa1. Theflagis

independent of the interrupt enable and software must

manuallyclearit. IfthePFIisenabledandtheband–gap

select bit (BGS) is set, a PFI will bring the device out of

Stop mode.

TIMER RATE CONTROL

There is one important difference between the

DS87C530 and 8051 regarding timers. The original

8051 used 12 clocks per cycle for timers as well as for

machine cycles. The DS87C530 architecture normally

uses 4 clocks per machine cycle. However, in the area

of timers and serial ports, the DS87C530 will default to

12 clocks per cycle on reset. This allows existing code

with real–time dependencies such as baud rates to

operate properly.

WATCHDOG TIMER

To prevent software from losing control, the DS87C530

includes a programmable Watchdog Timer. The Watch-

dog is a free running timer that sets a flag if allowed to

reach a preselected time–out. It can be (re)started by

software.

If an application needs higher speed timers or serial

baudrates, theusercanselectindividualtimerstorunat

the 4 clock rate. The Clock Control register (CKCON;

8Eh)determinesthesetimerspeeds. Whentherelevant

CKCON bit is a logic 1, the DS87C530 uses 4 clocks per

cycle to generate timer speeds. When the bit is a 0, the

DS87C530 uses 12 clocks for timer speeds. The reset

condition is a 0. CKCON.5 selects the speed of Timer 2.

CKCON.4 selects Timer 1 and CKCON.3 selects Timer

0. Unless a user desires very fast timing, it is unneces-

sary to alter these bits. Note that the timer controls are

independent.

A typical application is to select the flag as a reset

source. When the Watchdog times out, it sets its flag

which generates reset. Software must restart the timer

before it reaches its time–out or the processor is reset.

Softwarecanselectoneoffourtime–outvalues. Then, it

restarts the timer and enables the reset function. After

enabling the reset function, software must then restart

the timer before its expiration or hardware will reset the

CPU. Both the Watchdog Reset Enable and the Watch-

dog Restart control bits are protected by a “Timed

Access” circuit. This prevents errant software from acci-

dentally clearing the Watchdog. Time–out values are

precisesincetheyareafunctionofthecrystalfrequency

as shown below in Table 8. For reference, the time peri-

ods at 33 MHz also are shown.

POWER–FAIL RESET

The DS87C530 uses a precision band–gap voltage ref-

erence to decide if V is out of tolerance. While power-

CC

ing up, the internal monitor circuit maintains a reset

state until V rises above the V

level. Once above

RST

CC

this level, the monitor enables the crystal oscillator and

counts 65536 clocks. It then exits the reset state. This

power–on reset (POR) interval allows time for the oscil-

lator to stabilize.

TheWatchdogalsoprovidesausefuloptionforsystems

that do not require a reset circuit. It will set an interrupt

flag 512 clocks before setting the reset flag. Software

canoptionallyenablethisinterruptsource. Theinterrupt

is independent of the reset. A common use of the inter-

rupt is during debug, to show developers where the

Watchdog times out. This indicates where the Watch-

dog must be restarted by software. The interrupt also

can serve as a convenient time–base generator or can

wake–up the processor from power saving modes.

A system needs no external components to generate a

power–related reset. Anytime V

drops below V

,

RST

CC

asinpower–failureorapowerdrop,themonitorwillgen-

erate and hold a reset. It occurs automatically, needing

no action from the software. Refer to the Electrical

Specifications for the exact value of V

.

RST

POWER–FAIL INTERRUPT

The voltage reference that sets a precise reset thresh-

old also generates an optional early warning Power–fail

Interrupt (PFI). When enabled by software, the proces-

The Watchdog function is controlled by the Clock Con-

trol (CKCON – 8Eh), Watchdog Control (WDCON –

D8h), andExtendedInterruptEnable(EIE–E8h)SFRs.

CKCON.7 and CKCON.6 are WD1 and WD0 respec-

tively and they select the Watchdog time–out period as

shown in Table 8.

sor will vector to program memory address 0033h if V

CC

drops below V

. PFI has the highest priority. The PFI

PFW

enable is in the Watchdog Control SFR (WDCON –

022197 21/40

DS87C530

WATCHDOG TIME–OUT VALUES Table 8

INTERRUPT

TIME–OUT

WD1

WD0

TIME (33 MHz)

3.9718 ms

31.77 ms

RESET TIME–OUT

TIME (33 MHz)

3.9874 ms

31.79 ms

17

0

1

0

1

0

1

2

clocks

2

+ 512 clocks

20

23

26

20

23

26

254.20 ms

2033.60 ms

254.21 ms

2033.62 ms

As shown above, the Watchdog Timer uses the crystal

frequency as a time base. A user selects one of four

counter values to determine the time–out. These clock

EWT (WDCON.1) is the enable for the Watchdog timer

reset function. RWT (WDCON.0) is the bit that software

uses to restart the Watchdog Timer. Setting this bit

restarts the timer for another full interval. Application

software must set this bit before the time–out. Both of

these bits are protected by Timed Access discussed

below. Asmentionedpreviously, WD1and0(CKCON.7

and 6) select the time–out. Finally, the user can enable

the Watchdog Interrupt using EWDI (EIE.4). The Spe-

cial Function Register map is shown above.

17

20

counter lengths are

2

= 131,072 clocks; 2

=

23

26

1,048,576;

2

= 8,388,608 clocks; and 2

67,108,864 clocks. The times shown in Table 8 above

are with a 33 MHz crystal frequency. Once the counter

chain has completed a full interrupt count, hardware will

set an interrupt flag. Regardless of whether the user

enablesthis interrupt, there are then 512 clocks left until

the reset flag is set. Software can enable the interrupt

and reset individually. Note that the Watchdog is a free

running timer and does not require an enable.

INTERRUPTS

TheDS87C530provides14interruptsourceswiththree

priority levels. The Power–fail Interrupt (PFI) has the

highest priority. Software can assign high or low priority

to other sources. All interrupts that are new to the 8051

family, except for the PFI, have a lower natural priority

than the originals.

There are five control bits in special function registers

that affect the Watchdog Timer and two status flags that

reportto the user. WDIF (WDCON.3) is the interrupt flag

thatissetattimerterminationwhenthereare512clocks

remaining until the reset flag is set. WTRF (WDCON.2)

is the flag that is set when the timer has completely

timed out. This flag is normally associated with a CPU

resetandallowssoftwaretodeterminetheresetsource.

INTERRUPT SOURCES AND PRIORITIES Table 9

NATURAL

PRIORITY

NAME

PFI

DESCRIPTION

Power Fail Interrupt

External Interrupt 0

Timer 0

VECTOR

33h

8051/DALLAS

DALLAS

8051

1

2

INT0

TF0

03h

0Bh

13h

3

8051

INT1

TF1

External Interrupt 1

Timer 1

4

8051

1Bh

23h

5

8051

SCON0

TF2

TI0 or RI0 from serial port 0

Timer 2

6

8051

2Bh

3Bh

43h

7

8051

SCON1

INT2

INT3

INT4

INT5

WDTI

RTCI

TI1 or RI1 from serial port 1

External Interrupt 2

External Interrupt 3

External Interrupt 4

External Interrupt 5

Watchdog Time–Out Interrupt

Real Time Clock Interrupt

8

DALLAS

9

4Bh

53h

10

11

12

13

14

5Bh

63h

6Bh

022197 22/40

DS87C530

1. Apply the address value,

2. Apply the data value,

TIMED ACCESS PROTECTION

It is useful to protect certain SFR bits from an accidental

write operation. The Timed Access procedure stops an

errant CPU from accidentally changing these bits. It

requires that the following instructions precede a write

of a protected bit.

3. Select the programming option from Table 10 using

the control signals,

4. Increase the voltage on V from 5V to 12.75V if

PP

writing to the EPROM,

MOV

0C7h, #0AAh

0C7h, #55h

5. Pulse the PROG signal five times for EPROM array

and25timesforencryptiontable, lockbits, andother

EPROM bits,

Writing an AAh then a 55h to the Timed Access register

(location C7h) opens a 3 cycle window for write access.

Thewindowallowssoftwaretomodifyaprotectedbit(s).

If these instructions do not immediately precede the

write operation, then the write will not take effect. The

protected bits are:

6. Repeat as many times as necessary.

SECURITY OPTIONS

The DS87C530 employs a standard three–level lock

that restricts viewing of the EPROM contents. A

64–byte Encryption Array allows the authorized user to

verify memory by presenting the data in encrypted form.

EXIF.0

BGS

POR

EWT

RWT

WDIF

Band–gap Select

WDCON.6

WDCON.1

WDCON.0

WDCON.3

ROMSIZE.2 RMS2

ROMSIZE.1 RMS1

ROMSIZE.0 RMS0

TRIM.7–0

Power–on Reset flag

Enable Watchdog Reset

Restart Watchdog

Watchdog Interrupt Flag

ROM size select 2

ROM size select 1

ROM size select 0

All RTC trim functions

Lock Bits

The security lock consists of three lock bits. These bits

selectatotalof4levelsofsecurity. Higherlevelsprovide

increasing security but also limit application flexibility.

Table 11 shows the security settings. Note that the pro-

grammer cannot directly read the state of the security

lock. User software has access to this information as

described in the Memory section.

RTCC.2

RTCC.0

RTCWE RTC Write Enable

RTCE

RTC Oscillator Enable

Encryption Array

TheEncryptionArrayallowsanauthorizedusertoverify

EPROM without allowing the true memory to be

dumped. During a verify, each byte is Exclusive NORed

(XNOR) with a byte in the Encryption Array. This results

inatruerepresentationoftheEPROMwhiletheEncryp-

tionisunprogrammed(FFh). OncetheEncryptionArray

is programmed in a non–FFh state, the verify value will

be encrypted.

EPROM PROGRAMMING

The DS87C530 follows standards for a 16K byte

EPROMversioninthe8051family. It is available in a UV

erasable, ceramic windowed package and in plastic

packages for one–time user–programmable versions.

The part has unique signature information so program-

mers can support its specific EPROM options.

For encryption to be effective, the Encryption Array

must be unknown to the party that is trying to verify

memory. The entire EPROM also should be a non–FFh

state or the Encryption Array can be discovered.

PROGRAMMING PROCEDURE

The DS87C530 should run from a clock speed between

4 and 6 MHz when programmed. The programming fix-

ture should apply address information for each byte to

the address lines and the data value to the data lines.

The control signals must be manipulated as shown in

Table 10. The diagram in Figure 5 shows the expected

electrical connection for programming. Note that the

programmer must apply addresses in demultiplexed

fashion to Ports 1 and 2 with data on Port 0. Waveforms

and timing are provided in the Electrical Specifications.

Program the DS87C530 as follows:

The Encryption Array is programmed as shown in Table

10. Note that the programmer can not read the array.

Also note that the verify operation always uses the

Encryption Array. The array has no impact while FFh.

Simply programming the array to a non–FFh state will

cause the encryption to function.

022197 23/40

DS87C530

OTHER EPROM OPTIONS

SIGNATURE

The DS87C530 has user selectable options that must

be set before beginning software execution. These

options use EPROM bits rather than SFRs.

The Signature bytes identify the product and program-

ming revision to EPROM programmers. This informa-

tion is at programming addresses 30h, 31h, and 60h.

This information is as follows::

Program the EPROM selectable options as shown in

Table10.TheOptionRegistersetsorreadstheseselec-

tions. The bits in the Option Control Register have the

following function:

Address

30h

31h

Value

DAh

30h

Meaning

Manufacturer

Model

60h

01h

Extension

Bit 7 –4 Reserved, program to a 1.

Bit 3 Watchdog POR default. Set=1; Watchdog reset

function is disabled on power–up. Set=0; Watchdog

reset function is enabled automatically.

Bit 2–0 Reserved. Program to a 1.

EPROM PROGRAMMING MODES Table 10

MODE

Program Code Data

Verify Code Data

RST

H

PSEN ALE/PROG EA/VPP P2.6

P2.7

H

P3.3

H

P3.6

P3.7

H

L

PL

H

12.75V

H

L

H

L

H

L

H

Program Encryption Array

Address 0–3Fh

H

PL

12.75V

H

Program Lock Bits LB1

H

L

PL

12.75V

H

L

H

L

H

L

H

L

LB2

LB3

H

L

Program Option Register

Address FCh

H

Read Signature or Option

Registers 30, 31, 60, FCh

H

L

H

L

* PL indicates pulse to a logic low.

EPROM LOCK BITS Table 11

LEVEL

LOCK BITS

PROTECTION

LB1

U

LB2

U

LB3

U

1

2

No program lock. Encrypted verify if encryption table was pro-

grammed.

P

U

Prevent MOVC instructions in external memory from reading pro-

gram bytes in internal memory. EA is sampled and latched on reset.

Allow no further programming of EPROM.

3

4

P

U

P

Level 2 plus no verify operation. Also, prevent MOVX instructions in

external memory from reading SRAM (MOVX) in internal memory.

Level 3 plus no external execution.

022197 24/40

DS87C530

EPROM PROGRAMMING CONFIGURATION Figure 5

A0 – A7

+5V

PROG/VERIFY DATA

7

6

5

4

3

2

50 49 48 47

PORT 0

8

9

46

45

44

43

PORT 1

RST

10

11

PROGRAM SIGNALS

CONTROL SIGNALS

EA/V

PP

13

41

40

14

15

ALE/PROG

PROGRAM SIGNALS

CONTROL SIGNALS

16

17

PSEN

P2.7

P2.6

CONTROL SIGNALS

P3.3

P3.4

P3.5

A14

A15

35

34

PORT 2

27 28 29 30 31 32 33

A8 – A13

022197 25/40

DS87C530

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground

Operating Temperature

–0.3V to +7.0V

0°C to 70°C

Storage Temperature

Soldering Temperature

–55°C to +125°C

260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods of time may affect reliability.

DC ELECTRICAL CHARACTERISTICS

(0°C to 70°C; V_CC=4.0V to 5.5V)

PARAMETER

SYMBOL

MIN

4.5

TYP

5.0

MAX

5.5

UNITS

NOTES

Supply Voltage

V

CC

V

1

Power–fail Warning

Minimum Operating Voltage

Backup Battery Voltage

V

PFW

4.25

4.0

4.38

4.13

3.0

4.5

V

RST

4.25

V

I

2.5

V

–0.7

V

BAT

CC

Supply Current Active Mode

@ 33 MHz

30

mA

2

3

CC

Supply Current Idle Mode

@ 33 MHz

I

15

1

mA

µA

Idle

Supply Current Stop Mode,

Band–gap Disabled

I

4

Stop

Supply Current Stop Mode,

Band–gap Enabled

I

50

4

SPBG

Backup Supply Current, Data

Retention Mode

I

0

0.5

+0.8

11

BAT

Input Low Level

V

IL

–0.3

2.0

V

1

Input High Level

V

IH

V

+0.3

CC

Input High Level XTAL1 and RST

V

IH2

3.5

+0.3

Output Low Voltage

V

OL1

0.15

0.45

@ I =1.6 mA

OL

Output Low Voltage Ports 0, 2,

ALE, and PSEN @ I =3.2 mA

V

0.45

V

1

OL2

OH1

OH2

OH3

OL

Output High Voltage Ports 1, 2, 3,

ALE, PSEN @ I =–50 µA

V

2.4

1,6

1, 7

1, 5

OH

Output High Voltage Ports 1, 2, 3

V

@ I = –1.5 mA

OH

Output High Voltage Port 0 in Bus

V

Mode I = –8 mA

OH

Input Low Current Ports 1, 2, 3

@ 0.45V

I

–55

–650

+10

µA

IL

Transition Current from 1 to 0

Ports 1, 2, 3 @ 2V

I

TL

8

10

9

Input Leakage Port 0, EA pins, I/O

Mode

I

–10

L

Input Leakage Port 0, Bus Mode

RST Pull–down Resistance

I

–300

50

+300

170

µA

kΩ

L

R

RST

022197 26/40

DS87C530

NOTES FOR DC ELECTRICAL CHARACTERISTICS:

All parameters apply to both commercial and industrial temperature operation unless otherwise noted.

1. All voltages are referenced to ground.

2. Active current is measured with a 33 MHz clock source driving XTAL1, V =RST=5.5V, all other pins discon-

CC

nected.

3. Idle mode current is measured with a 33 MHz clock source driving XTAL1, V =5.5V, RST at ground, all other

CC

pins disconnected.

4. Stop mode current measured with XTAL1 and RST grounded, V =5.5V, all other pins disconnected. This value

CC

is not guaranteed. Users that are sensitive to this specification should contact Dallas Semiconductor for more

information.

5. When addressing external memory.

6. RST=V . This condition mimics operation of pins in I/O mode. Port 0 is tristated in reset and when at a logic

CC

high state during I/O mode.

7. During a 0 to 1 transition, a one–shot drives the ports hard for two clock cycles. This measurement reflects port

in transition mode.

8. Ports 1, 2, and 3 source transition current when being pulled down externally. It reaches its maximum at approxi-

mately 2V.

9. 0.45<V <V . Not a high impedance input. This port is a weak address holding latch in Bus Mode. Peak current

IN

CC

occurs near the input transition point of the latch, approximately 2V.

10.0.45<V <V RST=V . This condition mimics operation of pins in I/O mode.

.

IN

CC

11. V =0V, V

=3.3V. 32.768 KHz crystal with 12.5 pF load capacitance between RTCX1 and RTCX2 pins. RTCE

BAT

CC

bit set to 1.

TYPICAL I_CCVERSUS FREQUENCY Figure 6

I

CC

@ 5V

mA

30

25

20

15

5

3

2

0

2

4

6

8

10 12

16

20

24

30

33 MHz XTAL

FREQUENCY

022197 27/40

DS87C530

AC ELECTRICAL CHARACTERISTICS

(0°C to 70°C; V_CC=4.0V to 5.5V)

33 MHz

VARIABLE CLOCK

MIN

MAX

MIN

MAX

PARAMETER

SYMBOL

UNITS

MHz

ns

Oscillator Frequency

1/t

0

33

0

33

CLCL

LHLL

AVLL

ALE Pulse Width

t

40

10

1.5t

–5

CLCL

Port 0 Address Valid to ALE Low

Address Hold after ALE Low

ALE Low to Valid Instruction In

ALE Low to PSEN Low

0.5t

ns

t

ns

LLAX1

t

56

41

2.5t

–20

ns

LLIV

CLCL

t

10

55

0.5t

–5

ns

LLPL

CLCL

PSEN Pulse Width

t

2t

– 5

ns

PLPH

CLCL

PSEN Low to Valid Instr. In

Input Instruction Hold after PSEN

Input Instruction Float after PSEN

Port 0 Address to Valid Instr. In

Port 2 Address to Valid Instr. In

PSEN Low to Address Float

t

2t

–20

ns

PLIV

CLCL

t

0

ns

PXIX

t

26

71

81

0

t

–5

ns

PXIZ

CLCL

3t

–20

–25

ns

AVIV

CLCL

t

3.5t

ns

AVIV2

CLCL

t

0

ns

PLAZ

NOTES FOR AC ELECTRICAL CHARACTERISTICS:

All parameters apply to both commercial and industrial temperature range operation unless otherwise noted. All sig-

nals rated over operating temperature. All signals characterized with load capacitance of 80 pF except Port 0, ALE,

PSEN, RD and WR with 100 pF. Interfacing to memory devices with float times (turn off times) over 25 ns may cause

contention. This will not damage the parts, but will cause an increase in operating current.

022197 28/40

DS87C530

MOVX CHARACTERISTICS USING STRETCH MEMORY CYCLES (0°C to 70°C; V_CC=4.0V to 5.5V)

VARIABLE CLOCK

PARAMETER

SYMBOL

UNITS

STRETCH

MIN

1.5t

MAX

Data Access ALE Pulse Width

t

–5

ns

t

=0

>0

LHLL2

CLCL

MCS

2t

CLCL

–5

Address Hold after ALE Low for

MOVX Write

t

0.5t

ns

t

=0

>0

LLAX2

CLCL

MCS

t

–5

CLCL

RD Pulse Width

t

2t

–5

–10

t

=0

>0

RLRH

CLCL

MCS

t

MCS

WR Pulse Width

t

2t

–5

–10

t

=0

>0

WLWH

CLCL

MCS

t

MCS

RD Low to Valid Data In

t

2t

t

–20

t

=0

>0

RLDV

CLCL

MCS

–20

MCS

Data Hold after Read

Data Float after Read

t

0

ns

RHDX

t

2t

–5

t

=0

>0

RHDZ

CLCL

MCS

–5

CLCL

2.5t

–20

–40

ALE Low to Valid Data In

t

ns

t

=0

>0

CLCL

LLDV

MCS

t

+t

MCS CLCL

Port 0 Address to Valid Data In

Port 2 Address to Valid Data In

ALE Low to RD or WR Low

t

3t

CLCL

–20

t

=0

>0

AVDV1

AVDV2

MCS

t

+1.5t

MCS

–20

CLCL

3.5t

–20

t

=0

>0

CLCL

+2t

MCS

t

–20

CLCL

MCS

t

0.5t

–5

0.5t

+5

t

=0

>0

LLWL

CLCL

MCS

t

+5

CLCL

Port 0 Address to RD or WR Low

Port 2 Address to RD or WR Low

t

–5

t

=0

>0

AVWL1

AVWL2

CLCL

MCS

2t

CLCL

1.5t

2.5t

–10

t

=0

>0

CLCL

MCS

Data Valid to WR Transition

Data Hold after Write

t

–5

ns

QVWX

t

2t

–5

t

=0

>0

WHQX

CLCL

MCS

RD Low to Address Float

t

–0.5t

–5

ns

RLAZ

CLCL

RD or WR High to ALE High

t

0

10

t

=0

>0

WHLH

MCS

t

–5

t

+5

CLCL

NOTE: t

is a time period related to the Stretch memory cycle selection. The following table shows the value of

MCS

t

for each Stretch selection.

MCS

M2

0

M1

0

M0

0

MOVX CYCLES

2 machine cycles

3 machine cycles (default)

4 machine cycles

5 machine cycles

6 machine cycles

7 machine cycles

8 machine cycles

9 machine cycles

t

MCS

0

1

4 t

CLCL

8 t

CLCL

0

1

0

1

12 t

16 t

20 t

24 t

28 t

CLCL

1

0

1

0

1

0

1

022197 29/40

DS87C530

EXTERNAL CLOCK CHARACTERISTICS

(0°C to 70°C; V_CC=4.0V to 5.5V)

PARAMETER

SYMBOL

MIN

10

TYP

MAX

UNITS

ns

NOTES

Clock High Time

Clock Low Time

Clock Rise Time

Clock Fall Time

t

CHCX

t

10

ns

CLCX

t

5

ns

CLCL

t

ns

CHCL

SERIAL PORT MODE 0 TIMING CHARACTERISTICS

(0°C to 70°C; V_CC=4.0V to 5.5V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Serial Port Clock Cycle Time

SM2=0, 12 clocks per cycle

SM2=1, 4 clocks per cycle

t

XLXL

12t

4t

ns

CLCL

Output Data Setup to Clock Rising

SM2=0, 12 clocks per cycle

SM2=1, 4 clocks per cycle

t

QVXH

XHQX

10t

3t

ns

CLCL

Output Data Hold from Clock Rising

SM2=0, 12 clocks per cycle

SM2=1, 4 clocks per cycle

2t

ns

CLCL

t

Input Data Hold after Clock Rising

SM2=0, 12 clocks per cycle

SM2=1, 4 clocks per cycle

t

XHDX

XHDV

t

ns

CLCL

Clock Rising Edge to Input

Data Valid

t

SM2=0, 12 clocks per cycle

SM2=1, 4 clocks per cycle

11t

3t

ns

CLCL

EXPLANATION OF AC SYMBOLS

In an effort to remain compatible with the original 8051

family, this device specifies the same parameters as

such devices, using the same symbols. For complete-

ness, the following is an explanation of the symbols.

t

Time

A

C

D

H

L

Address

Clock

Input data

Logic level high

Logic level low

Instruction

PSEN

Output data

RD signal

Valid

I

P

Q

R

V

W

X

Z

WR signal

No longer a valid logic level

Tristate

022197 30/40

DS87C530

POWER CYCLE TIMING CHARACTERISTICS

(0°C to 70°C; V_CC=4.0V to 5.5V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Cycle Start–up Time

Power–on Reset Delay

t

1.8

ms

1

2

CSU

POR

t

65536

t

CLCL

NOTES FOR POWER CYCLE TIMING:

1. Start–up time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592 MHz

crystal manufactured by Fox.

2. Reset delay is a synchronous counter of crystal oscillations after crystal start–up. At 33 MHz, this time is

1.99 ms.

EPROM PROGRAMMING AND VERIFICATION

(21°C to 27°C; V_CC=4.5V to 5.5V)

PARAMETER

SYMBOL

MIN

TYP

MAX

13.0

50

UNITS

V

NOTES

Programming Voltage

Programming Supply Current

Oscillator Frequency

V

12.5

1

PP

I

mA

1/t

4

6

MHz

CLCL

AVGL

Address Setup to PROG Low

Address Hold after PROG

Data Setup to PROG Low

Data Hold after PROG

t

48t

CLCL

t

48t

GHAX

t

DVGL

GHDX

t

Enable High to V

t

EHSH

PP

V

Setup to PROG Low

Hold after PROG

t

10

90

µs

PP

SHGL

GHSL

GLGH

PROG Width

t

110

Address to Data Valid

Enable Low to Data Valid

Data Float after Enable

PROG High to PROG Low

t

48t

AVQV

CLCL

t

48t

ELQV

EHQZ

GHGL

t

0

t

10

µs

NOTE:

1. All voltages are referenced to ground.

022197 31/40

DS87C530

EXTERNAL PROGRAM MEMORY READ CYCLE

t

LHLL

t

LLIV

ALE

t

AVLL

t

PLPH

t

PLIV

PSEN

t

LLPL

t

PXIZ

PLAZ

t

PXIX

t

LLAX1

ADDRESS

A0–A7

INSTRUCTION

IN

ADDRESS

A0–A7

PORT 0

t

AVIV1

t

AVIV2

ADDRESS A8–A15 OUT

PORT 2

EXTERNAL DATA MEMORY READ CYCLE

t

LLDV

ALE

t

WHLH

t

LLWL

LLAX1

PSEN

RD

t

RLRH

t

RLDV

t

AVLL

t

RLAZ

t

RHDZ

t

RHDX

t

AVWL1

INSTRUCTION

IN

ADDRESS

A0–A7

ADDRESS

A0–A7

DATA IN

PORT 0

t

AVDV1

t

AVDV2

PORT 2

ADDRESS A8–A15 OUT

t

AVWL2

022197 32/40

DS87C530

DATA MEMORY WRITE CYCLE

ALE

t

WHLH

t

LLWL

PSEN

WR

t

LLAX2

t

WLWH

t

AVLL

t

WHQX

INSTRUCTION

IN

ADDRESS

A0–A7

ADDRESS

A0–A7

DATA OUT

PORT 0

PORT 2

t

QVWX

t

AVWL1

ADDRESS A8–A15 OUT

t

AVWL2

DATA MEMORY WRITE WITH STRETCH=1

Last Cycle of

First

Machine

Cycle

Second

Machine

Cycle

Third

Machine

Cycle

Need

Instruction

Machine Cycle

MOVX Instruction

C1

C2

C3

C4

C1

C2

C3

C4

C1

C2

C3

C4

C1

C2

C3

C4

C1

C2

C3

C4

CLK

ALE

PSEN

WR

PORT 0

A0–A7

D0–D7

A0–A7

D0–D7

A0–A7

D0–D7

MOVX

Instruction

Address

Next Instr.

Address

MOVX

Data

Address

MOVX Data

MOVX

Instruction

Read

PORT 2

A8–A15

022197 33/40

DS87C530

DATA MEMORY WRITE WITH STRETCH=2

Last Cycle

of Previous

Instruction

First

Machine

Cycle

Second

Machine

Cycle

Third

Machine

Cycle

Fourth

Machine

Cycle

Need

Instruction

Machine

Cycle

MOVX Instruction

C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4

C1 C2 C3 C4

C1 C2 C3 C4 C1 C2 C3 C4

CLK

ALE

PSEN

WR

A0–A7

D0–D7

A0–A7

D0–D7

A0–A7

D0–D7

A0–A7

D0–D7

PORT 0

MOVX

Instruction

Address

Next Instr.

Address

MOVX

Data

Address

MOVX Data

MOVX

Instruction

Read

PORT 2

A8–A15

FOUR CYCLE DATA MEMORY WRITE

STRETCH VALUE=2

EXTERNAL CLOCK DRIVE

t

CLCL

t

CHCX

XTAL1

t

CLCH

CHCL

t

CLCX

022197 34/40

DS87C530

SERIAL PORT MODE 0 TIMING

SERIAL PORT 0 (SYNCHRONOUS MODE)

HIGH SPEED OPERATION SM2=1=>TXD CLOCK=XTAL/4

ALE

PSEN

t

QVXH

D0

t

XHQX

WRITE TO SBUF

RXD

D1

D2

D3

D4

D5

D7

D8

DATA OUT

TRANSMIT

TXD

CLOCK

t

XLXL

TI

WRITE TO SCON

TO CLEAR RI

RXD

DATA IN

D0

D1

D2

D3

D4

D5

D7

D8

TXD

CLOCK

RECEIVE

t

XHDX

XHDV

RI

SERIAL PORT 0 (SYNCHRONOUS MODE)

SM2=0=>TXD CLOCK=XTAL/12

ALE

PSEN

1/(XTAL FREQ/12)

D1

WRITE TO SBUF

RXD

DATA OUT

D0

D6

D7

TXD

CLOCK

TI

WRITE TO SCON TO CLEAR RI

RXD DATA IN

D0

D1

D6

D7

TXD CLOCK

RI

022197 35/40

DS87C530

POWER CYCLE TIMING

V

CC

PFW

V

RST

SS

INTERRUPT

SERVICE ROUTINE

t

CSU

XTAL1

t

POR

INTERNAL RESET

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS

PROGRAMMING

VERIFICATION

ADDRESS

A0–A15

D0–D7

ADDRESS

t

AVQV

DATA IN

DATA OUT

t

GHDX

DVGL

5 PULSES

t

GHAX

AVGL

ALE/PROG

t

GHSL

t

SHGL

t

GHGL

GLGH

EA/V

PP

t

EHQZ

EHSH

ELQV

CONTROL

SIGNALS

022197 36/40

DS87C530

52–PIN PLCC

INCHES.

PKG

DIM

A

52–PIN

MIN

MAX

0.180

0.120

–

0.165

0.090

0.020

0.026

0.013

0.008

0.042

0.785

0.750

0.690

0.785

0.750

0.690

A1

A2

B

0.032

0.021

0.013

0.048

0.795

0.756

0.730

0.795

0.756

0.730

B1

c

CH1

D

D1

D2

E

E1

E2

e1

N

0.050 BSC

52

–

56–G4006–001

022197 37/40

DS87C530

52–PIN CER QUAD

PKG

DIM

A

52–PIN

MIN

MAX

0.185

–

0.165

0.040

0.026

0.013

0.008

0.035

A1

B

0.032

0.021

0.013

0.040

B1

c

52–PIN CER QUAD

CH1–

45°

D

D1

D2

E

0.760

0.740

0.700

0.760

0.740

0.700

0.800

0.770

0.730

0.800

0.770

0.730

E1

E2

e1

N

0.050 BSC

52

–

56–G4007–001

022197 38/40

DS87C530

52–PIN TQFP

PKG

52–PIN

NOM

DIM

A

MIN

–

MAX

1.20

0.15

1.05

0.40

0.20

12.20

SUGGESTED PAD LAYOUT

52–PIN TQFP

–

A1

A2

b

0.05

0.95

0.25

0.09

11.80

0.10

1.00

0.32

c

–

D

12.00

10.00 BSC

12.00

10.00 BSC

0.65 BSC

0.60

D1

E

11.80

0.45

12.20

0.75

E1

e

L

022197 39/40

DS87C530

DATA SHEET REVISION SUMMARY

The following represent the key differences between 06/08/95 and 02/20/97 version of the DS87C530 data sheet.

Please review this summary carefully.

1. Update ALE pin description.

2. Add note pertaining to erasure window.

3. Add note pertaining to internal MOVX SRAM.

4. Change Note 6 from RST=5.5V to RST=V

.

CC

5. Change Note 10 from RST=5.5V to RST=V

.

CC

6. Change serial port mode 0 timing diagram label from t

7. Add information pertaining to 52–pin TQFP package.

to t

.

QVXH

QVXL

022197 40/40


型号：	DS87C530-KCL
厂家：	DALLAS SEMICONDUCTOR
描述：	EPROM MICRO WITH REAL TIME CLOCK EPROM微与实时时钟微控制器和处理器外围集成电路装置静态存储器可编程只读存储器电动程控只读存储器时钟
文件：	总40页 (文件大小：435K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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