1516A-800-301E [DATADELAY]
Delay Line;型号: | 1516A-800-301E |
厂家: | DATA DELAY DEVICES, INC. |
描述: | Delay Line |
文件: | 总3页 (文件大小:274K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1516
5-TAP DIP/SMD DELAY LINE
TD/TR = 3
(SERIES 1516)
FEATURES
PACKAGES
•
•
•
•
•
5 taps of equal delay increment
Delays to 200ns
IN
Signal Input
GND
IN
T1
GND
T5
T4
1
2
3
4
8
7
6
5
T1-T5 Tap Outputs
GND Ground
Low profile
Epoxy encapsulated
Meets or exceeds MIL-D-23859C
Note: Standard pinout shown
Other pinouts available
T2
T3
PART NUMBER CONSTRUCTION
FUNCTIONAL DESCRIPTION
The 1516-series device is a fixed, single-input, five-
output, passive delay line. The signal input (IN) is
reproduced at the outputs (T1-T5) in equal increments.
The delay from IN to T5 (TD) and the characteristic
impedance of the line (Z) are determined by the dash
number. The rise time (TR) of the line is 30% of TD, and
the 3dB bandwidth is given by 1.05 / TD. The device is
available in a 8-pin DIP (1516) or a 8-pin SMD (1516S),
and a wide range of pinouts may be specified.
1516(S)m - xxx - zzz p
MOUNTING HEIGHT CODE
See Table
DELAY TIME
Expressed in nanoseconds (ns)
First two digits are significant figures
Last digit specifies # of zeros to follow
IMPEDANCE
Expressed in nanoseconds (ns)
First two digits are significant figures
Last digit specifies # of zeros to follow
Part numbers are constructed according to the scheme
shown at right. For example, 1516C-101-500B is a 290
mil DIP, 100ns, 50Ω delay line with pinout code B.
Similarly, 1516SB-151-501 is a 240 mil SMD, 150ns,
500Ω delay line with standard pinout.
PINOUT CODE
See Table
Omit for STD pinout
SERIES SPECIFICATIONS
DELAY SPECIFICATIONS
•
•
•
•
•
Dielectric breakdown:
Distortion @ output:
50 Vdc
TD
TI
TR
ATTENUATION (%) TYPICAL
(ns)
(ns)
(ns)
Z=50Ω Z=100Ω Z=200Ω Z=300Ω Z=500Ω
10% max.
5
1.0
2.0
3.0
4.0
N/A
3
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
7
8
N/A
5
N/A
N/A
N/A
5
N/A
N/A
N/A
N/A
7
Operating temperature: -55°C to +125°C
10
15
3.0
5.0
3
5
Storage temperature:
-55°C to +125°C
20
4.0
6.0
3
5
Temperature coefficient: 100 PPM/°C
25
5.0
7.0
3
5
5
30
6.0
10.0
13.0
15.0
20.0
25.0
26.0
30.0
32.0
40.0
50.0
60.0
70.0
3
5
5
7
40
8.0
3
5
5
7
PINOUT CODES
50
10.0
12.0
15.0
16.0
20.0
22.0
25.0
30.0
36.0
50.0
3
5
7
7
60
3
6
7
8
CODE IN T1 T2 T3 T4 T5
GND
1,8
5,8
8
75
3
6
7
8
STD
A
2
1
1
7
1
1
3
2
7
2
2
7
4
3
3
6
7
2
5
4
6
3
3
6
6
6
4
5
6
3
7
7
5
4
4
4
80
4
6
7
8
100
110
125
150
180
200
4
6
7
8
B
4
6
7
8
C
1,8
5,8
5,8
4
6
7
8
D
N/A
N/A
N/A
8
10
10
12
10
10
12
E
8
10
MOUNTING HEIGHT CODES
Notes: TI represents nominal tap-to-tap delay increment
Tolerance on TD = ±5% or ±2ns, whichever is greater
Tolerance on TI = ±5% or ±1ns, whichever is greater
“N/A” indicates that delay is not available at this Z
CODE
HEIGHT (MAX)
0.187
DIP
Yes
Yes
Yes
SMD
No
A
B
C
0.240
Yes
Yes
0.290
Note: Codes A and B are not available
for all values of TD
2008 Data Delay Devices
Contact technical staff for details
Doc #97029
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1/11/2008
1516
FUNCTIONAL DIAGRAM
T1 T2 T3 T4
IN
T5
GND
GND
PACKAGE DIMENSIONS
8
7
6
5
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
1
2
3
4
.280
.500 MAX.
MAX.
See
Table
.015 TYP.
.070 MAX.
.010 .002
±
.018
TYP.
.350
.300 .010
±
MAX.
3 Equal spaces
each .100 .010
±
Non-Accumulative
.020
.040
.010 TYP.
TYP.
TYP.
8
1
7
2
6
3
5
4
.270
.430
TYP.
TYP.
.100
.300
.520 MAX.
.110
See
.050
Table
TYP.
1516S-xx (Gull-Wing)
Doc #97029
1/11/2008
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
1516
PASSIVE DELAY LINE TEST SPECIFICATIONS
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature:
Input Pulse:
25oC ± 3oC
Rload
Cload
:
:
10MΩ
High = 3.0V typical
Low = 0.0V typical
50Ω Max.
10pf
Threshold: 50% (Rising & Falling)
Source Impedance:
Rise/Fall Time:
3.0 ns Max. (measured
at 10% and 90% levels)
Pulse Width (TD <= 75ns): PWIN = 100ns
Period
Pulse Width (TD > 75ns): PWIN = 2 x TD
Period (TD > 75ns): PERIN = 10 x TD
(TD <= 75ns): PERIN = 1000ns
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PERIN
PWIN
TRISE
TFALL
INPUT
VIH
90%
50%
90%
50%
10%
SIGNAL
VIL
10%
TRISE
TFALL
TRISE
TFALL
OUTPUT
SIGNAL
VOH
90%
50%
90%
50%
10%
VOL
10%
Timing Diagram For Testing
IN
RIN
T1
OUT
IN
T2
OSCILLOSCOPE
PULSE
GENERATOR
TRIG
DEVICE UNDER T3
TRIG
TEST (DUT)
T4
T5
50 Ω
ROUT
RIN = ROUT = ZLINE
Test Setup
Doc #97029
1/11/2008
DATA DELAY DEVICES, INC.
3
3 Mt. Prospect Ave. Clifton, NJ 07013
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