1518-5-80IN [DATADELAY]
5-TAP SMD DELAY LINE; 5 -TAP贴片延迟线
| 型号： | 1518-5-80IN |
| 厂家： | 
DATA DELAY DEVICES, INC. |
| 描述： | 5-TAP SMD DELAY LINE |
| 文件： | 总2页 (文件大小：28K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1518
Ò
5-TAP SMD DELAY LINE
TD/TR = 3
(SERIES 1518)
data
delay
3
devices, inc.
FEATURES
PACKAGES
IN
N/C
T2
N/C
T1
1
2
3
4
5
6
7
14
13
12
11
10
9
·
·
·
·
·
5 taps of equal delay increment
Delays to 200ns
Low profile
Epoxy encapsulated
Meets or exceeds MIL-D-23859C
IN
Signal Input
T1-T5 Tap Outputs
GND Ground
N/C
T3
N/C
T4
N/C
N/C
N/C
Note: Standard pinout shown
Alt. pinout available
T5
GND
8
PART NUMBER CONSTRUCTION
FUNCTIONAL DESCRIPTION
The 1518-series device is a fixed, single-input, five-
output, passive delay line. The signal input (IN) is
reproduced at the outputs (T1-T5) in equal increments.
The delay from IN to T5 (TD) and the characteristic
impedance of the line (Z) are determined by the dash
number. The rise time (TR) of the line is 30% of TD, and
the 3dB bandwidth is given by 1.05 / TD. The device is
available in a 14-pin SMD with two pinout options.
1518 - xxx - zzz p
DELAY TIME
Expressed in nanoseconds (ns)
First two digits are significant figures
Last digit specifies # of zeros to follow
IMPEDANCE
Expressed in nanoseconds (ns)
First two digits are significant figures
Last digit specifies # of zeros to follow
Part numbers are constructed according to the scheme
shown at right. For example, 1518-101-500A is a 100ns,
50W delay line with pinout code A. Similarly, 1518-151-
501 a is 150ns, 500W delay line with standard pinout.
PINOUT CODE
See Table
Omit for STD pinout
SERIES SPECIFICATIONS
DELAY SPECIFICATIONS
TD
(ns)
TI
(ns)
TR
(ns)
ATTENUATION (%) TYPICAL
·
·
·
·
·
Dielectric breakdown:
Distortion @ output:
Operating temperature: -55°C to +125°C
Storage temperature: -55°C to +125°C
50 Vdc
10% max.
Z=50W Z=100W Z=200W Z=300W Z=500W
5
10
15
20
25
30
40
50
60
75
80
100
110
125
150
180
200
1.0
2.0
3.0
4.0
5.0
6.0
8.0
10.0
12.0
15.0
16.0
20.0
22.0
25.0
30.0
36.0
50.0
3.0
4.0
5.0
6.0
7.0
10.0
13.0
15.0
20.0
25.0
26.0
30.0
32.0
40.0
50.0
60.0
70.0
N/A
3
3
3
3
3
3
3
3
3
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
7
8
N/A
5
5
5
5
5
5
5
6
6
6
6
6
6
8
8
10
N/A
N/A
N/A
5
5
5
5
7
7
7
7
7
7
7
10
10
12
N/A
N/A
N/A
N/A
7
7
7
7
8
8
8
8
8
8
10
10
12
Temperature coefficient: 100 PPM/°C
T1 T2 T3 T4
IN
T5
4
GND
GND
N/A
N/A
N/A
Functional Diagram
.505
Notes: TI represents nominal tap-to-tap delay increment
.018
.050
Tolerance on TD = ±5% or ±2ns, whichever is greater
Tolerance on TI = ±5% or ±1ns, whichever is greater
“N/A” indicates that delay is not available at this Z
.185
14
1
8
7
.290
.100
.425
PINOUT CODES
CODE IN T1 T2 T3 T4 T5
GND
7
8,14
STD
A
1
1
13
12
3
4
11
10
5
6
6
7
.300
Package Dimensions
Ó1997 Data Delay Devices
Doc #97030
2/7/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1518
PASSIVE DELAY LINE TEST SPECIFICATIONS
TEST CONDITIONS
INPUT:
Ambient Temperature:
Input Pulse:
OUTPUT:
25oC ± 3oC
High = 3.0V typical
Low = 0.0V typical
50W Max.
3.0 ns Max. (measured
at 10% and 90% levels)
Rload
Cload
:
:
10MW
10pf
Threshold: 50% (Rising & Falling)
Source Impedance:
Rise/Fall Time:
Pulse Width (TD <= 75ns): PWIN = 100ns
Period (TD <= 75ns): PERIN = 1000ns
Pulse Width (TD > 75ns): PWIN = 2 x TD
Period (TD > 75ns): PERIN = 10 x TD
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PERIN
PWIN
TRISE
TFALL
INPUT
SIGNAL
VIH
90%
50%
10%
90%
50%
10%
VIL
TRISE
TFALL
TRISE
TFALL
OUTPUT
SIGNAL
VOH
90%
50%
10%
90%
50%
10%
VOL
Timing Diagram For Testing
IN
RIN
T1
T2
OUT
IN
OSCILLOSCOPE
PULSE
GENERATOR
TRIG
DEVICE UNDER T3
TRIG
TEST (DUT)
T4
T5
50 W
ROUT
RIN = ROUT = ZLINE
Test Setup
Doc #97030
2/7/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
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