3D3324G-50 [DATADELAY]
MONOLITHIC QUADRUPLE FIXED DELAY LINE; 单片翻两番固定延迟线
| 型号： | 3D3324G-50 |
| 厂家： | 
DATA DELAY DEVICES, INC. |
| 描述： | MONOLITHIC QUADRUPLE FIXED DELAY LINE |
| 文件： | 总4页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3D3324
MONOLITHIC QUADRUPLE
FIXED DELAY LINE
(SERIES 3D3324)
FEATURES
PACKAGES
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All-silicon, low-power CMOS technology
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
I1
N/C
I2
I3
I4
VDD
N/C
O1
N/C
O2
1
2
3
4
5
6
7
14
13
12
11
10
9
I1
N/C
I2
1
2
3
4
5
6
7
14
VDD
N/C
O1
Low ground bounce noise
13
12
11
10
9
Leading- and trailing-edge accuracy
Delay range: 10 through 6000ns
Delay tolerance: 2% or 1.0ns
I3
N/C
O2
I4
N/C
GND
O3
N/C
GND
O3
O4
8
O4
Temperature stability: ±3% typ (-40C to 85C)
Vdd stability: ±1% typical (3.0V to 3.6V)
Minimum input pulse width: 20% of total delay
14-pin Gull-Wing available as drop-in
replacement for hybrid delay lines
8
3D3324D-xx
SOIC
3D3324-xx
DIP
(150 Mil)
3D3324G-xx Gull-Wing
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3324 Quadruple Delay Line product family consists of fixed-
delay CMOS integrated circuits. Each package contains four matched,
independent delay lines. Delay values can range from 10ns through
6000ns. The input is reproduced at the output without inversion,
shifted in time as per the user-specified dash number. The 3D3324 is
CMOS-compatible and features both rising- and falling-edge accuracy.
I1
Delay Line 1 Input
Delay Line 2 Input
Delay Line 3 Input
Delay Line 4 Input
Delay Line 1 Output
Delay Line 2 Output
Delay Line 3 Output
Delay Line 4 Output
I2
I3
I4
O1
O2
O3
O4
The all-CMOS 3D3324 integrated circuit has been designed as a
reliable, economic alternative to hybrid fixed delay lines. It is offered in
a standard 14-pin auto-insertable DIP and a space saving surface
mount 14-pin SOIC.
VDD +3.3 Volts
GND Ground
N/C
No Connection
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
DELAY
PER LINE
(ns)
INPUT RESTRICTIONS
DIP-14
3D3324
-10
DIP-14
SOIC-14
Max Operating Absolute Max
Min Operating
Absolute Min
Oper. P.W.
5.0 ns
3D3324G 3D3324D
Frequency
33.3 MHz
22.2 MHz
16.7 MHz
13.3 MHz
11.1 MHz
8.33 MHz
6.67 MHz
3.33 MHz
1.67 MHz
Oper. Freq.
100.0 MHz
100.0 MHz
100.0 MHz
83.3 MHz
71.4 MHz
62.5 MHz
50.0 MHz
25.0 MHz
12.5 MHz
0.67 MHz
0.33 MHz
0.05 MHz
Pulse Width
15.0 ns
-10
-15
-10
-15
10 ± 1.0
15 ± 1.0
20 ± 1.0
25 ± 1.0
30 ± 1.0
40 ± 1.0
50 ± 1.0
100 ± 2.0
200 ± 4.0
-500
-15
22.5 ns
5.0 ns
-20
-20
-20
30.0 ns
5.0 ns
-25
-25
-25
37.5 ns
6.0 ns
-30
-30
-30
45.0 ns
7.0 ns
-40
-40
-40
60.0 ns
8.0 ns
-50
-50
-50
75.0 ns
10.0 ns
20.0 ns
40.0 ns
750.0 ns
1500.0 ns
9000.0 ns
-100
-200
-500
-1000
-6000
-100
-200
-500
-1000
-6000
-100
-200
-500
-1000
-6000
150.0 ns
300.0 ns
5.00 MHz
2.50 MHz
0.42 MHz
500 ± 10.0
1000 ± 20
6000 ±120
-1000
-6000
NOTES: Any delay between 10 and 6000 ns not shown is also available.
2006 Data Delay Devices
Doc #06018
5/10/2006
DATA DELAY DEVICES, INC.
1
3 Mt. Prospect Ave. Clifton, NJ 07013
3D3324
APPLICATION NOTES
To guarantee the Table 1 delay accuracy for
input frequencies higher than the Maximum
Operating Frequency, the 3D3324 must be
tested at the user operating frequency.
OPERATIONAL DESCRIPTION
The 3D3324 quadruple delay line architecture is
shown in Figure 1. The individual delay lines are
composed of a number of delay cells connected
in series. Each delay line produces at its output
a replica of the signal present at its input, shifted
in time. The delay lines are matched and share
the same compensation signals, which minimizes
line-to-line delay deviations over temperature and
supply voltage variations.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY
DEVICES be consulted.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Maximum and
an Absolute Maximum operating input
frequency and a Minimum and an Absolute
Minimum operating pulse width have been
specified.
OPERATING PULSE WIDTH
The Absolute Minimum Operating Pulse
Width (high or low) specification, tabulated in
Table 1, determines the smallest Pulse Width of
the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.
OPERATING FREQUENCY
The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.
The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D3324 must be
tested at the user operating pulse width.
The Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.
Therefore, to facilitate production and device
identification, the part number will include a
VDD
O1
O2
O3
O4
Dela
y
Dela
y
Dela
y
Dela
y
Temp & VDD
Compensatio
GND
I1
I2
I3
I4
Figure 1: 3D3324 Functional Diagram
Doc #06018
5/10/2006
DATA DELAY DEVICES, INC.
2
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D3324
APPLICATION NOTES (CONT’D)
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
The thermal coefficient is reduced to 300
PPM/C, which is equivalent to a variation , over
the -40C to 85C operating range, of ±3% from
the room-temperature delay settings and/or
1.0ns, whichever is greater. The power supply
coefficient is reduced, over the 3.0V to 3.6V
operating range, to ±1% of the delay settings at
the nominal 3.3VDC power supply and/or 2.0ns,
whichever is greater. It is essential that the
power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D3324 programmable delay line
utilizes novel and innovative compensation
construction as possible. Power planes are
preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
UNITS NOTES
V
V
VIN
VDD+0.3
1.0
IIN
TSTRG
TLEAD
mA
C
25C
150
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
SYMBOL
MIN
MAX
UNITS
mA
V
NOTES
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
IDD
VIH
VIL
IIH
5
2.0
0.8
1
V
-1
-1
VIH = VDD
VIL = 0V
VDD = 4.75V
VOH = 2.4V
VDD = 4.75V
VOL = 0.4V
CLD = 5 pf
µA
IIL
IOH
1
µA
-4.0
mA
Low Level Output Current
IOL
4.0
mA
ns
Output Rise & Fall Time
TR & TF
2
*IDD(Dynamic) = 4 * CLD * VDD * F
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
where: CLD = Average capacitance load/line (pf)
F = Input frequency (GHz)
Doc #06018
5/10/2006
DATA DELAY DEVICES, INC.
3
3 Mt. Prospect Ave. Clifton, NJ 07013
3D3324
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 3.3V ± 0.1V
Rload
Cload
:
:
10KΩ ± 10%
5pf ± 10%
Input Pulse:
High = 3.0V ± 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
50Ω Max.
Source Impedance:
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
PWIN = 1.25 x Total Delay
PERIN = 2.5 x Total Delay
Device
Digital
Scope
10KΩ
Under
Test
Pulse Width:
Period:
5pf
470Ω
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
OUT4
PULSE
OUT
IN
DIGITAL SCOPE/
DEVICE UNDER
TEST (DUT)
GENERATOR
TIME INTERVAL COUNTER
TRIG
TRIG
Figure 2: Test Setup
PERIN
PWIN
tRISE
tFALL
INPUT
VIH
2.4V
1.5V
2.4V
1.5V
0.6V
SIGNAL
VIL
0.6V
tPLH
tPHL
OUTPUT
SIGNAL
VOH
1.5V
1.5V
VOL
Figure 3: Timing Diagram
Doc #06018
5/10/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4
相关型号：
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Silicon Delay Line, Programmable, 1-Func, 255-Tap, True Output, CMOS, PDSO16, GULLWING, 16 PIN
DATADELAY
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