3D3438x-150 [DATADELAY]
MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7438);
| 型号： | 3D3438x-150 |
| 厂家： | 
DATA DELAY DEVICES, INC. |
| 描述： | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7438) |
| 文件： | 总6页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3D3438
MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
Super-Fine Resolution
(SERIES 3D3438)
FEATURES
PACKAGES
IN
SO
AE
1
2
3
4
8
VDD
OUT
SC
7
6
5
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Leading- and trailing-edge accuracy
Programmable via serial or parallel interface
Increment range: 50ps through 250ps
Delay tolerance: 0.5% (See Table 1)
Supply current: 3mA typical
GND
SI
IN
AE
SO/P0
P1
P2
P3
P4
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
OUT
MD
P7
P6
SC
P5
3D3438Z-xx SOIC8
IN
AE
P0
P1
P2
P3
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
VDD
OUT
P7
P6
P5
P4
GND
SI
8
3D3438S-xx SOW16
Temperature stability: 1.5% max (-40C to 85C)
Vdd stability: 0.5% max (3.0V to 3.6V)
3D3438D-xx SOIC14
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3438 device is a versatile 8-bit programmable monolithic delay
line. The input (IN) is reproduced at the output (OUT) without inversion,
shifted in time as per the user selection. Delay values, programmed
either via the serial or parallel interface, can be varied over 255 equal
steps according to the formula:
IN
Signal Input
OUT Signal Output
MD
AE
Mode Select
Address Enable
P0-P7 Parallel Data Input
SC
SI
SO
Serial Clock
Serial Data Input
Serial Data Output
Ti,nom = Tinh + i * Tinc
where i is the programmed address, Tinc is the delay increment (equal
to the device dash number), and Tinh is the inherent (address zero)
delay. The device features both rising- and falling-edge accuracy.
VDD +3.3 Volts
GND Ground
The all-CMOS 3D3438 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard surface mount 16-pin SOL. An 8-pin SOIC
package is available for applications where the parallel interface is not needed. Similarly, a 14-pin SOIC is
offered for applications where the serial interface is not needed.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
DELAYS AND TOLERANCES
INPUT RESTRICTIONS
Inherent
Delay (ns) Range (ns)
Delay
Delay
Step (ps)
Max Freq
(Addr=0)
150 MHz
Max Freq
(Addr=255)
98 MHz
Min P.Width
(Addr=0)
3.3 ns
Min P.Width
(Addr=255)
5.1 ns
NUMBER
3D3438x-50
3D3438x-60
3D3438x-75
3D3438x-80
3D3438x-100
3D3438x-125
3D3438x-150
3D3438x-200
3D3438x-250
7.0 0.5
7.0 0.5
7.0 0.5
7.0 0.5
7.0 0.5
7.0 0.5
7.0 0.5
7.0 0.5
7.0 0.5
12.750 .05
15.300 .06
19.125 .08
20.400 .08
25.500 .10
31.875 .13
38.250 .15
51.000 .20
63.750 .25
50 25
60 30
75 38
150 MHz
150 MHz
150 MHz
150 MHz
150 MHz
150 MHz
150 MHz
150 MHz
82 MHz
65 MHz
61 MHz
49 MHz
39 MHz
32 MHz
24 MHz
19 MHz
3.3 ns
3.3 ns
3.3 ns
3.3 ns
3.3 ns
3.3 ns
3.3 ns
3.3 ns
6.1 ns
7.6 ns
8.1 ns
10.0 ns
12.7 ns
15.3 ns
20.4 ns
25.5 ns
80 40
100 50
125 63
150 75
200 100
250 125
NOTES: Replace the ‘x’ in the part number with D, S or Z, depending on choice of package.
Any dash number between 50 and 250 not shown is also available as standard.
See application notes section for more details
2010 Data Delay Devices
Doc #10005
7/8/2010
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D3438
APPLICATION NOTES
where Tinh is the nominal inherent delay. The
absolute error is limited to 1.5 LSB or 1.0 ns,
whichever is greater, at every address.
GENERAL INFORMATION
The 8-bit programmable 3D3438 delay line
architecture is comprised of a sequence of five
identical delay cells connected in series, all of
which are controlled by a common current. This
current, in turn, is controlled by the user-selected
programming data (the address). The delay cells
produce at their output a replica of the signal
present at the input, shifted in time. The change
in delay from one address setting to the next is
called the increment, or LSB. It is nominally equal
to the device dash number. The minimum delay,
achieved by setting the address to zero, is called
the inherent delay.
The inherent delay error is the deviation of the
inherent delay from its nominal value. For all
dash numbers, it is limited to 0.5 ns.
DELAY STABILITY
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The 3D3438 utilizes novel compensation circuitry
to minimize the delay variations induced by
fluctuations in power supply and/or temperature.
The 3D3438 is designed to be most stable at the
maximum address setting (255). At this operating
condition, the thermal coefficient of the absolute
delay is limited to 250 PPM/C, which is
equivalent to a variation, over the -40C to 85C
operating range, of 1.5% from the room-
For best performance, it is essential that the
power supply pin be adequately bypassed and
filtered. In addition, the power bus should be of
as low an impedance construction as possible.
Power planes are preferred. Also, signal traces
should be kept as short as possible.
temperature delay. At smaller address settings
the thermal coefficient will be somewhat larger.
DELAY ACCURACY
There are a number of ways of characterizing the
delay accuracy of a programmable line. The first
is the differential nonlinearity (DNL), also referred
to as the increment error. It is defined as the
deviation of the increment at a given address
from its nominal value. For all dash numbers, the
DNL is within 0.5 LSB at every address (see
Table 1: Delay Step).
At the maximum address, the power supply
sensitivity of the absolute delay is 0.5% over the
3.0V to 3.6V operating range, with respect to the
delay at the nominal 3.3V power supply. At
smaller address settings the sensitivity will be
somewhat larger.
INPUT SIGNAL CHARACTERISTICS
The integrated nonlinearity (INL) is determined
by first constructing the least-squares best fit
straight line through the delay-versus-address
data. The INL is then the deviation of a given
delay from this line. For all dash numbers, the
INL is within 1.0 LSB at every address.
The maximum input frequency and minimum
input pulse width are both limited by the device.
Exceeding either limit will cause the signal to be
blocked by the line. Furthermore, for a given
device, these limitations vary with the user-
specified address. The relationships are:
The relative error is defined as follows:
FMax = 1250 / (i * Tinc)
PWMin = 0.4 * (i * Tinc),
erel = (Ti – T0) – i * Tinc
where i is the address, Ti is the measured delay
at the i’th address, T0 is the measured inherent
delay, and Tinc is the nominal increment. It is very
similar to the INL, but simpler to calculate. For all
dash numbers, the relative error is less than 1.0
LSB at every address (see Table 1: Delay
Range).
where FMax is in MHz, and PWMin & Tinc are in ns.
These relationships break down for small delays:
FMax can never be greater than 150 MHz, and
PWMin can never be smaller than 3.3 ns.
PROGRAMMING INTERFACE
Figure 1 illustrates the main functional blocks of
the 3D3438 delay program interface. Since the
3D3438 is a CMOS design, all unused input pins
must be returned to well defined logic levels,
VDD or Ground.
The absolute error is defined as follows:
eabs = Ti – (Tinh + i * Tinc)
Doc #10005
7/8/2010
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
3D3438
APPLICATION NOTES (CONT’D)
order, thus allowing cascading of multiple
TRANSPARENT PARALLEL MODE
(MD = 1, AE = 1)
devices by connecting the serial output pin (SO)
of the preceding device to the serial data input
pin (SI) of the succeeding device, as illustrated in
Figure 5. The total number of serial data bits in a
cascade configuration must be eight times the
number of units, and each group of eight bits
must be transmitted in MSB-to-LSB order.
The eight program pins P0 - P7 directly control
the output delay. A change on one or more of
the program pins will be reflected on the output
delay after a time tPDV, as shown in Figure 2. A
register is required if the programming data is
bused.
To initiate a serial read, enable (AE) is driven
high. After a time tEQV, bit 7 (MSB) is valid at the
serial output port pin (SO). On the first rising
edge of the serial clock (SC), bit 7 is loaded with
the value present at the serial data input pin (SI),
while bit 6 is presented at the serial output pin
(SO). To retrieve the remaining bits seven more
rising edges must be generated on the serial
clock line. The read operation is destructive.
Therefore, if it is desired that the original delay
setting remain unchanged, the read data must be
written back to the device(s) before the enable
(AE) pin is brought low.
LATCHED PARALLEL MODE
(MD = 1, AE PULSED)
The eight program pins P0 - P7 are loaded by the
falling edge of the Enable pulse, as shown in
Figure 3. After each change in delay value, a
settling time tEDV is required before the input is
accurately delayed.
SERIAL MODE (MD = 0)
While observing data setup (tDSC) and data hold
(tDHC) requirements, timing data is loaded in
MSB-to-LSB order by the rising edge of the clock
(SC) while the enable (AE) is high, as shown in
Figure 4. The falling edge of the enable (AE)
activates the new delay value which is reflected
at the output after a settling time tEDV. As data is
shifted into the serial data input (SI), the previous
contents of the 8-bit input register are shifted out
of the serial output port pin (SO) in MSB-to-LSB
The SO pin, if unused, must be allowed to float if
the device is configured in the serial
programming mode.
The serial mode is the only mode available on
the 8-pin version of the 3D3438, and this mode is
unavailable on the 14-pin version of the 3D3438.
PROGRAMMABLE
DELAY LINE
SIGNAL IN
OUT
IN
SIGNAL OUT
ADDRESS ENABLE
AE
LATCH
SO
SERIAL INPUT
SHIFT CLOCK
SERIAL OUTPUT
SI
8-BIT INPUT
REGISTER
SC
MODE SELECT MD
P0 P1 P2 P3 P4 P5 P6 P7
PARALLEL INPUTS
Figure1: Functional block diagram
PARALLEL
INPUTS
P0-P7
PREVIOUS
NEW VALUE
tPDX
tPDV
DELAY
TIME
PREVIOUS
NEW VALUE
Figure 2: Non-latched parallel mode (MD=1, AE=1)
Doc #10005
7/8/2010
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D3438
APPLICATION NOTES (CONT’D)
tEW
ENABLE
(AE)
tDSE
tDHE
PARALLEL
INPUTS
P0-P7
NEW VALUE
tEDX
tEDV
DELAY
TIME
PREVIOUS
NEW VALUE
Figure 3: Latched parallel mode (MD=1)
tEW
ENABLE
(AE)
tCW
tCW
tES
tDSC
tEGV
tEH
CLOCK
(SC)
tDHC
SERIAL
INPUT
(SI)
NEW
BIT 7
NEW
BIT 6
NEW
BIT 0
tCQV
tCQX
tEQZ
SERIAL
OUTPUT
(SO)
OLD
BIT 7
OLD
BIT 6
OLD
BIT 0
tEDV
tEDX
DELAY
TIME
NEW
VALUE
PREVIOUS VALUE
Figure 4: Serial mode (MD=0)
3D3438
3D3438
3D3438
SI
SO
SI
SO
SI
SO
SC AE
SC AE
SC AE
FROM
TO
WRITING
DEVICE
NEXT
DEVICE
Figure 5: Cascading Multiple Devices
TABLE 2: DELAY VS. PROGRAMMED ADDRESS
PROGRAMMED ADDRESS
NOMINAL DELAY (NS)
PER 3D3438 DASH NUMBER
-75 -100 -125 -150
PARALLEL
SERIAL
STEP 0
STEP 1
STEP 2
STEP 3
STEP 4
STEP 5
P7
Msb
P6
P5
P4
P3
P2
P1
P0
Lsb
-50
-200
-250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
7.000 7.000 7.000 7.000 7.000
7.050 7.075 7.100 7.125 7.150
7.100 7.150 7.200 7.250 7.300
7.150 7.225 7.300 7.375 7.450
7.200 7.300 7.400 7.500 7.600
7.250 7.375 7.500 7.625 7.750
7.000 7.000
7.200 7.250
7.400 7.500
7.600 7.750
7.800 8.000
8.000 8.250
STEP 253
STEP 254
STEP 255
CHANGE
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
19.650 25.975 32.300 38.625 44.950 57.600 70.250
19.700 26.050 32.400 38.750 45.100 57.800 70.500
19.750 26.125 32.500 38.875 45.250 58.000 70.750
12.750 19.125 25.500 31.875 38.250 51.000 63.750
Doc #10005
7/8/2010
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4
3D3438
DEVICE SPECIFICATIONS
TABLE 3: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
VIN
IIN
TSTRG
TLEAD
MIN
-0.3
-0.3
-10
MAX
7.0
VDD+0.3
10
150
300
UNITS NOTES
V
V
mA
C
25C
-55
C
10 sec
TABLE 4: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
SYMBOL
MIN
TYP
3.0
MAX
5.0
UNITS
mA
V
V
A
NOTES
Addr = 128
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output
Current
Low Level Output Current
IDD
VIH
VIL
IIH
IIL
IOH
2.0
0.8
1.0
1.0
-4.0
VIH = VDD
VIL = 0V
VDD = 3.0V
A
mA
-15.0
15.0
2.0
V
OH = 2.4V
IOL
4.0
mA
ns
VDD = 3.0V
VOL = 0.4V
CLD = 5 pf
Output Rise & Fall Time
TR & TF
2.5
*IDD(Dynamic) = CLD * VDD * F
where: CLD = Average capacitance load/line (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
TABLE 5: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
SYMBOL MIN TYP MAX
UNITS
NOTES
Clock Frequency
Enable Width
Clock Width
Data Setup to Clock
fC
tEW
tCW
80
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
3
10
3
tDSC
tDHC
tDSE
tDHE
tEQV
tEQZ
tCQV
tCQX
tES
Data Hold from Clock
Data Setup to Enable
Data Hold from Enable
Enable to Serial Output Valid
Enable to Serial Output High-Z
Clock to Serial Output Valid
Clock to Serial Output Invalid
Enable Setup to Clock
Enable Hold from Clock
Parallel Input Valid to Delay Valid
Parallel Input Change to Delay Invalid
Enable to Delay Valid
Enable to Delay Invalid
Input Pulse Width
20
20
20
10
10
10
tEH
tPDV
tPDX
tEDV
tEDX
tWI
20
35
40
45
0
0
40
80
% of Delay
% of Delay
ns
See Table 1
See Table 1
See Table 2
Input Period
Input to Output Delay
Period
tPLH, tPHL
Doc #10005
7/8/2010
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
3D3438
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC 3oC
Supply Voltage (Vcc): 5.0V 0.1V
Rload
Cload
:
:
10K 10%
5pf 10%
Input Pulse:
High = 3.0V 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V 0.1V
Source Impedance:
Rise/Fall Time:
50 Max.
3.0 ns Max. (measured
between 0.6V and 2.4V )
PWIN = 2 x Max Delay
PERIN = 10 x Max Delay
Device
Under
Test
Digital
Scope
10K
Pulse Width:
Period:
5pf
470
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
PULSE
GENERATOR
OUT
IN DEVICE UNDER OUT
TEST (DUT)
IN
DIGITAL SCOPE/
TIME INTERVAL COUNTER
TRIG
TRIG
Figure 6: Test Setup
PERIN
PWIN
tRISE
tFALL
INPUT
SIGNAL
VIH
2.4
1.5
0.6
2.4
1.5
0.6
VIL
tPLH
tPHL
OUTPUT
SIGNAL
VOH
1.5
1.5
VOL
Figure 7: Timing Diagram
Doc #10005
7/8/2010
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
6
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