3D3622 [DATADELAY]
22-BIT PROGRAMMABLE PULSE GENERATOR; 22位可编程脉冲发生器
| 型号： | 3D3622 |
| 厂家： | 
DATA DELAY DEVICES, INC. |
| 描述： | 22-BIT PROGRAMMABLE PULSE GENERATOR |
| 文件： | 总7页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3D3622
22-BIT PROGRAMMABLE PULSE
GENERATOR
(SERIES 3D3622 – SERIAL INTERFACE)
FEATURES
PACKAGE / PINOUT
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All-silicon, low-power CMOS technology
3.3V operation
1
2
3
4
5
6
7
14
13
12
11
10
9
VDD
OUT
OUTB
SI
TRIG
RES
GND
NC
Vapor phase, IR and wave solderable
Programmable via serial interface
Increment range: 0.25ns through 50.0ns
Pulse width tolerance: 1% (See Table 1)
Supply current: 8mA typical
SC
NC
NC
SO
8
AE
GND
3D3622D-xx SOIC
Temperature stability: ±1.5% max (-40C to 85C)
Vdd stability: ±1.0% max (3.0V to 3.6V)
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3622 device is a versatile 22-bit programmable monolithic
pulse generator. A rising-edge on the trigger input (TRIG) initiates
the pulse, which is presented on the output pins (OUT,OUTB). The
pulse width, programmed via the serial interface, can be varied
over 4,194,303 equal steps according to the formula:
TRIG Trigger Input
RES
Reset Input
OUT Pulse Output
OUTB Complementary
Pulse Output
AE
SC
SI
Address Enable Input
tPW = tinh + addr * tinc
Serial Clock Input
Serial Data Input
Serial Data Output
where addr is the programmed address, tinc is the pulse width
increment (equal to the device dash number), and tinh is the
inherent (address zero) pulse width. The device also offers a reset
input (RES), which can be used to terminate the pulse before the
programmed time has expired.
SO
VDD +3.3 Volts
GND Ground
NC
No Internal Connection
The all-CMOS 3D3622 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL pulse generators. It is
offered in a standard 14-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
Pulse Width
Minimum
Maximum
PART
Step (ns)
P.W. (ns)
Pulse Width
NUMBER
3D3622D-0.25
3D3622D-0.4
3D3622D-0.5
3D3622D-1
0.25 ± 0.12
0.40 ± 0.20
0.50 ± 0.25
1.00 ± 0.50
2.00 ± 1.00
2.50 ± 1.25
4.00 ± 2.00
5.00 ± 2.50
10.0 ± 5.00
20.0 ± 10.0
20.0 ± 10.0
40.0 ± 20.0
50.0 ± 25.0
10.0 ± 2.0
10.0 ± 2.0
10.0 ± 2.0
10.0 ± 2.0
10.0 ± 2.0
10.0 ± 2.0
10.0 ± 2.0
15.0 ± 5.0
24.0 ± 6.0
42.0 ± 8.0
15.0 ± 5.0
15.0 ± 5.0
15.0 ± 5.0
1.05 ms ± 10 us
1.68 ms ± 17 us
2.10 ms ± 21 us
4.19 ms ± 42 us
8.39 ms ± 84 us
10.5 ms ± 105 us
16.8 ms ± 170 us
21.0 ms ± 210 us
41.9 ms ± 420 us
83.9 ms ± 840 us
105 ms ± 1.0 ms
168 ms ± 1.7 ms
210 ms ± 2.1 ms
3D3622D-2
3D7622D-2.5
3D3622D-4
3D3622D-5
3D3622D-10
3D3622D-20 *
3D7622D-25 *
3D3622D-40 *
3D3622D-50 *
NOTES: Any increment between 0.25 and 50 ns not shown is also available as a standard device.
* Some restrictions apply to dash numbers greater than 15. See application notes for more details.
2006 Data Delay Devices
Doc #06008
5/8/2006
DATA DELAY DEVICES, INC.
1
3 Mt. Prospect Ave. Clifton, NJ 07013
3D3622
APPLICATION NOTES
inherent width, and tinc is the nominal increment.
GENERAL INFORMATION
It is very similar to the INL, but simpler to
calculate. For most dash numbers, the relative
error is less than 1.0 LSB at every address (see
Table 1).
Figure 1 illustrates the main functional blocks of
the 3D3622. Since the 3D3622 is a CMOS
design, all unused input pins must be returned to
well-defined logic levels, VDD or Ground.
The absolute error is defined as follows:
The pulse generator architecture is comprised of
a number of delay cells, which are controlled by
the 6 LSB bits of the address, and an oscillator &
counter, which are controlled by the 16 MSB bits
of the address. Each device is individually
trimmed for maximum accuracy and linearity
throughout the address range. The change in
pulse width from one address setting to the next
is called the increment, or LSB. It is nominally
equal to the device dash number. The minimum
pulse width, achieved by setting the address to
zero, is called the inherent pulse width.
eabs = tPW – (tinh + addr * tinc)
where tinh is the nominal inherent delay. The
absolute error is limited to 1.5 LSB or 3.0 ns,
whichever is greater, at every address.
The inherent pulse width error is the deviation of
the inherent width from its nominal value. It is
limited to 1.0 LSB or 2.0 ns, whichever is greater.
PULSE WIDTH STABILITY
The characteristics of CMOS integrated circuits
are strongly dependent on power supply and
temperature. The 3D3622 utilizes novel
compensation circuitry to minimize the
performance variations induced by fluctuations in
power supply and/or temperature.
For dash numbers larger than 15, the 6 LSB bits
are invalid, and the address loaded must
therefore be a multiple of 64 (ie, 0, 64, 128, 192,
etc). When used in this manner, the device is
essentially a 16-bit generator, with an effective
increment equal to 64 times the dash number.
With regard to stability, the output pulse width of
the 3D3622 at a given address, addr, can be split
into two components: the inherent pulse width
(tinh) and the relative pulse width (tPW – tinh).
These components exhibit very different stability
coefficients, both of which must be considered in
very critical applications.
For best performance, it is essential that the
power supply pin be adequately bypassed and
filtered. In addition, the power bus should be of
as low an impedance construction as possible.
Power planes are preferred. Also, signal traces
should be kept as short as possible.
The thermal coefficient of the relative pulse width
is limited to ±250 PPM/C (except for the -0.25),
which is equivalent to a variation, over the -40C
to 85C operating range, of ±1.5% (±9% for the
dash 0.25) from the room-temperature pulse
width. This holds for all dash numbers. The
thermal coefficient of the inherent pulse width is
nominally +20ps/C for dash numbers less than 5,
and +30ps/C for all other dash numbers.
PULSE WIDTH ACCURACY
There are a number of ways of characterizing the
pulse width accuracy of a programmable pulse
generator. The first is the differential nonlinearity
(DNL), also referred to as the increment error. It
is defined as the deviation of the increment at a
given address from its nominal value. For most
dash numbers, the DNL is within 0.5 LSB at
every address (see Table 1: Pulse Width Step).
The power supply sensitivity of the relative pulse
width is ±1.0% (±3.0% for the dash 0.25) over the
3.0V to 3.6V operating range, with respect to the
pulse width at the nominal 3.3V power supply.
This holds for all dash numbers. The sensitivity of
the inherent pulse width is nominally -5ps/mV for
all dash numbers.
The integrated nonlinearity (INL) is determined
by first constructing the least-squares best fit
straight line through the pulse-width-versus-
address data. The INL is then the deviation of a
given width from this line. For all dash numbers,
the INL is within 1.0 LSB at every address.
The relative error is defined as follows:
It should also be noted that the DNL is also
adversely affected by thermal and supply
variations, particularly at the MSL/LSB
crossovers (ie, 63 to 64, 127 to 128, etc).
erel = (tPW – tinh) – addr * tinc
where addr is the address, tPW is the measured
width at this address, tinh is the measured
Doc #06008
5/8/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
3D3622
APPLICATION NOTES (CONT’D)
TRIGGER & RESET TIMING
As shown in the figure, most of the address
Figure 2 shows the timing diagram of the device
when the reset input (RES) is not used. In this
case, the pulse is triggered by the rising edge of
the TRIG signal and ends at a time determined
by the address loaded into the device. While the
pulse is active, any additional triggers occurring
are ignored. Once the pulse has ended, and after
a short recovery time, the next trigger is
information for the next pulse can be loaded
while the current pulse is active. It is only on the
falling-edge of AE that the device adjusts to the
new pulse width setting. In other words, the
device controller does not need to wait for the
current pulse to end before beginning an address
update sequence. This can save a considerable
amount of time in certain applications.
recognized. Figure 3 shows the timing for the
case where a reset is issued before the pulse
has ended. Again, there is a short recovery time
required before the next trigger can occur.
As data is shifted into the serial data input (SI),
the previous contents of the 22-bit input register
are shifted out of the serial output pin (SO) in
MSB-to-LSB order. This allows cascading of
multiple devices by connecting SO of the
preceding device to SI of the succeeding device,
as illustrated in Figure 5. The total number of
serial data bits in a cascade configuration must
be 22 times the number of units, and each group
of 22 bits must be transmitted in MSB-to-LSB
order.
ADDRESS UPDATE
While observing data setup (tDS) and data hold
(tDH) requirements, timing data is loaded in MSB-
to-LSB order by the rising edge of the clock (SC)
while the enable (AE) is high, as shown in Figure
4. The falling edge of the AE activates the new
pulse width value, which is reflected at the output
upon the next trigger.
TRIGGER
RESET
TRG
RES
OUT
INPUT
LOGIC
DELAY
LINE
OSCILLATOR/
COUNTER
OUTPUT
LOGIC
OUTB
PULSE OUT
6
16
LSB
MSB
ADDR ENABLE
AE
22-BIT LATCH
22-BIT INPUT
REGISTER
SERIAL IN
SERIAL OUT
SI
SO
SERIAL CLK
SC
Figure 1: Functional block diagram
Doc #06008
5/8/2006
DATA DELAY DEVICES, INC.
3
3 Mt. Prospect Ave. Clifton, NJ 07013
3D3622
APPLICATION NOTES (CONT’D)
tTW
TRIG
tID
tPW
tRTO
OUT
OUTB
Figure 2: Timing Diagram (RES=0)
tTW
TRIG
RES
tRTR
tRW
tID
tRD
OUT
OUTB
Figure 3: Timing Diagram (with reset)
AE
SC
tCW tCW
tES
tEH
tDS
tDH
SI
A21
A20
A19
A1
A0
tEV
OLD A21
tCQ
OLD A19
tEX
A21
SO
OLD A20
OLD A18
OLD A0
tAT
tOA
TRIG
OUT
Figure 4: Address Update
3D3622
3D3622
3D3622
SI
SC AE
SO
SI
SO
SI
SO
FROM
TO
SC AE
SC AE
SERIAL
SOURCE
NEXT
DEVICE
Figure 5: Cascading Multiple Devices
DATA DELAY DEVICES, INC.
Doc #06008
5/8/2006
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D3622
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
MIN
-0.3
-0.3
-10
MAX
7.0
UNITS NOTES
V
V
VIN
VDD+0.3
10
IIN
TSTRG
TLEAD
mA
C
25C
-55
150
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
mA
V
NOTES
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
IDD
VIH
VIL
IIH
8.0
12.0
2.0
0.8
1.0
1.0
-4.0
V
VIH = VDD
VIL = 0V
VDD = 3.0V
VOH = 2.4V
VDD = 3.0V
VOL = 0.4V
CLD = 5 pf
µA
IIL
IOH
µA
High Level Output
-35.0
15.0
2.0
mA
Current
Low Level Output Current
IOL
4.0
mA
ns
Output Rise & Fall Time
TR & TF
2.5
*IDD(Dynamic) = 2 * CLD * VDD * F
Input Capacitance = 5 pf typical
Output Load Capacitance (CLD) = 25 pf max
where: CLD = Average capacitance load/output (pf)
F = Trigger frequency (GHz)
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
SYMBOL MIN
TYP
MAX UNITS
REFER TO
Figure 2 & 3
Figure 2 & 3
Figure 2
Figure 2
Figure 3
Figure 3
Figure 3
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Trigger Width
tTW
tID
5
ns
Trigger Inherent Delay
Output Pulse Width
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPW
tRTO
tRW
tRD
tRTR
tES
Re-trigger Time
3
Reset Width
TBD
Reset to Output Low
End of Reset to Next Trigger
AE High to First Clock Edge
AE High to Serial Output Valid
Serial Clock Width
5
3
10
tEV
20
tCW
tDS
tDH
tCQ
tEH
tOA
tEX
tAT
8
10
3
Data Setup to Clock
Data Hold from Clock
Clock to Serial Output
Last Clock Edge to AE Low
Output Low to AE Low
AE Low to Serial Output High-Z
AE Low to Trigger
8
8
TBD
20
10
Doc #06008
5/8/2006
DATA DELAY DEVICES, INC.
5
3 Mt. Prospect Ave. Clifton, NJ 07013
3D3622
TYPICAL APPLICATIONS
EN
FOUT
TRIG
RES
OUT
OUTB
AE
SCLK
SDAT
3D3622
AE
SC
SI
FOUT = 1 / (tPW + tID + tNOR
)
SO
EN
tID + tNOR
FOUT
Figure 6: Programmable Oscillator
TRIG
RES
OUT
SETB
D
OUT
+3.3
+3.3
IN
OUTB
Q
0V
0V
D-FF
D-FF
CK
QB
3D3622
AE
SC
SI
R-Edge
Delay
RESB
SO
TRIG
RES
OUT
SETB
D
OUTB
Q
CK
QB
AE
SCLK
SDAT
3D3622
AE
SC
SI
F-Edge
Delay
RESB
SO
IN
tPWR + tID + tFF
tPWF + tID + tFF
OUT
Figure 7: Programmable Delay Line
Doc #06008
5/8/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
6
3D3622
SILICON DEVICE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Rload
Cload
:
:
10KΩ ± 10%
5pf ± 10%
Input Pulse:
High = 3.0V ± 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
50Ω Max.
Source Impedance:
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
PWIN = 20ns
Device
Under
Test
Digital
Scope
10KΩ
Pulse Width:
Period:
PERIN = 2 x Prog’d Pulse Width
5pf
470Ω
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
PULSE
OUT TRIG DEVICE UNDER OUT
IN
DIGITAL SCOPE/
GENERATOR
TEST (DUT)
TIME INTERVAL COUNTER
TRIG
TRIG
Figure 8: Test Setup
PERIN
PWIN
tRISE
tFALL
INPUT
VIH
2.4
1.5
0.6
2.4
1.5
0.6
SIGNAL
VIL
tID
tPW
OUTPUT
SIGNAL
VOH
1.5
1.5
VOL
Figure 9: Timing Diagram
Doc #06008
5/8/2006
DATA DELAY DEVICES, INC.
7
3 Mt. Prospect Ave. Clifton, NJ 07013
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