3D7110G-.75 [DATADELAY]
MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7110); 单片10 -TAP固定的延时线（系列3D7110 ）
| 型号： | 3D7110G-.75 |
| 厂家： | 
DATA DELAY DEVICES, INC. |
| 描述： | MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7110) |
| 文件： | 总5页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3D7110
MONOLITHIC 10-TAP
FIXED DELAY LINE
(SERIES 3D7110)
FEATURES
PACKAGES
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•
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•
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•
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All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
IN
1
2
3
4
5
6
7
14
VDD
O1
IN
N/C
O2
O4
O6
VDD
O1
O3
O5
O7
1
2
3
4
5
6
7
14
13
12
11
10
9
N/C
O2
13
12
11
10
9
O3
O4
O5
O6
O7
O8
O9
GND
8
O10
Low ground bounce noise
3D7110D SOIC
(150 Mil)
Leading- and trailing-edge accuracy
Delay range: .75 through 80ns
O8
GND
O9
O10
Delay tolerance: 5% or 1ns
8
Temperature stability: ±3% typical (0C-70C)
Vdd stability: ±1% typical (4.75V-5.25V)
Minimum input pulse width: 15% of total delay
14-pin Gull-Wing and 16-pin SOIC
IN
N/C
N/C
O2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
N/C
O1
3D7110 DIP
3D7110G Gull-Wing
O3
O4
O5
O6
O7
O8
O9
available as drop-in replacements
for hybrid delay lines
For mechanical dimensions, click here.
GND
O10
For package marking details, click here.
3D7110S SOL
(300 Mil)
PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
IN
Delay Line Input
The 3D7110 10-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 0.75ns through 8.0ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D7110 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.
O1
O2
O3
O4
O5
O6
O7
O8
O9
Tap 1 Output (10%)
Tap 2 Output (20%)
Tap 3 Output (30%)
Tap 4 Output (40%)
Tap 5 Output (50%)
Tap 6 Output (60%)
Tap 7 Output (70%)
Tap 8 Output (80%)
Tap 9 Output (90%)
The all-CMOS 3D7110 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is offered
in a standard 14-pin auto-insertable DIP and space saving surface
mount 14- and 16-pin SOIC packages.
O10 Tap 10 Output (100%)
VDD +5 Volts
GND Ground
Doc #96005
12/2/96
DATA DELAY DEVICES, INC.
1
3 Mt. Prospect Ave. Clifton, NJ 07013
3D7110
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
SOIC-14
TOLERANCES
INPUT RESTRICTIONS
DIP-14
3D7110
3D7110G
-.75
SOIC-16
TOTAL
TAP-TAP
DELAY
Max
Absolute
Max
Min
Operating
Pulse Width
17.6 ns
Absolute
Min
3D7110D 3D7110S
DELAY
Operating
Frequency
28.4 MHz
23.8 MHz
18.0 MHz
14.5 MHz
18.2 MHz
8.33 MHz
6.67 MHz
4.17 MHz
(ns)
(ns)
Oper. Freq.
166.7 MHz
166.7 MHz
166.7 MHz
166.7 MHz
125.0 MHz
133.3 MHz
66.7 MHz
41.7 MHz
Oper. P.W.
3.00 ns
3.00 ns
3.00 ns
3.00 ns
4.00 ns
6.00 ns
7.50 ns
12.0 ns
-.75
-1
-1.5
-2
-2.5
-4
-.75
-1
-1.5
-2
-2.5
-4
6.75 ± 1.0*
9.0 ± 1.0*
13.5 ± 1.0*
18.0 ± 1.0*
22.5 ± 1.1*
36.0 ± 1.8*
50.0 ± 2.5
80.0 ± 4.0
0.75 ± 0.4
1.0 ± 0.5
1.5 ± 0.7
2.0 ± 0.8
2.5 ± 1.0
4.0 ± 1.3
5.0 ± 1.5
8.0 ± 1.5
-1
21.0 ns
-1.5
27.8 ns
-2
34.5 ns
-2.5
27.5 ns
-4
60.0 ns
-5
-5
-8
-5
-8
75.0 ns
-8
120.0 ns
* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns ± 1.0ns
NOTE: Any dash number between .75 and 8 not shown is also available.
1996 Data Delay Devices
Doc #96005
12/2/96
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
3D7110
APPLICATION NOTES
To guarantee the Table 1 delay accuracy for
OPERATIONAL DESCRIPTION
input frequencies higher than the Maximum
Operating Frequency, the 3D7110 must be
tested at the user operating frequency.
The 3D7110 ten-tap delay line architecture is
shown in Figure 1. The delay line is composed
of a number of delay cells connected in series.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time.
The delay cells are matched and share the same
compensation signals, which minimizes tap-to-
tap delay deviations over temperature and supply
voltage variations.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY
DEVICES be consulted.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Maximum and
an Absolute Maximum operating input
frequency and a Minimum and an Absolute
Minimum operating pulse width have been
specified.
OPERATING PULSE WIDTH
The Absolute Minimum Operating Pulse
Width (high or low) specification, tabulated in
Table 1, determines the smallest Pulse Width of
the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.
OPERATING FREQUENCY
The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.
The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D7110 must be
tested at the user operating pulse width.
The Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.
Therefore, to facilitate production and device
identification, the part number will include a
IN
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
Temp & VDD
Compensation
VDD
GND
Figure 1: 3D7110 Functional Diagram
Doc #96005
12/2/96
DATA DELAY DEVICES, INC.
3
3 Mt. Prospect Ave. Clifton, NJ 07013
3D7110
APPLICATION NOTES (CONT’D)
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
The thermal coefficient is reduced to 600
PPM/C, which is equivalent to a variation , over
the 0C-70C operating range, of ±3% from the
room-temperature delay settings and/or 1.0ns,
whichever is greater. The power supply
coefficient is reduced, over the 4.75V-5.25V
operating range, to ±1% of the delay settings at
the nominal 5.0VDC power supply and/or 1.5ns,
whichever is greater. It is essential that the
power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7110 programmable delay line
utilizes novel and innovative compensation
construction as possible. Power planes are
preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
UNITS NOTES
V
V
VIN
VDD+0.3
1.0
IIN
TSTRG
TLEAD
mA
C
25C
150
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
MAX
UNITS
mA
V
NOTES
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
IDD
VIH
VIL
IIH
30
2.0
0.8
1
1
V
VIH = VDD
VIL = 0V
VDD = 4.75V
VOH = 2.4V
VDD = 4.75V
VOL = 0.4V
CLD = 5 pf
µA
IIL
IOH
µA
-4.0
4.0
mA
Low Level Output Current
IOL
mA
ns
Output Rise & Fall Time
TR & TF
2
*IDD(Dynamic) = 10 * CLD * VDD * F
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
where: CLD = Average capacitance load/tap (pf)
F = Input frequency (GHz)
Doc #96005
12/2/96
DATA DELAY DEVICES, INC.
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7110
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Rload
Cload
:
:
10KΩ ± 10%
5pf ± 10%
Input Pulse:
High = 3.0V ± 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
50Ω Max.
Source Impedance:
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V
Device
Under
Test
Digital
10KΩ
Scope
)
Pulse Width:
Delay
PWIN = 1.25 x Total
PERIN = 2.5 x Total
5pf
470Ω
Period:
Delay
PRINTER
COMPUTER
SYSTEM
OUT1
REF
IN
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
PULSE
OUT
DIGITAL SCOPE/
DEVICE UNDER
GENERATOR
TIME INTERVAL COUNTER
TEST (DUT)
TRIG
IN
TRIG
Figure 2: Test Setup
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PERIN
PWIN
tRISE
tFALL
INPUT
VIH
2.4V
1.5V
2.4V
1.5V
0.6V
SIGNAL
VIL
0.6V
tPLH
tPHL
OUTPUT
SIGNAL
VOH
1.5V
1.5V
VOL
Figure 3: Timing Diagram
Doc #96005
12/2/96
DATA DELAY DEVICES, INC.
5
3 Mt. Prospect Ave. Clifton, NJ 07013
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