3D7418-5 [DATADELAY]
MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7418 - LOW NOISE); 单片8位可编程延迟线（系列3D7418 - 低噪音）
| 型号： | 3D7418-5 |
| 厂家： | 
DATA DELAY DEVICES, INC. |
| 描述： | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7418 - LOW NOISE) |
| 文件： | 总7页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3D7418
MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D7418 – LOW NOISE)
FEATURES
PACKAGES
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All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
IN
AE
SO/P0
P1
P2
P3
P4
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
OUT
MD
P7
P6
SC
P5
SI
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
OUT
MD
P7
Low ground bounce noise
AE
SO/P0
Leading- and trailing-edge accuracy
Increment range: 0.25 through 5.0ns
Delay tolerance: 1% (See Table 1)
Temperature stability: ±3% typical (0C-70C)
Vdd stability: ±1% typical (4.75V-5.25V)
Minimum input pulse width: 10% of total
delay
P1
P2
P3
P6
SC
P5
P4
GND
SI
3D7418S SOL
(300 Mil)
3D7418 DIP
3D7418G Gull Wing
•
Programmable via 3-wire serial or 8-bit
parallel interface
For mechanical dimensions, click here.
PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
IN
Signal Input
The 3D7418 Programmable 8-Bit Silicon Delay Line product family
consists of 8-bit, user-programmable CMOS silicon integrated
circuits. Delay values, programmed either via the serial or parallel
interface, can be varied over 255 equal steps ranging from 250ps
to 5.0ns inclusively. Units have a typical inherent (zero step)
delay of 12ns to 17ns (See Table 1). The input is reproduced at
the output without inversion, shifted in time as per user selection.
The 3D7418 is TTL- and CMOS-compatible, capable of driving ten
74LS-type loads, and features both rising- and falling-edge
accuracy.
OUT Signal Output
MD
AE
Mode Select
Address Enable
P0-P7 Parallel Data Input
SC
SI
Serial Clock
Serial Data Input
Serial Data Output
SO
VDD +5 Volts
GND Ground
The all-CMOS 3D7418 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space saving
surface mount 16-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
DELAYS AND TOLERANCES
INPUT RESTRICTIONS
Step 0
Step 255
Delay
Max Operating
6.25 MHz
Absolute Max Min Operating
Absolute Min
Oper P.W.
5.5 ns
NUMBER
Delay (ns) Delay (ns)
12 ± 2 75.75 ± 4.0
12 ± 2 139.5 ± 4.0
12 ± 2 267.0 ± 5.0
14 ± 2 522.0 ± 6.0
17 ± 2 782.0 ± 8.0
Increment (ns) Frequency
Oper Freq
P.W.
3D7418-0.25
3D7418-0.5
3D7418-1
3D7418-2
3D7418-3
3D7418-4
3D7418-5
90 MHz
80.0 ns
160.0 ns
320.0 ns
640.0 ns
960.0 ns
1280.0 ns
1600.0 ns
0.25 ± 0.15
0.50 ± 0.25
1.00 ± 0.50
2.00 ± 1.00
3.00 ± 1.50
4.00 ± 2.00
5.00 ± 2.50
3.15 MHz
1.56 MHz
0.78 MHz
0.52 MHz
0.39 MHz
0.31 MHz
45 MHz
22 MHz
11 MHz
7.5 MHz
5.5 MHz
4.4 MHz
11.0 ns
22.0 ns
44.0 ns
66.0 ns
88.0 ns
17 ± 2
17 ± 2
1037 ± 9.0
1292 ± 10
110.0 ns
NOTES: Any delay increment between 0.25 and 5.0 ns not shown is also available.
All delays referenced to input pin
2002 Data Delay Devices
Doc #02005
6/17/02
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7418
APPLICATION NOTES
The 8-bit programmable 3D7418 delay line
architecture is comprised of a number of delay
cells connected in series with their respective
outputs multiplexed onto the Delay Out pin (OUT)
by the user-selected programming data. Each
delay cell produces at its output a replica of the
signal present at its input, shifted in time.
OPERATING PULSE WIDTH
The Absolute Minimum Operating Pulse
Width (high or low) specification, tabulated in
Table 1, determines the smallest Pulse Width of
the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.
INPUT SIGNAL CHARACTERISTICS
The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay and increment accuracy of the particular
device. The reasons for the dependency of the
output delay accuracy on the input signal
characteristics are varied and complex.
To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D7418 must be
tested at the user operating pulse width.
Therefore a Maximum and an Absolute
Maximum operating input frequency and a
Minimum and an Absolute Minimum operating
pulse width have been specified.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
OPERATING FREQUENCY
The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
The Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.
SPECIAL HIGH ACCURACY
REQUIREMENTS
To guarantee the Table 1 delay accuracy for
input frequencies higher than the Maximum
Operating Frequency, the 3D7418 must be
tested at the user operating frequency.
The Table 1 delay and increment accuracy
specifications are aimed at meeting the
requirements of the majority of the applications
encountered to date. However, some systems
may place tighter restrictions on one accuracy
parameter in favor of others. For example, a
channel delay equalizing system is concerned in
minimizing delay variations among the various
channels. Therefore, because the inter channel
skew is a delay difference, the programmed
delay tolerance may need to be considerably
decreased, while the increment and its tolerance
are of no consequence. The opposite is true for
an under-sampled multi-channel data acquisition
system.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY
DEVICES be consulted.
Doc #02005
6/17/02
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
3D7418
APPLICATION NOTES (CONT’D)
The flexible 3D7418 architecture can be
exploited to conform to these more demanding
user-dictated accuracy constraints. However, to
facilitate production and device identification, the
part number will include a custom reference
designator identifying the user requested
accuracy specifications and operating conditions.
It is strongly recommended that the
In order to ensure that spurious outputs do not
occur, it is essential that the input signal be idle
(held high or low) for a short duration prior to
updating the programmed delay. This duration is
given by the maximum programmable delay.
Satisfying this requirement allows the delay line
to “clear” itself of spurious edges. When the new
address is loaded, the input signal can begin to
switch (and the new delay will be valid) after a
time given by tPDV or tEDV (see section below).
engineering staff at DATA DELAY DEVICES
be consulted.
PROGRAMMED DELAY (ADDRESS)
INTERFACE
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
Figure 1 illustrates the main functional blocks of
the 3D7418 delay program interface. Since the
3D7418 is a CMOS design, all unused input pins
must be returned to well defined logic levels,
VCC or Ground.
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7418 programmable delay line
utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
TRANSPARENT PARALLEL MODE
(MD = 1, AE = 1)
The thermal coefficient is reduced to 600
PPM/C, which is equivalent to a variation, over
the 0C-70 C operating range, of ±3% from the
room-temperature delay settings. The power
supply coefficient is reduced, over the 4.75V-
5.25V operating range, to ±1% of the delay
settings at the nominal 5.0VDC power supply
and/or ±2ns, whichever is greater.
The eight program pins P0 - P7 directly control
the output delay. A change on one or more of
the program
pins will be reflected on the output delay after a
time tPDV, as shown in Figure 2. A register is
required if the programming data is bused.
LATCHED PARALLEL MODE
(MD = 1, AE PULSED)
It is essential that the power supply pin be
adequately bypassed and filtered. In addition,
the power bus should be of as low an
impedance construction as possible. Power
planes are preferred.
The eight program pins P0 - P7 are loaded by the
falling edge of the Enable pulse, as shown in
Figure 3. After each change in delay value, a
settling time tEDV is required before the input is
accurately delayed.
PROGRAMMED DELAY (ADDRESS)
UPDATE
SERIAL MODE (MD = 0)
A delay line is a memory device. It stores
information present at the input for a time equal
to the delay setting before presenting it at the
output with minimal distortion. The 3D7418 8-bit
programmable delay line can be represented by
256 serially connected delay elements
While observing data setup (tDSC) and data hold
(tDHC) requirements, timing data is loaded in
MSB-to-LSB order by the rising edge of the clock
(SC) while the enable (AE) is high, as shown in
Figure 4. The falling edge of the enable (AE)
activates the new delay value which is reflected
at the output after a settling time tEDV. As data is
shifted into the serial data input (SI), the previous
contents of the 8-bit input register are shifted out
of the serial output port pin (SO) in MSB-to-LSB
order, thus allowing cascading of multiple
(individually addressed by the programming
data), each capable of storing data for a time
equal to the device increment (step time). The
delay line memory property, in conjunction with
the operational requirement of “instantaneously”
connecting the delay element addressed by the
programming data to the output, may inject
spurious information onto the output data stream.
devices by connecting the serial output pin (SO)
of the preceding device to the serial data input
Doc #02005
6/17/02
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D7418
APPLICATION NOTES (CONT’D)
pin (SI) of the succeeding device, as illustrated in
Figure 5. The total number of serial data bits in
a cascade configuration must be eight times the
number of units, and each group of eight bits
must be transmitted in MSB-to-LSB order.
(SO). To retrieve the remaining bits seven more
rising edges must be generated on the serial
clock line. The read operation is destructive.
Therefore, if it is desired that the original delay
setting remain unchanged, the read data must be
written back to the device(s) before the enable
(AE) pin is brought low.
To initiate a serial read, enable (AE) is driven
high. After a time tEQV , bit 7 (MSB) is valid at the
serial output port pin (SO). On the first rising
edge of the serial clock (SC), bit 7 is loaded with
the value present at the serial data input pin (SI),
while bit 6 is presented at the serial output pin
Pin 3, if unused, must be allowed to float if the
device is configured in the serial programming
mode.
PROGRAMMABLE
DELAY LINE
SIGNAL IN
OUT SIGNAL OUT
IN
ADDRESS ENABLE
AE
LATCH
SERIAL INPUT
SHIFT CLOCK
SERIAL OUTPUT
SI
SO
8-BIT INPUT
REGISTER
SC
MODE SELECT MD
P0 P1 P2 P3 P4 P5 P6 P7
PARALLEL INPUTS
Figure1: Functional block diagram
PARALLEL
INPUTS
P0-P7
PREVIOUS VALUE
NEW VALUE
tPDX
tPDV
DELAY
TIME
PREVIOUS VALUE
NEW VALUE
Figure 2: Non-latched parallel mode (MD=1, AE=1)
tEW
ENABLE
(AE)
tDSE
tDHE
PARALLEL
INPUTS
P0-P7
NEW VALUE
tEDX
tEDV
DELAY
TIME
PREVIOUS VALUE
NEW VALUE
Figure 3: Latched parallel mode (MD=1)
DATA DELAY DEVICES, INC.
Doc #02005
6/17/02
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7418
APPLICATION NOTES (CONT’D)
tEW
ENABLE
(AE)
tCW tCW
tES
tDSC
tEGV
tEH
CLOCK
(SC)
tDHC
SERIAL
INPUT
(SI)
NEW
BIT 7
NEW
NEW
BIT 0
BIT 6
tCQV
tCQX
tEQZ
SERIAL
OUTPUT
(SO)
OLD
BIT 7
OLD
OLD
BIT 0
BIT 6
tEDV
tEDX
DELAY
TIME
NEW
PREVIOUS VALUE
VALUE
Figure 4: Serial mode (MD=0)
3D7418
3D7418
3D7418
SI
SC AE
SO
SI
SC AE
SO
SI
SC AE
SO
FROM
TO
WRITING
DEVICE
NEXT
DEVICE
Figure 5: Cascading Multiple Devices
TABLE 2: DELAY VS. PROGRAMMED ADDRESS
PROGRAMMED ADDRESS
NOMINAL DELAY (NS)
3D7418 DASH NUMBER
PARALLEL
P7
Msb
0
P6
P5
P4
P3
P2
P1
P0
Lsb
0
SERIAL
STEP 0
STEP 1
STEP 2
STEP 3
STEP 4
STEP 5
-.25
12.00
12.25
12.50
12.75
13.00
13.25
-.5
12.0
12.5
13.0
13.5
14.0
14.5
-1
12
13
14
15
16
17
-2
12
14
16
18
20
22
-5
17
22
27
32
37
42
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
STEP 253
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
75.25
75.50
75.75
63.75
138.5 265 518 1283
139.0 266 520 1287
139.5 267 522 1292
127.5 255 510 1275
STEP 254
STEP 255
DELAY CHANGE
Doc #02005
6/17/02
DATA DELAY DEVICES, INC.
5
3 Mt. Prospect Ave. Clifton, NJ 07013
3D7418
DEVICE SPECIFICATIONS
TABLE 3: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
MIN
-0.3
-0.3
-10
MAX
7.0
UNITS NOTES
V
V
VIN
VDD+0.3
10
IIN
TSTRG
TLEAD
mA
C
25C
-55
150
300
C
10 sec
TABLE 4: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
1.0
MAX
3.0
UNITS
mA
V
NOTES
Static Supply Current*
Input Threshold Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
IDD
VTH
IIH
2.2
2.8
1.0
VIH = VDD
VIL = 0V
VDD = 4.75V
VOH = 4.0V
VDD = 4.75V
VOL = 0.4V
CLD = 5 pf
µA
IIL
IOH
1.0
µA
mA
-4.0
Low Level Output Current
IOL
4.0
mA
ns
Output Rise & Fall Time
TR & TF
2
*IDD(Dynamic) = CLD * VDD * F
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
where: CLD = Average capacitance load/line (pf)
F = Input frequency (GHz)
TABLE 5: AC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL MIN TYP MAX
UNITS
NOTES
Clock Frequency
fC
tEW
80
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Enable Width
10
10
10
3
Clock Width
tCW
Data Setup to Clock
tDSC
tDHC
tDSE
tDHE
tEQV
tEQZ
tCQV
tCQX
tES
Data Hold from Clock
Data Setup to Enable
Data Hold from Enable
Enable to Serial Output Valid
Enable to Serial Output High-Z
Clock to Serial Output Valid
Clock to Serial Output Invalid
Enable Setup to Clock
Enable Hold from Clock
Parallel Input Valid to Delay Valid
Parallel Input Change to Delay Invalid
Enable to Delay Valid
Enable to Delay Invalid
Input Pulse Width
10
3
20
20
20
10
10
10
tEH
tPDV
tPDX
tEDV
tEDX
tWI
20
35
40
45
1
1
1
1
0
0
8
20
% of Total Delay See Table 1
% of Total Delay See Table 1
Input Period
Input to Output Delay
Period
tPLH, tPHL
ns
See Table 2
NOTES: 1 - Refer to PROGRAMMED DELAY (ADDRESS) UPDATE section
Doc #02005
6/17/02
DATA DELAY DEVICES, INC.
6
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7418
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Rload
Cload
:
:
10KΩ ± 10%
5pf ± 10%
Input Pulse:
High = 3.0V ± 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
50Ω Max.
Source Impedance:
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
PWIN = 1.25 x Total Delay
PERIN = 2.5 x Total Delay
Device
Under
Test
Digital
Scope
10KΩ
Pulse Width:
Period:
5pf
470Ω
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
PULSE
OUT
IN DEVICE UNDER OUT
TEST (DUT)
IN
DIGITAL SCOPE/
GENERATOR
TIME INTERVAL COUNTER
TRIG
TRIG
Figure 6: Test Setup
PERIN
PWIN
tRISE
tFALL
INPUT
VIH
2.4V
1.5V
2.4V
1.5V
0.6V
SIGNAL
VIL
0.6V
tPLH
tPHL
OUTPUT
SIGNAL
VOH
1.5V
1.5V
VOL
Figure 7: Timing Diagram
Doc #02005
6/17/02
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
7
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