3D7502H-50 [DATADELAY]
Manchester Decoder, CMOS, PDSO8, DIP-8;
| 型号： | 3D7502H-50 |
| 厂家： | 
DATA DELAY DEVICES, INC. |
| 描述： | Manchester Decoder, CMOS, PDSO8, DIP-8 电信 光电二极管 电信集成电路 |
| 文件： | 总4页 (文件大小：37K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3D7502
Ò
MONOLITHIC MANCHESTER
DECODER
(SERIES 3D7502)
data
delay
3
devices, inc.
PACKAGES
FEATURES
RX
1
2
3
4
5
6
7
14
13
12
11
10
9
VDD
N/C
·
·
·
All-silicon, low-power CMOS
technology
TTL/CMOS compatible inputs and
outputs
Vapor phase, IR and wave
solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Maximum data rate: 50 MBaud
Data rate range: ±15%
N/C
N/C
N/C
CLK
N/C
N/C
RX
CLK
N/C
1
2
3
4
8
7
6
5
VDD
N/C
N/C
N/C
N/C
N/C
·
·
·
·
GND
8
DATB
GND
DATB
3D7502M-xxx DIP (.300)
3D7502H-xxx Gull Wing (.300)
3D7502Z-xxx SOIC (.150)
3D7502-xxx
3D7502G-xxx Gull Wing (.300)
3D7502D-xxx SOIC (.150)
DIP (.300)
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7502 product family consists of monolithic CMOS Manchester
Decoders. The unit accepts at the RX input a bi-phase-level,
embedded-clock signal. In this encoding mode, a logic one is
represented by a high-to-low transition within the bit cell, while a logic
zero is represented by a low-to-high transition. The recovered clock
and data signals are presented on CLK and DATB, respectively, with
RX
CLK
Signal Input
Signal Output (Clock)
DATB Signal Output (Data)
VCC +5 Volts
GND Ground
the data signal inverted. The operating baud rate (in MBaud) is specified by the dash number. The input
baud rate may vary by as much as ±15% from the nominal device baud rate without compromising the
integrity of the information received.
Because the 3D7502 is not PLL-based, it does not require a long preamble in order to lock onto the
received signal. Rather, the device requires at most one bit cell before the data presented at the output is
valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise
turned off.
The all-CMOS 3D7502 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL Manchester Decoders. It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads. It is
offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving surface mount 8-pin and 14-
pin SOICs.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
3D7502-5
3D7502-10
3D7502-20
3D7502-25
3D7502-30
3D7502-40
3D7502-50
BAUD RATE (MBaud)
Nominal Minimum Maximum
5.00
10.00
20.00
25.00
30.00
40.00
50.00
4.25
8.50
5.75
11.50
23.00
28.75
34.50
46.00
57.50
17.00
21.25
25.50
34.00
42.50
NOTES: Any baud rate between 5 and 50 MBaud not shown is also available at no extra cost. Ó1997 Data Delay Devices
Doc #97032
5/19/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7502
APPLICATION NOTES
The 3D7502 Manchester Decoder samples the
input at precise pre-selected intervals to retrieve
the data and to recover the clock from the
received data stream. Its architecture comprises
finely tuned delay elements and proprietary
circuitry which, in conjunction with other circuits,
implement the data decoding and clock recovery
function.
OUTPUT SIGNAL CHARACTERISTICS
The 3D7502 presents at its outputs the decoded
data (inverted) and the recovered clock. The
decoded data is valid at the rising edge of the
clock.
The clock recovery function operates in two
modes dictated by the input data stream bit
sequence. When a data bit is succeeded by its
inverse, the clock recovery circuit is engaged
and forces the clock output low for a time equal
to one over twice the baud rate. Otherwise,
the input is presented at the clock output
unchanged, shifted in time.
INPUT SIGNAL CHARACTERISTICS
Encoded data transmitted from a source arrives
at its destination corrupted. Such corruption of
the received data manifests itself as jitter and/or
pulse width distortion at the input to the device.
The instantaneous deviations from nominal Baud
Rate and/or Pulse Width (high or low) adversely
impact the data extraction and clock recovery
function if their published limits are exceeded.
See Table 4, Allowed Baud Rate/Duty Cycle.
When engaged, the clock recovery circuit
generates a low-going pulse of fixed width.
Therefore, the clock duty cycle is strongly
dependent on the baud rate, as this will affect
the clock-high duration.
The 3D7502 Manchester Decoder Data Input is
TTL compatible. The user should assure
himself that the 1.5 volt TTL threshold is used
when referring to all timing, especially the input
pulse widths.
The clock output falling edge is not operated on
by the clock recovery circuitry. It, therefore,
preserves more accurately the clock frequency
information embedded in the transmitted data.
Therefore, it can be used, if it is desired, to
retrieve clock frequency information.
FREQUENCY (JITTER) ERRORS
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The 3D7502 Manchester Decoder, being a self-
timed device, is tolerant of frequency
modulation (jitter) present in the input data
stream, provided that the input data pulse width
variations remain within the allowable ranges.
CMOS integrated circuitry is strongly dependent
on power supply and temperature. The
monolithic 3D7502 Manchester Decoder utilizes
novel and innovative compensation circuitry to
minimize timing variations induced by
fluctuations in power supply and/or temperature.
ENCODED
0
1
0
1
1
0
0
1
RECEIVED
(RX)
tC
tCL
tCWL
tCD
CLOCK
(CLK)
DATA
(DATB)
DECODED
1
0
1
1
0
0
1
Figure 1: Timing Diagram
Doc #97032
5/19/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
3D7502
.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
VIN
IIN
TSTRG
TLEAD
MIN
-0.3
-0.3
-10
MAX
7.0
VDD+0.3
10
150
300
UNITS NOTES
V
V
mA
C
25C
-55
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
MAX
40
UNITS
mA
V
V
mA
NOTES
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
IDD
VIH
VIL
IIH
IIL
IOH
2.0
0.8
1.0
1.0
VIH = VDD
VIL = 0V
VDD = 4.75V
VOH = 2.4V
VDD = 4.75V
VOL = 0.4V
CLD = 5 pf
mA
mA
-4.0
4.0
Low Level Output Current
IOL
mA
ns
Output Rise & Fall Time
TR & TF
2
*IDD(Dynamic) = 2 * CLD * VDD * F
where: CLD = Average capacitance load/pin (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V, except as noted)
SYMBOL
PARAMETER
MIN
5
-0.15 fBN
-0.05 fBN
TYP
MAX
50
0.15 fBN MBaud
0.05 fBN MBaud
UNITS
MBaud
NOTES
Nominal Input Baud Rate
Allowed Input Baud Rate Deviation
Allowed Input Baud Rate Deviation
fBN
fB
fB
25C, 5.00V
-40C to 85C
4.75V to 5.25V
-55C to 125C
4.75V to 5.25V
Allowed Input Baud Rate Deviation
fB
-0.03 fBN
42.5
0.03 fBN MBaud
Allowed Input Duty Cycle
Bit Cell Time
Input Data Edge to Clock Falling Edge
Clock Width Low
50.0
1000/fB
0.75 tc
500/fBN
4.0
57.5
5.0
%
ns
ns
ns
ns
tc
tCL
tCWL
tCD
±2ns or 5%
Clock Falling Edge to Data Transition
3.0
Doc #97032
5/19/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D7502
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Rload
Cload
:
:
10KW ± 10%
5pf ± 10%
Input Pulse:
High = 3.0V ± 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
50W Max.
3.0 ns Max. (measured
between 0.6V and 2.4V )
PWIN = 1/(2*BAUD)
PERIN = 1/BAUD
Source Impedance:
Rise/Fall Time:
Device
Under
Test
Digital
Scope
10KW
Pulse Width:
Period:
5pf
470W
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
WAVEFORM
GENERATOR
OUT
IN DEVICE UNDER OUT
TEST (DUT)
IN
DIGITAL SCOPE
TRIG
TRIG
Figure 2: Test Setup
PERIN
PWIN
tRISE
tFALL
INPUT
SIGNAL
VIH
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
VIL
tPLH
tPHL
OUTPUT
SIGNAL
VOH
1.5V
1.5V
VOL
Figure 3: Timing Diagram
Doc #97032
5/19/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4
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