DDU8C3-5150A1 [DATADELAY]
Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, LOW PROFILE, GULLWING, DIP-8;
| 型号： | DDU8C3-5150A1 |
| 厂家： | 
DATA DELAY DEVICES, INC. |
| 描述： | Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, LOW PROFILE, GULLWING, DIP-8 延迟线 |
| 文件： | 总4页 (文件大小：45K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDU8C3
Ò
5-TAP, 3.3V CMOS-INTERFACED
FIXED DELAY LINE
(SERIES DDU8C3)
data
delay
devices,
3
inc.
FEATURES
PACKAGES
IN
T2
VDD
T1
·
·
·
·
·
·
Five equally spaced outputs
Fits standard 8-pin DIP socket
Low profile
1
2
3
4
8
7
6
5
T4
T3
GND
T5
Auto-insertable
Input & outputs fully CMOS interfaced & buffered
DDU8C3-xx
DDU8C3-xxA1 Gull-Wing
DIP
10 T2L fan-out capability
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The DDU8C3-series device is a 5-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
amount determined by the device dash number (See Table). For dash
numbers 5020 and above, the total delay of the line is measured from IN to
T5, and the nominal tap-to-tap delay increment is given by one-fifth of the
IN
T1-T5 Tap Outputs
VDD +3.3 Volts
GND Ground
Signal Input
total delay. For dash numbers below 5020, the total delay is measured from T1 to T5, and the delay
increment is given by one-fourth of the total delay.
SERIES SPECIFICATIONS
DASH NUMBER SPECIFICATIONS
·
·
·
·
Minimum input pulse width: 40% of total delay
Output rise time: 2ns typical
Supply voltage: 3.3VDC ± 0.3V
Supply current: ICCL = 40ma typical
ICCH = 7ma typical
Part
Number
Total
Delay Per
Tap (ns)
1.0 ± 0.5
1.5 ± 0.5
2.0 ± 1.0
2.5 ± 1.0
3.0 ± 1.0
3.5 ± 1.0
4.0 ± 1.0
5.0 ± 1.5
6.0 ± 1.5
7.0 ± 1.8
8.0 ± 2.0
9.0 ± 2.0
10.0 ± 2.0
12.0 ± 2.0
15.0 ± 2.5
20.0 ± 3.0
25.0 ± 3.0
30.0 ± 3.0
35.0 ± 4.0
40.0 ± 4.0
50.0 ± 5.0
Delay (ns)
4 ± 1.0 *
6 ± 1.0 *
8 ± 2.0 *
10 ± 2.0 *
12 ± 2.0 *
14 ± 2.0 *
20 ± 2.0
25 ± 2.0
30 ± 2.0
35 ± 2.0
40 ± 2.0
45 ± 2.25
50 ± 2.5
60 ± 3.0
75 ± 3.75
100 ± 5.0
125 ± 6.5
150 ± 7.5
175 ± 8.0
200 ± 10.0
250 ± 12.5
DDU8C3-5004
DDU8C3-5006
DDU8C3-5008
DDU8C3-5010
DDU8C3-5012
DDU8C3-5014
DDU8C3-5020
DDU8C3-5025
DDU8C3-5030
DDU8C3-5035
DDU8C3-5040
DDU8C3-5045
DDU8C3-5050
DDU8C3-5060
DDU8C3-5075
DDU8C3-5100
DDU8C3-5125
DDU8C3-5150
DDU8C3-5175
DDU8C3-5200
DDU8C3-5250
·
·
Operating temperature: -40° to 85° C
Temp. coefficient of total delay: 300 PPM/°C
3.0ns
25%
25%
25%
25%
VDD IN
T1
T2
T3
T4
T5 GND
Functional diagram for dash numbers < 5020
20%
20%
20%
20%
20%
VDD IN
T1
T2
T3
T4
T5 GND
* Total delay is referenced to first tap output
Input to first tap = 3.0ns ± 1ns
Functional diagram for dash numbers >= 5020
NOTE: Any dash number between 5004 and 5250
not shown is also available.
Ó2000 Data Delay Devices
Doc #00115
5/19/00
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
DDU8C3
APPLICATION NOTES
Delay Devices if your application requires device
testing at a specific input condition.
HIGH FREQUENCY RESPONSE
The DDU8C3 tolerances are guaranteed for input
pulse widths and periods greater than those
specified in the test conditions. Although the
device will function properly for pulse widths as
small as 40% of the total delay and periods as
small as 80% of the total delay (for a symmetric
input), the delays may deviate from their values at
low frequency. However, for a given input
POWER SUPPLY BYPASSING
The DDU8C3 relies on a stable power supply to
produce repeatable delays within the stated
tolerances. A 0.1uf capacitor from VDD to GND,
located as close as possible to the VDD pin, is
recommended. A wide VDD trace and a clean
ground plane should be used.
condition, the deviation will be repeatable from
pulse to pulse. Contact technical support at Data
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
VDD
VIN
TSTRG
TLEAD
MIN
-0.3
-0.3
-55
MAX
7.0
VDD+0.3
150
UNITS NOTES
V
V
C
300
C
10 sec
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.00V to 3.60V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
High Level Output Voltage
VOH
3.00
3.20
V
VDD = 3.3, IOH = MAX
VIH = MIN, VIL = MAX
VDD = 3.3, IOL = MAX
VIH = MIN, VIL = MAX
Low Level Output Voltage
VOL
0.10
0.30
V
High Level Output Current
Low Level Output Current
High Level Input Voltage
Low Level Input Voltage
Input Current
IOH
IOL
VIH
VIL
IIH
-24.0
24.0
mA
mA
V
V
mA
2.50
0.80
0.10
VDD = 3.3
Doc #00115
5/19/00
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 www.datadelay.com
2
DDU8C3
PACKAGE DIMENSIONS
8
7
6
5
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
1
2
3
4
.280
MAX.
.500 MAX.
.290
MAX.
.015 TYP.
.070 MAX.
.010 .002
±
.018
TYP.
.350
MAX.
.300 .010
3 Equal spaces
±
each .100 .010
±
Non-Accumulative
DDU8C3-xx (DIP)
.020
TYP.
.040
TYP.
.010 TYP.
8
1
7
2
6
3
5
4
.270
TYP.
.430
TYP.
.100
.300
.110
.300
MAX.
.050
TYP.
.520 MAX.
DDU8C3-xxA1 (Gull-Wing)
Doc #00115
5/19/00
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
DDU8C3
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (VDD): 3.3V ± 0.1V
Load:
Cload
1 CMOS Gate
5pf ± 10%
:
Input Pulse:
High = 3.3V ± 0.1V
Threshold: 1.65V (Rising & Falling)
Low = 0.0V ± 0.1V
Source Impedance:
Rise/Fall Time:
50W Max.
3.0 ns Max. (measured
between 0.5V and 2.8V )
PWIN = 1.5 x Total Delay
PERIN = 10 x Total Delay
Pulse Width:
Period:
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
PULSE
GENERATOR
OUT
IN
T1
T2
T3
T4
T5
IN
TIME INTERVAL
COUNTER
DEVICE UNDER
TEST (DUT)
TRIG
TRIG
Test Setup
PERIN
PWIN
VIH
TRISE
TFALL
INPUT
SIGNAL
2.8V
1.5V
0.5V
2.8V
1.5V
0.5V
VIL
TRISE
TFALL
OUTPUT
SIGNAL
VOH
1.5V
1.5V
VOL
Timing Diagram For Testing
Doc #00115
5/19/00
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 www.datadelay.com
4
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