DDU8F-5006 [DATADELAY]
5-TAP, TTL-INTERFACED FIXED DELAY LINE; 5抽头， TTL -接口固定的延时线
| 型号： | DDU8F-5006 |
| 厂家： | 
DATA DELAY DEVICES, INC. |
| 描述： | 5-TAP, TTL-INTERFACED FIXED DELAY LINE |
| 文件： | 总4页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDU8F
Ò
5-TAP, TTL-INTERFACED
FIXED DELAY LINE
(SERIES DDU8F)
data
delay
3
devices, inc.
FEATURES
PACKAGES
1
2
3
4
5
6
7
14
13
12
11
10
9
VDD
N/C
T1
N/C
T3
N/C
T5
IN
N/C
N/C
T2
N/C
T4
IN
T2
VCC
·
·
·
·
·
·
Five equally spaced outputs
Fits standard 8-pin DIP socket
Low profile
1
2
3
4
8
T1
T3
T5
7
6
5
T4
GND
Auto-insertable
8
GND
Input & outputs fully TTL interfaced & buffered
DDU8F-xx
DDU8F-xxA1 Gull-Wing
DDU8F-xxB1 J-Lead
DIP
10 T2L fan-out capability
Military SMD
DDU8F-xxMD1
DDU8F-xxMD4
DDU8F-xxM Military DIP
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The DDU8F-series device is a 5-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
amount determined by the device dash number (See Table). For dash
numbers less than 5025, the total delay of the line is measured from T1 to
T5. The nominal tap-to-tap delay increment is given by one-fourth of the
IN
Signal Input
T1-T5 Tap Outputs
VCC +5 Volts
GND Ground
total delay, and the inherent delay from IN to T1 is nominally 3.5ns. For dash numbers greater than or
equal to 5025, the total delay of the line is measured from IN to T5. The nominal tap-to-tap delay
increment is given by one-fifth of this number.
SERIES SPECIFICATIONS
DASH NUMBER SPECIFICATIONS
·
·
·
·
Minimum input pulse width: 40% of total delay
Output rise time: 2ns typical
Supply voltage: 5VDC ± 5%
Supply current: ICCL = 32ma typical
ICCH = 7ma typical
Part
Total
Delay (ns)
4 ± 1.0 *
6 ± 1.0 *
8 ± 2.0 *
10 ± 2.0 *
12 ± 2.0 *
16 ± 2.0 *
20 ± 3.0 *
25 ± 3.0
Delay Per
Tap (ns)
1.0 ± 0.5
1.5 ± 0.5
2.0 ± 1.0
2.5 ± 1.0
3.0 ± 1.0
4.0 ± 1.5
5.0 ± 2.0
5.0 ± 2.0
6.0 ± 2.0
7.0 ± 2.0
8.0 ± 2.0
9.0 ± 3.0
10.0 ± 3.0
12.0 ± 3.0
15.0 ± 3.0
20.0 ± 3.0
25.0 ± 3.0
30.0 ± 3.0
35.0 ± 4.0
40.0 ± 4.0
50.0 ± 5.0
Number
DDU8F-5004
DDU8F-5006
DDU8F-5008
DDU8F-5010
DDU8F-5012
DDU8F-5016
DDU8F-5020
DDU8F-5025
DDU8F-5030
DDU8F-5035
DDU8F-5040
DDU8F-5045
DDU8F-5050
DDU8F-5060
DDU8F-5075
DDU8F-5100
DDU8F-5125
DDU8F-5150
DDU8F-5175
DDU8F-5200
DDU8F-5250
·
·
Operating temperature: 0° to 70° C
Temp. coefficient of total delay: 100 PPM/°C
30 ± 3.0
35 ± 3.0
40 ± 3.0
45 ± 3.0
50 ± 3.0
60 ± 3.0
75 ± 4.0
100 ± 5.0
125 ± 6.5
150 ± 7.5
175 ± 8.0
200 ± 10.0
250 ± 12.5
3.5ns
25%
25%
25%
25%
VCC IN
T1
T2
T3
T4
T5 GND
Functional diagram for dash numbers < 5025
20%
20%
20%
20%
20%
* Total delay is referenced to first tap output
Input to first tap = 3.5ns ± 1ns
VCC IN
T1
T2
T3
T4
T5 GND
Functional diagram for dash numbers >= 5025
NOTE: Any dash number between 5004 and 5250
not shown is also available.
Ó1997 Data Delay Devices
Doc #97012
1/28/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
DDU8F
APPLICATION NOTES
Delay Devices if your application requires device
testing at a specific input condition.
HIGH FREQUENCY RESPONSE
The DDU8F tolerances are guaranteed for input
pulse widths and periods greater than those
specified in the test conditions. Although the
device will function properly for pulse widths as
small as 40% of the total delay and periods as
small as 80% of the total delay (for a symmetric
input), the delays may deviate from their values
at low frequency. However, for a given input
condition, the deviation will be repeatable from
pulse to pulse. Contact technical support at Data
POWER SUPPLY BYPASSING
The DDU8F relies on a stable power supply to
produce repeatable delays within the stated
tolerances. A 0.1uf capacitor from VCC to GND,
located as close as possible to the VCC pin, is
recommended. A wide VCC trace and a clean
ground plane should be used.
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
VCC
VIN
TSTRG
TLEAD
MIN
-0.3
-0.3
-55
MAX
7.0
VDD+0.3
150
UNITS NOTES
V
V
C
300
C
10 sec
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
High Level Output Voltage
VOH
2.5
3.4
V
VCC = MIN, IOH = MAX
VIH = MIN, VIL = MAX
VCC = MIN, IOL = MAX
VIH = MIN, VIL = MAX
Low Level Output Voltage
VOL
0.35
0.5
V
High Level Output Current
Low Level Output Current
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current at Maximum
Input Voltage
High Level Input Current
Low Level Input Current
Short-circuit Output Current
Output High Fan-out
IOH
IOL
VIH
VIL
VIK
IIHH
-1.0
20.0
mA
mA
V
V
V
2.0
-60
0.8
-1.2
0.1
VCC = MIN, II = IIK
VCC = MAX, VI = 7.0V
mA
IIH
IIL
IOS
20
-0.6
-150
25
VCC = MAX, VI = 2.7V
VCC = MAX, VI = 0.5V
VCC = MAX
mA
mA
mA
Unit
Load
Output Low Fan-out
12.5
Doc #97012
1/28/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
DDU8F
PACKAGE DIMENSIONS
8
1
7
2
6
3
5
4
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
8
7
2
6
3
5
4
.440
MAX.
.280
MAX.
1
.500 MAX.
.500 MAX.
.290
MAX.
.290
MAX.
.020
TYP.
.015 TYP.
.070 MAX.
.010±.002
.018
TYP.
.180
TYP.
.350
MAX.
.300±.010
.010 TYP.
3 Equal spaces
each .100±.010
Non-Accumulative
.020
TYP.
.300
TYP.
.300
TYP.
DDU8F-xxM (Military DIP)
DDU8F-xx (Commercial DIP)
.020
.040
.010 TYP.
.020
.040
.050 TYP.
TYP.
TYP.
TYP.
TYP.
8
1
7
2
6
3
5
4
8
1
7
2
6
3
5
4
.320
TYP.
.270
TYP.
.430
TYP.
.270
TYP.
.100
.300
.110
.300
MAX.
.100
.300
.110
.350
MAX.
.110
TYP.
.050
TYP.
.520 MAX.
.520 MAX.
DDU8F-xxA1 (Commercial Gull-Wing)
DDU8F-xxB1 (Commercial J-Lead)
.650
.100
.100
.017
.017
1
7
14
8
1
7
14
8
.510
MAX.
.510
MAX.
.300
TYP.
.300
TYP.
.050
.025
.050
.100
.100
.080
.300
.510 MAX.
.300
.510 MAX.
.360 TYP.
.080
.200 MAX. (Com)
.225 MAX. (Mil)
.008
.200 MAX. (Com)
.225 MAX. (Mil)
.008
.045
.065
TYP.
.360
TYP.
.065
TYP.
.005
.065 TYP.
.065 TYP.
DDU8F-xxD1 (Commercial SMD)
DDU8F-xxMD1 (Military SMD)
DDU8F-xxD4 (Commercial SMD)
DDU8F-xxMD4 (Military SMD)
Doc #97012
1/28/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
DDU8F
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Load:
Cload
1 FAST-TTL Gate
5pf ± 10%
:
Input Pulse:
High = 3.0V ± 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
Source Impedance:
Rise/Fall Time:
50W Max.
3.0 ns Max. (measured
between 0.6V and 2.4V )
PWIN = 1.5 x Total Delay
PERIN = 10 x Total Delay
Pulse Width:
Period:
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
PULSE
GENERATOR
OUT
IN
T1
T2
T3
T4
T5
IN
TIME INTERVAL
COUNTER
DEVICE UNDER
TEST (DUT)
TRIG
TRIG
Test Setup
PERIN
PWIN
VIH
TRISE
TFALL
INPUT
SIGNAL
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
VIL
TRISE
TFALL
OUTPUT
SIGNAL
VOH
1.5V
1.5V
VOL
Timing Diagram For Testing
Doc #97012
1/28/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4
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