PDU1032H-.5 [DATADELAY]
5-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1032H); 5位, ECL -接口可编程延迟线(系列PDU1032H )型号: | PDU1032H-.5 |
厂家: | DATA DELAY DEVICES, INC. |
描述: | 5-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1032H) |
文件: | 总5页 (文件大小:262K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PDU1032H
5-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU1032H)
FEATURES
PACKAGES
GND
1
GND
OUT
32
31
•
•
•
•
Digitally programmable in 32 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
A2
NC
NC
ENB
2
2
3
OUT
GND
ENB
NC
4
A1
5
VEE
A0
Input & outputs fully 10KH-ECL interfaced &
buffered
6
7
NC
NC
A4
NC
A0
VEE
GND
A1
A2
GND
7
8
9
26
25
24
8
NC
•
Fits 32-pin DIP socket
9
GND
ENB
NC
10
11
12
13
14
15
16
17
18
19
20
VEE
A3
NC
NC
NC
NC
NC
NC
NC
VEE
NC
NC
IN
NC
11
NC
NC
NC
NC
GND
ENB
IN
A3
15
VEE
A4
16 17
PDU1032H-xx DIP
PDU1032H-xxC5 SMD
PDU1032H-xxM Mil DIP PDU1032H-xxMC5 Mil SMD
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU1032H-series device is a 5-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends
on the address code (A4-A0) according to the following formula:
IN
Signal Input
OUT Signal Output
A0-A4 Address Bits
ENB Output Enable
VEE -5 Volts
TDA = TD0 + TINC * A
GND Ground
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 20ns, inclusively. The
enable pin (ENB) is held LOW during normal operation. When this signal is brought HIGH, OUT is forced
into a LOW state. The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
DASH NUMBER SPECIFICATIONS
•
•
•
Total programmed delay tolerance: 5% or 2ns,
Part
Incremental Delay
Per Step (ns)
0.5 ± 0.3
Total
whichever is greater
Number
Delay (ns)
15.5 ± 2.0
31 ± 2.0
PDU1032H-.5
PDU1032H-1
PDU1032H-2
PDU1032H-3
PDU1032H-4
PDU1032H-5
PDU1032H-6
PDU1032H-8
PDU1032H-10
PDU1032H-12
PDU1032H-15
PDU1032H-20
Inherent delay (TD0): 5.5ns typical for dash numbers
up to 5, greater for larger #’s
1.0 ± 0.5
2.0 ± 0.5
62 ± 3.1
Setup time and propagation delay:
3.0 ± 1.0
93 ± 4.6
Address to input setup (TAIS): 3.6ns
Disable to output delay (TDISO): 1.7ns typical
Operating temperature: 0° to 70° C
4.0 ± 1.0
124 ± 6.2
155 ± 7.8
186 ± 9.3
248 ± 12.4
310 ± 15.5
372 ± 18.6
465 ± 23.2
620 ± 31.0
5.0 ± 1.0
•
•
•
•
•
6.0 ± 1.0
Temperature coefficient: 100PPM/°C (excludes TD0)
Supply voltage VEE: -5VDC ± 5%
8.0 ± 1.0
10.0 ± 1.5
12.0 ± 1.5
15.0 ± 1.5
20.0 ± 2.0
Power Dissipation: 615mw typical (no load)
Minimum pulse width: 20% of total delay
NOTE: Any dash number between .5 and 20
not shown is also available.
2003 Data Delay Devices
Doc #97045
2/25/03
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU1032H
APPLICATION NOTES
spurious signals persists until the required TDISH
ADDRESS UPDATE
has elapsed.
The PDU1032H is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time, TOAX
is required before the address lines can change.
This time is given by the following relation:
,
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.
TOAX = max { (Ai - A i-1) * TINC , 0 }
where A i-1 and Ai are the old and new address
codes, respectively. Violation of this constraint
When operating the unit between the
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required TOAX has elapsed.
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
A similar situation occurs when using the ENB
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the ENB signal high and
the IN signal low for a time given by:
TDISH = Ai * TINC
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
Violation of this constraint may, depending on the
history of the input signal, cause spurious signals
to appear on the OUT pin. The possibility of
A4-A0
ENB
IN
A i-1
Ai
TAENS
TOAX
TAIS
TENIS
PWIN
TDISH
TDA
PWOUT
TDISO
OUT
Figure 1: Timing Diagram
Doc #97045
2/25/03
DATA DELAY DEVICES, INC.
2
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU1032H
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER
Total Programmable Delay
Inherent Delay
Disable to Output Low Delay
Address to Enable Setup Time
Address to Input Setup Time
Enable to Input Setup Time
Output to Address Change
Disable Hold Time
SYMBOL
TDT
MIN
TYP
31
5.5
1.7
UNITS
TINC
ns*
ns
TD0
TDISO
TAENS
TAIS
1.0
3.6
3.6
ns
ns
TENIS
ns
TOAX
See Text
See Text
16
TDISH
PERIN
PERIN
PERIN
PWIN
PWIN
PWIN
Absolute
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
Input Period
Suggested
Recommended
Absolute
40
200
8
Input Pulse Width
Suggested
20
Recommended
100
* Greater for dash numbers larger than 5
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
VEE
MIN
-7.0
VEE - 0.3
-55
MAX
0.3
UNITS NOTES
V
V
C
C
VIN
0.3
TSTRG
TLEAD
150
300
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 75C)
PARAMETER
SYMBOL
MIN
TYP
MAX
-0.735
-1.600
-1.070
UNITS
NOTES
High Level Output Voltage
Low Level Output Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
VOH
VOL
VIH
VIL
IIH
-1.020
-1.950
V
V
VIH = MAX,50Ω to -2V
VIL = MIN, 50Ω to -2V
V
V
µA
µA
-1.480
0.5
475
VIH = MAX
VIL = MIN
IIL
Doc #97045
2/25/03
DATA DELAY DEVICES, INC.
3
3 Mt. Prospect Ave. Clifton, NJ 07013
PDU1032H
PACKAGE DIMENSIONS
32 31
26 25 24
17
.400
TYP.
1
2
7
8
9
11
15 16
1.650 TYP.
.320
.020
MAX.
TYP.
.150
.030
±
.012 TYP.
.018
.100
.300
TYP.
.600
.700
.800
TYP.
1.000
1.400
1.500
.075
PDU1032H-xx (Commercial DIP)
PDU1032H-xxM (Military DIP)
.020 TYP.
.040 TYP.
.010±.002
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
.882
.710 .590
MAX.
±.00
±.00
.007
±.00
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
.090
.100
.280
.050
±.01
MAX.
1.100
2.080±.020
PDU1032H-xxC5 (Commercial SMD)
PDU1032H-xxMC5 (Military SMD)
Doc #97045
2/25/03
DATA DELAY DEVICES, INC.
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU1032H
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): -5.0V ± 0.1V
Load:
50Ω to -2V
5pf ± 10%
Cload
:
Input Pulse:
Standard 10KH ECL
Threshold: (VOH + VOL) / 2
levels
50Ω Max.
(Rising & Falling)
Source Impedance:
Rise/Fall Time:
2.0 ns Max. (measured
between 20% and 80%)
PWIN = 1.5 x Total Delay
PERIN = 10 x Total Delay
Pulse Width:
Period:
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
REF
PULSE
OUT
IN
OUT
IN
DEVICE UNDER
TEST (DUT)
OSCILLOSCOPE
GENERATOR
TRIG
TRIG
ADDRESS SELECT
Test Setup
PERIN
PWIN
TRISE
TFALL
INPUT
VIH
80%
50%
80%
50%
20%
SIGNAL
VIL
20%
DRISE
DFALL
OUTPUT
SIGNAL
VOH
50%
50%
VOL
Timing Diagram For Testing
Doc #97045
2/25/03
DATA DELAY DEVICES, INC.
5
3 Mt. Prospect Ave. Clifton, NJ 07013
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