DCAN [DCD]
Configurable CAN Bus Controller; 可配置的CAN总线控制器
| 型号： | DCAN |
| 厂家： | 
DIGITAL CORE DESIGN |
| 描述： | Configurable CAN Bus Controller |
| 文件： | 总3页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DCAN
Configurable CAN Bus Controller
ver 1.01
● Last Error Code
O V E R V I E W
The DCAN is a stand-alone controller for the
● Fully synthesizable
Controller Area Network (CAN) widely used in
automotive and industrial applications. DCAN
conforms to Bosch CAN 2.0B specification
(2.0B Active). Core has simple CPU interface
(8/16/32 bit configurable data width) with little
or big endian adressing scheme. Hardware
message filtering and 64 byte receive FIFO
enables back-to-back message reception with
minimum CPU load. The DCAN is described
at RTL level allowing target use in FPGA or
ASIC technologies.
● Static synchronous design with positive
edge clocking and synchronous reset
● No internal tri-states
● Scan test ready
A P P L I C A T I O N S
● Embedded communication systems
● Automotive, industrial
● Medical equipment
K E Y F E A T U R E S
● Conforms to Bosch CAN 2.0B Active
● 8/16/32-bit CPU slave interface with little
D E L I V E R A B L E S
Source code:
or big endianess
♦
♦
● Simple interface allows easy connection
◊ VHDL Source Code
VHDL test bench environment
◊ Active-HDL automatic simulation mac-
ros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
Technical documentation
◊ Installation notes
to CPU
● Supports both standard (11-bit identifier)
and extended (29 bit identifier) frames.
● Data rate up to 1 Mbps
♦
● Hardware message filtering (dual/single
filter)
◊ HDL core specification
◊ Datasheet
● 64 byte receive FIFO
♦
♦
♦
Synthesis scripts
Example application
Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● One transmit buffer
● No overload frames are generated
● Normal & Listen Only Mode
● Single Shot transmission
● Ability to abort transmission
● Readable error counters
●
Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support
●
●
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
enrmt
enwmt
txd
output
output
output
output
TX DPRAM read enable
TX DPRAM write enable
CAN transmit data
S Y M B O L
docdbusctrl
dmt(31:0)
waddrmt(1:0)
raddrmt(1:0)
enrmt
sclk
SCLK clock output
rst
cs
qmt(31:0)
enwmt
B L O C K D I A G R A M
Figure below shows the DCAN IP Core block
diagram.
rd
wr
datao(31:0)1
int
TX RAM pins
be(3:0)2
datai(31:0)1
addr(4:0)
clk
dmr(31:0)
waddrmr(3:0)
raddrmr(3:0)
enrmr
TX RAM
interface
clk
sclk
BRP
Baud Rate
Prescaler
rst
BSP
Bit Stream
Processor
cs
rd
wr
BTL
Bit Timing
Logic
txd
rxd
IML
Interface
Management
Logic
qmr(31:0)
rxd
enwmr
be(3:0)
EML
Error
Management
Logic
addr(4:0)
datai(31:0)
ACF
Acceptance Filtering
int
txd
sclk
datao(31:0)
RX RAM
interface
Receive
FIFO
RX RAM pins
1 – data bus can be configured as 8-, 16- or 32- bit depends
on processor’s bus size
Interface Management Logic (IML) – inter-
prets commands from the CPU, provides in-
terrupt and status indication.
2 – byte enable (be) size is set accordingly to data bus size
P I N S D E S C R I P T I O N
Bit Stream Processor (BSP) – translates
messages into frames and vice versa.
PIN
TYPE
DESCRIPTION
Baud Rate Prescaler (BRP) – defines the
length of time quantum.
clk
rst
cs
rd
input
input
Global clock
Bit Timing Logic (BTL) – processes the bit
time, calculates position of the sample point
and performs synchronization.
Global reset
input
Chip select
input
Read data strobe
Error Management Logic (EML) – is re-
wr
input
Write data strobe
sponsible for fault confinement handling.
addr(4:0)
be(3:0) 2
datai(31:0)1
qmr(31:0)
qmt(31:0)
rxd
input
Host address bus
Acceptance Filter (ACF) – decides whether
incoming messages are accepted or not
based upon filter registers settings.
input
Host byte enable
input
Host output data bus
RX DPRAM data output
TX DPRAM data output
CAN receive data
input
TX/RX RAM interfaces – interfaces to exter-
nal dual port memories used by the DCAN
core to store received and transmitted
frames.
input
input
docdbusctrl
datao(31:0)1
int
input
DoCD debugger input
Host input data bus
Interrupt signal
output
output
output
output
output
output
output
output
output
output
dmr(31:0)
waddrmr(3:0)
raddrmr(3:0)
enrmr
RX DPRAM data input
RX DPRAM write address
RX DPRAM read address
RX DPRAM read enable
RX DPRAM write enable
TX DPRAM data input
TX DPRAM write address
TX DPRAM read address
enwmr
dmt(31:0)
waddrmt(1:0)
raddrmt(1:0)
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
P E R F O R M A N C E
C O N T A C T S
The following table gives a survey about the
Core area and performance in the ALTERA®
devices after Place & Route (all key features
have been included):
For any modification or special request
please contact Digital Core Design or local
distributors.
Headquarters:
Wroclawska 94
Speed
grade
-6
Device
Logic Cells
Fmax
41-902 Bytom, POLAND
CYCLONE
CYCLONE2
STRATIX
1956 + 2 ESB 123 MHz
1899 + 2 ESB 137 MHz
1956 + 2 ESB 130 MHz
1956 + 2 ESB 188 MHz
1956 + 2 ESB 131 MHz
1956 + 2 ESB 138 MHz
info@dcd.pl
e-mail:
-6
-5
-3
-5
-5
-1
tel. : +48 32 282 82 66
fax : +48 32 282 74 37
Distributors:
STRATIX2
STRATIXGX
MERCURY
EXCALIBUR
APEX2A
APEX20KC
APEX20KE
APEX20K
ACEX1K
1956 + 2 ESB
79 MHz
-7
-7
-1
-1
-1
-1
1956 + 2 ESB 108 MHz
l
http://www.dcd.pl/apartn.php
Please check
l
1956 + 2 ESB
1956 + 2 ESB
1956 + 2 ESB
1956 + 2 ESB
1956 + 2 ESB
94 MHz
83 MHz
66 MHz
66 MHz
66 MHz
FLEX10KE
8-bit CPU Core performance in ALTERA® devices
Speed
grade
-6
Device
Logic Cells
Fmax
CYCLONE
CYCLONE2
STRATIX
STRATIX2
STRATIXGX
MERCURY
EXCALIBUR
APEX2A
1967 + 2 ESB 124 MHz
1890 + 2 ESB 135 MHz
1967 + 2 ESB 131 MHz
1523 + 2 ESB 187 MHz
1967 + 2 ESB 132 MHz
1967 + 2 ESB 141 MHz
-6
-5
-3
-5
-5
-1
-7
1967 + 2 ESB
1967 + 2 ESB 113 MHz
79 MHz
APEX20KC
APEX20KE
APEX20K
ACEX1K
-7
-1
-1
-1
1967 + 2 ESB
1937 + 2 ESB
1967 + 2 ESB
1967 + 2 ESB
1967 + 2 ESB
95 MHz
78 MHz
68 MHz
63 MHz
63 MHz
FLEX10KE
-1
16-bit Core performance in ALTERA® devices
Speed
grade
-6
Device
Logic Cells
Fmax
CYCLONE
CYCLONE2
STRATIX
STRATIX2
STRATIXGX
MERCURY
EXCALIBUR
APEX2A
1931 + 2 ESB 123 MHz
1879 + 2 ESB 136 MHz
1931 + 2 ESB 134 MHz
1510 + 2 ESB 185 MHz
1931 + 2 ESB 130 MHz
1931 + 2 ESB 143 MHz
-6
-5
-3
-5
-5
-1
-7
1931 + 2 ESB
1931 + 2 ESB 110 MHz
84 MHz
APEX20KC
APEX20KE
APEX20K
ACEX1K
-7
-1
-1
-1
1931 + 2 ESB
1931 + 2 ESB
1931 + 2 ESB
1931 + 2 ESB
1931 + 2 ESB
94 MHz
83 MHz
66 MHz
66 MHz
66 MHz
FLEX10KE
-1
32-bit Core performance in ALTERA® devices
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
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