DCORDIC [DCD]

CORDIC processor; CORDIC处理器


型号：	DCORDIC
厂家：	DIGITAL CORE DESIGN
描述：	CORDIC processor CORDIC处理器
文件：	总3页 (文件大小：127K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DCORDIC

CORDIC processor

ver 1.16

◊ sin(θ), cos(θ)

◊ sinh(θ), cosh(θ)

◊ arctan(x)

◊ arctanh(x)

◊ ln(x), e^x, x

O V E R V I E W

The DCORDIC uses the CORDIC algorithm

to compute trigonometric, reverse trigono-

metric, hyperbolic and reverse hyperbolic

functions.

It supports sine, cosine, arcus tangent func-

tions for hyperbolic and trigonometric sys-

tems. Logarithm, square root and exponent

functions can also be computed. It supports

fixed point 24-bit numbers.

D E L I V E R A B L E S

Source code:

◊ VHDL Source Code or/and

◊ VERILOG Source Code or/and

◊ Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench environ-

ment

♦

O P E R A T I N G M O D E S

◊ Active-HDL automatic simulation mac-

ros

◊ ModelSim automatic simulation macros

◊ Tests with reference responses

Technical documentation

◊ Installation notes

● Trigonometric system

● Hyperbolic system

● Rotation mode

● Vectoring mode

♦

◊ HDL core specification

◊ Datasheet

Synthesis scripts

Example application

Technical support

◊ IP Core implementation support

◊ 3 months maintenance

● Delivery the IP Core updates, mi-

nor and major versions changes

● Delivery the documentation up-

dates

A P P L I C A T I O N S

● DSP algorithms

♦

● Digital filtering

● Math coprocessors

K E Y F E A T U R E S

● 24-bit precision (IEEE-754 single preci-

● Phone & email support

sion real mantissa format)

● 4-ulp accuracy (34-bit internal registers)

● Fully configurable

● Performs the following functions:

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

TYPE

DESCRIPTION

Global clock

L I C E N S I N G

Comprehensible and clearly defined licensing

methods without royalty fees make using of

IP Core easy and simply.

clk

rst

Input

Global reset

Enable computing

Single Design license allows use IP Core in

single FPGA bitstream and ASIC implemen-

tation.

datai[29:0]

Data bus (input)

Write data into register

Read data from register

Chip select

Unlimited Designs, One Year licenses allow

use IP Core in unlimited number of FPGA

bitstreams and ASIC implementations.

addr[1:0]

rotatemode

vectormode

hyprsel

trigsel

Select register to read/write

Rotate mode select

Vectoring mode select

Hyperbolic system select

Trigonometric system select

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

datao[29:0] Output Data bus (output)

● Single Design license for

busy

Output Busy indicator

○

VHDL, Verilog source code called HDL

Source

○

Encrypted, or plain text EDIF called Netlist

B L O C K D I A G R A M

● One Year license for

Encrypted Netlist only

● Unlimited Designs license for

ROM – stores constant coefficients used

for hyperbolic and trigonometric opera-

tions.

○

Registers – contains all data registers

hold temporary operation results as well

as final results. Input arguments are writ-

ten to this register also.

○

HDL Source

Netlist

● Upgrade from

○

HDL Source to Netlist

Control Unit – maintains control opera-

tion on Registers module, Shifters module

and ROM unit, while busy is active.

Single Design to Unlimited Designs

S Y M B O L

datai(29:0)

ROM

datai(29:0) datao(29:0)

datao(29:0)

addr(1:0)

busy

Interface

addr(1:0)

busy

Registers

trigsel

hyprsel

rotatemode

vectormode

rotatemode

vectormode

Control

unit

trigsel

hyprsel

Shifters

clk

rst

clk

Shifters – performs shifting operations in

successful iterations. Number of shifts

P I N S D E S C R I P T I O N

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

vary and depend on internal iteration cy-

cle and computed functions.

C O N T A C T S

For any modification or special request

please contact to Digital Core Design or local

distributors.

Interface – performs communication be-

tween internal CORDIC modules and ex-

ternal devices. Signalizes when output

registers contain a valid result.

Headquarters:

Wroclawska 94

41-902 Bytom, POLAND

info@dcd.pl

e-mail:

tel. : +48 32 282 82 66

fax : +48 32 282 74 37

Distributors:

http://www.dcd.pl/apartn.php

Please check

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

DCORDIC [DCD]

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