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DSPIS

更新时间：2024-09-18 06:44:26

品牌：DCD

描述：Serial Peripheral Interface - Slave

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概述
数据手册

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DSPIS 概述

Serial Peripheral Interface - Slave 串行外设接口 - 从

DSPIS 数据手册

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DSPIS

Serial Peripheral Interface –Slave

ver 1.01

master. Transmission is ended when the SS

line goes high.

O V E R V I E W

The DSPIS is a fully configurable SPI ma

slave device, designated to operate with pas-

sive devices like memories, LCD drivers etc.

The DSPIS allows user to configure polarity

and phase of serial clock signal SCK.

A serial clock line (SCK) synchronizes shift-

ing and sampling of the information on the two

independent serial data lines. DSPIS data are

simultaneously transmitted and received.

The DSPIS is a technology independent

design that can be implemented in a variety of

process technologies.

DSPIS is fully customizable, which means

it is delivered in the exact configuration to

meet users’ requirements. There is no need to

pay extra for not used features and wasted

silicon. It includes fully automated testbench

with complete set of tests allowing easy

package validation at each stage of SoC de-

sign flow.

The DSPIS system is flexible enough to in-

terface directly with numerous standard prod-

uct peripherals from several manufacturers.

Data rates as high as CLK/4. Clock control

logic allows a selection of clock polarity and a

choice of two fundamentally different clocking

protocols to accommodate most available

synchronous serial peripheral devices.

The DSPIS allows the SPI Master to com-

municate with passive devices. When trans-

mission starts (SS Line goes low) the first por-

tion of data is copied to the address register

and then to the ADDRESS bus output, after

transmission of the address the DSPIS gener-

ates the read signal (RD) and copy DATAI bus

contents to the transmitter shift register, and

prepare data to be exchanged with SPI Mas-

ter. During the next data portion transmission

DSPIS simultaneously transmits data out and

in. When the first data portion is received the

DSPIS asserts DATAO bus generates the

write signal (WE), then increments ADDRESS

bus performs a read operation and prepare

another data portion to be exchanged with SPI

A P P L I C A T I O N S

● Embedded microprocessor boards

● Consumer and professional audio/video

● Home and automotive radio

● Digital multimeters

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

K E Y F E A T U R E S

L I C E N S I N G

● SPI Slave

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

○

Slave operation

Automatic read and write operations

Single Design license allows use IP Core in

single FPGA bitstream and ASIC implementa-

tion.

Automatic address incrementation after any

data portion transfer

○

Configurable address and data length.

Configurable SCK phase and polarity.

Supports speeds up ¼ of system clock

Unlimited Designs, One Year licenses allow

use IP Core in unlimited number of FPGA bit-

streams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

Simple interface allows easy connection to

passive devices, and SPI Master

● Fully synthesizable, static synchronous

design with no internal tri-states

● Single Design license for

D E L I V E R A B L E S

Source code:

○

VHDL, Verilog source code called HDL

Source

♦

◊ VHDL Source Code or/and

◊ VERILOG Source Code or/and

◊ Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench environ-

ment

◊ Active-HDL automatic simulation macros

◊ ModelSim automatic simulation macros

◊ Tests with reference responses

Technical documentation

◊ Installation notes

○

Encrypted, or plain text EDIF called Netlist

● One Year license for

Encrypted Netlist only

● Unlimited Designs license for

○

HDL Source

Netlist

♦

● Upgrade from

◊ HDL core specification

◊ Datasheet

Synthesis scripts

○

HDL Source to Netlist

Single Design to Unlimited Designs

♦

Example application

Technical support

◊ IP Core implementation support

◊ 3 months maintenance

● Delivery the IP Core updates, minor

and major versions changes

● Delivery the documentation updates

● Phone & email support

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

ments. The flexibility of the SPI system on the

DSPIS allows direct interface to almost any

existing synchronous serial peripheral.

S Y M B O L

clk

rst

Shift register– is a central element in the SPI

system. When an SPI transfer occurs, an 8-bit

character is shifted out on data pin while a

different 8-bit character is simultaneously

shifted in a second data pin. Another way to

view this transfer is that an 8-bit shift register

in the master and another 8-bit shift register in

the slave are connected as a circular 16-bit

shift register. When a transfer occurs, this

distributed shift register is shifted eight bit po-

sitions; thus, the characters in the master and

slave are effectively exchanged.

datai(D:0)

datao(D:0)

address(A:0)

cpha

cpol

sck

P I N S D E S C R I P T I O N

TYPE

DESCRIPTION

cpha

cpol

sck

clk

rst

SPI Clock Logic

clk

rst

input Global clock

input Global reset

datai(D:0)

cpha

cpol

input Data bus input

input SCK clock phase

input SCK clock polarity

input SPI serial clock

input SPI serial data input

input Slave select

MSB

LSB

Shift Reg.

sck

Data reg.

Adr. reg.

datai

datao

address

SPI

Controller

datao(D:0)

output Data bus output

addres(A:0) output Address bus output

Data Register holds data read from passive

device and to be sent serially to the SPI Mas-

ter.

output Read output

output Write enable

output Slave serial data output

Address Register holds address presented

on Address bus. it’s contents is incremented

every single data portion sent/received serially

through the SPI bus.

B L O C K D I A G R A M

SPI Clock logic controls phase and polarity of

the SCK clock line, and detects correct sam-

ple and shift edge for the Shift register. SPI

clock Logic allow user to select any of four

combinations of serial clock (SCK) phase and

polarity using two pins CPHA and CPOL. The

clock polarity is specified by the CPOL, which

selects an active high or active low clock and

has no significant effect on the transfer format.

The clock phase CPHA selects one of two

fundamentally different transfer formats. The

clock phase and polarity should be identical

for the master SPI device and the communi-

cating slave device. In some cases, the phase

and polarity are changed between transfers to

allow a master device to communicate with

peripheral slaves having different require-

SPI Controller - detects begin and end of SPI

transfer. Manages data exchange between

DSPIS and passive device controlled by

DSPIS, and increment Address Register

(SPAD) after any successful transfer.

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

Speed

grade

-6

P E R F O R M A N C E

Device

Logic Cells

F_max

The following table gives a survey about

the Core performance in the ALTERA® de-

vices after Place & Route (all key features

have been included):

CYCLONE

CYCLONE2

STRATIX

STRATIX2

STRATIXGX

MERCURY

EXCALIBUR

APEX2A

APEX20KC

APEX20KE

APEX20K

ACEX1K

354 MHz

329 MHz

386 MHz

422 MHz

382 MHz

347 MHz

224 MHz

320 MHz

241 MHz

202 MHz

140 MHz

196 MHz

204 MHz

257 MHz

114 MHz

-6

-5

-3

-5

-1

-7

-1

-3

-5

FLEX10KE

MAX2

MAX3K

MAX7K

Core performance in ALTERA® devices

T r a n s f e r F o r m a t s

Software can select any of four combinations of serial clock (SCK) phase and polarity using two

bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit,

which selects an active high or active low clock and has no significant effect on the transfer format.

The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats.

The clock phase and polarity should be identical for the master SPI device and the communicating

slave device. In some cases, the phase and polarity are changed between transfers to allow a

master device to communicate with peripheral slaves having different requirements. The flexibility

of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial

peripheral.

SCK CYCLE#

SCK (CPOL=0)

SCK (CPOL=1)

LSB

M SB

MOSI

M ISO

M SB

LSB

SCK CYCLE#

SCK (CPOL=0)

SCK (CPOL=1)

LSB

M SB

MOSI

M ISO

M SB

LSB

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

C O N T A C T S

For any modification or special request

please contact to Digital Core Design or local

distributors.

Headquarters:

Wroclawska 94

41-902 Bytom, POLAND

info@dcd.pl

e-mail:

tel. : +48 32 282 82 66

fax : +48 32 282 74 37

Distributors:

http://www.dcd.pl/apartn.php

Please check

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

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