DEI1071A-SES-G_技术文档

Device

Engineering

Incorporated

DEI1070A-DEI1075A

ARINC 429 LINE DRIVER FAMILY

385 East Alamo Drive

Chandler, AZ 85225

Phone: (480) 303-0822

Fax: (480) 303-0824

E-mail: admin@deiaz.com

FEATURES

x

TTL/CMOS to ARINC 429 Line Driver

HI/LO Speed Control Pin for Hi (100KBS) or Lo (12.5KBS) speed slew rates

±9.5V to ±16.5V supplies

Drives full ARINC load

Output resistor options: 0, 10 or 37.5 Ohms

Tristate Output options

8 lead SOICN package with exposed pad for thermal enhancement (shown actual size)

The DEI1070A family is an improved version of the popular DEI1070 family

Pin for pin replacements with the HI8585 and HI8586

GENERAL DESCRIPTION

The DEI107xA is a family of 8 pin bipolar integrated circuit line drivers which directly drive the ARINC 429

avionics serial digital data bus. These ARINC 429 Line Drivers convert TTL/CMOS serial input data to the “Tri-

level RZ bipolar differential modulation format” of the ARINC bus. The output slew rate is selectable for HI speed

(100KBS) or LOW speed (12.5KBS) operation. No external timing capacitors are required.

The DEI107xA Line Driver family is an improved version of the popular DEI107x family. It provides:

x

Lower power consumption

Excellent waveform fidelity

Improved transient immunity. This improvement simplifies the equipment design for lightning and RF

immunity requirements.

This new Line Driver family provides options for various output resistor values and output tri-state capability (see

table 1). There are three output resistor options: 0ȍ, 10ȍ and 37ȍ. The 0ȍ and 10ȍ versions require external

resistors to achieve the 37ȍ output resistance of the ARINC 429 standard. The external resistors are normally used

to simplify the external transient voltage protection network. The outputs are tri-state capable on the 1073/4/5

versions. This feature is useful in non-standard applications where there are multiple drivers on a wire pair.

Table 1 Line Driver Options

1070A

37 Ohms

No

1071A

10 Ohms

No

1072A

0 Ohms

No

1073A

37 Ohms

Yes

1074A

10 Ohms

Yes

1075A

0 Ohms

Yes

Output Resistor Value

Tri-state Capability

Page 1 of 12

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TERMINAL DESCRIPTION

Table 2 Pin Description

NAME

HI/LO

TTLIN0

TTLIN1

GND

DESCRIPTION

LOGIC INPUT. Slew rate control. 1 = Hi speed. 0 = Low speed.

LOGIC INPUT. Serial digital data input 0.

LOGIC INPUT. Serial digital data input 1.

POWER INPUT. Ground.

1

2

3

4

8

7

6

5

HI/LO

1

2

3

4

5

6

7

8

V+

TTLIN0

TTLIN1

429OUTB

429OUTA

GND

V-

POWER INPUT. –9.5 to –16.5 VDC

V-

Note:

429 OUTPUT. ARINC 429 format serial digital data output A.

429 OUTPUT. ARINC 429 format serial digital data output B.

POWER INPUT. +9.5 to +16.5 VDC.

429OUTA

429OUTB

V+

Heatsink pad is electrically Isolated.

FUNCTIONAL DESCRIPTION

HI/LO

429OUTA

Rout:

0, 10, or

37.5 Ohms

TTLIN1

INPUT LOGIC

and

LEVEL SHIFT

OUTPUT

DRIVERS

EDGE

SHAPING

TTLIN0

429OUTB

Rout:

TRI-STATE

0, 10, or

37.5 Ohms

Figure 1 Block Diagram

Table 3 Speed Control Function Table

HI/LO

OUTPUT TRANSITION TIME

10uS (12.5KBS data)

L

H

1.5uS (100KBS data)

Table 4 Transmit Data Function Table

TTLIN1

TTLIN0

429OUTA

0V

429OUTB

0V

NOTES

Null output

Zero output

One output

Null output

L

H

L

H

L

-5V

5V

0V

5V

-5V

0V

H

1070A/1071A/1072A

H

Hi-Z

Hi-Z output

1073A/1074A/1075A

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TTLIN1

TTLIN0

Tf

+5

90%

Tr

Tf

429OUTA

10%

-5

90%

Tr

+5

429OUTB

-5

Tfall

+10

90%

Differential

429OUT

(A-B)

Tfall

Trise

10%

Trise

90%

-10

Figure 2 Line Driver Waveforms

ELECTRICAL DESCRIPTION

Table 5 Absolute Maximum Ratings

PARAMETER

MIN

MAX

UNITS

V+ Supply Voltage

V- Supply Voltage

-0.3

0.3

-65

+20

-20

V

Storage Temperature

Input Voltage

+150

°C

TTLIN and HI/LO Inputs

429OUT Outputs (175uS surge)

Gnd – 0.5

‘V+’ + 0.5

V

1072A/1075A ‘V-’ – 1.0

1071A/1074A ‘V-’ – 5.0

1070A/1073A ‘V-’– 20

‘V+’ + 1.0

‘V+’ + 5.0

‘V+’ + 20

V

Input Current

429OUT Outputs (175uS surge)

-0.5

0.5

A

Power Dissipation @ 85°C

8L EP SOIC, thermal pad soldered to heat spreader land

8L SB DIP

1.2

0.72

W

Junction Temperature:

Tjmax, Plastic Packages

Tjmax, Ceramic Packages

150

175

°C

ESD per JEDEC A114-A Human Body Model

2000

V

Peak body Temperature:

8L EP SOIC

260

°C

Notes:

1. Stresses above absolute maximum ratings may cause permanent damage to the device.

2. The device is tolerant of one or both outputs shorted to Ground and of both outputs shorted together.

3. Voltages referenced to Ground

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Table 6 Recommended Operating Conditions

PARAMETER

SYMBOL

CONDITIONS

Supply Voltage

V+

V-

9.5 to 16.5V

-9.5 to –16.5V

Operating Temperature

-xEx parts

-55 to +85 °C

-55 to +125 °C

T_op

-xMx parts

Table 7 Electrical Characteristics

PARAMETER

TEST CONDITIONS (1) SYMBOL

MIN

NOM

MAX

UNITS

LOGIC INPUTS

VIH

Input Voltage, Logic 1

2.0

V+

0.8

V

Input Voltage, Logic 0

Input Current, Logic 1

Input Current, Logic 0

VIL

-0.3

VIN = 5.0V

VIN = 0.0V

IIH

0

25

100

uA

IIL

-20

-100

ARINC OUTPUTS

ARINC Output Voltage

Single Ended

HI

NULL

LO

Referenced to Ground

No Load.

VoHI

VoNULL

VoLO

4.5

-0.25

-5.5

5.0

0

-5.0

5.5

+0.25

-4.5

V

Output Tristate Leakage

Current

Force output to -5V and +5V

Iz

-200

+200

uA

1073A/1074A/1075A

ARINC Output Short Circuit External 37.5ȍ resistor

Current

to GND

1072A/1075A

Output LO IscLO

Output HI IscHI

100

-146

133

-133

146

-100

mA

ARINC Output Short Circuit External 27.5 ȍ resistor

Current

to GND

1071A/1074A

Output LO IscLO

Output HI IscHI

67

-175

133

-133

175

-67

mA

ARINC Output Short Circuit Output shorted to GND

Current

Output LO IscLO

Output HI IscHI

64

-283

133

-133

283

-64

mA

1070A/1073A

Output Resistance:

1070A/1073A

1071A/1074A

1072A/1075A

Room Temperature

Calculated from

Rout37

24

6

0

37.5

10

0.2

50

13.5

2

Ohms

delta-Vout / delta-Iload

Where Iload = 0 and 20mA

See Figure 3

Rout10

Rout0

Output Slew Rate, Hi Speed

Lo to Hi and Hi to Lo

transitions

HI/LO = 1

No Load, 10% to 90%

single ended output

HI/LO = 0

No Load, 10% to 90%

single ended output

Tr/Tf

1

5

2

us

Output Slew Rate, Lo Speed

Lo to Hi and Hi to Lo

transitions

15

SUPPLY CURRENT

V+ =15V, V- = -15V

Quiescent Operating Supply

Current:

IV+

HI/LO = 0 or 1

TTLIN0=TTLIN1= 0V

No Load

IV+

IV-

-

3.0

-2.5

6.0

-

mA

IV-

-6.0

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PARAMETER

TEST CONDITIONS (1) SYMBOL

MIN

NOM

MAX

UNITS

Notes:

1. General Conditions: Tcase = rated operating temperature, -55/+85°C or -55/+125°C.

V+/- = +/-9.5 to +/-16.5V

2. Unless otherwise noted, currents flowing in to DUT are positive, currents flowing out of DUT are

negative, voltages are referenced to Ground.

3. Not production tested.

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

-100

-50

0

50

100

150

200

Temperature (°C)

Figure 3 Normalized Output Resistance vs. Temperature

OUTPUT V-I CHARACTERISTICS

1000

800

600

400

200

NULL output

HI output

0

LO output

-200

-400

-600

-800

-1000

-20

-15

-10

-5

0

5

10

15

20

Output Voltage (V)

Figure 4 429OUT V-I Characteristics, ±15V supplies

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DESIGN CONSIDERATIONS

Power Supplies and Bypass Capacitors

The DEI107XA Line Driver operates from ±9.5V to ±16.5V dual supplies. Proper bypassing ensures stability while driving

large capacitive loads. The Line Driver requires a minimum of a 0.1uF bypass capacitor placed as close as possible to the V+

and V- pins.

Transient Voltage Protection

The DEI107xA Line Driver requires external components to achieve immunity from surges such as those defined by DO160D

Section 22, “Lightning Induced Transient Susceptibility”. Typical surge protection includes silicon Transient Voltage

Suppressor (TVS) devices and may include all or part of the 37.5 Ohm output resistance as external resistors to limit the surge

current.

V+

DEI107xA

The 107xA has a robust output stage which includes large

driver devices and clamp diodes to the V+ and V- power

R2

R1

rails as shown in Figure 5. It withstands surge currents of

±0.5A for 175us without damage when powered with

±15V supplies. At that surge current, the diodes clamp at

~1V above (below) the V+ ( V-) supply rail. ~350mA

flows to the V- (V+) supply through the output amplifier,

and ~150ma flows to the V+ (V-) supply through the

clamp diode. The outputs may be damaged by surges

greater than 1A / 175uS. At that current, the diodes

clamp at ~1.8V above (below) the supply.

OUTPUT

AMP

OUTA

Rout:

0, 10, or

37.5 Ohms

V-

TVS

to

ARINC DATA BUS

Twisted Shielded Pair cable

V+

OUTPUT

AMP

OUTB

Figure 5 Surge Protection Network

V-

The external lightning protection network should be

designed to meet the specific requirements and constraints

of the application equipment. The protection network should limit the OUTA/B pin surge current to the 0.5A / 175uS

maximum. The generalized circuit of Figure 5 represents several TVS protection network options:

x

The on-chip Rout value is 0, 10, or 37 Ohms depending on the 1070A – 1075A part number

Select the total output resistance, Rout + R1 + R2, = 37 Ohms to meet ARINC bus requirements

o

Select R1 = 37ȍ, R2 = 0ȍ, Rout = 0ȍ for lowest TVS surge current rating (smallest TVS devices)

Select R1 = 0ȍ, Rout + R2 = 37ȍ for highest TVS clamp voltage (20V + V+/-)

If the V+/V- supplies are un-powered or below operating voltage during the surge event, large currents may flow

through the internal clamp diodes and damage the driver. If the application requires lightning immunity while un-

powered, Select R1 = 0ȍ, Rout + R2 = 37ȍ, and select the TVS clamp voltage for <20V.

x

Select TVS devices for the following

o

TVS Surge power/current rating must withstand the application requirements for Lightning Induced Transient

Levels and Waveforms. Microsemi Corporation publishes an application note specific to the DO160 lightning

requirements, available at: http://www.microsemi.com/micnotes/126.pdf

o

Select low capacitance TVS devices to minimize the load on the line driver. (Examples: Microsemi LC and

HSMBJSA series TVS)

This is a priority for Hi Speed ARINC applications where the low capacitance is

important for optimum signal integrity and power consumption. Note that the maximum total capacitance on the

ARINC bus is 30nF line to line.

o

Select the TVS clamp voltage at the lightning surge conditions such that the voltage/current into the 107XA OUT

pin is within the safe region.

x

If R1 is used to limit the TVS surge current, the resistor must withstand the surge current and voltage.

Alternate protection methods may be appropriate in some applications.

x

External clamp diodes to the supply rails may be used to shunt surge current to the supply rails rather than to Ground.

PTC “resetable fuses” may be used for R1 to protect the driver and TVS from shorts to 28V aircraft power.

Page 6 of 12

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Some general considerations related to Lightning Immunity:

x

Analyze the TVS high current signal and ground return path to insure adequate surge current capability. The IR

voltage and L*di/dt voltage in the ground return will add additional stress beyond the TVS clamp voltage.

Observe suitable PCB design rules for traces subject to high voltage and high current surges.

When possible, locate TVS devices close to the equipment connector to minimize the length of the surge

voltage/current traces within the equipment.

x

The shields of ARINC 429 data bus cables should be terminated to aircraft ground at all ends and at all bulkhead

disconnects.

Thermal Management

Good thermal management is fundamental to Line Driver device reliability. It is particularly important in designs operating at

the HI speed data rate (100KBS) with high capacitive loads as this produces maximum power dissipation. While the 107xA

device will function at a junction temperature (Tj) above 190°C, it is inappropriate to continuously operate the plastic package

above 150°C. Like all microcircuits, long term reliability is improved with lower operating temperatures.

The Line Driver’s operating Tj is determined by internal power dissipation, package thermal resistance, and ambient

temperature. The internal power dissipation (Pd) varies greatly with several variables:

x

Data Rate – The Hi Speed (100kbs) rate produces maximum power dissipation

Load – The maximum ARINC 429 load is 30nF||400 ȍ line-to-line. Many applications only drive a fraction of the

full load.

x

Data Duty Cycle - ARINC bus activity, averaged over 10 seconds = Bits transmitted / total possible bits. Many

applications are active <70%.

x

Supply Voltage – V+/V- supply range is from ±9.5V to ±16.5V. Higher voltage => higher power

Rout configuration - The power dissipated in the two 37ȍ output resistors is internal to the IC for the 1070/3, and

external for the 1072/5.

The internal power dissipation for 100kbs applications can be estimated from Figure 6. Pd for low speed operation (12.5kbs) is

normally not an issue, so is not considered here. The curves in Figure 6 indicate Pd for various loads, supply voltage, and Rout

configuration. It represents Pd for 100% Data Duty Cycle at 100KBS with no word gap null times. Thus the indicated Pd

values are considered maximum values and should be reduced to account for the Data Duty Cycle as follows:

x

Estimate DDC = total bits transmitted in 10 sec period / 1,000,000

= 32 x total ARINC words transmitted in 10 sec period / 1,000,000

Use Figure 6 to select an indicated Pd for the application supply voltage and load. This may involve estimating the

Line Driver’s load and interpolating between the curves.

Calculate adjusted Pd = DDC * (Pd - 0.1) + 0.1 (W)

The operating junction temperature is calculated as follows:

Tj = Ta + Pd*Ĭja

where

Tj = junction temperature (°C)

Ta = Ambient temperature (°C)

Pd = Internal power dissipation (W)

Ĭja = IC package thermal resistance from junction to ambient (°C/W). Refer to package details.

The ARINC 429 Line Driver outputs may be subject to short circuit conditions due to cable wiring errors or faults which

typically occur during equipment test and aircraft installation environments. The common cases are one or both outputs

shorted to Ground, or both outputs shorted together. These conditions may cause considerable internal power dissipation

depending on the following:

x

Data Duty Cycle – The line-to-line and line-to-Ground shorts cause little or no power dissipation when the outputs are

in the Null state. However when the output is driving a HI/LO state, the short circuit current is limited by the 37.5ȍ

Rout at about ~133mA. This is modulated by the ARINC waveform, producing an effective current of ~88mA*

DDC. This current causes heating in the output amplifier and Rout resistor.

x

Supply Voltage – A lower supply voltage results in lower Pd during short circuit conditions. The internal Pd for both

outputs shorted while operating at 100% DDC is ~2W with ±15V supplies, but is reduced to ~1.5W with ±12V

supplies. This is for 0ȍ Rout configurations.

Page 7 of 12

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x

Rout configuration – Each of the two 37.5ȍ Rout resistors dissipates ~0.29W when shorted at 100% DDC. This

power is dissipated in the external resistors for the 1072A or 1075A parts, and internal to the IC for the 1070A or

1073A parts. Thus the 1072A or 1075A have a lower Tj and are more tolerant to short circuit conditions.

The PCB design and layout is a significant factor in determining thermal resistance (Ĭja) of the Line Driver IC package. Use

maximum trace width on all power and signal connections at the IC. These traces serve as heat spreaders which improve heat

flow from the IC leads. The exposed heat sink pad of the SOIC package should be soldered to a heat-spreader land pattern on

the PCB. The IC exposed pad is electrically isolated, so the PCB land may be at any potential; typically Ground for the best

heat sink. Maximize the PCB land size by extending it beyond the IC outline if possible. A grid of thermal VIAs, which drop

down and connect to the buried copper plane(s), should be placed under the heat-spreader land. A typical VIA grid is 12mil

holes on a 50mil pitch. The barrel is plated to about 1.0 ounce copper. Use as many VIAs as space allows. VIAs should be

plugged to prevent voids being formed between the exposed pad and PCB heat-spreader land due to solder escaping by the

capillary effect. This can be avoided by tenting the VIAs with solder mask.

DEI107xA POWER DISSIPATION

100kbs Data Rate, 100% Duty Cycle

1.6

1.4

1.2

1

No Load

15nF/800ȍ Load - Internal 37ȍ

15nF/800ȍ Load - External 37ȍ

30nF/400ȍ Load - Internal 37ȍ

30nF/400ȍ Load- External 37ȍ

0.8

0.6

0.4

0.2

0

8

10

12

14

16

18

Supply Voltage (+/-V)

Figure 6 Internal Power Dissipation

Page 8 of 12

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PACKAGE DESCRIPTION

Table 8 Package Characteristics

PACKAGE TYPE

PACKAGE THERMAL

JEDEC MOISTURE

SENSITIVITY LEVEL &

PEAK BODY TEMP

LEAD FINISH

MATERIAL /

JEDEC Pb-Free

CODE

Pb Free

DESIGNATON

REF

RESIST.

șJC / șJA

(ºC/W)

8L SB DIP

8 SB DIP

55 / 125

HERMETIC

Au

e4

Pb Free solder

terminals

8L EP SOIC

(Exposed Pad)

8 EP SOIC 10 / 49 (1)

G

MSL 1

260ºC

NiPdAu

e4

RoHS Compliant

8L ES SOIC

(Exposed Slug)

8 ES SOIC 10 / 49 (1)

G

MSL 1

260ºC

Matte Sn

e3

RoHS Compliant

Notes:

1. șJA with the exposed pad soldered to a PCB land with (6) 12mil thermal vias connected to an internal ground plane which

is one of the 2 center layers on a 4 layer board .

Figure 7 Mechanical Outline - 8L EP SOIC (Exposed Pad)

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Figure 8 Mechanical Outline - 8L ES SOIC (Exposed Slug)

Figure 9 Mechanical Outline - 8L Ceramic Sidebrazed DIP

Page 10 of 12

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PROCESS DESCRIPTION

Table 9 Process Flow

PROCESS STEP

PRE-BURN-IN Electrical Test

BURN-IN

YES

STANDARD

N/A

BURN IN (1)

N/A

96hrs @ +125 °C

FINAL ELECTRICAL TEST,

Room Temperature

FINAL ELECTRICAL TEST,

High Temperature

FINAL ELECTRICAL TEST,

Low Temperature

100%

100% @

+85 or +125°C

0.65% AQL

@ -55°C

100%

100% @

+85 or +125°C

0.65% AQL

@ -55°C

NOTES:

1. Burn-in conditions: 125°C, 96 hrs, V+/V- = +/-15.0V Inputs = 0V,

Outputs open.

Page 11 of 12

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ORDERING INFORMATION

Table 10 Ordering Information

Part Number

Marking

Package

Output

Resistor

37

Tri State

Output

No

Burn-In

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

Temperature

DEI1070A-SES-G

DEI1070A-SMS-G DE1070A / MS

DEI1070A-SMB-G DE1070A / MB

DEI1070A-DMS

DEI1070A-DMB

DEI1071A-SES-G

DEI1071A-SMS-G DE1071A / MS

DEI1071A-SMB-G DE1071A/MB

DEI1071A-DMS

DEI1071A-DMB

DEI1072A-SES-G

DEI1072A-SMS-G DE1072A / MS

DEI1072A-SMB-G DE1072A / MB

DEI1072A-DMS

DEI1072A-DMB

DEI1072A-YES-G DEI / 1072AYES 8L ES SOIC G

DEI1073A-SES-G

DEI1073A-SMS-G DE1073A / MS

DEI1073A-SMB-G DE1073A / MB

DEI1073A-DMS

DEI1073A-DMB

DEI1074A-SES-G

DEI1074A-SMS-G DE1074A / MS

DEI1074A-SMB-G DE1074A / MB

DEI1074A-DMS

DEI1074A-DMB

DEI1075A-SES-G

DEI1075A-SMS-G DE1075A / MS

DEI1075A-SMB-G DE1075A / MB

DE1070A / ES

8L EP SOIC G

-55 / +85 ºC

-55 / +125 ºC

-55 / +85 ºC

-55 / +125 ºC

-55 / +85 ºC

-55 / +125 ºC

-55 / +85 ºC

-55 / +125 ºC

-55 / +85 ºC

-55 / +125 ºC

-55 / +85 ºC

-55 / +125 ºC

37

10

0

DEI1070A / DMS 8L SB DIP

DEI1070A / DMB 8L SB DIP

DE1071A / ES

8L EP SOIC G

DEI1071A / DMS 8L SB DIP

DEI1071A / DMB 8L SB DIP

DE1072A / ES

8L EP SOIC G

0

DEI1072A / DMS 8L SB DIP

DEI1072A / DMB 8L SB DIP

0

No

DE1073A / ES

8L EP SOIC G

37

10

0

Yes

DEI1073A / DMS 8L SB DIP

DEI1073A / DMB 8L SB DIP

DE1074A / ES

8L EP SOIC G

DEI1074A / DMS 8L SB DIP

DEI1074A / DMB 8L SB DIP

DE1075A / ES

8L EP SOIC G

0

DEI1075A-DMS

DEI1075A-DMB

DEI1075A / DMS 8L SB DIP

DEI1075A / DMB 8L SB DIP

DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or

guarantee regarding suitability of its products for any particular purpose.

Page 12 of 12

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型号：	DEI1071A-SES-G
厂家：	Device Engineering Incorporated
描述：	ARINC 429 LINE DRIVER FAMILY 驱动光电二极管接口集成电路驱动器
文件：	总12页 (文件大小：315K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DEI1071A-SES-G [DEIAZ]

相关型号：

DEI1071A-SMB-G

DEI1071A-SMS-G

DEI1072A-DMB

DEI1072A-DMS

DEI1072A-SES-G

DEI1072A-SMB-G

DEI1072A-SMS-G

DEI1072A-YES-G

DEI1073A-DMB

DEI1073A-DMS

DEI1073A-SES-G

DEI1073A-SMB-G