AT25EU0011A [DIALOG]
1-Mbit, Ultra-Low Energy Serial Flash Memory;
| 型号： | AT25EU0011A |
| 厂家： | 
Dialog Semiconductor |
| 描述： | 1-Mbit, Ultra-Low Energy Serial Flash Memory |
| 文件： | 总62页 (文件大小：1039K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
Key Features
Voltage Range: 1.65 V – 3.6 V
Serial Peripheral Interface (SPI) compatible
Supports SPI modes 0 and 3 (1,1,1)
Supports dual input and dual output operations (1,1,2)
Supports quad input and quad output operations (1,1,4)
85 MHz Maximum Operating Frequency
Program
Serial-input Page Program up to 256 bytes
Program Suspend and Resume
Erase
Page erase (256-byte)
Block erase (4/32/64 kbyte)
Full Chip erase
Erase Suspend and Resume
Program/Erase Speed
Page Program time: 2 ms typical
Page Erase time: 8 ms typical
Block Erase time: 8 ms typical
Chip Erase time: 8 ms typical
Flexible Architecture: 4/32/64 kbyte blocks
Hardware Reset (HOLD pin)
Software-controlled Reset
Software/Hardware Write Protection
3x512-Byte Security Registers with OTP Lock
Enable/Disable protection with WP Pin
Write protect all/portion of memory via software protect
Top or Bottom Block selection
Low Power Consumption
1.2 mA active read current (typical)
100 nA deep power-down (DPD) current (typical)
Temperature Range: -40 °C to +85 °C
Cycling Endurance/Data Retention
10k program and erase cycles
Typical 20-year data retention
Industry standard green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad 2x3x0.6 UDFN
Datasheet
29-Jul-2021
Revision B
1
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
Contents
Key Features............................................................................................................................................................................. 1
1 General Description ............................................................................................................................................................. 6
2 Package Types and Pinouts ................................................................................................................................................ 7
2.1 Pin Configuration - SOP 150-mil................................................................................................................................ 7
2.2 Pad Configuration - UDFN 2X3 MM........................................................................................................................... 7
3 Block Addresses .................................................................................................................................................................. 9
4 Functional and Operational Description .......................................................................................................................... 10
4.1 Dual SPI Commands ............................................................................................................................................... 10
4.2 Quad SPI Commands.............................................................................................................................................. 10
4.3 Supply Voltage......................................................................................................................................................... 10
4.3.1 Operating Supply Voltage .......................................................................................................................... 10
4.3.2 Power-up Conditions.................................................................................................................................. 10
4.3.3 Device Reset.............................................................................................................................................. 10
4.3.4 Power-Down............................................................................................................................................... 10
4.4 Active Power and Standby Power Modes................................................................................................................ 10
4.5 Hold Condition ......................................................................................................................................................... 11
4.6 Software Reset and Hardware RESET.................................................................................................................... 11
4.6.1 Software Reset........................................................................................................................................... 11
4.6.2 Hardware Reset (HOLD pin) ...................................................................................................................... 11
5 Status and Configuration Registers ................................................................................................................................. 12
5.1 Status Register 1 ..................................................................................................................................................... 12
5.2 Status Register 2 ..................................................................................................................................................... 13
5.3 Status Register 3 ..................................................................................................................................................... 13
5.4 Status Register Memory Protection ......................................................................................................................... 15
5.4.1 Protection Tables ....................................................................................................................................... 15
6 Command Set ..................................................................................................................................................................... 17
6.1 Configuration and Status Commands...................................................................................................................... 19
6.1.1 Write Enable (06h) ..................................................................................................................................... 19
6.1.2 Write Enable for Volatile Status Register (50h).......................................................................................... 19
6.1.3 Write Disable (04h) .................................................................................................................................... 20
6.1.4 Read Status Register-1 (05h), Status Register-2 (35h), Status Register-3 (15h) ...................................... 20
6.1.5 Active Status Interrupt (25h) ...................................................................................................................... 21
6.1.6 Write Status Register (01h or 31h or 11h) ................................................................................................. 21
6.2 Read Commands ..................................................................................................................................................... 23
6.2.1 Normal Read Data (03h)............................................................................................................................ 23
6.2.2 Fast Read (0Bh)......................................................................................................................................... 24
6.2.3 Fast Read Dual Output (3Bh)..................................................................................................................... 25
6.2.4 Fast Read Dual I/O (BBh) .......................................................................................................................... 26
6.2.5 Fast Read Quad Output (6Bh) ................................................................................................................... 28
6.2.6 Fast Read Quad I/O (EBh)......................................................................................................................... 29
6.2.7 Set Burst with Wrap (77h).......................................................................................................................... 31
6.3 ID and Power Commands........................................................................................................................................ 31
6.3.1 Release Power-down / Device ID (ABh) .................................................................................................... 32
6.3.2 Read Manufacturer / Device ID (90h) ........................................................................................................ 33
6.3.3 Dual I/O Read Manufacture ID/ Device ID (92h)........................................................................................ 34
6.3.4 Quad I/O Read Manufacture ID / Device ID (94h) ..................................................................................... 35
6.3.5 Read JEDEC ID (9Fh)................................................................................................................................ 36
6.3.6 Read Unique ID Number (4Bh).................................................................................................................. 37
6.3.7 Deep Power-Down (B9h) ........................................................................................................................... 38
6.4 Program / Erase and Security Commands............................................................................................................... 39
6.4.1 Page Program (02h)................................................................................................................................... 39
6.4.2 Dual Page Program (A2h).......................................................................................................................... 40
6.4.3 Quad Page Program (32h)......................................................................................................................... 41
6.4.4 Page Erase (81h/DBh)............................................................................................................................... 42
Datasheet
29-Jul-2021
Revision B
2
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.4.5 4 kB Block Erase (20h) .............................................................................................................................. 42
6.4.6 32 kB Block Erase (52h) ............................................................................................................................ 43
6.4.7 64 kB Block Erase (D8h)............................................................................................................................ 44
6.4.8 Chip Erase (C7h / 60h) .............................................................................................................................. 45
6.4.9 Program/Erase Suspend (75h) .................................................................................................................. 45
6.4.10 Program/Erase Resume (7Ah)................................................................................................................. 47
6.4.11 Erase Security Registers (44h) ................................................................................................................ 48
6.4.12 Program Security Registers (42h)............................................................................................................ 49
6.4.13 Read Security Registers (48h) ................................................................................................................. 50
6.4.14 Enable Reset (66h) and Reset Device (99h) ........................................................................................... 51
6.4.15 Read Serial Flash Discoverable Parameter (5Ah) ................................................................................... 51
7 Electrical Characteristics .................................................................................................................................................. 52
7.1 Absolute Maximum RatinGS.................................................................................................................................... 52
7.2 Operating ranges ..................................................................................................................................................... 52
7.3 Power-Up / Power-Down Timing and Requirements ............................................................................................... 53
7.4 DC Characteristics................................................................................................................................................... 54
7.5 AC Measurement conditions.................................................................................................................................... 54
7.6 AC Characteristics ................................................................................................................................................... 55
7.7 Serial output timing .................................................................................................................................................. 56
7.8 Serial input timing .................................................................................................................................................... 56
7.9 HOLD Timing ........................................................................................................................................................... 56
7.10 WP Timing ............................................................................................................................................................. 57
8 Ordering Information ......................................................................................................................................................... 58
9 Packaging Information ....................................................................................................................................................... 59
9.1 eight-pin SOIC 150-mil............................................................................................................................................. 59
9.2 eight-pAD 2 x 3 x 0.6 mm UDFN ............................................................................................................................. 60
Revision History..................................................................................................................................................................... 61
Datasheet
29-Jul-2021
Revision B
3
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
Figures
Figure 1: AT25EU0011A Logic Diagram................................................................................................................................... 6
Figure 2: AT25EU0011A Pin Assignments, Eight-pin SOP 150-mil (Top View) ....................................................................... 7
Figure 3: AT25EU0011A Pad Assignments, Eight-pad UDFN 2x3 mm (Top View).................................................................. 7
Figure 4: Hold Condition Activation......................................................................................................................................... 11
Figure 5: Write Enable Command for SPI Mode..................................................................................................................... 19
Figure 6: Write Enable for Volatile Status Register (50h)........................................................................................................ 19
Figure 7: Write Disable Command, SPI Mode ........................................................................................................................ 20
Figure 8: Read Status Register Command ............................................................................................................................. 20
Figure 9: Active Status Interrupt Command ............................................................................................................................ 21
Figure 10: Write Status Register Command............................................................................................................................ 22
Figure 11: Read Data Command ............................................................................................................................................ 23
Figure 12: Fast Read Command............................................................................................................................................. 24
Figure 13: Fast Read Dual Output Command......................................................................................................................... 25
Figure 14: Fast Read Dual I/O Command (Initial command or previous M5-4≠10) ................................................................ 26
Figure 15: Fast Read Dual I/O Command (Previous command M5-4=10) ............................................................................. 27
Figure 16: Fast Read Quad Output Command ....................................................................................................................... 28
Figure 17: Fast Read Quad I/O Command (Initial command or previous M5-4≠10)............................................................... 29
Figure 18: Fast Read Quad I/O Command (Previous command set M5-4=10)...................................................................... 30
Figure 19: Set Burst with Wrap Command.............................................................................................................................. 31
Figure 20: Release Power-Down Command........................................................................................................................... 32
Figure 21: Release Power-Down / Device ID Command ........................................................................................................ 32
Figure 22: Read Manufacturer / Device ID Command ............................................................................................................ 33
Figure 23: Dual I/O Read Manufacture ID/ Device ID Timing ................................................................................................. 34
Figure 24: Quad I/O Read Manufacture ID / Device ID Sequence Diagram........................................................................... 35
Figure 25: Read JEDEC ID Command.................................................................................................................................... 36
Figure 26: Read Unique ID Sequence Diagram...................................................................................................................... 37
Figure 27: Deep Power-Down Command ............................................................................................................................... 38
Figure 28: Page Program Command ...................................................................................................................................... 39
Figure 29: Dual Page Program Command.............................................................................................................................. 40
Figure 30: Quad Input Page Program Command.................................................................................................................... 41
Figure 31: Page Erase Command........................................................................................................................................... 42
Figure 32: 4 kB Block Erase Command .................................................................................................................................. 42
Figure 33: 32 kB Block Erase Command ................................................................................................................................ 43
Figure 34: 64 kB Block Erase Command ................................................................................................................................ 44
Figure 35: Chip Erase Command............................................................................................................................................ 45
Figure 36: Program/Erase Suspend Command ...................................................................................................................... 46
Figure 37: Program/Erase Resume Command....................................................................................................................... 47
Figure 38: Erase Security Register Command........................................................................................................................ 48
Figure 39: Program Security Register Command ................................................................................................................... 49
Figure 40: Read Security Command....................................................................................................................................... 50
Figure 41: Enable Reset and Reset Command Sequence ..................................................................................................... 51
Figure 42: Read Serial Flash Discoverable Parameter Command ......................................................................................... 51
Figure 43: Power-Up Timing and Voltage Levels.................................................................................................................... 53
Figure 44: AC Measurement I/O Waveform............................................................................................................................ 54
Figure 45: Serial Output Timing .............................................................................................................................................. 56
Figure 46: Serial Input Timing................................................................................................................................................. 56
Figure 47: HOLD Timing ......................................................................................................................................................... 56
Figure 48: WP Timing.............................................................................................................................................................. 57
Datasheet
29-Jul-2021
Revision B
4
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
Tables
Table 1: Block Addresses of the AT25EU0011A........................................................................................................................9
Table 2: Status Register 1 Format ...........................................................................................................................................12
Table 3: Status Register 2 Format ...........................................................................................................................................13
Table 4: Status Register 3 Format ...........................................................................................................................................13
Table 5: Status Register Protect Table ....................................................................................................................................14
Table 6: AT25EU0011A Status Register Memory Protection (CMP = 0).................................................................................15
Table 7: AT25EU0011A Status Register Memory Protection (CMP = 1) ................................................................................16
Table 8: Command Set Table 1 ...............................................................................................................................................17
Table 9: Wrap Around Length Based on Wrap Bits ................................................................................................................31
Table 10: AT25EU0011A ID Definition Table...........................................................................................................................31
Table 11: Readable Area of Memory While a Program or Erase Operation is Suspended .....................................................45
Table 12: Acceptable Commands During Program/Erase Suspend After tPSL/tESL- ...............................................................46
Table 13: Acceptable Commands During Suspend (tPSL/tESL Not Required)..........................................................................46
Table 14: Erase Security Coding..............................................................................................................................................48
Table 15: Program Security Register Coding...........................................................................................................................49
Table 16: Read Secutiry Register Coding................................................................................................................................50
Table 17: Absolute Maximum Ratings......................................................................................................................................52
Table 18: Operating Ranges ....................................................................................................................................................52
Table 19: Timing Requirements for Power-Up/Down...............................................................................................................53
Table 20: DC Electrical Characteristics....................................................................................................................................54
Table 21: AC Measurement Conditions ...................................................................................................................................54
Table 22: AC Electrical Characteristics....................................................................................................................................55
Table 23: Ordering Codes........................................................................................................................................................58
Table 24: Package Types ........................................................................................................................................................58
Datasheet
29-Jul-2021
Revision B
5
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
1
General Description
The AT25EU0011A is 1-Mbit Serial Peripheral Interface (SPI) Flash memory, designed for a wide variety of high-volume consum-
er-based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution.
The flexible erase architecture of the device, with its page erase granularity, is ideal for data storage as well, eliminating the need
for additional data storage devices.
The erase block sizes of the device have been optimized to meet the needs of today's code and data storage applications. By
optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules
and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that
occurs with large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows
additional code routines and data storage segments to be added while still maintaining the same overall device density.
The device uses a single low-voltage power supply, ranging from 1.65 V to 3.6 V, and supports JEDEC standard manufacturer
and device ID, a 128-bit Unique Serial Number, and three 512-bytes Security Registers.
Figure 1 shows the logic diagram of the AT25EU0011A device.
VCC
SCK
SO (IO๛)
SI (IO๚)
AT25EU0011A
CS
WP (IO)
HOLD (IO)
VSS
Figure 1: AT25EU0011A Logic Diagram
Datasheet
29-Jul-2021
Revision B
6
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
2
Package Types and Pinouts
2.1 PIN CONFIGURATION - SOP 150-MIL
CS
1
2
3
4
8
7
6
5
VCC
SO (IO1)
WP (IO2)
GND
HOLD (IO3)
SCK
SI (IO0)
Figure 2: AT25EU0011A Pin Assignments, Eight-pin SOP 150-mil (Top View)
2.2 PAD CONFIGURATION - UDFN 2X3 MM
CS
SO (IO1)
1
2
3
4
8
7
6
5
VCC
HOLD (IO3)
SCK
WP (IO2, ACC)
GND
SI (IO0)
Figure 3: AT25EU0011A Pad Assignments, Eight-pad UDFN 2x3 mm (Top View)
During all operations, VCC must be held stable and within the specified valid range: VCC (min) to VCC (max).
All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL, or VOL; see Section 7.6, AC
Characteristics).
Asserted
State
Symbol Name and Function
CHIPSELECT:Asserting the CS pin selects the device. When the CSpin is deasserted,
Type
the device is deselected and normally be placed in standby mode (all input signals are
ignored, and all output signals are high impedance).
Unless an internal Program, Erase, or Write Status Registers embedded operation is
in progress, the device is in the Standby Power mode. Driving the CS input to low
enables the device, placing it in the Active Power mode. After power-up, a falling edge
on CS is required before the start of any command.
CS
Low
Input
A high-to-low transition on the CS pin is required to start an operation; a low-to-high
transition is required to end an operation. When ending an internally self-timed opera-
tion, such as a program or erase cycle, the device does not enter the standby mode
until the operation is complete.
SERIAL CLOCK: This pin provides a clock to the device. Command, address, and
input data present on the SI pin is latched in on the rising edge of SCK, while output
data on the SO pin is clocked out on the falling edge of SCK.
SCK
-
-
-
Input
SERIAL INPUT: The SI pin is used for all data input, including command and address
sequences. Data on the SI pin is latched in on the rising edge of SCK.
Data present on the SI pin is ignored whenever the device is deselected (CS is deas-
serted).
SI (I/O0)
Input/Output
Input/Output
SERIAL OUTPUT: Data on the SO pin is clocked out on the falling edge of SCK.
SO (I/O1) The SO pin is in a high-impedance state whenever the device is deselected (CS is
deasserted).
Datasheet
29-Jul-2021
Revision B
7
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
Asserted
State
Symbol Name and Function
Type
WRITE PROTECT: The WP pin controls the hardware locking feature of the device.
When WP is driven low (VIL), while the Status Register Protect bits (SRP1 and SRP0)
of the Status Registers (SR2[0] and SR1[7]) are set to 0 and 1, respectively, it is not
WP (I/O2) possible to write to the Status Registers. This prevents any alteration of the Status
Registers. As a consequence, all the data bytes in the memory area that are protected
by the Block Protect, BP4, BP3 bits in the status registers, are also hardware-protected
against data modification while WP remains low.
-
Input/Output
HOLD:TheHOLD functionis only available when QE=0, which can be configured either
as a HOLD pin or as a RESET pin, depending on the Status Register setting.
When QE=0 and HOLD/RES= 0, the HOLD signal goes low to stop any serial commu-
nications with the device, but does not stop write status register, programming, or erase
operations in progress.
HOLD (I/
O3)
-
Input/Output
To use HOLD, CS must be kept low. It starts on falling edge of the HOLD signal, and
SCK must be low. The HOLD condition ends on the rising edge of the HOLD signal
when SCK is low.
VCC
DEVICE POWER SUPPLY: The VCC pin supplies the source voltage to the device.
-
-
Power
Power
GROUND: The ground reference for the power supply. Connect GND to the system
ground.
GND
Datasheet
29-Jul-2021
Revision B
8
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
3
Block Addresses
Table 1: Block Addresses of the AT25EU0011A
Memory Density
Block (64 kB)
Block (32 kB)
Block No.
Block Size
Address Range
Block 0
4
000000h-000FFFh
.
.
.
.
.
.
.
.
.
Half Block 0
Block 7
Block 8
4
4
007000h-007FFFh
008000h-008FFFh
Block 0
.
.
.
.
.
.
Half Block 1
Half Block 2
Half Block 3
4
Block 15
Block 16
4
4
00F000h-00FFFFh
010000h-010FFFh
1 Mbit
.
.
.
.
.
.
.
.
.
Block 23
Block 24
4
4
017000h-017FFFh
018000h-018FFFh
Block 1
.
.
.
.
.
.
.
.
.
Block 31
4
01F000h-01FFFFh
Datasheet
29-Jul-2021
Revision B
9
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
4
Functional and Operational Description
The AT25EU0011A features a serial peripheral interface on a four-signals bus: SCK, CS, SI, and SO. Both SPI bus mode 0 and
3 are supported.
The SPI mode has input bits (including commands, addresses, data, M7~M0, W6~W4, etc.) latched on the rising edge of SCK,
as well as output bits transferred out on the falling edge of SCK.
4.1 DUAL SPI COMMANDS
The AT25EU0011A supports Dual SPI operation. when using the Dual Output Fast Read (3Bh) or Dual I/O Fast read (BBh)
commands. These commands allow data to be transferred to, and from, the device at two times the rate of the standard SPI.
When using the Dual SPI command, the SI and SO pins become bidirectional I/O pins IO0 and IO1, respectively.
4.2 QUAD SPI COMMANDS
The AT25EU0011A supports Quad SPI operation when using the Quad Output Fast Read (6Bh) or Quad I/O Fast Read (EBh)
commands. These commands allow the data to be transferred to, and from, the device at four times the rate of standard SPI.
When using the Quad SPI command, the SI and SO pins become bidirectional I/O pins, and the WP and HOLD pins become IO2
and IO3, respectively. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status Register 2 to be set to 1.
4.3 SUPPLY VOLTAGE
4.3.1 Operating Supply Voltage
Before selecting the memory and issuing commands to it, a valid and stable VCC voltage within the specified [VCC(min),
VCC(max)] range must be applied (see operating ranges). To secure a stable DC supply voltage, it is recommended to decouple
the VCC line with a suitable capacitor (usually of the order of 100 nF to 1 μF) close to the VCC/VSS package pins. This voltage
must remain stable and valid until the end of the transmission of the command; for a Write command, it must be stable until the
completion of the internal write cycle.
4.3.2 Power-up Conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the CS line is not allowed to
float; it must follow the VCC voltage. Thus, it is recommended to connect the CS line to VCC through a suitable pull-up resistor.
Also, the CS input offers a built-in safety feature: the CS input is edge sensitive and level sensitive: after power-up, the device
does not become selected until a falling edge has first been detected on CS. This ensures that CS must have been high before
going low to start the first operation.
4.3.3 Device Reset
To prevent inadvertent Write operations during power-up (continuous rise of VCC), a power-on reset (POR) circuit is included. At
power-up, the device does not respond to any command until VCC has reached the power-on reset threshold voltage (this
threshold is lower than the minimum VCC operating voltage defined in Power-up Timing). When VCC is lower than VWI, the
device is reset.
4.3.4 Power-Down
At power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to below the power-on
reset threshold voltage (VWI), the device stops responding to any command sent to it. During power-down, the device must be
deselected (CS must be allowed to follow the voltage applied on VCC) and in Standby power mode (there must be no internal
Write cycle in progress).
4.4 ACTIVE POWER AND STANDBY POWER MODES
When CS is low, the device is selected, and in the Active Power mode. The device consumes ICC. When CS is high, the device
is deselected. If a Write cycle is not currently in progress, the device then goes in to the Standby Power mode, and the device
consumption drops to ICC1.
Datasheet
29-Jul-2021
Revision B
10
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
4.5 HOLD CONDITION
When QE=0, HOLD/RST=0, the HOLD signal is used to pause any serial communications with the device without resetting the
clocking sequence, but does not stop the in-progress operation of write status register, programming, or erasing. During the Hold
condition, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and SCK are don’t care. To enter the Hold
condition, the device must be selected, with CS low. Normally, the device is kept selected for the whole duration of the Hold
condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this
mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the
HOLD signal is driven low at the same time as SCK already being low (Figure 4).The Hold condition ends when the HOLD signal
is driven high at the same time as Serial Clock (SCK) is low. Figure 4 also shows what happens if the rising and falling edges are
not timed to coincide with SCK being low.
CS
SCK
HOLD
HOLD
Figure 4: Hold Condition Activation
4.6 SOFTWARE RESET AND HARDWARE RESET
HOLD
4.6.1 Software Reset
The AT25EU0011A can be reset to the initial power-on state by a software reset sequence. This sequence must include two
consecutive commands: Enable Reset (66h) and Reset (99h). If the command sequence is accepted, the device takes approxi-
mately 300 μs (tRST) to reset. No command is accepted during the reset period.
4.6.2 Hardware Reset (HOLD pin)
The AT25EU0011A can also be configured to use the hardware RESET pin. The HOLD/RST bit in the Status Register-3 is the
configuration bit for the HOLD pin function or the RESET pin function. When HOLD/RST=0 (factory default), the pin acts as a
HOLD pin, as described above; when HOLD/RST=1, the pin acts as a RESET pin. Driving the RESET pin low for a minimum of
~1 μs (tRESET(1)) resets the device to its initial power-on state. Any on-going program/erase operation is interrupted, and data
corruption can happen. While RESET is low, the device does not accept any command input.
If QE bit is set to 1, the HOLD or RESET function is disabled, the pin becomes one of the four data I/O pins. (Note that when
writing to the Status Register, QE must be 0.)
Note: While a faster RESET pulse (as short as a few hundred nanoseconds) often resets the device, a 1 μs minimum pulse is
recommended to ensure reliable operation.
Datasheet
29-Jul-2021
Revision B
11
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
5
Status and Configuration Registers
5.1 STATUS REGISTER 1
The following table shows the bit assignments for Status Register 1.
Table 2: Status Register 1 Format
Bit #
Acronym
Name
Type
Default Description
The Status Register Protect 0 bit is a non-volatile bit that, along
Status
Register
Protect 0
with the SRP1 and WP bits, controls the method of write pro-
tection: software protection, hardware protection, power supply
lock-down, or one time programmable protection. See Table 5.
7
SRP0
R/W
0
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-
volatile. They define the size of the area to be software-protect-
ed against Program and Erase commands. These bits are writ-
ten with the Write Status Register command. When the Block
Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the rele-
vant memory (as defined in Table 6 and Table 7) becomes
protected against Page Program, Page Erase, and Block Erase
commands. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits
can be written provided that the Hardware Protected mode has
not been set. The Chip Erase command is executed if the Block
Protect (BP2, BP1, and BP0) bits are 0 and CMP=0, or the
Block Protect (BP2, BP1 and BP0) bits are 1 and CMP=1.
Note that on power-up the device is unprotected.
Block
Protect Size
6:2
BP4-BP0
R/W
0
The Write Enable Latch bit indicates the status of the internal
Write Enable Latch. When WEL is 1, the internal Write Enable
Latch is set, when WEL is 0, the internal Write Enable Latch is
reset, and no Write Status Register, Program or Erase com-
mand is accepted.
Write
Enable
1
0
WEL
R
R
n/a
n/a
The Ready/Busy (RDY/BSY) bit indicates whether the memory
is busy in with a program, erase, or write status register com-
mand. When RDY/BSY is set to 1, the device is busy, when the
RDY/BSY bit is cleared to 0, the device is not busy.
RDY/BSY Ready/Busy
Datasheet
29-Jul-2021
Revision B
12
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
5.2 STATUS REGISTER 2
The following table shows the bit assignments for Status Register 2.
Table 3: Status Register 2 Format
Bit #
Acronym
Name
Type
Default Description
The SUS bit is a read-only bit in Status Register 2 (S15) that is set
to 1 after executing a Program/Erase Suspend (75h) command.
The SUS bit is cleared to 0 by a Program/Erase Resume (7Ah)
command, Software Reset (66h/99h) command, Hardware reset,
or power-down, power-up cycle.
Suspend
Status
7
SUS
R
n/a
This a non-volatile read/write bit in the status register that is used
in conjunction with the BP4, BP3, BP2, BP1, and BP0 bits to pro-
vide more flexibility for the array protection. See the Table 5 for
details.
Complement
Protect
6
CMP
R/W
0
The LB bits are non-volatile One-Time Program (OTP) bits in the
Status Register (S13-S11) that provide the write protect control
and status to the Security Registers. The default state of LB is 0
(the security registers are unlocked). LB can be set to 1 individually
using the Write Register command. LB is One-Time Programma-
ble; once it is set to 1, the Security Registers becomes read-only
permanently (LB3-1 corresponds to S13-11).
Write-Protect
and Control
Status
5:3
LB3-LB1
R
0
2
1
Reserved
QE
--
n/a
n/a
n/a
0
Reserved.
This is a non-volatile read/write bit that allows Quad SPI operation.
When 0, the WP and HOLD pins are enabled. When set to 1, the
quad IO2 and IO3 pins are enabled. Never set the QE pin to 1
during standard SPI or dual SPI operation. if the WP and HOLD
pins are connected directly to the power supply or ground.
Quad Enable
The Status Register Protect 1 is a non-volatile Read/Write bit that,
along with the SRP0 and WP bits, controls the method of write
protection:softwareprotection, hardwareprotection, powersupply
lock-down, or one time programmable protection. See Table 5.
Status
Register
Protect 1
0
SRP1
R/W
0
5.3 STATUS REGISTER 3
The following table shows the bit assignments for Status Register 3.
Table 4: Status Register 3 Format
Bit #
Acronym
HOLD/RST
Reserved
Name
Type
R/W
n/a
Default Description
The HOLD or RESET pin function (HOLD/RST) bit is used to
specify whether the HOLD or RESET function must be imple-
mented on the hardware pin. When HOLD/RST=0 (factory de-
fault), the pin acts as HOLD; when HOLD/RST=1, the pin acts
as RESET. However, HOLD or RESET functions are only avail-
able when QE=0.
HOLD or
RESET
7
0
6:0
--
n/a
Reserved
Note that the default value is set by the manufacturer during wafer sort, marked as default in following text.
Datasheet
29-Jul-2021
Revision B
13
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
Table 5: Status Register Protect Table
SRP1
SRP0
WP
Status Register
Description
The Status Register can be written to after a Write Enable
command, WEL=1 (default).
0
0
X
Software Protected
WP=0, the Status Register is locked and cannot be written
to.
0
0
1
1
1
1
0
1
0
1
Hardware Protected
WP=1, the Status Register is unlocked and can be written
to after a Write Enable command, WEL=1.
Hardware Unprotected
Power Supply
Lock-Down 1
Status Register is protected and cannot be written to until
the next power-down, power-up cycle.
X
X
Status Register is permanently protected and cannot be
written to.
One-Time Program
1. When SRP1, SRP0= (1, 0), a power-down, power-up cycle changes SRP1, SRP0 to (0, 0) state.
2. The One-Time Program feature is available upon special order. Contact Dialog Semiconductor for details.
Datasheet
29-Jul-2021
Revision B
14
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
5.4 STATUS REGISTER MEMORY PROTECTION
5.4.1 Protection Tables
Table 6: AT25EU0011A Status Register Memory Protection (CMP = 0)
STATUS REGISTER 1
AT25EU0011A (1M-BIT) MEMORY PROTECTION 3
PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENSITY
PROTECTED
PORTION 2
BP4
BP3
BP2
BP1
BP0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
X
0
1
X
X
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
0
1
1
0
1
1
X
0
1
0
1
X
0
1
0
1
X
0
1
NONE
NONE
NONE
64 kB
64 kB
128 kB
NONE
4 kB
NONE
UPPER 1/2
LOWER 1/2
ALL
1
010000h – 01FFFFh
000000h – 00FFFFh
000000h – 01FFFFh
NONE
0
0
NONE
NONE
1
01F000h – 01FFFFh
01E000h – 01FFFFh
01C000h – 01FFFFh
018000h – 01FFFFh
018000h – 01FFFFh
000000h – 000FFFh
000000h – 001FFFh
000000h – 003FFFh
000000h – 007FFFh
000000h – 007FFFh
000000h – 01FFFFh
U - 1/32
U - 1/16
U - 1/8
U - 1/4
U - 1/4
L - 1/32
L - 1/16
L - 1/8
1
8 kB
1
16 kB
32 kB
32 kB
4 kB
1
1
0
0
8 kB
0
0
16 kB
32 kB
32 kB
128 kB
L - 1/4
0
L - 1/4
0 to 1
ALL
1. X = don’t care.
2. L = Lower; U = Upper.
3. If any Erase or Program command specifies a memory region that contains protected data portion, this command is ignored.
Datasheet
29-Jul-2021
Revision B
15
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
Table 7: AT25EU0011A Status Register Memory Protection (CMP = 1)
STATUS REGISTER 1
AT25EU0011A (1M-BIT) MEMORY PROTECTION 3
PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENISITY
PROTECTED
PORTION 2
BP4
BP3
BP2
BP1
BP0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
X
0
1
X
X
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
0
1
1
0
1
1
X
0
1
0
1
X
0
1
0
1
X
0
1
0 to 1
0
000000h – 01FFFFh
000000h – 00FFFFh
010000h – 01FFFFh
NONE
128 kB
64 kB
ALL
Lower 1/2
Upper 1/2
NONE
1
64 kB
NONE
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
NONE
NONE
128 kB
124 kB
120 kB
112 kB
96 kB
000000h – 01FFFFh
000000h – 01EFFFh
000000h – 01DFFFh
000000h – 01BFFFh
000000h – 017FFFh
000000h – 017FFFh
001000h – 01FFFFh
002000h – 01FFFFh
004000h – 01FFFFh
008000h – 01FFFFh
008000h – 01FFFFh
NONE
ALL
L - 31/32
L - 15/16
L - 7/8
L - 3/4
96 kB
L - 3/4
124 kB
120 kB
112 kB
96 kB
U - 31/32
U - 15/16
U - 7/8
U - 3/4
U - 3/4
NONE
96 kB
NONE
1. X = don’t care.
2. L = Lower; U = Upper.
3. If any Erase or Program command specifies a memory region that contains protected data portion, this command is ignored.
Datasheet
29-Jul-2021
Revision B
16
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6
Command Set
All commands, addresses, and data are transferred into and out of the device, beginning with the most significant bit on the first
rising edge of SCK after CS is driven low. Then, the one-byte opcode must be transferred into the device on SI, most significant
bit first, each bit being latched on a rising edge of SCK.
Every command sequence starts with a one-byte opcode. Depending on the command, this might be followed by address bytes.
See Table 8.
For the Read, Fast Read, Read Status Register-1, Read Status Register-2 or Release from Deep Power-Down, or Read Device
ID command, the transferred-in command sequence is followed by a data out sequence. CS can be driven high after any bit of
the data-out sequence is being transferred out.
For the Page Program, Page Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-
Down command, CS must be driven high exactly at a byte boundary; otherwise, the command is rejected. (CS must drive high
when the number of clock pulses after CS being driven low is an exact multiple of eight.) For Page Program, if at any time the
input byte is not a full byte, nothing happens, and WEL is not reset.
Table 8: Command Set Table 1
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n- Bytes
Command Name
READ
Normal Read Data
Fast Read
03h
0Bh
3Bh
6Bh
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
(D7-D0)
Dummy
Dummy
Dummy
(Next Byte) (continuous)
(D7-D0)
(D7-D0) 2
(D7-D0) 3
(continuous)
(continuous)
(continuous)
Dual Output Fast Read
Quad Output Fast Read
A7-A0
Dual I/O Fast Read
BBh
A23-A8 4
(D7-D0)
(continuous)
(continuous)
M7-M0 4
A23-A0
Quad I/O Fast Read
Set Burst with Wrap
EBh
77h
Dummy
(D7-D0) 6
M7-M0 5
W6-W4
Program/Erase and Suspend
Page Program
02h
A2h
32h
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
(D7-D0) 7
(D7-D0) 7
(D7-D0) 7
(D7-D0) 7
(D7-D0) 7
(Next Byte)
(Next Byte)
(Next Byte)
(Next Byte)
(Next Byte)
Dual Page Program
Quad Page Program
Page Erase
81h/DBh
20h
Block Erase (4 kB)
Block Erase (32 kB)
Block Erase (64 kB)
Chip Erase
52h
D8h
C7h/60h
75h
Program/Erase Suspend
Program/Erase Resume
Security
7Ah
Erase Security Registers
44h
42h
48h
5Ah
A23-A16 8
A23-A16 8
A23-A16 8
A23-A16
A15-A8 8
A15-A8 8
A15-A8 8
A15-A8
A7-A0 8
A7-A0 8
A7-A0 8
A7-A0
Program Security
Registers
D7-D0
Dummy
Dummy
Next Byte
D7-D0
Read Security Registers
Read Serial Flash
Discoverable Parameter
(D7-D0)
(continuous)
Datasheet
29-Jul-2021
Revision B
17
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
Table 8: Command Set Table 1 (Continued)
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n- Bytes
Command Name
Configuration
Write Enable
06h
50h
04h
Volatile SR Write Enable
Write Disable
Status Register
Read Status Register-1
Write Status Register 10
Read Status Register-2
Write Status Register-2
Read Status Register-3
Write Status Register-3
Active Status Interrupt
ID and Power
05h
01h
35h
31h
15h
11h
25h
(S7-S0) 9
S7-S0
(S15-S8) 9
(continuous)
(continuous)
(continuous)
S15-S8
S7-S0
(S15-S8) 9
S7-S0
Deep Power-down
Release Power-down / ID
Release Power-down
B9h
ABh
ABH
Dummy
Dummy
Dummy
Dummy
00/01h
ID7-ID0
(continuous)
(MF7-MF0)/ (ID7-ID0) 9/
(ID7-ID0) (MF7-MF0) 9
Manufacturer/Device ID
Mftr./Device ID Dual IO
Mftr./Device ID Quad IO
90h
92h
94h
Dummy
(continuous)
(continuous)
A7-A0 4
(M7-M0)
(M7-M0)
(D7-D0)
A23-A8 4
A23-A0
(M7-M0)
(continuous)
(continuous)
(M7-M0) 5
(D7-D0) 6
Read JEDEC ID
Read Unique ID Number
Other Commands
Enable Reset
9Fh
4Bh
(MF7-MF0) (ID15-ID8)
Dummy Dummy
(ID7-ID0) 9
Dummy
Dummy
(ID127-ID0)
66h
99h
Reset Device
1. Data bytes are transferred with Most Significant Bit first. Byte fields with data in parenthesis ( ) indicate data output from the device.
2. Dual SPI data output format:
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
3. Quad SPI data output format:
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
4. Dual SPI address input format:
IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3, M1
5. Quad SPI address input format:
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
6. Fast Read Quad I/O data output format:
IO0 = (x, x, x, x, D4, D0, D4, D0)
IO1 = (x, x, x, x, D5, D1, D5, D1)
IO2 = (x, x, x, x, D6, D2, D6, D2)
IO3 = (x, x, x, x, D7, D3, D7, D3)
Datasheet
29-Jul-2021
Revision B
18
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
7. At least one byte of data input is required for Page Program, Dual Page Program, Quad Page Program and Program Security Registers, up to 256 bytes
of data input. If more than 256 bytes of data are sent to the device, the addressing wraps to the beginning of the page and overwrites previously sent data.
8. Security Register Address:
Security Register1 A23-16 = 00h A15-9 = 0001000 A8-0 = byte address
Security Register2 A23-16 = 00h A15-9 = 0010000 A8-0 = byte address
Security Register3 A23-16 = 00h A15-9 = 0011000 A8-0 = byte address
9. The Status Register contents and Device ID repeat continuously until CS terminates the command.
10. Write Status Register (01h) can also be used to write Status Register-1 and 2, see Table 6.1.6.
6.1 CONFIGURATION AND STATUS COMMANDS
6.1.1 Write Enable (06h)
The Write Enable command sets the Write Enable Latch (WEL) bit in the Status Register to 1. The WEL bit must be set before
every Page Program, Page Erase, Block Erase, Chip Erase, Write Status Register, and Erase/Program Security Registers com-
mand. The Write Enable command is entered by driving CS low, transferring the opcode 06h into the Data Input (SI) pin on the
rising edge of SCK, and then driving CS high.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
SI
06h
High-Impedance
SO
Figure 5: Write Enable Command for SPI Mode
6.1.2 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in Section 5 can also be written to as volatile bits. This gives more flexibility to
change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write
cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile values into the Status Register bits,
the Write Enable for Volatile Status Register (50h) command must be issued before a Write Status Register (01h) command. The
Write Enable for Volatile Status Register command does not set the Write Enable Latch (WEL) bit; it is only valid for the Write
Status Register command to change the volatile Status Register bit values.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
SI
50h
High-Impedance
SO
Figure 6: Write Enable for Volatile Status Register (50h)
Datasheet
29-Jul-2021
Revision B
19
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.1.3 Write Disable (04h)
The Write Disable command resets the Write Enable Latch (WEL) bit in the Status Register to 0. The Write Disable command is
entered by driving CS low, transferring the opcode 04h onto the SI pin, and then driving CS high. Note that the WEL bit is
automatically reset after power-up and upon completion of the Write Status Register, Erase/Program Security Registers, Page
Program, Page Erase, Block Erase, Chip Erase, and Reset command.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
&RPPDQGꢁꢂꢃꢄKꢀ
SI(IO๚ꢀ
High-Impedance
SO(IO๛ꢀ
Figure 7: Write Disable Command, SPI Mode
6.1.4 Read Status Register-1 (05h), Status Register-2 (35h), Status Register-3 (15h)
The Read Status Register commands allow the eight-bit Status Registers to be read. The command is entered by driving CS low
and transferring the opcode 05h for Status Register-1, 35h for Status Register-2, 15h for Status Register-3 onto the SI pin on the
rising edge of SCK. The status register bits are then transferred out on the SO pin at the falling edge of SCK, with most significant
bit (MSB) first, as shown in Figure 8. See Section 5 for Status Register descriptions. The Read Status Register command can be
used at any time, even while a Program, Erase or Write Status Register cycle is in progress. This allows the RDY/BSY status bit
to be checked to determine when the cycle is complete and if the device can accept another command. The Status Register can
be read continuously, as shown in Figure 8. The command is completed by driving CS high.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Mode 3
Mode 0
SCK
SI
Command
05h or 35h or 15h
Register 1/2/3
Register 1/2/3
High-Impedance
SO
7
MSB
6
5
4
3
2
1
0
7
MSB
6
5
4
3
2
1
0
Figure 8: Read Status Register Command
Datasheet
29-Jul-2021
Revision B
20
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.1.5 Active Status Interrupt (25h)
The Active Status Interrupt improves the ability to determine if the device is busy or not. It is not necessary to continuously read
the Status Register; it is sufficient to monitor the value of the SO line. If the SO line is connected to an interrupt line on the host
controller, the host controller can be in sleep mode until the SO line indicates that the device is ready for the next command. The
RDY/BSY bit can be read at any time, including during an internally self-timed program or erase operation. To enable the Active
Status Interrupt command, the CS pin must first be asserted, and the opcode of 25h must be clocked into the device. The value
of the SI line after the opcode being clocked in is of no significance to the operation. The value of RDY/BSY is then output on the
SO line, and is continuously updated by the device for as long as the CS pin remains asserted. Additional clocks on the SCK pin
are not required. That is, whether the additional clock on the SCK pin exists is independent of the correct output of the value of
RDY/BSY. (Figure 9 shows a case where additional clocks exist.) If the RDY/BSY bit changes from 1 to 0 while the CS pin is
asserted, the SO line changes from 1 to 0. (The RDY/BSY bit cannot change from 0 to 1 during an operation; so, if the SO line
already is 0, it does not change.) Deasserting the CS pin terminates the Active Status Interrupt operation and puts the SO pin into
a high-impedance state. The sequence of issuing the ASI command is: CS goes low → sending ASI opcode → RDY/BSY data
out on SO.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
SCK
Command
25h
SI
High-Impedance
SO
RDY/BSY
Figure 9: Active Status Interrupt Command
6.1.6 Write Status Register (01h or 31h or 11h)
The Write Status Register command allows the Status Registers to be written. Status Register-1 can be written by the Write Status
Register 01h command; Status Register-2 be written by the Write Status Register 01h or 31h command; Status Register-3 can
be written by the Write Status Register 11h command. When the Write Status Register command 01h writes one byte data, it is
written to Status Register-1. When the Write Status Register command 01h writes two bytes of data, the first byte data is written
to Status Register-1, and the second byte data is written to Status Register-2. Commands 31h or 11h are used with one byte only
(any additional ones are ignored), which is written to the corresponding Status Register: command 31h writes the byte to Status
Register 2; command 11h writes the byte to Status Register 3. The writable Status Register bits include: SRP0, BP[4:0] in Status
Register-1; CMP, LB[3:1], QE, and SRP1 in Status Register- 2; HOLD/RST in Status Register- 3. All other Status Register bit
locations are read-only and are not affected by the Write Status Register command. LB[3:1] are non-volatile OTP bits; once set
to 1, they cannot be cleared to 0.
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted,
a Write Enable (WREN) or Write Enable For Volatile SR command must previously have been executed After the Write Enable
(WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register command has no effect on S15 (SUS), S1 (WEL), and S0 (RDY/BSY) of the Status Register. CS must
be driven high after the 8 or 16 bits of data have been latched in. If not, the Write Status Register (WRSR) command is not
executed. As soon as CS is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the
Write Status Register cycle is in progress, the Status Register can still be read to check the value of the Write In Progress (RDY/
BSY) bit. The RDY/BSY bit is 1 during the self-timed Write Status Register cycle; it is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
The Write Status Register command lets the user change the values of the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits,
to define the size of the area that is to be treated as read-only, as defined in Table 6 and Table 7. The Write Status Register
(WRSR) command also lets the user set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write
Datasheet
29-Jul-2021
Revision B
21
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
Protect (WP) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP) signal allow the device to be put
in the Hardware Protected Mode. The Write Status Register command is not executed once the Hardware Protected Mode is
entered.
The sequence of issuing WRSR command is: CS goes low → sending WRSR opcode → Status Register data on SI → CS goes
high.
The CS must go high exactly at the 8-bit or 16-bit data boundary; otherwise, the command is rejected. The self-timed Write Status
Register cycle time (tW) is initiated as soon as CS goes high. The Ready/Busy (RDY/BSY) bit can be checked during the Write
Status Register cycle is in progress. The RDY/BSY is set 1 during the tW timing, and is set to 0 when the Write Status Register
Cycle is completed and the Write Enable Latch (WEL) bit is reset.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode 3
Mode 0
SCK
Command
01h
Status Register-1 in
2
Status Register-2 in
SI
1
0
7
6
5
4
3
15 14 13 12 11 10
9
8
MSB
MSB
High-Impedance
SO
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SR1/SR2/SR3 in
Mode 3
Mode 0
SCK
Command
01h/31h/11h
High-Impedance
SI
2
1
0
7
6
5
4
3
MSB
SO
Figure 10: Write Status Register Command
Datasheet
29-Jul-2021
Revision B
22
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.2 READ COMMANDS
6.2.1 Normal Read Data (03h)
The Read Data command allows one or more data bytes to be sequentially read from the memory. The command is initiated by
driving the CS pin low, then transferring the opcode 03h, followed by a 24-bit address (A23-A0), onto the SI pin. The code and
address bits are latched on the rising edge of the SCK pin. After the address is received, the data byte of the addressed memory
location is transferred out on the SO pin at the falling edge of SCK, with most significant bit (MSB) first. The address is automat-
ically incremented to the next higher address after each byte of data is transferred out, allowing for a continuous stream of data.
This means that the entire memory can be accessed with a single command as long as the clock continues. The command is
completed by driving CS high. The Read Data command sequence is shown in Figure 11. If a Read Data command is issued
while an Erase, Program, or other Write cycle is in progress (RDY/BSY=1), the command is ignored and has no effect on the
current cycle. The Read Data command allows a clock frequency up to a maximum of fR (see Section 7.6, AC Characteristics).
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCK
Command
03h
24-Bit Address
23 22 21
MSB
3
2
1
0
SI
Data Byte 1
HIGH-IMP.
High-Impedance
7
6
5
4
3
2
1
0
SO
Figure 11: Read Data Command
Datasheet
29-Jul-2021
Revision B
23
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.2.2 Fast Read (0Bh)
The Fast Read command is similar to the Read Data command except that it can operate at the highest possible frequency of fC
(see Section 7.6, AC Characteristics). In standard SPI mode, this is done by adding eight dummy clocks after the 24-bit address,
as shown in Figure 12. The dummy clocks allow the devices internal circuits additional time for setting up the initial address.
During the dummy clocks the data value on the SO pin is a don’t care.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCK
Command
0Bh
24-Bit Address
23 22 21
3
2
1
0
SI
High-Impedance
SO
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
Dummy Clocks
Data Out
High-Impedance
7
6
5
4
3
2
1
0
SO
Figure 12: Fast Read Command
Datasheet
29-Jul-2021
Revision B
24
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.2.3 Fast Read Dual Output (3Bh)
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially read a
continuous stream of data from the device by providing the clock pin once the initial starting address has been specified. Unlike
the standard Read Array command, the Dual-Output Read Array command allows two bits of data to be clocked out of the device
on every clock cycle, rather than just one.
To perform the Dual-Output Read Array operation, the CS pin must first be asserted; then, the opcode 3Bh must be clocked into
the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first
byte to read within the memory array. Following the three address bytes, a single dummy byte also must be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles output data on both the SO and
SI pins. The data is output with the MSB of a byte first, and the MSB is output on the SO pin. During the first clock cycle, bit seven
of the first data byte is output on the SO pin, while bit six of the same data byte is output on the SI pin. During the next clock cycle,
bits five and four of the first data byte are output on the SO and SI pins, respectively. The sequence continues with each byte of
data being output after every four clock cycles. When the last byte (0FFFFFh) of the memory array has been read, the device
continues reading from the beginning of the array (000000h). There are no delays when wrapping around from the end of the
array to the beginning of the array. Deasserting the CS pin terminates the read operation and puts the SO and SI pins into a high-
impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.
CS
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCK
SI
Command
3Bh
24-Bit Address
23 22 21
3
2
1
0
High-Impedance
SO
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Dummy Clocks
6
7
4
2
0
6
7
4
2
0
SI
Data Byte 1
Data Byte 2
High-Impedance
5
3
1
5
3
1
SO
Figure 13: Fast Read Dual Output Command
Datasheet
29-Jul-2021
Revision B
25
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.2.4 Fast Read Dual I/O (BBh)
The Dual-I/O Fast Read Array command is similar to the Dual-Output Read Array command and can be used to sequentially read
a continuous stream of data from the device by providing the clock pin once the initial starting address with two bits of address
on each clock and two bits of data on every clock cycle.
To perform the Dual-I/O Fast Read Array operation, the CS pin must first be asserted; then, the opcode BBh must be clocked into
the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first
byte to read within the memory array. Following the three address bytes, a single mode byte also must be clocked into the device.
After the three address bytes and the mode byte have been clocked in, additional clock cycles output data on both the SO and
SI pins. The data is always output with the MSB of a byte first, and the MSB is always output on the SO pin. During the first clock
cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same data byte is output on the SI pin. During the
next clock cycle, bits five and four of the first data byte are output on the SO and SI pins, respectively. The sequence continues
with each byte of data output after every four clock cycles. When the last byte (0FFFFFh) of the memory array has been read,
the device continues reading from the beginning of the array (000000h). No delays are incurred when wrapping around from the
end of the array to the beginning of the array. Deasserting the CS pin terminates the read operation and puts the SO and SI pins
into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Command
BBh
A23-16
A15-8
A7-0
M7-0
SI
6
4
2
0
1
6
4
2
0
1
6
4
2
0
1
6
4
2
0
1
(IO๚)
High-Impedance
SO
7
MSB
5
3
7
MSB
5
3
7
MSB
5
3
7
MSB
5
3
(IO๛)
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Mode 3
Mode 0
SCK
I/Os switch from
Input to Output
High-Impedance
High-Impedance
6
4
2
0
1
6
4
2
0
1
6
4
2
0
1
6
4
2
0
1
SI
(IO๚)
Byte 1
Byte 2
Byte 3
Byte 4
SO
7
5
3
7
5
3
7
5
3
7
5
3
(IO๛)
MSB
MSB
MSB
MSB
Figure 14: Fast Read Dual I/O Command (Initial command or previous M5-4≠10)
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O command can further reduce command overhead through setting the Continuous Read Mode bits (M7-
0) after the input Address bits (A23-0), as shown in Figure 7-5. The upper nibble of M7-4 controls the length of the next Fast Read
Dual I/O command through the inclusion, or exclusion, of the first byte command code. The lower nibble bits of M3-0 are don't
care (“x”). However, the I/O pins must be high-impedance prior to the falling edge of the first data out clock. If the “Continuous
Read Mode” bits M5-4 = (1,0), the next Fast Read Dual I/O command (after CS is raised and then lowered) does not require the
BBh command code. This reduces the command sequence by eight clocks and allows the Read address to be immediately
entered after CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next command (after CS is
raised and then lowered) requires the first byte command code, thus returning to normal operation. A Continuous Read Mode
Reset command can also be used to reset M7-0 before issuing normal commands.
Datasheet
29-Jul-2021
Revision B
26
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
A23-16
A15-8
A7-0
M7-0
SI(IO0)
22 20 18 16 14 12 10
8
6
4
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
23 21 19 17 15 13 11
MSB
9
7
MSB
5
CS
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
IOs switch from
Input to Output
SI(IO0)
0
1
6
4
2
3
0
1
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
7
SO(IO1)
7
MSB
5
7
MSB
7
MSB
7
MSB
Byte 1
Byte 2
Byte 3
Byte 4
Figure 15: Fast Read Dual I/O Command (Previous command M5-4=10)
Datasheet
29-Jul-2021
Revision B
27
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.2.5 Fast Read Quad Output (6Bh)
The Quad-Output Fast Read Array command is followed by a three-byte address (A23 - A0) and one dummy byte, each bit being
latched in during the rising edge of SCK; then, the memory contents are shifted out four bits per clock cycle from I/O3, I/O2, I/O1,
and I/O0. The first byte addressed can be at any location. The address automatically increments to the next higher address after
each byte of data is shifted out.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCK
Command (6Bh)
24-Bit Address
IO๚
23 22 21
MSB
3
2
1
0
High-Impedance
High-Impedance
IO๛
IO
IO
High-Impedance
CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
IO0 switches from
Dummy Clocks
Input to Output
IO๚
IO๛
0
4
5
0
1
4
5
0
1
4
5
0
1
4
5
0
1
4
5
High-Impedance
High-Impedance
High-Impedance
IO
IO
6
7
2
3
6
7
2
3
6
7
2
3
6
7
2
3
6
7
Byte 1 Byte 2
Byte 3
Byte 4
Figure 16: Fast Read Quad Output Command
Datasheet
29-Jul-2021
Revision B
28
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.2.6 Fast Read Quad I/O (EBh)
The Quad-I/O Fast Read Array command is similar to the Quad-Output Fast Read Array command. It allows four bits of address
to be clocked into the device on every clock cycle, rather than just one.
To perform the Quad-I/O Read Array operation, the CS pin must first be asserted; then, the opcode EBh must be clocked into the
device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte
to read within the memory array. Following the three address bytes, a single mode byte must also be clocked into the device.
After the three address bytes, the mode byte and two dummy bytes have been clocked in, additional clock cycles output data on
the I/O3-0 pins. The data is output with the MSB of a byte first, and the MSB is output on the I/O3 pin. During the first clock cycle,
bit 7 of the first data byte is output on the I/O3 pin while bits 6, 5, and 4 of the same data byte are output on the I/O2, I/O1, and
I/O0 pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the first data byte are output on the I/O3, I/O2, I/O1, and
I/O0 pins, respectively. The sequence continues with each byte of data being output after every two clock cycles.
When the last byte (0FFFFFh) of the memory array has been read, the device continues reading from the beginning of the array
(000000h). No delays are incurred when wrapping around from the end of the array to the beginning of the array. Deasserting the
CS pin terminates the read operation and puts the I/O3, I/O2, I/O1, and I/O0 pins into a high-impedance state. The CS pin can
be deasserted at any time and does not require a full byte of data to be read. The Quad Enable bit (QE) of the Status Register
must be set to enable for the Quad-I/O Read Array command.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A15-8 A7-0 M7-0
SCK
Command
A23-16
SI
4
5
6
0
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
EBh
(IO๚)
High-Impedance
High-Impedance
High-Impedance
SO
1
2
3
5
6
7
5
6
7
5
6
(IO๛)
WP
(IO)
7
MSB
7
MSB
HOLD
(IO)
CS
16 17 18 19 20 21 22 23 24 25 26 27
SCK
Data Out 1 Data Out 2 Data Out 3 Data Out 4
Dummy
Clocks
SI
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
(IO๚)
SO
(IO๛)
WP
(IO)
7
7
7
7
HOLD
MSB
MSB
MSB
MSB
(IO)
Figure 17: Fast Read Quad I/O Command (Initial command or previous M5-4≠10)
Quad-I/O Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O command can further reduce command overhead through setting the Continuous Read Mode bits (M7-
0) after the input Address bits (A23-0), as shown in Figure 17. The upper nibble (M7-4) of the Continuous Read Mode bits controls
the length of the next Fast Read Quad I/O command through the inclusion, or exclusion, of the first byte command code. The
lower nibble bits (M3-0) of the Continuous Read Mode bits are don't care. However, the IO pins must be high-impedance before
the falling edge of the first data out clock. If the Continuous Read Mode bits M5-4 = (1,0), the next Quad-I/O Read Array command
(after CS is raised and then lowered) does not require the EBh command code, as shown in Figure 18. This reduces the command
sequence by eight clocks and allows the Read address to be immediately entered after CS is asserted low. If the Continuous
Read Mode bits M5-4 do not equal to (1,0), the next command (after CS is raised and then lowered) requires the first byte
Datasheet
29-Jul-2021
Revision B
29
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
command code, thus returning to normal operation. A Continuous Read Mode Reset command can also be used to reset M7-0
before issuing normal commands.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Byte 1 Byte 2
SCK
A23-16
A15-8
A7-0
M7-0
Dummy
SI
4
5
6
7
0
4
0
4
0
4
0
4
0
1
2
3
4
0
1
2
3
(IO๚)
SO
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
5
6
7
(IO๛)
WP
(IO)
HOLD
(IO)
Figure 18: Fast Read Quad I/O Command (Previous command set M5-4=10)
Datasheet
29-Jul-2021
Revision B
30
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.2.7 Set Burst with Wrap (77h)
The Set Burst with Wrap command is used in conjunction with the Quad I/O Fast Read and Quad I/O Word Fast Read command
to access a fixed length (8-, 16-, 32-, or 64-byte) section within a 256-byte page in standard SPI mode (see Table 9 and Figure 19).
Table 9: Wrap Around Length Based on Wrap Bits
W6
0
W5
0
W4 = 0
W4 = 1 (default)
Wrap Around
Wrap Length
8-byte
Wrap Around
Wrap Length
0
1
Yes
Yes
Yes
Yes
No
No
No
No
N/A
N/A
N/A
N/A
0
1
16-byte
1
0
32-byte
1
1
64-byte
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Mode 3
Mode 0
Mode 3
Mode 0
SCK
Command
Byte 1
Byte 2
Byte 3
Byte 4
High-Impedance
High-Impedance
High-Impedance
High-Impedance
SI
X
X
X
X
X
X
X
X
X
X
X
X
W4
X
X
X
X
77h
(IO๚)
High-Impedance
High-Impedance
High-Impedance
SO
X
X
X
X
X
X
X
X
X
X
X
W5
W6
X
(IO๛)
WP
(IO)
X
MSB
HOLD
(IO)
Figure 19: Set Burst with Wrap Command
The Set Burst with Wrap command sequence is: CS goes low → Send Set Burst with Wrap command → Send 24 Dummy bits
→ Send 8 “Wrap bits” → CS goes high.
If W6-4 is set by a Set Burst with Wrap command, all the following “Fast Read Quad I/O” and “Word Read Quad I/O” commands
use the W6-4 setting to access the 8-, 16-, 32-, or 64-byte section within any page. To exit the “Wrap Around” function and return
to normal read operation, issue another Set Burst with Wrap command to set W4=1. The default value of W4 at power-on is 1.
6.3 ID AND POWER COMMANDS
Three commands (9Fh/90h/ABh) are supported to access device identification that can indicate the manufacturer, device type,
and capacity (density). The returned data bytes provide the information, as shown in Table 10.
Table 10: AT25EU0011A ID Definition Table
Command
Opcode
Mfg ID (Byte #1)
Device ID (Byte #2)
Device ID (Byte #3)
Read Manufacturing and Device ID
Read ID (Legacy Command)
Read ID (Dual I/O)
9Fh
90h
92h
94h
1Fh
1Fh
1Fh
1Fh
11h
01h
11h
11h
11h
Read ID (Quad I/O)
Resume from Deep Power-Down
and Read Device ID
ABh
11h
Datasheet
29-Jul-2021
Revision B
31
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.3.1 Release Power-down / Device ID (ABh)
The Release from Power-down / Device ID command is a multi-purpose command. It can be used to release the device from the
power-down state, or obtain the devices electronic identification (ID) number.
To release the device from the power- down state, the command is issued by driving the CS pin low, transferring the opcode ABh
and driving CS high, as shown in Figure 20. Release from power-down takes the time of tRES1 (see Section 7.6, AC Character-
istics) before the device resumes normal operation and other commands are accepted. The CS pin must remain high during the
tRES1 time.
When used only to obtain the Device ID while not in the power-down state, the command is initiated by driving the CS pin low
and transferring the opcode ABh, followed by three dummy bytes. The Device ID bits are then transferred out on the falling edge
of SCK, with the most significant bit (MSB) first. The Device ID value for the AT25EU0011A is listed in Manufacturer and Device
Identification table. The Device ID can be read continuously. The command is completed by driving CS high.
When used to release the device from the power-down state and obtain the Device ID, the command is the same as previously
described and shown in Figure 21, except that after CS is driven high it must remain high for a time of tRES2 (see Section 7.6, AC
Characteristics). After this time, the device resumes normal operation, and other commands are accepted. If the Release from
Power- down / Device ID command is issued while an Erase, Program, or Write cycle is in process (when RDY/BSY = 1) the
command is ignored and has no effect on the current cycle.
CS
tRES1
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
SI
Command
ABh
Power-down mode
Stand-by mode
Figure 20: Release Power-Down Command
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
Mode 3
Mode 0
SCK
tRES2
Command
ABh
3 Dummy Bytes
23 22 21
MSB
3
2
1
0
SI
Device ID
High-Impedance
7
6
5
4
3
2
1
0
SO
Stand-by mode
Deep Power-down mode
Figure 21: Release Power-Down / Device ID Command
Datasheet
29-Jul-2021
Revision B
32
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.3.2 Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-down / Device ID command that
provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer / Device ID command can operate at the highest possible frequency of fC (see Section 7.6, AC Charac-
teristics). The command is initiated by driving the CS pin low and transferring the opcode 90h followed by a 24-bit address (A23-
A0). After this, the Manufacturer ID for Dialog Semiconductor (1Fh) and the Device ID are transferred out on the falling edge of
SCK, with most significant bit (MSB) first, as shown in Section 22, Read Manufacturer / Device ID Command. The Device ID
values for the AT25EU0011A are listed in Manufacturer and Device Identification table. The address A23-A1 is an unrelated item
and has no effect on the result of the command. If the A0 is initially set to 1, the Device ID is read first and then followed by the
Manufacturer ID. If the A0 is initially set to 0 the Manufacturer ID is read first and then followed by the Device ID. The Manufacturer
and Device IDs can be read continuously, alternating from one to the other. The command is completed by driving CS high.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCK
Command
90h
24-Bit Address
23 22 21
3
2
1
0
SI
High-Impedance
SO
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Mode 3
Mode 0
SCK
SI
Manufacturer ID
Device ID
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Figure 22: Read Manufacturer / Device ID Command
Datasheet
29-Jul-2021
Revision B
33
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.3.3 Dual I/O Read Manufacture ID/ Device ID (92h)
The Dual I/O Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device ID instruction
that provides both the JEDEC-assigned Manufacturer ID and the specific Device ID by Dual I/O.
The instruction is initiated by driving the CS pin low and shifting the instruction code 92h, followed by a 24-bit address (A23 - A0)
of 000000h. If the 24-bit address is initially set to 000001h, the Device ID is read first.
CS
0
2
4
5
6
7
12
15
21
1
3
8
9
10 11
13 14
16 17 18 19 20
22 23
SCK
Command
92h
SI
4
2
0
6
4
2
3
0
1
6
0
6
2
2
0
4
4
5
6
(IO0)
High-Impedance
SO
(IO1)
7
5
7
3
1
7
5
3
1
7
5
1
3
A23-16
A15-8
A7-0
Dummy
CS
23 24 25 26
28 29 30 31 32
39
42 43 44 45 46 47
27
40 41
SCK
SI
High-Impedance
High-Impedance
6
7
2
6
7
0
4
5
2
4
5
6
7
4
5
0
6
7
2
3
4
5
0
1
(IO0)
2
0
1
MFR and Device ID
(repeat)
SO
( IO1)
1
3
3
3
1
MFR ID (repeat)
Device ID (repeat)
MFR ID
Device ID
Figure 23: Dual I/O Read Manufacture ID/ Device ID Timing
Datasheet
29-Jul-2021
Revision B
34
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.3.4 Quad I/O Read Manufacture ID / Device ID (94h)
The Quad I/O Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device ID instruction
that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O.
The instruction is initiated by driving the CS pin low and shifting the instruction code 94h, followed by a 24-bit address (A23 - A0)
of 000000h and four dummy clocks. If the 24-bit address is initially set to 000001h, the Device ID is read out first.
CS
0
2
4
5
6
7
12
4
15
21
0
1
3
8
9
10 11
13 14
16 17 18
20
4
19
22 23
SCK
Command
94h
SI
0
4
0
4
0
0
4
4
0
(IO0)
High-Impedance
High-Impedance
SO
5
6
5
6
1
2
5
6
1
2
1
2
1
2
5
6
1
2
5
6
1
2
5
6
(IO1)
WP
(IO2)
High-Impedance
HOLD
(IO3)
7
7
3
7
3
3
3
7
3
7
3
7
Device ID
MFR ID
dummy
A7-0
A15-8
dummy
A23-16
CS
23 24 25 26
28 29 30 31
27
SCK
SI
4
0
0
4
4
4
0
0
(IO0)
SO
5
6
1
1
2
5
6
1
2
5
6
1
2
5
6
(IO1)
2
WP
(IO2)
7
3
3
7
3
7
3
7
HOLD
(IO3)
MFR ID DID ID MFR ID DID ID
(repeat) (repeat)(repeat) (repeat)
Figure 24: Quad I/O Read Manufacture ID / Device ID Sequence Diagram
Datasheet
29-Jul-2021
Revision B
35
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.3.5 Read JEDEC ID (9Fh)
The Read JEDEC ID command can operate at the highest possible frequency of fC (see Section 7.6, AC Characteristics). For
compatibility reasons, the AT25EU0011A provides several commands to electronically determine the identity of the device. The
Read JEDEC ID command is compatible with the JEDEC standard for SPI-compatible serial memories that was adopted in 2003.
The command is initiated by driving the CS pin low and transferring the opcode 9Fh. The JEDEC assigned Manufacturer ID byte
for Dialog Semiconductor (1Fh) and two Device ID bytes are then transferred out on the falling edge of SCK, with the most
significant bit (MSB) first (see Figure 25). For memory type and capacity values, see Table 10.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
Command
9Fh
SI
(IO๚)
Manufacturer ID
1Fh
High-Impedance
SO
(IO๛)
CS
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Mode 3
Mode 0
SCK
SI
(IO๚)
Device ID 15-8
Device ID 7-0
SO
2
1
0
2
1
0
7
6
5
4
3
7
6
5
4
3
(IO๛)
MSB
MSB
Figure 25: Read JEDEC ID Command
Datasheet
29-Jul-2021
Revision B
36
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.3.6 Read Unique ID Number (4Bh)
The Read Unique ID Number command can operate at the highest possible frequency of fC (see Section 7.6, AC Characteris-
tics).The Read Unique ID Number command accesses a factory-set, read-only, 128-bit number that is unique to each AT25EU-
0011A device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a
system. The Read Unique ID command is initiated by driving the CS pin low and transferring the opcode 4Bh, followed by a four
bytes of dummy clocks. After this, the 128-bit ID is transferred out on the falling edge of SCK, as shown in Figure 26.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
Command
4Bh
Data Byte 1
Data Byte 2
High-Impedance
SO
CS
Mode 3
Mode 0
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
172 173 174 175
Mode 3
Mode 0
SCK
Data Byte 3
Data Byte 4
SI
High-Impedance
SO
2
1
0
127 126
MSB
128-bit Unique
Serial Number
Figure 26: Read Unique ID Sequence Diagram
Datasheet
29-Jul-2021
Revision B
37
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.3.7 Deep Power-Down (B9h)
Although the standby current during normal operation is relatively low, it can be reduced further with the Power-down command.
The lower power consumption makes the Power-down command especially useful for battery-powered applications (see ICC1
and ICC2 in Section 7.4, DC Characteristics). The command is initiated by driving the CS pin low and transferring the opcode
B9h, as shown in Figure 27. The CS pin must be driven high after the eighth bit has been latched. If this is not done, the Power-
down command is not executed. After CS is driven high, the power-down state is entered within the time of tDP (see Section 7.6,
AC Characteristics). While in the power-down state, only the Release Power-down / Device ID (ABh) command, which restores
the device to normal operation, is recognized. All other commands are ignored. This includes the Read Status Register command,
which is always available during normal operation. Ignoring all but one command makes the power-down state a useful condition
for securing maximum write-protection. The device always powers-up in the normal operation with the standby current of ICC1
CS
t
DP
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 3
Mode 0
SCK
SI
Command
B9h
Stand-by mode
Power-down mode
Figure 27: Deep Power-Down Command
Datasheet
29-Jul-2021
Revision B
38
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.4 PROGRAM / ERASE AND SECURITY COMMANDS
6.4.1 Page Program (02h)
The Page Program command allows from one to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory
locations. AWrite Enable command must be executed before the device can accept the Page Program command (Status Register
bit WEL= 1). The command is initiated by driving the CS pin low then transferring the opcode 02h, followed by a 24-bit address
(A23-A0) and at least one data byte, onto the SI pin. The CS pin must be held low for the entire length of the command while data
is being sent to the device. The Page Program command sequence is shown in Figure 28. If more than 256 bytes are sent to the
device, previously latched data are discarded, and the last 256 data bytes are guaranteed to be programmed correctly within the
same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without
having any effects on the other bytes of the same page. CS must be driven high after the eighth bit of the last data byte has been
latched in; otherwise, the Page Program command is not executed. As with the write and erase commands, the CS pin must be
driven high after the eighth bit of the last byte has been latched. If this is not done, the Page Program command is not executed.
After CS is driven high, the self-timed Page Program command commences for a time of tPP (see Section 7.6, AC Characteristics).
While the Page Program cycle is in progress, the Read Status Register command can be accessed for checking the status of the
RDY/BSY bit. The RDY/BSY bit is a 1 during the Page Program cycle; it becomes a 0 when the cycle is finished and the device
is ready to accept other commands. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0. The Page Program command is not executed if the addressed page is protected by the Block Protect
(BP4, BP3, BP2, BP1, and BP0) bits.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCK
&RPPDQGꢁꢂꢃꢅKꢀ
24-Bit Address
Data Byte 1
SI(IO๚ꢀ
23 22 21
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
CS
Mode 3
Mode 0
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK
Data Byte 2
Data Byte 3
Data Byte 256
SI(IO๚ꢀ
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
Figure 28: Page Program Command
Datasheet
29-Jul-2021
Revision B
39
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.4.2 Dual Page Program (A2h)
This command allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using the SI SO
pins. The Dual Page Program can improve performance for PROM Programmer and applications that have slow clock speeds
<5MHz. Systems with faster clock speed do not realize much benefit from this command since the inherent page program time
is much longer than the time it takes to clock in the data.
A Write Enable command must be executed before the device can accept the Dual Page Program command (Status Register 1,
WEL=1). The command is initiated by driving the /CS pin low, then shifting the opcode A2h, followed by a 24-bit address (A23-
A0) and at least one data byte, into the IO pins. The /CS pin must be held low for the entire length of the command while data is
being sent to the device. All other functions of Dual input Page Program are identical to standard Page Program. The Dual Page
Program instruction sequence is shown in Figure 29.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39
SCK
SI (IOO)
SO (IO1)
Input
Input
Input
Opcode
Address Bits A23-A0
Data Byte 1
Data Byte 2
Data Byte n
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
1
MSB
0
1
0
0
0
1
0
A
MSB
A
A
A
A
A
A
A
A
6
4
2
0
1
6
4
2
0
1
6
4
2
0
1
High-Impedance
D
D
D
D
D
D
D
D
D
7
5
3
7
5
3
7
5
3
MSB
MSB
MSB
Figure 29: Dual Page Program Command
Datasheet
29-Jul-2021
Revision B
40
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.4.3 Quad Page Program (32h)
The Quad Page Program command allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations
using the SI, SO, WP, and HOLD pins. The Quad Page Program can improve performance for PROM Programmer and applica-
tions that have slow clock speeds <5 MHz. Systems with faster clock speed do not realize much benefit for the Quad Page
Program command since the inherent page program time is much longer than the time it take to clock-in the data.
To use Quad Page Program, the Quad Enable (QE) bit in Status Register-2 must be set to 1. A Write Enable command must be
executed before the device can accept the Quad Page Program command (Status Register-1, WEL=1). The command is initiated
by driving the CS pin low, then shifting the opcode 32h, followed by a 24-bit address (A23-A0) and at least one data byte, into the
IO pins. TheCS pin must be held low for the entire length of the command while data is being sent to the device. All other functions
of Quad Page Program are identical to standard Page Program. The Quad Page Program command sequence is shown in Figure
30.
CS
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
Mode 3
Mode 0
SCK
Command
32h
24-Bit Address
IO๚
IO๛
23 22 21
3
2
1
0
MSB
IO
IO
CS
31 32 33 34 35 36 37
Mode 3
Mode 0
SCK
Byte 1 Byte 2 Byte 3
Byte 253 Byte 254 Byte 255 Byte 256
IO๚
0
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
IO๛
IO
IO
7
7
7
7
7
7
7
MSB
MSB
MSB
MSB
MSB
MSB
MSB
Figure 30: Quad Input Page Program Command
Datasheet
29-Jul-2021
Revision B
41
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.4.4 Page Erase (81h/DBh)
The Page Erase (PE) command erases the data of the chosen Page to be logical 1. A Write Enable (WREN) command must
execute to set the Write Enable Latch (WEL) bit before sending the Page Erase (PE). To perform a Page Erase with the standard
page size (256 bytes), clock the opcode 81h or DBh into the device, followed by three address bytes comprised of two page
address bytes that specify the page in the main memory to be erased. The address A7-A0 is an unrelated item.
The sequence of issuing PE command is: CS goes low → sending PE opcode → three-byte address on SI → CS goes high.
CS
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCK
SI
Command
81h/DBh
24-Bit Address
23 22 21
3
2
1
0
MSB
Figure 31: Page Erase Command
6.4.5 4 kB Block Erase (20h)
This command sets all memory within a specified block (4 kB) to the erased state of all 1s (FFh). A Write Enable command must
be executed before the device can accept the 4 kB Block Erase command (Status Register bit WEL must equal 1). The command
is initiated by driving the CS pin low and transferring the opcode 20h, followed a 24-bit block address. The address A11-A0 is an
unrelated item and has no effect on the result of the command. The 4 kB Block Erase command sequence is shown in Figure 32.
The CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done, the 4 kB Block Erase
command is not executed. After CS is driven high, the self-timed 4 kB Block Erase command commences for a time of tSE (see
Section 7.6, AC Characteristics). While the Block Erase cycle is in progress, the Read Status command can still be accessed for
checking the status of the RDY/BSY bit. The RDY/BSY bit is a 1 during the Block Erase cycle; it becomes a 0 when the cycle is
finished and the device is ready to accept other commands. After the Block Erase cycle has finished, the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Block Erase command is not executed if the addressed page is protected by
the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31 Mode 3
Mode 0
SCK
SI
Command
20h
24-Bit Address
2
1
0
23 22
MSB
Figure 32: 4 kB Block Erase Command
Datasheet
29-Jul-2021
Revision B
42
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.4.6 32 kB Block Erase (52h)
The 32 kB Block Erase command sets all memory within a specified block (32 kB) to the erased state of all 1s (FFh). A Write
Enable command must be executed before the device can accept the 32 kB Block Erase command (Status Register bit WEL must
equal 1). The command is initiated by driving the CS pin low and transferring the opcode 52h followed a 24-bit block address
(A23-A0). The address A14-A0 is an unrelated item and has no effect on the result of the command.The Block Erase command
sequence is shown in Figure 33.
The CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done, the 32 kB Block Erase
command is not executed. After CS is driven high, the self-timed 32 kB Block Erase command commences for a time duration of
tBE1 (see Section 7.6, AC Characteristics). While the 32 kB Block Erase cycle is in progress, the Read Status Register command
can still be accessed for checking the status of the RDY/BSY bit. The RDY/BSY bit is a 1 during the 32 kB Block Erase cycle and
becomes a 0 when the cycle is finished and the device is ready to accept other commands. After the 32 kB Block Erase cycle
has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The 32 kB Block Erase command is not
executed if the addressed page is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31 Mode 3
Mode 0
SCK
Command
52h
24-Bit Address
2
1
0
23 22
SI
MSB
HIGH-IMPEDANCE
SO
Figure 33: 32 kB Block Erase Command
Datasheet
29-Jul-2021
Revision B
43
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.4.7 64 kB Block Erase (D8h)
The 64 kB Block Erase command sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write
Enable command must be executed before the device can accept the 64 kB Block Erase command (Status Register bit WEL must
equal 1). The command is initiated by driving the CS pin low and transferring the opcode D8h, followed a 24-bit block address
(A23-A0). The address A15-A0 is an unrelated item and has no effect on the result of the command.The 64 kB Block Erase
command sequence is shown in Figure 34.
The CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done, the 64 kB Block Erase
command is not executed. After CS is driven high, the self-timed 64 kB Block Erase command commences for a time of tBE2 (see
Section 7.6, AC Characteristics). While the 64 kB Block Erase cycle is in progress, the Read Status Register command can be
accessed for checking the status of the RDY/BSY bit. The RDY/BSY bit is 1 during the 64 kB Block Erase cycle; it becomes a 0
when the cycle is finished and the device is ready to accept other commands. After the 64 kB Block Erase cycle has finished, the
Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The 64 kB Block Erase command is not executed if the
addressed page is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31 Mode 3
Mode 0
SCK
Command
D8h
24-Bit Address
2
1
0
23 22
SI
MSB
High-Impedance
SO
Figure 34: 64 kB Block Erase Command
Datasheet
29-Jul-2021
Revision B
44
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.4.8 Chip Erase (C7h / 60h)
The Chip Erase command sets all memory within the device to the erased state of 1s (FFh). A Write Enable command must be
executed before the device can accept the Chip Erase command (Status Register bit WELmust equal 1). The command is initiated
by driving the CS pin low and transferring the opcode C7h or 60h. The Chip Erase command sequence is shown in Figure 35.
The CS pin must be driven high after the eighth bit has been latched. If this is not done, the Chip Erase command is not executed.
After CS is driven high, the self-timed Chip Erase command commences for a time of tCE (see Section 7.6, AC Characteristics).
While the Chip Erase cycle is in progress, the Read Status Register command can still be accessed to check the status of the
RDY/BSY bit. The RDY/BSY bit = 1 during the Chip Erase cycle; it becomes a 0 when finished and the device is ready to accept
other commands. After the Chip Erase cycle has finished, the Write Enable Latch (WEL) bit in the Status Register is cleared to
0. The Chip Erase command is not executed if any memory region is protected by the Block Protect (BP4, BP3, BP2, BP1, and
BP0) bits.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
&RPPDQGꢁꢂ&ꢆKꢇꢈꢃKꢀ
SI(IO๚ꢀ
High-Impedance
SO(IO๛ꢀ
Figure 35: Chip Erase Command
6.4.9 Program/Erase Suspend (75h)
The Program/Erase Suspend command 75h allows the system to interrupt a Page Program or a Page/4K/32K/64K Block Erase
operation and then read data from any other block. After the program or erase operation has entered the suspended state, the
memory array can be read except for the page being programmed or the page/block being erased. And after the erase operation
has entered the suspended state, the memory array can be programed (except for the page/block being erased. Write status
register operation cannot be suspended. The Erase/Program security registers operation cannot be suspended. The Program/
Erase Suspend command sequence is shown in Figure 36.
Table 11: Readable Area of Memory While a Program or Erase Operation is Suspended
Suspended Operation
Page Program
Readable Region Of Memory Array
All but the Page being programmed.
All but the Page being Erased.
Page Erase
Block Erase(4 kB)
Block Erase(32 kB)
Block Erase(64 kB)
All but the 4 kB Block being Erased.
All but the 32 kB Block being Erased.
All but the 64 kB Block being Erased.
When the Serial NOR Flash receives the Suspend command, there is a latency of tPSL or tESL before the Write Enable Latch
(WEL) bit clears to 0 and the SUS sets to 1. After the latency, the device is ready to accept one of the commands listed in Table
8 (for example: FAST READ). See the Section 7.6, AC Characteristics for tPSL and tESL timings. Table 13 lists the commands for
which the tPSL and tESL latencies do not apply. For example, 05h, 48h, 66h, and 99h can be issued at any time after the Suspend
command. Status Register bit 15 (SUS) can be read to check the suspend status. The SUS sets to 1 when a program or erase
command is suspended. The SUS clears to 0 when the program or erase command is resumed.
Datasheet
29-Jul-2021
Revision B
45
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
Table 12: Acceptable Commands During Program/Erase Suspend After tPSL/tESL
Suspend Type
-
Command Name
Opcode
Program
Erase
Read Data
03h
0Bh
3Bh
BBh
6Bh
EBh
5Ah
9Fh
90h
48h
77h
06h
04h
7Ah
02h
A2h
32h
ABh
*
*
*
*
*
*
*
*
Fast Read
Dual Output Fast Read
Dual I/O Fast Read
Quad Output Fast Read
Quad I/O Fast Read
Read SFDP
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Read JEDEC ID
Mftr./Device ID
Read Security Registers
Set Burst with Wrap
Write Enable
Write Disable
*
*
Program/Erase Resume
Page Program
Dual Page Program
Quad Page Program
Release Power-Down/Device ID
*
Table 13: Acceptable Commands During Suspend (tPSL/tESL Not Required)
Suspend Type
Command Name
Opcode
Program
Erase
Read Status Register-1
Read Status Register-2
Active Status Interrupt
Enable Reset
05H
35H
25H
66H
99H
*
*
*
*
*
*
*
*
*
*
Reset Device
CS
SCK
SI
tPSL/tESL
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 3
Mode 0
Command
75h
High-Impedance
SO
Accept Commands
Figure 36: Program/Erase Suspend Command
Datasheet
29-Jul-2021
Revision B
46
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.4.10 Program/Erase Resume (7Ah)
The Program/Erase Resume command 7Ah must be written to resume the Program or Page/Block Erase operation after the
Program/Erase Suspend. The Program/Erase Resume command 7Ah is accepted by the device only if the SUS bit in the Status
Register is 1 and the RDY/BSY bit is 0. After the command is issued, the SUS bit is cleared from 1 to 0, the RDY/BSY bit is set
from 0 to 1 within 200 ns, and the Page, or 4/32/64 kB block completes the program/erase operation. If the SUS bit is 0 or the
RDY/BSY bit is 1, the Program/Erase Resume command 7Ah is ignored. The Program/Erase Resume command sequence is
shown in Figure 37.
Program/Erase Resume command is ignored if the previous Program/Erase Suspend operation was interrupted by an unexpected
power-off. It is required that a subsequent Program/Erase Suspend command not to be issued within a minimum of time of tSUS
following a previous Resume command.
CS
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 3
Mode 0
SCK
SI
Command
7Ah
Resume previously
suspended Program
or Erase
High-Impedance
SO
Figure 37: Program/Erase Resume Command
Datasheet
29-Jul-2021
Revision B
47
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.4.11 Erase Security Registers (44h)
The AT25EU0011A offers three 512-byte Security Registers that can be erased and programmed individually. These registers
can be used by the system manufacturers to store security and other important information separately from the main memory
array.
The Erase Security Register command is similar to the 4 kB Block Erase command. A Write Enable command must be executed
before the device can accept the Erase Security Register command (Status Register bit WELmust be 1). The command is initiated
by driving the CS pin low and transferring the opcode 44h, followed by a 24-bit address (A23-A0).
Table 14: Erase Security Coding
Address
A23-16
00h
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-9
0 0 0
0 0 0
0 0 0
A8-0
Security Register #1
Security Register #2
Security Register #3
Don’t Care
Don’t Care
Don’t Care
00h
00h
The Erase Security Register command sequence is shown in Figure 38. The CS pin must be driven high after the eighth bit of
the last byte has been latched. If this is not done, the command is not executed. After CS is driven high, the self-timed Erase
Security Register operation commences for a time of tSE (see Section 7.6, AC Characteristics). While the Erase Security Register
cycle is in progress, the Read Status Register command can be accessed for checking the status of the RDY/BSY bit. The RDY/
BSY bit is a 1 during the erase cycle; it becomes a 0 when the cycle is finished and the device is ready to accept other commands.
After the Erase Security Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The
Security Register Lock Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is
set to 1, the corresponding security register (LB3-1 corresponds to S13-11) is permanently locked, and the Erase Security Register
command to that register is ignored (see Section 5 for details).
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
Mode 3
Mode 0
SCK
Command
44h
24-Bit Address
23 22 21
MSB
3
2
1
0
SI
High-Impedance
SO
Figure 38: Erase Security Register Command
Datasheet
29-Jul-2021
Revision B
48
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.4.12 Program Security Registers (42h)
The Program Security Register command is similar to the Page Program command. It allows from one to 512 bytes of security
register data to be programmed by two times (one time program 256 bytes) at previously erased (FFh) memory locations. A Write
Enable command must be executed before the device can accept the Program Security Register command (Status Register bit
WEL= 1). The command is initiated by driving the CS pin low, then transferring the opcode 42h, followed by a 24-bit address
(A23-A0) and at least one data byte, onto the SI pin. The CS pin must be held low for the entire length of the command while data
is being sent to the device.
Table 15: Program Security Register Coding
Address
A23-16
00h
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-9
0 0 0
0 0 0
0 0 0
A8-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00h
00h
The Program Security Register command sequence is shown in Figure 39. The Security Register Lock Bits (LB3-1) in the Status
Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register is
permanently locked, and the Program Security Register command to that register is ignored.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
SCK
SI
Command
42h
24-Bit Address
Data Byte 1
2
1
0
5
4
3
2
1
0
23 22
7
6
MSB
CS
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Mode 3
Mode 0
SCK
Data Byte 2
Data Byte 3
Data Byte 256
5
4
3
2
1
0
5
4
3
2
1
0
5
4
3
2
1
0
7
6
7
6
7
6
SI
Figure 39: Program Security Register Command
Datasheet
29-Jul-2021
Revision B
49
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.4.13 Read Security Registers (48h)
The Read Security Register command is similar to the Fast Read command; it allows one or more data bytes to be sequentially
read from one of the three security registers. The command is initiated by driving the CS pin low and then transferring the opcode
48h followed by a 24-bit address (A23-A0) and eight dummy clocks into the SI pin. The code and address bits are latched on the
rising edge of the SCK pin. After the address is received, the data byte of the addressed memory location is transferred out on
the SO pin at the falling edge of SCK, with the most significant bit (MSB) first. The byte address is automatically incremented to
the next byte address after each byte of data is transferred out. Once the byte address reaches the last byte of the register (byte
address FFh), it resets to address 00h, the first byte of the register, and continue to increment. The command is completed by
driving CS high. The Read Security Register command sequence is shown in Figure 40. If a Read Security Register command
is issued while an Erase, Program, or Write cycle is in progress (RDY/BSY=1), the command is ignored and does not have any
effect on the current cycle. The Read Security Register command allows a clock frequency up to the maximum of fC (see Section
7.6, AC Characteristics).
Table 16: Read Secutiry Register Coding
Address
A23-16
00h
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-9
0 0 0
0 0 0
0 0 0
A8-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00h
00h
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCK
Command
48h
24-Bit Address
3
23 22 21
2
1
0
SI
High-Impedance
SO
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Mode 3
Mode 0
SCK
SI
Dummy Byte
7
6
5
4
3
2
1
0
Data Byte 1
High-Impedance
7
6
5
4
3
2
1
0
SO
Figure 40: Read Security Command
Datasheet
29-Jul-2021
Revision B
50
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
6.4.14 Enable Reset (66h) and Reset Device (99h)
The AT25EU0011Aprovides a software Reset command. Once the Reset command is accepted, any on-going internal operations
are terminated, and the device returns to its default power-on state; it then also loses all the current volatile settings, such as
Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Continuous Read Mode bit setting
(M7-M0), Wrap Bit setting (W6-W4). To avoid accidental reset, both commands must be issued in sequence. Any commands
other than Reset (99h) after the Enable Reset (66h) command disables the Reset Enable state, and a new sequence of Enable
Reset (66h) and Reset (99h) is needed to reset the device. Once the Reset command is accepted by the device, the device takes
tRST to reset. During this period, no command is accepted. Data corruption can happen if there is an on-going or suspended
internal Erase or Program operation when the Reset command sequence is accepted by the device. Check the RDY/BSY bit and
the SUS bit in the Status Register before issuing the Reset command sequence.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 3
Mode 0
Mode 3
Mode 0
SCK
SI
Command
66h
Command
99h
Figure 41: Enable Reset and Reset Command Sequence
6.4.15 Read Serial Flash Discoverable Parameter (5Ah)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature
capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by
host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is
similar to the one found in the Introduction of JEDEC Standard JESD68 on CFI. SFDP is based on JEDEC Standard JESD216B.
The SFDP is a special order. Contact Dialog Semiconductor.
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCK
Command
5Ah
24-Bit Address
23 22 21
3
2
1
0
SI
High-Impedance
SO
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Mode 3
Mode 0
SCK
SI
IOs switch from Input to Output
Dummy Byte
7
6
5
4
3
2
1
0
Data Byte 1
High-Impedance
7
6
5
4
3
2
1
0
SO
Figure 42: Read Serial Flash Discoverable Parameter Command
Datasheet
29-Jul-2021
Revision B
51
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
7
Electrical Characteristics
7.1 ABSOLUTE MAXIMUM RATINGS
This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not
guaranteed. Exposure to absolute maximum ratings can affect device reliability. Exposure beyond absolute maximum ratings can
cause permanent damage.
Table 17: Absolute Maximum Ratings
Parameter
Symbol
VCC
Conditions
Range
Unit
V
Supply Voltage
–0.6 to VCC+0.6
–0.6 to VCC+0.6
Voltage Applied to Any Pin
VIO
Relative to Ground
V
<20 ns Transient
Relative to Ground
Transient Voltage on any Pin
VIOT
–1.0 V to VCC+1.0 V
V
Storage Temperature
TSTG
TLEAD
VESD
–65 to +150
See Note 2
°C
°C
V
Lead Temperature
Electrostatic Discharge Voltage
Human Body Model(3)
–2000 to +2000
Notes:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed.
Exposure to absolute maximum ratings can affect device reliability. Exposure beyond absolute maximum ratings can cause permanent dam-
age.
2. Compliant with JEDEC Standard J-STD-20C for small-body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on
hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
7.2 OPERATING RANGES
Table 18: Operating Ranges
Parameter
Symbol
VCC
TA
Conditions
fC = 85 MHz, FR = 33 MHz
Industrial
Min
1.65
-40
Max
3.6
85
Unit
V
Supply Voltage
Operating Temperature
°C
Datasheet
29-Jul-2021
Revision B
52
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
7.3 POWER-UP / POWER-DOWN TIMING AND REQUIREMENTS
The parameters in the following table are characterized only.
Table 19: Timing Requirements for Power-Up/Down
Parameter
Symbol
tVSL
Min
1.5
1.0
Max
Unit
ms
V
VCC (min) to CS Low
Write Inhibit Threshold Voltage
VWI
1.4
VCC
VCC
max
Chip selection is not allowed
VCC
min
tVSL
Device is fully accessible
Reset
State
VWI
Time
Figure 43: Power-Up Timing and Voltage Levels
Datasheet
29-Jul-2021
Revision B
53
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
7.4 DC CHARACTERISTICS
Table 20: DC Electrical Characteristics
Parameter
Input Capacitance 1
Output Capacitance 1
Input Leakage
Symbol
CIN
Conditions
VIN = 0 V 1
Min
Typ
Max
6
Unit
pF
pF
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
V
COUT
ILI
VOUT = 0 V 1
8
All inputs at CMOS level
All inputs at CMOS level
CS = VCC, VIN = GND or VCC
CS = VCC, VIN = GND or VCC
F = 1 MHz; IOUT = 0 mA
F = 33 MHz; IOUT = 0 mA
F = 50 MHz; IOUT = 0 mA
F=85 MHz; IOUT = 0 mA
CS = VCC RDY/BSY = 1
CS = VCC RDY/BSY = 1
±2
Output Leakage
ILO
±2
Standby Current
ICC1
ICC2
10
0.1
0.7
1.0
1.2
1.5
1.5
1.5
14.5
1.8
Power-Down Current
1.0
Normal Read Current (03h)
Read Current (0Bh)
ICC3
ICC4
2.0
2.1
3.0
Program Current
Erase Current
ICC5
ICC6
VIL
3.0
3.0
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VCC x 0.2
VIH
VCC x 0.8
VCC – 0.2
V
VOL
VOH
IOL = 100 µA
0.2
V
IOH = –100 µA
V
1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 1.8 V.
7.5 AC MEASUREMENT CONDITIONS
Table 21: AC Measurement Conditions
Parameter
Input Capacitance
Symbol
CIN
Min
Max
6
Unit
pF
pF
pF
ns
V
Output Capacitance
COUT
CL
6
Load Capacitance
30
5
Input Rise and Fall Times
Input Pulse Voltages
TR, TF
VIN
0.2 VCC - 0.8 VCC
0.5 VCC - 0.5 VCC
0.5 VCC - 0.5 VCC
Input Timing Reference Voltages
Output Timing Reference Voltages
IN
V
OUT
V
Input Timing
Input Levels Reference Levels
Output Timing
Reference Levels
0.8 VCC
0.2 VCC
0.5 VCC
0.5 VCC
Figure 44: AC Measurement I/O Waveform
Datasheet
29-Jul-2021
Revision B
54
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
7.6 AC CHARACTERISTICS
Table 22: AC Electrical Characteristics
Parameter
Symbol
fC
ALT
Min
Typ
Max
Unit
Maximum clock frequency for all opcodes except 03h,
6Bh, and EBh
85
MHz
fC1
Maximum Clock Frequency for opcodes 6Bh and EBh
Maximum Clock Frequency for 03h
Clock High, Low Time
70
33
MHz
MHz
ns
fR
tCLH, CLL
1
t
5.5
0.1
0.1
5
2
Clock Rise Time peak to peak
Clock Fall Time peak to peak
tCLCH
tCHCL
V/ns
V/ns
ns
2
CS Active Setup Time relative to CLK
CS Not Active Hold Time relative to CLK
Data In Setup Time
tSLCH
tCHSL
tDVCH
tCHDX
tCSS
5
ns
tDSU
tDH
tDIS
tCSS
2
ns
Data In Hold Time
3
ns
2
Output Disable Time
tSHQZ
tCHSH
tSHCH
tCLQV1
6
7
ns
CS Active Hold Time relative to CLK
CS Not Active Setup Time relative to CLK
Clock Low to Output Valid
5
5
ns
ns
tV1
ns
CS Deselect Time from read to next Read
15
30
ns
tSHSL
tCSH
CS Deselect Time from Write,Erase,Program to Read
Status Register
ns
Clock Low to Output Valid loading 30pF
Clock Low to Output Valid loading 15pF
Output Hold Time
7
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
ms
ms
µs
µs
µs
µs
ms
ms
ms
tCLQV
tV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHO
0
5
5
5
5
HOLD Active Setup Time relative to CLK
HOLD Active Hold Time relative to CLK
HOLD Not Active Setup Time relative to CLK
HOLD Not Active Hold Time relative to CLK
HOLD to Output Low-Z
2
tHHQX
tHLQZ
tWHSL
tSHWL
tLZ
6
6
2
3
3
HOLD to Output High-Z
tHZ
Write Protect Setup Time Before CS Low
Write Protect Hold Time After CS High
CS High to Deep Power-down Mode
CS High to Standby Mode without ID Read
CS High to Standby Mode with ID Read
CS High to next command after Reset
Write Status Register Cycle Time
Byte Program Time
20
100
2
tDP
tRES1
tRES2
tRST
tW
3
8
8
2
2
2
300
6.5
2
12
3
tBP1
tESL
tPSL
tPRS
tERS
tPP
Erase Suspend Latency
30
30
Program Suspend Latency
LatencybetweenProgramResumeandnextSuspend
Latency between Erase Resume and next Suspend
Page Program Time
20
20
2
8
8
3
Page Erase Time
tPE
12
12
Block Erase Time (4 kB)
tBLKE-4kB
Datasheet
29-Jul-2021
Revision B
55
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
Table 22: AC Electrical Characteristics (Continued)
Parameter
Symbol
ALT
Min
Typ
8
Max
12
Unit
ms
Block Erase Time (32 kB)
Block Erase Time (64 kB)
Chip Erase Time
tBLKE-32kB
tBLKE-64kB
tCE
8
12
ms
8
12
ms
1. Clock high + clock low must be less than, or equal to, 1/fC.
2. Value guaranteed by design and/or characterization; not 100% tested in production.
3. Only applicable as a constraint for a write Status Register command when SRP[1:0] = (0,1).
7.7 SERIAL OUTPUT TIMING
CS
SCK
tCLH
tCLQV
tCLQV
tCLL
tSHQZ
tCLQX
tCLQX
IO
LSB OUT
output
Figure 45: Serial Output Timing
7.8 SERIAL INPUT TIMING
tSHSL
tSHCH
CS
tCHCL
tCHSL
tSLCH
SCK
tCLCH
tCHCL
tDVCH
tCHDX
IO
MSB IN
LSB IN
output
Figure 46: Serial Input Timing
7.9 HOLD TIMING
CS
SCK
tCHHL
tHLCH
tHHCH
tCHHH
HOLD
tHHQX
tHLQZ
IO
output
IO
input
Figure 47: HOLD Timing
Datasheet
29-Jul-2021
Revision B
56
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
7.10 WP TIMING
CS
tWHSL
tSHWL
WP
SCK
IO
input
Write Status Register is allowed
Write Status Register is not allowed
Figure 48: WP Timing
Datasheet
29-Jul-2021
Revision B
57
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
8
Ordering Information
AT 25EU 0011 A - MA H N - T
Delivery Option
T = Tape and reel
B = Bulk
Designator
Product Family
Voltage
N = 1.65 V to 3.6 V
Device Density
0011 = 1 Mbit
Green Code
H = Pb and halogen free green package
Generation
Package Type
SS = 8-lead 150 mil SOIC
MA = 8-pad 2x3x0.6 mm UDFN
Table 23: Ordering Codes
Ordering Code
Operating
Package
Lead Finish
Delivery Option
Voltage
AT25EU0011A-SSHN-T
AT25EU0011A-SSHN-B
Tape and Reel
8-lead SOIC (150 mil)
Bulk
Pb and Halogen Free
1.65 V - 3.6 V
AT25EU0011A-MAHN-T
8-pad 2x3x0.6 mm UDFN
Tape and Reel
Table 24: Package Types
Designation
8S1
Description
8-lead, 150 mil Narrow, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-pad, 2x3x0.6 mm, Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN)
8MA3
Datasheet
29-Jul-2021
Revision B
58
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
9
Packaging Information
9.1 EIGHT-PIN SOIC 150-MIL
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
C
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
–
D
–
D
E1
E
–
–
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
e
1.27 BSC
L
0.40
0°
–
–
1.27
8°
ꢀꢀꢀØꢀ
5/19/10
TITLE
GPC
DRAWING NO.
REV.
8S1, 8-lead (150 mil Narrow Body), Plastic Gull
Wing Small Outline (JEDEC SOIC)
SWB
8S1
F
Datasheet
29-Jul-2021
Revision B
59
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
9.2 EIGHT-PAD 2 X 3 X 0.6 MM UDFN
E
Pin 1 ID
D
SIDE VIEW
A3
A1
TOP VIEW
A
COMMON DIMENSIONS
(Unit of Measure = mm)
K
Option A
0.45
SYMBOL
MIN
0.50
0.00
NOM
0.55
0.02
MAX
0.60
0.05
Pin #1
Chamfer
(C 0.35)
8
7
6
5
1
2
Pin #1 Notch
(0.20 R)
A
(Option B)
A1
A3
0.150 REF
D2
e
b
b
D
D2
E
0.20
1.55
0.25
2.00 BSC
1.60
0.30
1.65
3
4
3.00 BSC
0.50 BSC
0.45
e
L
0.40
0.50
L
BOTTOM VIEW
Notes:
1. This package conforms to JEDEC reference MO-229, Saw Singulation.
2. The terminal #1 ID is a Laser-marked Feature.
TITLE
GPC
REV.
D
DRAWING NO.
8MA3, 8-pad (2 x 3 x 0.6 mm Body), Thermally
Enhanced Plastic Ultra Thin Dual Flat No Lead
Package (UDFN)
YFG
8MA3
Datasheet
29-Jul-2021
Revision B
60
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
Revision History
Revision
Date
Description
A
04-2021
Initial release.
Removed “Advanced” and inserted “Preliminary.”
Added Sections 4.1 and 4.2.
Corrected the definition of the QE bit in Table 3.
B
07-2021
Added information for opcodes A2h and 32h in Table 8.
Added descriptions for opcodes A2h and 32h in Sections 6.4.2 and 6.4.3, respectively.
Completed the command names in Table 12.
Updated values in Tables 19 and 20, as well as Section 8.6.
Datasheet
29-Jul-2021
Revision B
61
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
AT25EU0011A
Preliminary Datasheet
1-Mbit, Ultra-Low Energy Serial Flash Memory
Disclaimer
Unless otherwise agreed in writing, the Dialog Semiconductor products (and any associated software) referred to in this document are not designed, authorized or warranted
to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Dialog Semiconductor product (or
associated software) can reasonably be expected to result in personal injury, death or severe property or environmental damage. Dialog Semiconductor and its suppliers
accept no liability for inclusion and/or use of Dialog Semiconductor products (and any associated software) in such equipment or applications and therefore such inclusion
and/or use is at the customer's own risk.
Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or warranties, express or implied, as
to the accuracy or completeness of such information. Dialog Semiconductor furthermore takes no responsibility whatsoever for the content in this document if provided by any
information source outside of Dialog Semiconductor.
Dialog Semiconductor reserves the right to change without notice the information published in this document, including, without limitation, the specification and the design of
the related semiconductor products, software and applications. Notwithstanding the foregoing, for any automotive grade version of the device, Dialog Semiconductor
reserves the right to change the information published in this document, including, without limitation, the specification and the design of the related semiconductor products,
software and applications, in accordance with its standard automotive change notification process.
Applications, software, and semiconductor products described in this document are for illustrative purposes only. Dialog Semiconductor makes no representation or warranty
that such applications, software and semiconductor products will be suitable for the specified use without further testing or modification. Unless otherwise agreed in writing,
such testing or modification is the sole responsibility of the customer and Dialog Semiconductor excludes all liability in this respect.
Nothing in this document may be construed as a license for customer to use the Dialog Semiconductor products, software and applications referred to in this document. Such
license must be separately sought by customer with Dialog Semiconductor.
All use of Dialog Semiconductor products, software and applications referred to in this document are subject to Dialog Semiconductor's Standard Terms and Conditions
of Sale, available on the company website (www.dialog-semiconductor.com) unless otherwise stated.
Dialog, Dialog Semiconductor and the Dialog logo are trademarks of Dialog Semiconductor Plc or its subsidiaries. All other product or service names and marks are
the property of their respective owners.
© 2021 Dialog Semiconductor. All rights reserved.
RoHS Compliance
Dialog Semiconductor's suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction
of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our suppliers are available on request.
Contacting Dialog Semiconductor
United Kingdom (Headquarters)
Dialog Semiconductor (UK) LTD
Phone: +44 1793 757700
North America
Dialog Semiconductor Inc.
Phone: +1 408 845 8500
Hong Kong
Dialog Semiconductor Hong Kong
Phone: +852 2607 4271
China (Shenzhen)
Dialog Semiconductor China
Phone: +86 755 2981 3669
Germany
Japan
Korea
China (Shanghai)
Dialog Semiconductor GmbH
Phone: +49 7021 805-0
Dialog Semiconductor K. K.
Phone: +81 3 5769 5100
Dialog Semiconductor Korea
Phone: +82 2 3469 8200
Dialog Semiconductor China
Phone: +86 21 5424 9058
The Netherlands
Taiwan
62
Dialog Semiconductor B.V.
Phone: +31 73 640 8822
Dialog Semiconductor Taiwan
Phone: +886 281 786 222
Email:
Web site:
enquiry@diasemi.com
www.dialog-semiconductor.com
Datasheet
29-Jul-2021
Revision B
62
DS-AT25EU0011A-203
© 2021 Dialog Semiconductor
相关型号：
©2020 ICPDF网 联系我们和版权申明