AT25FF161A-DWF [DIALOG]
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory with Multi-I/O Support;
| 型号： | AT25FF161A-DWF |
| 厂家： | 
Dialog Semiconductor |
| 描述： | 16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory with Multi-I/O Support |
| 文件： | 总120页 (文件大小：1176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Features
Voltage Range: 1.65 V - 3.6 V
16 Mbit (2M x 8) Flash Memory
Serial Peripheral Interface (SPI) compatible
- Supports SPI modes 0 and 3 (1-1-1)
- Supports dual output operation (1-1-2)
- Supports quad output operation (1-1-4)
- Supports quad I/O operation (1-4-4)
- Supports XiP operation (1-4-4, 0-4-4)
133 MHz maximum operating frequency
- Clock-to-output of 8 ns
Flexible, optimized erase architecture for code + data storage applications
- Uniform 4-kByte block erase
- Uniform 32-kByte block erase
- Uniform 64-kByte block erase
- Full chip erase
Flexible non-volatile block protection
1 x 128-byte factory-programmed unique identifier
3 x 128-byte, One Time Programmable (OTP) security registers
Flexible programming
- Byte/Page program (1 to 256 Bytes)
- Sequential program mode capability
Erase program suspend resume
Software controlled Reset and Terminate commands
Hardware reset option (via HOLD pin)
JEDEC hardware reset
Non-volatile status register configuration option
JEDEC standard manufacturer and device ID read methodology
Serial Flash Discoverable Parameters (SFDP) version 1.6
Low power dissipation:
- 30 µA standby current (typical)
- 8.2 µA Deep Power-Down (DPD) current (typical)
- 5 - 7 nA Ultra Deep Power Down (UDPD) current (typical)
- 8.6 mA active read current (1-1-1 — 108 MHz)
- 9.2 mA program current
- 10.2 mA erase current
User configurable and auto I/O pin drive levels
Endurance
- 100,000 program/erase cycles
Data Retention
- 20 years
Temperature Range
- -40 oC to +85 oC
Industry standard green (Pb/Halide-free/RoHS Compliant) Package Options
- 8-lead SOIC (150-mil) including silver free
- 8-lead SOIC (208-mil)
- 8-pad Ultra-thin DFN (2 x 3 x 0.6 mm)
- 8-ball WLCSP (3 x 2 x 3 ball matrix)
- Die in Wafer Form (DWF)
Datasheet
2021-08-13
Revision H
1
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Contents
Features .................................................................................................................................................................................... 1
Contents.................................................................................................................................................................................... 2
Figures ...................................................................................................................................................................................... 8
Tables........................................................................................................................................................................................ 9
1 Block Diagram .................................................................................................................................................................... 10
2 Package Pinout and Pin Descriptions .............................................................................................................................. 11
3 Device Operation ................................................................................................................................................................ 14
3.1 Data Transfer Modes ...............................................................................................................................................14
3.2 Standard SPI Operation ...........................................................................................................................................14
3.2.1 Command Only, No Address or Data (1-0-0) ............................................................................................. 15
3.2.2 Command and Address Only, No Data (1-1-0) .......................................................................................... 15
3.2.3 Command and Data Only, No Address (1-0-1) .......................................................................................... 16
3.2.4 Command, Address, and Data (1-1-1) ....................................................................................................... 17
3.3 Dual Output Operation (1-1-2) .................................................................................................................................18
3.4 Quad Output Operation (1-1-4) ................................................................................................................................19
3.5 Quad I/O Operation (1-4-4) ......................................................................................................................................20
3.6 XiP Mode Operation .................................................................................................................................................21
3.6.1 Initial Transfer and XiP Mode Detection (M[5:4]) ....................................................................................... 21
3.6.2 Subsequent Transfers ................................................................................................................................ 22
3.6.3 Set Burst with Wrap ................................................................................................................................... 23
3.7 Memory Architecture ................................................................................................................................................23
3.8 Memory Protection ...................................................................................................................................................26
3.8.1 Standard Memory Protection ..................................................................................................................... 26
3.8.2 Individual Block Lock and Unlock ............................................................................................................... 29
3.8.3 Global Block Lock and Unlock ................................................................................................................... 29
3.8.4 Reading the State of the Lock Bits ............................................................................................................. 29
3.9 Power Down Considerations ....................................................................................................................................29
3.9.1 Entering Power Down Mode ...................................................................................................................... 30
3.9.2 Exiting Power Down Mode ......................................................................................................................... 30
3.9.3 ABh Command ........................................................................................................................................... 30
3.9.4 Device Resets ............................................................................................................................................ 31
3.9.5 Enable Reset (66h) / Reset (99h) Command ............................................................................................. 31
3.9.6 Terminate Command (F0h) ........................................................................................................................ 31
3.9.7 Reset During Program and Erase Commands ........................................................................................... 31
3.10 Erase/Program Suspend Considerations and Nested Operations .........................................................................32
3.10.1 Nested Operations ................................................................................................................................... 32
3.10.2 Program and Erase Errors ....................................................................................................................... 34
3.10.3 Suspending and Terminating a Program or Erase Operation .................................................................. 35
3.10.4 Terminating a Non-Volatile Operation in Progress ................................................................................... 36
3.11 OTP Security Register Lock ...................................................................................................................................37
3.12 Standard JEDEC Hardware Reset .........................................................................................................................37
3.13 Chip Select Restrictions .........................................................................................................................................38
3.14 HOLD / RESET Function .......................................................................................................................................38
4 Status Registers ................................................................................................................................................................. 40
4.1 Register Structure and Updates ...............................................................................................................................40
4.2 Register Accesses ...................................................................................................................................................41
4.2.1 Direct and Indirect Addressing ................................................................................................................... 41
4.2.2 Volatile and Non-Volatile Register Accesses ............................................................................................. 41
4.3 Status Register 1 .....................................................................................................................................................42
4.4 Status Register 2 .....................................................................................................................................................43
4.5 Status Register 3 .....................................................................................................................................................46
4.6 Status Register 4 .....................................................................................................................................................47
4.7 Status Register 5 ....................................................................................................................................................48
Datasheet
2021-08-13
Revision H
2
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
5 Commands and Addressing .............................................................................................................................................. 49
5.1 Read Array (03h, 0Bh) .............................................................................................................................................52
5.1.1 Command Prerequisites ............................................................................................................................. 52
5.1.2 Transfer Format ......................................................................................................................................... 52
5.1.3 Transfer Sequence ..................................................................................................................................... 52
5.1.4 Programming Restrictions .......................................................................................................................... 52
5.2 Dual Output Read Array (3Bh) .................................................................................................................................53
5.2.1 Command Prerequisites ............................................................................................................................. 53
5.2.2 Transfer Format ......................................................................................................................................... 53
5.2.3 Transfer Sequence ..................................................................................................................................... 53
5.2.4 Programming Restrictions .......................................................................................................................... 53
5.3 Quad Output Read Array (6Bh) ...............................................................................................................................53
5.3.1 Command Prerequisites ............................................................................................................................. 54
5.3.2 Transfer Format ......................................................................................................................................... 54
5.3.3 Transfer Sequence ..................................................................................................................................... 54
5.3.4 Programming Restrictions .......................................................................................................................... 54
5.4 XiP Read (EBh), XiP Read with Double-word Aligned Address (E7h) .....................................................................55
5.4.1 Command Prerequisites ............................................................................................................................. 55
5.4.2 Transfer Format ......................................................................................................................................... 55
5.4.3 Mode Bits ................................................................................................................................................... 55
5.4.4 Transfer Sequence — Initial Transfer ........................................................................................................ 55
5.4.5 Transfer Sequence — Subsequent Transfers ............................................................................................ 56
5.4.6 Programmable Number of Dummy Clocks ................................................................................................. 56
5.4.7 Programming Restrictions .......................................................................................................................... 58
5.5 Block Erase (20h, 52h, D8h) ....................................................................................................................................59
5.5.1 Command Prerequisites ............................................................................................................................. 59
5.5.2 Transfer Format ......................................................................................................................................... 59
5.5.3 Transfer Sequence ..................................................................................................................................... 59
5.5.4 Erase Operation ......................................................................................................................................... 59
5.5.5 Command Status ....................................................................................................................................... 59
5.5.6 Programming Restrictions .......................................................................................................................... 59
5.5.7 Error Reporting ........................................................................................................................................... 60
5.6 Chip Erase (60h, C7h) .............................................................................................................................................60
5.6.1 Command Prerequisites ............................................................................................................................. 60
5.6.2 Transfer Format ......................................................................................................................................... 60
5.6.3 Transfer Sequence ..................................................................................................................................... 60
5.6.4 Device Status ............................................................................................................................................. 60
5.6.5 Programming Restrictions .......................................................................................................................... 60
5.6.6 Error Reporting ........................................................................................................................................... 60
5.7 Byte/Page Program (02h) ........................................................................................................................................61
5.7.1 Command Prerequisites ............................................................................................................................. 61
5.7.2 Transfer Format ......................................................................................................................................... 61
5.7.3 Transfer Sequence ..................................................................................................................................... 61
5.7.4 Device Status ............................................................................................................................................. 61
5.7.5 Programming Restrictions .......................................................................................................................... 61
5.8 Sequential Program Mode (ADh/AFh) .....................................................................................................................62
5.8.1 Command Prerequisites ............................................................................................................................. 62
5.8.2 Transfer Format ......................................................................................................................................... 62
5.8.3 Transfer Sequence — Initial Transfer ........................................................................................................ 62
5.8.4 Transfer Sequence — Subsequent Transfers ............................................................................................ 63
5.8.5 Program Status .......................................................................................................................................... 63
5.8.6 Commands Allowed and Not Allowed in Sequential Program Mode .......................................................... 63
5.8.7 Programming Restrictions .......................................................................................................................... 64
5.8.8 Error Reporting ........................................................................................................................................... 65
Datasheet
2021-08-13
Revision H
3
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
5.9 Dual Output Byte/Page Program (A2h) ....................................................................................................................65
5.9.1 Command Prerequisites ............................................................................................................................. 65
5.9.2 Transfer Format ......................................................................................................................................... 65
5.9.3 Transfer Sequence ..................................................................................................................................... 65
5.9.4 Program Status .......................................................................................................................................... 66
5.9.5 Programming Restrictions .......................................................................................................................... 66
5.9.6 Error Reporting ........................................................................................................................................... 66
5.10 Quad Output Page Program (32h) .........................................................................................................................67
5.10.1 Command Prerequisites ........................................................................................................................... 67
5.10.2 Transfer Format ....................................................................................................................................... 67
5.10.3 Transfer Sequence ................................................................................................................................... 67
5.10.4 Programming Restrictions ........................................................................................................................ 67
5.10.5 Error Reporting ......................................................................................................................................... 68
5.11 Program/Erase Suspend (75h/B0h) .......................................................................................................................68
5.11.1 Command Prerequisites ........................................................................................................................... 68
5.11.2 Transfer Format ....................................................................................................................................... 68
5.11.3 Transfer Sequence ................................................................................................................................... 68
5.11.4 Command Behavior During a Program/Erase Operation ......................................................................... 68
5.11.5 Device Status ........................................................................................................................................... 70
5.11.6 Programming Restrictions ........................................................................................................................ 70
5.12 Program/Erase Resume (7Ah/D0h) .......................................................................................................................71
5.12.1 Command Prerequisites ........................................................................................................................... 71
5.12.2 Transfer Format ....................................................................................................................................... 71
5.12.3 Transfer Sequence ................................................................................................................................... 71
5.12.4 Command Behavior ................................................................................................................................. 72
5.12.5 Programming Restrictions ........................................................................................................................ 72
5.13 Set Burst Wrap (77h) .............................................................................................................................................73
5.13.1 Command Prerequisites ........................................................................................................................... 73
5.13.2 Transfer Format ....................................................................................................................................... 73
5.13.3 Transfer Sequence ................................................................................................................................... 73
5.13.4 Wrap Bits .................................................................................................................................................. 73
5.13.5 Programming Restrictions ........................................................................................................................ 74
5.14 \Write Enable (06h) ................................................................................................................................................74
5.14.1 Command Prerequisites ........................................................................................................................... 74
5.14.2 Transfer Format ....................................................................................................................................... 74
5.14.3 Transfer Sequence ................................................................................................................................... 74
5.14.4 Programming Restrictions ........................................................................................................................ 74
5.15 Write Disable (04h) ................................................................................................................................................75
5.15.1 Command Prerequisites ........................................................................................................................... 75
5.15.2 Transfer Format ....................................................................................................................................... 75
5.15.3 Transfer Sequence ................................................................................................................................... 75
5.15.4 Programming Restrictions ........................................................................................................................ 75
5.16 Volatile Status Register Write Enable (50h) ...........................................................................................................76
5.16.1 Command Prerequisites ........................................................................................................................... 76
5.16.2 Transfer Format ....................................................................................................................................... 76
5.16.3 Transfer Sequence ................................................................................................................................... 76
5.16.4 Programming Restrictions ........................................................................................................................ 76
5.17 Individual Block Lock (36h) ....................................................................................................................................77
5.17.1 Command Prerequisites ........................................................................................................................... 77
5.17.2 Transfer Format ....................................................................................................................................... 77
5.17.3 Transfer Sequence ................................................................................................................................... 77
5.17.4 Programming Restrictions ........................................................................................................................ 77
5.18 Individual Block Unlock (39h) .................................................................................................................................78
5.18.1 Command Prerequisites ........................................................................................................................... 78
5.18.2 Transfer Format ....................................................................................................................................... 78
5.18.3 Transfer Sequence ................................................................................................................................... 78
5.18.4 Programming Restrictions ........................................................................................................................ 78
Datasheet
2021-08-13
Revision H
4
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
5.19 Read Block Lock (3Ch/3Dh) ..................................................................................................................................79
5.19.1 Command Prerequisites ........................................................................................................................... 79
5.19.2 Transfer Format ....................................................................................................................................... 79
5.19.3 Transfer Sequence ................................................................................................................................... 79
5.19.4 Programming Restrictions ........................................................................................................................ 79
5.20 Global Block Lock (7Eh) ........................................................................................................................................80
5.20.1 Command Prerequisites ........................................................................................................................... 80
5.20.2 Transfer Format ....................................................................................................................................... 80
5.20.3 Transfer Sequence ................................................................................................................................... 80
5.20.4 Programming Restrictions ........................................................................................................................ 80
5.21 Global Block Unlock (98h) .....................................................................................................................................81
5.21.1 Command Prerequisites ........................................................................................................................... 81
5.21.2 Transfer Format ....................................................................................................................................... 81
5.21.3 Transfer Sequence ................................................................................................................................... 81
5.21.4 Programming Restrictions ........................................................................................................................ 81
5.22 Program Security Register (9Bh) ...........................................................................................................................82
5.22.1 Command Prerequisites ........................................................................................................................... 82
5.22.2 OTP Security Register Layout .................................................................................................................. 82
5.22.3 Transfer Format ....................................................................................................................................... 82
5.22.4 Transfer Sequence ................................................................................................................................... 82
5.22.5 Addressing the OTP Security Registers ................................................................................................... 83
5.22.6 Programming Status ................................................................................................................................ 83
5.22.7 Locking OTP Registers 1 - 3 .................................................................................................................... 83
5.22.8 Verifying the Locked Status of a Security Register .................................................................................. 84
5.22.9 Programming Restrictions ........................................................................................................................ 84
5.23 Read OTP Security Register (4Bh) ........................................................................................................................85
5.23.1 Command Prerequisites ........................................................................................................................... 85
5.23.2 Transfer Format ....................................................................................................................................... 85
5.23.3 Transfer Sequence — Single Register ..................................................................................................... 85
5.23.4 Transfer Sequence — All Registers ......................................................................................................... 85
5.23.5 Programming Restrictions ........................................................................................................................ 85
5.24 Read Status Registers 1 - 3 (05h, 35h, 15h) .........................................................................................................86
5.24.1 Command Prerequisites ........................................................................................................................... 86
5.24.2 Transfer Format ....................................................................................................................................... 86
5.24.3 Transfer Sequence ................................................................................................................................... 86
5.24.4 Programming Restrictions ........................................................................................................................ 86
5.25 Read Status Registers (65h) ..................................................................................................................................87
5.25.1 Command Prerequisites ........................................................................................................................... 87
5.25.2 Transfer Format ....................................................................................................................................... 87
5.25.3 Transfer Sequence ................................................................................................................................... 87
5.25.4 Reading a Single Status Register ............................................................................................................ 87
5.25.5 Continuous Read of All Status Registers ................................................................................................. 88
5.25.6 Transfer Diagram ..................................................................................................................................... 88
5.25.7 Programming Restrictions ........................................................................................................................ 88
5.26 Write Status Registers 1 - 3 — Direct (01h, 31h, 11h) ...........................................................................................89
5.26.1 Command Prerequisites ........................................................................................................................... 89
5.26.2 Transfer Format ....................................................................................................................................... 89
5.26.3 Transfer Sequence ................................................................................................................................... 89
5.26.4 Programming Restrictions ........................................................................................................................ 89
5.27 Write Status Registers — Indirect (71h) .................................................................................................................90
5.27.1 Command Prerequisites ........................................................................................................................... 90
5.27.2 Transfer Format ....................................................................................................................................... 90
5.27.3 Transfer Sequence ................................................................................................................................... 90
5.27.4 Writing to a Status Register ..................................................................................................................... 91
5.27.5 Transfer Diagram ..................................................................................................................................... 91
5.27.6 Programming Restrictions ........................................................................................................................ 91
Datasheet
2021-08-13
Revision H
5
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
5.28 Status Register Lock (6Fh) ....................................................................................................................................92
5.28.1 Command Prerequisites ........................................................................................................................... 92
5.28.2 Transfer Format ....................................................................................................................................... 92
5.28.3 Transfer Sequence ................................................................................................................................... 92
5.28.4 Transfer Diagram ..................................................................................................................................... 92
5.28.5 Programming Restrictions ........................................................................................................................ 92
5.29 Deep Power Down (B9h) .......................................................................................................................................93
5.29.1 Command Prerequisites ........................................................................................................................... 93
5.29.2 Transfer Format ....................................................................................................................................... 93
5.29.3 Transfer Sequence ................................................................................................................................... 93
5.29.4 Programming Restrictions ........................................................................................................................ 93
5.30 Resume from Ultra-Deep Power Down / Deep Power Down with Device ID (ABh) ...............................................94
5.30.1 Command Options ................................................................................................................................... 94
5.30.2 Command Prerequisites ........................................................................................................................... 94
5.30.3 Transfer Format — Resume from Deep Power Down ............................................................................. 94
5.30.4 Transfer Format — Resume from Deep Power Down and Obtain Device ID .......................................... 94
5.30.5 Transfer Sequence — Resume from Deep Power Down ......................................................................... 94
5.30.6 Transfer Sequence — Resume from Deep Power Down and Obtain Device ID ..................................... 95
5.30.7 Transfer Sequence — Resume from Ultra-Deep Power Down ................................................................ 95
5.30.8 Programming Restrictions ........................................................................................................................ 95
5.31 Ultra-Deep Power Down (79h) ...............................................................................................................................96
5.31.1 Command Prerequisites ........................................................................................................................... 96
5.31.2 Transfer Format ....................................................................................................................................... 96
5.31.3 Transfer Sequence ................................................................................................................................... 96
5.31.4 Programming Restrictions ........................................................................................................................ 97
5.32 Enable Reset (66h) and Reset Device (99h) .........................................................................................................98
5.32.1 Command Prerequisites ........................................................................................................................... 98
5.32.2 Transfer Format ....................................................................................................................................... 98
5.32.3 Transfer Sequence ................................................................................................................................... 98
5.32.4 Programming Restrictions ........................................................................................................................ 98
5.33 Terminate (F0h) .....................................................................................................................................................99
5.33.1 Command Prerequisites ........................................................................................................................... 99
5.33.2 Transfer Format ....................................................................................................................................... 99
5.33.3 Transfer Sequence ................................................................................................................................... 99
5.33.4 Programming Restrictions ........................................................................................................................ 99
5.34 Read Manufacturer/Device ID (90h) ....................................................................................................................100
5.34.1 Command Prerequisites ......................................................................................................................... 100
5.34.2 Transfer Format ..................................................................................................................................... 100
5.34.3 Transfer Sequence ................................................................................................................................. 100
5.34.4 Programming Restrictions ...................................................................................................................... 100
5.35 Quad I/O Read Manufacturer/Device ID (94h) .....................................................................................................101
5.35.1 Command Prerequisites ......................................................................................................................... 101
5.35.2 Transfer Format ..................................................................................................................................... 101
5.35.3 Transfer Sequence ................................................................................................................................. 101
5.35.4 Programming Restrictions ...................................................................................................................... 101
5.36 Read JEDEC ID (9Fh) .........................................................................................................................................102
5.36.1 Command Prerequisites ......................................................................................................................... 102
5.36.2 Transfer Format ..................................................................................................................................... 102
5.36.3 Transfer Sequence ................................................................................................................................. 102
5.36.4 Transfer Diagram ................................................................................................................................... 103
5.36.5 Programming Restrictions ...................................................................................................................... 104
5.37 Serial Flash Discoverable Parameters (5Ah) .......................................................................................................105
5.37.1 Command Prerequisites ......................................................................................................................... 105
5.37.2 Transfer Format ..................................................................................................................................... 105
5.37.3 Transfer Sequence ................................................................................................................................. 105
5.37.4 Programming Restrictions ...................................................................................................................... 105
5.37.5 SFDP Organization ................................................................................................................................ 105
Datasheet
2021-08-13
Revision H
6
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
6 Electrical Specifications .................................................................................................................................................. 106
6.1 Absolute Maximum Ratings ...................................................................................................................................106
6.2 DC and AC Operating Range ................................................................................................................................106
6.3 DC Characteristics for 1.65V to 3.6V .....................................................................................................................107
6.4 AC Characteristics - Maximum Clock Frequencies ................................................................................................107
6.5 AC Characteristics – All Other Parameters ............................................................................................................108
6.6 Program and Erase Characteristics .......................................................................................................................109
6.7 Power On Timing ...................................................................................................................................................110
6.8 AC Timing Diagrams ..............................................................................................................................................111
7 Ordering Information ....................................................................................................................................................... 113
8 Packaging Information ..................................................................................................................................................... 114
8.1 8S1 – JEDEC SOIC ...............................................................................................................................................115
8.2 8S2 – 8-lead EIAJ SOIC ........................................................................................................................................116
8.3 8MA3 – 2 x 3 UDFN ...............................................................................................................................................117
8.4 8-WLCSP — 8-ball 3 x 2 x 3 WLCSP ....................................................................................................................118
9 Revision History ............................................................................................................................................................... 119
Datasheet
2021-08-13
Revision H
7
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Figures
Figure 1: Block Diagram.......................................................................................................................................................... 10
Figure 2: Memory Package Types .......................................................................................................................................... 11
Figure 3: SPI Transfer — Command Only .............................................................................................................................. 15
Figure 4: SPI Transfer — Command and Address Only ......................................................................................................... 15
Figure 5: SPI Transfer — Command and Data Only — Read Operation................................................................................ 16
Figure 6: SPI Transfer — Command and Data Only — Write Operation................................................................................ 16
Figure 7: SPI Transfer — Command, Address, and Data — Read Operation with No Dummy Bytes.................................... 17
Figure 8: SPI Transfer — Command, Address, and Data — Read Operation with Dummy Bytes ......................................... 17
Figure 9: SPI Transfer — Command, Address, and Data — Write Operation ........................................................................ 18
Figure 10: Dual Output Read — 1-Pin Command, 1-Pin Address, and 2-Pin Data ................................................................ 18
Figure 11: Dual Output Write — 1-Pin Command, 1-Pin Address, and 2-Pin Data ................................................................ 18
Figure 12: Quad Output Transfer — 1-Pin Command, 1-Pin Address, and 4-Pin Data — Read Operation........................... 19
Figure 13: Quad Output Transfer — 1-Pin Command, 1-Pin Address, and 4-Pin Data — Write Operation ........................... 19
Figure 14: Quad I/O Transfer — 1-Pin Command, 4-Pin Address, and 4-Pin Data — Read Operation................................. 20
Figure 15: XiP Transfer — 1-Pin Command, 4-Pin Address, and 4-Pin Data — Initial Read (M[5:4] = 2’b10)....................... 21
Figure 16: XiP Transfer — 4-Pin Address, and 4-Pin Data — Subsequent Reads (M[5:4] = 2’b10) ...................................... 22
Figure 17: XiP Transfer — Command, 4-Pin Address, and 4-Pin Data — Write Operation.................................................... 23
Figure 18: AT25FF161A Device Block Memory Map.............................................................................................................. 24
Figure 19: AT25FF161A Device Block Memory Map — Page Program ................................................................................. 25
Figure 20: Flow Diagram of Nested Operations Example....................................................................................................... 33
Figure 21: Issuing a Terminate Command Before the Suspend Command has Completed .................................................. 36
Figure 22: Allowing Enough Time for the Suspend Operation to Complete............................................................................ 36
Figure 23: OTP Security Register Program and Lock............................................................................................................. 37
Figure 24: JEDEC Standard Hardware Reset......................................................................................................................... 38
Figure 25: AT25FF161A Register Structure............................................................................................................................ 40
Figure 26: Status Register Read Operation Showing 8-bit Address Field .............................................................................. 88
Figure 27: Status Register Write Operation Showing 8-bit Address Field............................................................................... 91
Figure 28: Status Register Lock Operation with Two Verification Bytes ................................................................................. 92
Figure 29: Resume from Deep Power Down or Ultra-Deep Power Down............................................................................... 95
Figure 30: Entering Ultra-Deep Power Down State................................................................................................................. 96
Figure 31: Enable Reset and Reset Command Sequence (SPI Mode) .................................................................................. 98
Figure 32: Read JEDEC ID ................................................................................................................................................... 104
Figure 33: AC Timing During Device Power Up.................................................................................................................... 110
Figure 34: AC Power-up Timing After a Brown-Out .............................................................................................................. 111
Figure 35: Serial Input Timing............................................................................................................................................... 111
Figure 36: Serial Output Timing ............................................................................................................................................ 111
Figure 37: WP Timing for Write Status Register Command.................................................................................................. 112
Figure 38: HOLD Timing – Serial Input ................................................................................................................................. 112
Figure 39: HOLD Timing – Serial Output .............................................................................................................................. 112
Datasheet
2021-08-13
Revision H
8
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Tables
Table 1: Pin Descriptions .........................................................................................................................................................12
Table 2: Bus Transfer Types....................................................................................................................................................14
Table 3: Protection Scheme (CMPRT = 0)...............................................................................................................................27
Table 4: Protection Bits (CMPRT 1).........................................................................................................................................28
Table 5: Entering DPD or UDPD Mode....................................................................................................................................30
Table 6: Exiting DPD or UDPD Mode.......................................................................................................................................30
Table 7: Resetting the Device During a Program or Erase Operation .....................................................................................31
Table 8: Encoding of Erase/Program Suspend Operations .....................................................................................................32
Table 9: Command Errors and Their Effect on the EE and PE Bits.........................................................................................34
Table 10: Address Field Encoding ...........................................................................................................................................41
Table 11: Status Register 1 Format .........................................................................................................................................42
Table 12: Status Register 2 Format .........................................................................................................................................43
Table 13: Status Register Protection During Normal Operation...............................................................................................45
Table 14: Status Register Protection During Reset..................................................................................................................45
Table 15: Status Register 3 Format .........................................................................................................................................46
Table 16: Status Register 4 Format .........................................................................................................................................47
Table 17: Status Register 5 Format .........................................................................................................................................48
Table 18: Command Listing .....................................................................................................................................................49
Table 19: Frequency and Number of Dummy Clocks Based on Command Type in Non-Wrap Mode (default) ......................57
Table 20: Frequency and Number of Dummy Clocks Based on Command Type in Wrap Mode (77h)...................................58
Table 21: Command Behavior During Sequential Programming Mode ...................................................................................63
Table 22: Command Behavior During Program/Erase or Program/Erase Suspend Operations..............................................69
Table 23: Encoding of Burst Wrap Bits ....................................................................................................................................73
Table 24: OTP Security Register 0 Bit Assignments................................................................................................................82
Table 25: OTP Security Register 1 Bit Assignments................................................................................................................82
Table 26: OTP Security Register 2 Bit Assignments................................................................................................................82
Table 27: OTP Security Register 3 Bit Assignments................................................................................................................82
Table 28: OTP Register Access Address Map.........................................................................................................................83
Table 29: Indirect Addressing of the Status Registers .............................................................................................................87
Table 30: Indirect Status Register Read Sequence.................................................................................................................88
Table 31: Indirect Addressing of the Status Registers .............................................................................................................90
Table 32: Indirect Status Register Write Sequence .................................................................................................................91
Table 33: Options for Exiting DPD and UDPD Modes .............................................................................................................94
Table 34: Manufacturer and Device ID Details.......................................................................................................................103
Table 35: Device ID Part 4 Variants — EDI String Value.......................................................................................................103
Table 36: Power On Timing Requirements ............................................................................................................................110
Table 37: Valid Ordering Codes for Operating Voltage 1.65 V to 3.6 V.................................................................................113
Datasheet
2021-08-13
Revision H
9
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
1
Block Diagram
Figure 1 shows a block diagram of the AT25FF161A device. The Interface Control Logic block connects to external device through
a set of pins. The state of these pins is distributed Interface Control Logic block to other blocks as necessary. The design also
contains a 16 Mbit serial Flash memory array, a 256-byte SRAM buffer, and an I/O Interface Unit that operates depending on the
type of data transfer mode.
Serial Flash Memory Array
CS
SCK
256-byte SRAM Buffer
SI (I/O0)
Interface
SO (I/O1)
Control Logic
WP (I/O2)
SPI
Dual
Quad
HOLD/RESET (I/O3)
Figure 1: Block Diagram
Datasheet
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Revision H
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DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
2
Package Pinout and Pin Descriptions
Figure 2 show the package pinouts for the following devices. Note that the Die Wafer Scale option is not shown.
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
VCC
VCC
CS
CS
HOLD/RESET (I/O3)
SO (I/O1)
SO (I/O1)
HOLD/RESET (I/O3)
WP (I/O2)
GND
SCK
WP (I/O2)
GND
SCK
SI (I/O0)
SI (I/O0)
8S1 8-lead SOIC Package (0.150”)
8S2 8-lead EIAJ SOIC Package (0.208”)
(Top View)
8MA3 8-pad Ultra-Thin DFN Package
2 x 3 x 0.6 mm (Top View)
VCC
A1
CS
A3
GND
B2
SO
C3
HOLD
C1
SI
D2
SCK
E1
WP
E3
8-ball WLCSP Package
3 x 2 x 3 ball matrix (bottom view)
Figure 2: Memory Package Types
Datasheet
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Revision H
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DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Table 1: Pin Descriptions
Asserted
State
Symbol
Name and Function
Type
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is
deasserted, the device is be deselected and normally be placed in standby mode
(not Deep Power-Down mode), and the SO pin is in a high-impedance state. When
the device is deselected, data are not accepted on the SI pin.
CS
Low
Input
A high-to-low transition on the CS pin is required to start an operation, and a low-to-
high transition is required to end an operation. When ending an internally self-timed
operation such as a program or erase cycle, the device does not enter the standby
mode until the completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to
control the flow of data to and from the device. Command, address, and input data
present on the SI pin is always latched in on the rising edge of SCK, while output
data on the SO pin is always clocked out on the falling edge of SCK.
SCK
-
Input
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for
all data input including command and address sequences. Data on the SI pin is
always latched in on the rising edge of SCK.
With the Multi I/O Read commands, the SI pin becomes an output pin (I/O0) in
conjunction with other pins to allow either two or four bits of data on (I/O1:0 or I/O3:0
to be clocked out on every falling edge of SCK.
Input/
Output
SI (I/O0)
-
)
Data present on the SI pin is ignored whenever the device is deselected (CS is
deasserted and the device is in the reset condition).
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the
SO pin is always clocked out on the falling edge of SCK.
With the Multi I/O Read commands, the SO pin remains an output pin (I/O1) in
conjunction with other pins to allow either two or four bits of data on (I/O1:0 or I/O3:0
to be clocked out on every falling edge of SCK.
Input/
Output
SO (I/O1)
)
-
The SO pin is in a high-impedance state whenever the device is deselected (CS is
deasserted and the device is in the reset condition).
WRITE PROTECT: The WP pin controls the hardware locking feature of the device.
When set, this bit prevents the Status Register from being written. This bit is used in
conjunction with other Status Register bits (CMPRT, BPSIZE, TB, and BP[2:0]) to
provide hardware protection of the memory array.
The WP pin is internally pulled-high and may be left floating if hardware controlled
protection is not used. However, it is recommended that the WP pin also be
externally connected to VCC whenever possible.
Input/
Output
WP (I/O2)
Low
When the QE bit in Status Register 2 is set, enabling quad output mode, the WP pin
becomes bidirectional and functions as the IO2 pin used to transmit address and/or
data, depending on the transfer mode.
Datasheet
2021-08-13
Revision H
12
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Table 1: Pin Descriptions (continued)
Asserted
State
Symbol
Name and Function
Type
HOLD / RESET: The HOLD pin is used to temporarily pause serial communication
without deselecting or resetting the device. While the HOLD pin is asserted,
transitions on the SCK pin and data on the SI pin are ignored and the SO pin is
placed in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a
Hold condition to start. A Hold condition pauses serial communication only and does
not have an effect on internally self-timed operations such as a program or erase
cycle.
With the Quad Output Byte/Page Program command (32h), the HOLD pin becomes
an input pin (I/O3) and, along with other pins, allows four bits (on I/O3-0) of data to be
clocked in on every rising edge of SCK. With the Quad-Output Read commands, the
HOLD Pin becomes an output pin (I/O3) in conjunction with other pins to allow four
bits of data on (I/O33-0) to be clocked in on every falling edge of SCK.
HOLD/
RESET
Input/
Output
Low
(I/O3)
To maintain consistency with the SPI nomenclature, the HOLD (I/O3) pin is
referenced as the HOLD pin unless specifically addressing quad output, in which
case it is referenced as I/O3.
The HOLD pin is internally pulled-high and may be left floating if the Hold function is
not used. However, it is recommended that the HOLD pin also be externally
connected to VCC whenever possible.
When the QE bit in the Status register is cleared, the IO3 pin can be configured
either as a HOLD pin or as a RESET pin depending on the state of the HOLD/
RESET bit 7 in Status Register 3. Note that when the QE bit is set, the HOLD or
RESET function is not available as this pin is used to transfer data.
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the
device. Operations at invalid VCC voltages can produce spurious results; do not
attempt.
VCC
-
-
Power
Power
GROUND: The ground reference for the power supply. Connect GND to the system
ground.
GND
Datasheet
2021-08-13
Revision H
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DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
3
Device Operation
This section describes the various data transfer modes supported by the device, as well as other system operations.
3.1 DATA TRANSFER MODES
The JEDEC specification uses a numerical system to indicate the type of transfer for a given command. The nomenclature for
this system is defined as (x-y-z) to indicate the number of active pins used for the command (x), address (y), and data (z). For an
example, a designation of 1-1-2 indicates that one pin (SI) is used to transfer the command, one pin (SI) for the address, and two
pins (SI and SO) for the data. The AT25FF161A supports the following transfer types.
Table 2: Bus Transfer Types
Transfer
Name
Pin(s) Used for
Command
Pin(s) Used for
Address
Pin(s) Used for
Data
Transfer
Type
Command
Address
Data
1-0-0
1-1-0
SPI
SPI
Yes
Yes
SI
SI
No
--
No
No
--
--
Yes
SI
SI (write)
SO (read)
1-0-1
SPI
Yes
SI
No
--
Yes
SI (write)
SO (read)
1-1-1
1-1-2
1-1-4
SPI
Yes
Yes
Yes
SI
SI
SI
Yes
Yes
Yes
SI
SI
SI
Yes
Yes
Yes
Dual Output
Quad Output
SI, SO
SI, SO, WP,
HOLD
SI, SO, WP,
HOLD
SI, SO, WP,
HOLD
1-4-4
0-4-4
Quad I/O
XiP
Yes
No
SI
--
Yes
Yes
Yes
Yes
SI, SO, WP,
HOLD
SI, SO, WP,
HOLD
As shown in the table above, the AT25FF161A supports the transfer formats below. These formats are described in the following
subsections:
Standard SPI Operation
Dual Output Operation
Quad Output Operation
Quad I/O Operation
XiP Operation
3.2 STANDARD SPI OPERATION
Standard SPI transfers are divided into three elements; command, address, and data. SPI mode support the following four transfer
types as described in Table 2.
Command only, no address or data (1-0-0)
Command and address only, no data (1-1-0)
Command and data only, no address (1-0-1)
Command, address, and data (1-1-1)
For standard SPI transfers, command and address are always transferred on the SI pin. For write operations, data is also
transferred on the SI pin. For read operations, data is transferred on the SO pin.
The AT25FF161A supports the two most common SPI modes, 0 and 3, meaning that data is always latched on the rising edge
of SCK and always output on the falling edge of SCK.
Datasheet
2021-08-13
Revision H
14
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
3.2.1 Command Only, No Address or Data (1-0-0)
The following diagram shows a command-only transfer. In this type of transfer no address or data are required. An example would
be the Chip Erase (60h/C7h) command. A 1-0-0 transfer type is shown in Figure 3.
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Figure 3: SPI Transfer — Command Only
3.2.2 Command and Address Only, No Data (1-1-0)
The following diagram shows a transfer with command and address only. In this type of transfer no data is required. An example
would be the Block Erase (20h) command, where the address indicates the location of the block to be erased.
The 1-1-0 transfer type is shown in Figure 4.
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Figure 4: SPI Transfer — Command and Address Only
Datasheet
2021-08-13
Revision H
15
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
3.2.3 Command and Data Only, No Address (1-0-1)
The following diagram shows a transfer with command and data only. In this type of transfer no address is required. An example
would be the Status Register Read (05h/35h/15h) and Status Register Write (01h/31h/11h) commands, where the command itself
indicates the location of the register. The 1-0-1 transfer type for a read operation is shown in Figure 5.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCK
SI
COMMAND
C
C
C
C
C
C
C
C
MSB
DATA OUT 1
DATA OUT 1
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
D
MSB
D
D
D
D
D
D
D
D
MSB
D
SO
Figure 5: SPI Transfer — Command and Data Only — Read Operation
The 1-0-1 transfer type for a write operation is shown in Figure 6.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
SI
COMMAND
DATA IN
C
C
C
C
C
C
C
C
D
D
D
D
D
D
D
D
MSB
MSB
HIGH-IMPEDANCE
SO
Figure 6: SPI Transfer — Command and Data Only — Write Operation
Datasheet
2021-08-13
Revision H
16
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
3.2.4 Command, Address, and Data (1-1-1)
The following diagram shows a command, address, and data transfer. In this type of transfer the command and address are
followed by one or more data types, depending on the command type.
Note that this type of transfer may contain one or more dummy bytes between the end of the address and the beginning of the
data output depending on the type of command. See Table 18 for more information.
The 1-1-1 transfer type for a read operation without dummy bytes is shown in Figure 7. An example would be the Read Array
(03h) command.
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Figure 7: SPI Transfer — Command, Address, and Data — Read Operation with No Dummy Bytes
The 1-1-1 transfer type for a read operation with dummy bytes is shown in Figure 8. An example would be the Fast Read Array
(0Bh) command. Note that eight dummy clocks are shown in the figure below for illustration purposes only. More than eight clocks
may be required depending on the type of operation and operating frequency.
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Figure 8: SPI Transfer — Command, Address, and Data — Read Operation with Dummy Bytes
The 1-1-1 transfer type for a write operation is shown in Figure 9. An example would be the Byte/Page Program (02h) command.
Datasheet
2021-08-13
Revision H
17
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
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Figure 9: SPI Transfer — Command, Address, and Data — Write Operation
3.3 DUAL OUTPUT OPERATION (1-1-2)
The AT25FF161A supports the dual output mode (1-1-2) transfer type which enhances overall throughput over the standard SPI
mode. This mode transfer command and address on the SI pin like in SPI mode, but the data is transferred on to the SI and SO
pins. This means that only half the number of clocks are required to transfer the data.
A dual output read operation is shown in Figure 10. An example of this operation would be a Dual Output Read (3Bh). Note that
this type of transfer may contain one or more dummy bytes between the end of the address and the beginning of the data output
depending on the type of command and the operating frequency. For more information, see the Command table in Section 5,
Commands and Addressing.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
6,ꢋꢌ6,2ꢍ
SO
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D
D
4
D
2
D
D
D
4
D
2
D
D
D
4
&
MS B
&
&
&
&
&
&
&
A
A
A
A
A
A
A
A
A
X
X
X
X
X
X
X
X
6
0
6
0
6
MS B
MS B
HIGH-IMPEDANCE
D
D
5
D
3
D
D
D
5
D
3
D
D
7
D
5
7
1
7
1
MS B
MS B
MS B
Figure 10: Dual Output Read — 1-Pin Command, 1-Pin Address, and 2-Pin Data
A dual output (1-1-2) write operation is shown in Figure 11. An example of this operation would be a Dual Output Byte/Page
Program (A2h).
CS
0
1
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39
SCK
6,ꢋꢌ6,2ꢍ
SO
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D
D
4
D
2
D
D
D
4
D
2
D
0
&
MS B
&
&
&
&
&
&
&
A
A
A
A
A
A
A
A
A
6
0
6
MS B
HIGH-IMPEDANCE
D
D
5
D
3
D
1
D
D
5
D
3
D
1
7
7
MS B
MS B
Figure 11: Dual Output Write — 1-Pin Command, 1-Pin Address, and 2-Pin Data
Datasheet
2021-08-13
Revision H
18
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
3.4 QUAD OUTPUT OPERATION (1-1-4)
The AT25FF161A supports the Quad Output which enhances overall throughput over the standard SPI and dual operating modes
by increasing the data transfer rate. In this mode, data is transferred on four pins; SI, SO, WP, and HOLD. This means that only
1/4th the number of clocks are required to transfer the data relative to standard SPI mode. This is known as a 1-1-4 transfer which
is defined as: 1-pin command, 1-pin address, 4-pin data (1-1-4)
In Quad Output the command (C) and address (A) are driven to the memory device on the SI (IO0) pin. During write operations,
the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins switched to inputs and the data is driven on all four pins, allowing four data
bits to be transferred on every clock. During read operations, once the command and address are transferred on the SI (IO0) pin,
the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins switched to outputs and the data is driven on all four pins, allowing four
data bits to be transferred on every clock.
A 1-1-4 Quad Output read operation is shown in Figure 12. An example of this operation would be a Quad Output Read (6Bh).
Note that this type of transfer may contain one or more dummy bytes between the end of the address and the beginning of the
data output depending on the type of command and the operating frequency. See Table 18 for more information.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
DATA DATA DATA DATA DATA
SCK
OUT 1 OUT 2 OUT 3 OUT 4 OUT 5
DUMMY
COMMAND
Address Bits A23-A0
C
C
C
C
C
C
C
C
A
A
A
A
A
A
A
A
A
X
X
X
X
X
X
X
X
D4 D0 D4 D0 D4 D0 D4 D0 D4 D0
D5 D1 D5 D1 D5 D1 D5 D1 D5 D1
D6 D2 D6 D2 D6 D2 D6 D2 D6 D2
I/O0
(SI)
High-impedance
High-impedance
High-impedance
I/O1
(SO)
I/O2
(WP)
D7 D3 D7 D3 D7 D3 D7 D3 D7 D3
I/O3
(HOLD)
MSB
MSB
MSB
MSB
MSB
Figure 12: Quad Output Transfer — 1-Pin Command, 1-Pin Address, and 4-Pin Data — Read Operation
A 1-1-4 Quad Output write operation is shown in Figure 13. An example of this operation would be a Quad Output Byte/Page
Program (32h).
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41
DATA DATA DATA DATA DATA
SCK
IN 1
IN 2
IN 3
IN 4
IN 5
COMMAND
Address Bits A23-A0
C
C
C
C
C
C
C
C
A
A
A
A
A
A
A
A
A
D4 D0 D4 D0 D4 D0 D4 D0 D4 D0
D5 D1 D5 D1 D5 D1 D5 D1 D5 D1
D6 D2 D6 D2 D6 D2 D6 D2 D6 D2
I/O0
(SI)
High-impedance
High-impedance
High-impedance
I/O1
(SO)
I/O2
(WP)
D7 D3 D7 D3 D7 D3 D7 D3 D7 D3
I/O3
(HOLD)
MSB
MSB
MSB
MSB
MSB
Figure 13: Quad Output Transfer — 1-Pin Command, 1-Pin Address, and 4-Pin Data — Write Operation
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
3.5 QUAD I/O OPERATION (1-4-4)
The AT25FF161A supports the Quad I/O mode which enhances overall throughput over the standard SPI and dual operation
modes by increasing the data transfer rate. In this mode, address and data are transferred on four pins; SI, SO, WP, and HOLD.
This means that only 1/4th the number of clocks are required to transfer the address and data relative to standard SPI mode. This
is known as a 1-4-4 transfer which is defined as: 1-pin command, 4-pin address, and 4-pin data (1-4-4)
In Quad I/O mode the command (C) is driven to the memory device on the SI (IO0) pin. During write operations, the SI (IO0), SO
(IO1), WP (IO2), and HOLD (IO3) pins switched to inputs and the address and data are driven on all four pins, allowing four bits
to be transferred on every clock. During read operations, once the command is transferred on the SI (IO0) pin, address is
transferred on the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins, allowing a 24-bit address to be transferred in only six clocks.
Once the address transfer is complete, these pins are switched to outputs and the data is driven on all four pins, allowing four
data bits to be transferred on every clock. Note that mode bits M[7:0] must not be in high-Z (tri-state) mode. For optimal perfor-
mance it is recommended to drive a value of 55h or FFh on these bits when not in XiP mode.
A 1-4-4 quad I/O read operation is shown in Figure 14. An example of this operation would be a Manufacturer/Device ID Read
(94h). Note that this type of transfer may contain one or more dummy bytes between the end of the address and the beginning
of the data output depending on the type of command and the operating frequency. See Table 18 for more information.
Command
Figure 14: Quad I/O Transfer — 1-Pin Command, 4-Pin Address, and 4-Pin Data — Read Operation
Datasheet
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
3.6 XIP MODE OPERATION
The XiP mode is similar to the Quad I/O mode in that both the address and data are transferred on all four pins, SI (IO0), SO
(IO1), WP (IO2), and HOLD (IO3). Using all four pins to transfer address and data allows XiP mode to reduce the overall number
of clocks required to complete the operation, thereby streamlining code execution.
The XiP mode is enabled by setting bit 2 (QE) of Status register 1, and bit 3 (XiP) of Status register 4. Setting the QE bit enables
Quad Output, allowing address and data to be transferred on all four pins. Setting the XiP bit enables continuous read mode,
allowing subsequent transfers to occur without the need for driving the command each time, controlled by mode bits M[5:4] as
explained below. Therefore, the initial EBh or E7h command requires the command to be driven, but for subsequent transfers the
command is not required.
The XiP mode is only used for the following commands:
— EBh: XiP mode initial read (1-4-4)
— EBh: XiP mode subsequent reads (0-4-4)
— E7h: XiP mode initial read with Doubleword Aligned (DWA) address (1-4-4)
— E7h: XiP mode subsequent reads with DWA address (0-4-4)
As shown above, the only difference between the EBh and E7h commands is that the E7h command is performed only on a
double-word aligned address boundary. The EBh command does not have this restriction. Note that mode bits M[7:0] must not
be in high-Z (tri-state) mode. For optimal performance it is recommended to drive a value of 55h or FFh on these bits when not
in XiP mode.
The Set Burst with Wrap (77h) command does not access the memory directly, but rather is used in conjunction with the EBh and
E7h commands to select 8-, 16-, 32-, or 64-Byte sections within a 256-byte page. The user selects the size by programming the
wrap bits as part of the 77h command. See the table in Section 5.13, Set Burst Wrap (77h) for more information.
When the EBh/E7h command is driven onto the bus, the associated data immediately following the address contains eight mode
bits, known as M[7:0]. Of these bits, M[5:4] are decoded and used by hardware to determine if the device is in XiP continuous
read mode. If the value on M[5:4] equals 2’b10, the device is placed into XiP mode to allow for continuous read operations to
occur, meaning that for subsequent operations the command field is not required. Each time a subsequent transfer is made, it
contains only the address and mode bits.
3.6.1 Initial Transfer and XiP Mode Detection (M[5:4])
The initial XiP transfer follows the 1-4-4 format, where the EBh or E7h command is transferred on the SI (IO0) pin, and address
and data are transferred on the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins. Because all four pins are used, the address
requires only six clocks to transfer. The initial 1-4-4 XiP mode transfer is shown in Figure 15.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
DATA
OUT 1
DATA
OUT 2
COMMAND
A23-A16 A15-A8
A7-A0
M7-M0
DUMMY
D0 D4
D0
I/O
0
D
4
C
C
C
C
C
C
C
C
A20
A16
A
12
A8
A4
A0 M4 M0
(SI)
MSB
D1 D5
D2 D6
D3 D7
I/O1
A
21
A
17
A
13
A
9
A
5
A
1
M
5
M
1
D
5
D1
(SO)
I/O2
D
6
D2
A22
A18
A14
A10
A
6
A2 M6 M2
(WP)
I/O3
D
7
D3
A
23
A19
A15
A11
A
7
A3 M7 M3
(HOLD)
Figure 15: XiP Transfer — 1-Pin Command, 4-Pin Address, and 4-Pin Data — Initial Read (M[5:4] = 2’b10)
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
3.6.2 Subsequent Transfers
Once XiP mode is detected, subsequent operations do not require the command to be transferred. After the data stream starts,
the user can deassert the CS pin. Once CS is deasserted, data output is suspended. Once CS is again driven low, only the address
and M[7:0] mode data are required because the device is already in XiP mode. Each time a new operation is transferred on the
bus, hardware decodes the M[7:0] bits. As long as M[5:4] have a value of 2’b10, the device is in XiP mode and it is not necessary
to transfer the command. Once M[5:4] ≠ 2’b10 (any value other than 2’b10), the operation completes and the device exits XiP
mode.
A subsequent 0-4-4 XiP mode transfer is shown in Figure 16.
CS
17
10 11 12 13 14 15 16
0
1
2
3
4
5
6
7
8
9
SCK
DATA
OUT 1
DATA
OUT 2
A23-A16 A15-A8
A7-A0
M7-M0
DUMMY
D0 D4
D0
I/O
0
D
4
A
20
A16
A
12
A8
A4
A0 M4 M0
(SI)
D1 D5
D2 D6
D3 D7
I/O1
A
21
A
17
A
13
A
9
A
5
A
1
M
5
M
1
D
5
D1
(SO)
I/O2
D
6
D2
A
22
A18
A14
A10
A
6
A2 M6 M2
(WP)
I/O3
D
7
D3
A
23
A19
A15
A11
A
7
A3 M7 M3
(HOLD)
Figure 16: XiP Transfer — 4-Pin Address, and 4-Pin Data — Subsequent Reads (M[5:4] = 2’b10)
Datasheet
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
3.6.3 Set Burst with Wrap
As mentioned above, the Set Burst with Wrap (77h) command is used in conjunction with the EBh and E7h commands to select
specific sections within a 256-byte page. When this command is transferred, the data field contains 8 wrap bits. Bits 6:4 of this
field determine the wrap length, which can be between 8 and 64 bytes. See Section 5.13, Set Burst Wrap (77h) for more
information.
Note that when the device receives the EBh/E7h command with M[5:4] = 2’b10, then the device enters XiP mode. While in the
XiP (0-4-4) mode (see Subsequent Transfers subsection above) the only command that the device can execute are EBh (or E7h).
This is mandatory since the command field for subsequent transfers does not exist.
During normal operation, the user sends the 77h command before entering XiP mode. If the user wants to issue a 77h command
after XiP mode has been entered (to change the wrap length/properties), they must exit the XiP mode by sending a 0-4-4
command with M[5:4] ≠ 2’b10. This exits XiP mode. Then the user can issue the 77h command.
The 77h command is a 1-4-4 XiP mode transfer, as shown in Figure 17.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
DON’T
CARE
DON’T
CARE
DON”T WRAP
CARE BIT
COMMAND
I/O0
C
C
C
C
C
C
C
C
W
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(SI)
MSB
X
X
X
I/O1
W5
(SO)
I/O2
X
X
X
X
X
X
X
X
X
X
W6
(WP)
I/O3
X
(HOLD)
Figure 17: XiP Transfer — Command, 4-Pin Address, and 4-Pin Data — Write Operation
See Section 5.13, Set Burst Wrap (77h) for more information.
3.7 MEMORY ARCHITECTURE
The memory array of the AT25FF161A memory array is divided into three levels of granularity comprised of blocks and pages;
64 kB blocks
32 kB blocks
4 kB blocks
The size of the erase blocks is optimized for both code and data storage applications, allowing both code and data segments to
reside in their own erase regions.
Datasheet
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Figure 18 illustrates the breakdown of each level and details the number of pages per block. The program operations to the
memory array can be done at the full page level or at the byte level (a variable number of bytes). Erase operations can be
performed at the chip or block level.
64 kB Block Erase (D8h)
32 kB Block Erase (52h)
4 kB Block Erase (20h)*
4 kB (B511)
4 kB (B510)
4 kB (B509)
4 kB (B508)
4 kB (B507)
4 kB (B506)
4 kB (B505)
4 kB (B504)
4 kB (B503)
4 kB (B502)
4 kB (B501)
4 kB (B500)
4 kB (B499)
4 kB (B498)
4 kB (B497)
4 kB (B496)
4 kB (B495)
to
Block Address Range
1FF000h - 1FFFFFh
1FE000h - 1FEFFFh
1FD000h - 1FDFFFh
1FC000h - 1FCFFFh
1FB000h - 1FBFFFh
1FA000h - 1FAFFFh
1F9000h - 1F9FFFh
1F8000h - 1F8FFFh
1F7000h - 1F7FFFh
1F6000h - 1F6FFFh
1F5000h - 1F5FFFh
1F4000h - 1F4FFFh
1F3000h - 1F3FFFh
1F2000h - 1F2FFFh
1F1000h - 1F1FFFh
1F0000h - 1F0FFFh
1EF000h - 1EFFFFh
to
32 kB
(block 63)
64 kB
(block 31)
32 kB
(block 62)
64 kB (block 30)
to
32 kB (block 61)
to
64 kB (block 1)
32 kB (block 2)
4 kB (B16)
4 kB (B15)
4 kB (B14)
4 kB (B13)
4 kB (B12)
4 kB (B11)
4 kB (B10)
4 kB (B9)
010000h - 010FFFh
00F000h - 00FFFFh
00E000h - 00EFFFh
00D000h - 00DFFFh
00C000h - 00CFFFh
00B000h - 00BFFFh
00A000h - 00AFFFh
009000h - 009FFFh
008000h - 008FFFh
007000h - 007FFFh
006000h - 006FFFh
005000h - 005FFFh
004000h - 004FFFh
003000h - 003FFFh
002000h - 002FFFh
001000h - 001FFFh
000000h - 000FFFh
32 kB
(block 1)
64 kB
4 kB (B8)
(block 0
4 kB (B7)
4 kB (B6)
4 kB (B5)
32 kB
4 kB (B4)
(block 0)
4 kB (B3)
4 kB (B2)
4 kB (B1)
4 kB (B0)
* B = Block
Figure 18: AT25FF161A Device Block Memory Map
Datasheet
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Figure 19 shows how one 4 kB block maps to sixteen 256 byte pages. The very top and bottom block ranges are shown.
1 - 256 Byte Page Program
4 kB Blocks
256 Byte Page
(02h)
4 kB (B511)
4 kB (B510)
4 kB (B509)
4 kB (B508)
4 kB (B507)
4 kB (B506)
4 kB (B505)
4 kB (B504)
4 kB (B503)
4 kB (B502)
4 kB (B501)
4 kB (B500)
4 kB (B499)
4 kB (B498)
4 kB (B497)
4 kB (B496)
4kB (B494)
to
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
.
1FFF00h - 1FFFFFh
1FFE00h - 1FFEFFh
1FFD00h - 1FFDFFh
1FFC00h - 1FFCFFh
1FFB00h - 1FFBFFh
1FFA00h - 1FFAFFh
1FF900h - 1FF9FFh
1FF800h - 1FF8FFh
1FF700h - 1FF7FFh
1FF600h - 1FF6FFh
1FF500h - 1FF5FFh
1FF400h - 1FF4FFh
1FF300h - 1FF3FFh
1FF200h - 1FF2FFh
1FF100h - 1FF1FFh
1FF000h - 1FF0FFh
.
.
.
.
.
.
4kB (B16)
4 kB (B15)
4 kB (B14)
4 kB (B13)
4 kB (B12)
4 kB (B11)
4 kB (B10)
4 kB (B9)
.
.
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
000F00h - 000FFFh
000E00h - 000EFFh
000D00h - 000DFFh
000C00h - 000CFFh
000B00h - 000BFFh
000A00h - 000AFFh
000900h - 0009FFh
000800h - 0008FFh
000700h - 0007FFh
000600h - 0006FFh
000500h - 0005FFh
000400h - 0004FFh
000300h - 0003FFh
000200h - 0002FFh
000100h - 0001FFh
000000h - 0000FFh
4 kB (B8)
4 kB (B7)
4 kB (B6)
4 kB (B5)
4 kB (B4)
4 kB (B3)
4 kB (B2)
4 kB (B1)
4 kB (B0)
Figure 19: AT25FF161A Device Block Memory Map — Page Program
Datasheet
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© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
3.8 MEMORY PROTECTION
The AT25FF161A device incorporates a robust memory protection scheme that allows memory locations to be protected down
to the 4 kB block level. The device provides the ability to globally lock all blocks in one operation, or to lock individual blocks on
a per-block basis.
3.8.1 Standard Memory Protection
The standard memory protection scheme is invoked by clearing bit 2 (WPS) of Status register 3. When this bit is cleared, the
AT25FF161A uses a combination of the following register fields to set the memory protection scheme:
CMPRT: When this bit is set, unprotected areas of memory become protected, and protected areas of memory become
unprotected. For example, when CMPRT = 0, a top 64 kB block can be protected while the rest of the array is not; when
CMP = 1, the same 64 kB block would become unprotected while the rest of the array becomes read-only. See bit 6 of Sec-
tion 4.4, Status Register 2 for more information.
BPSIZE: This bit works in conjunction with bits 4:2 (BP[2:0]) in Status register 1 to determine the size of the blocks to be
protected. Block sizes of 4 kB and 64 kB can be protected depending on the state of this bit. See bit 6 of Section 4.3, Status
Register 1 for more information.
TB: This bit indicates if the protection is from the bottom up of the top down of the memory. See bit 5 of Section 4.3, Status
Register 1 for more information.
BP[2:0]: This field can be programmed to protect all of the memory array, none of the memory array, or a portion of the
memory array. When that portion of the memory if protected, it is protected from the program and erase commands. See bit
4:2 of Section 4.3, Status Register 1 for more information.
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
The protection scheme differs based on the setting of the CMPRT bit described above. Table 3 shows the relationship between
the BPSIZE, BP[2:0], and TB bits when CMPRT = 0. The right-most column shows the protected address range. All addresses
not shown are unprotected.
Table 3: Protection Scheme (CMPRT = 0)
CMPRT
BPSIZE
TB
BP[2:0]
Protected Address Range
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
NONE
1F0000h - 1FFFFFh
1E0000h - 1FFFFFh
1C0000h - 1FFFFFh
180000h - 1FFFFFh
100000h - 1FFFFFh
000000h - 1FFFFFh
000000h - 1FFFFFh
NONE
000000h - 00FFFFh
000000h - 01FFFFh
000000h - 03FFFFh
000000h - 07FFFFh
000000h - 0FFFFFh
000000h - 1FFFFFh
000000h - 1FFFFFh
NONE
1FF000h - 1FFFFFh
1FE000h - 1FFFFFh
1FC000h - 1FFFFFh
1F8000h - 1FFFFFh
1F8000h - 1FFFFFh
000000h - 1FFFFFh
000000h - 1FFFFFh
NONE
000000h - 000FFFh
000000h - 001FFFh
000000h - 003FFFh
000000h - 007FFFh
000000h - 007FFFh
000000h - 1FFFFFh
000000h - 1FFFFFh
Datasheet
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Table 4 shows the relationship between the BPSIZE, BP[2:0], and TB bits when CMPRT = 1.
Table 4: Protection Bits (CMPRT 1)
CMPRT
BPSIZE
TB
BP[2:0]
Protected Address Range
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
000000h - 1FFFFFh
000000h - 1EFFFFh
000000h - 1DFFFFh
000000h - 1BFFFFh
000000h - 17FFFFh
000000h - 0FFFFFh
NONE
NONE
000000h - 1FFFFFh
010000h - 1FFFFFh
020000h - 1FFFFFh
040000h - 1FFFFFh
080000h - 1FFFFFh
100000h - 1FFFFFh
NONE
NONE
000000h - 1FFFFFh
000000h - 1FEFFFh ***
000000h - 1FDFFFh (1) (2)
000000h - 1FBFFFh(1) (2)
000000h - 1F7FFFh (2)
000000h - 1F7FFFh (2)
NONE
NONE
000000h - 1FFFFFh
001000h - 1FFFFFh*******
002000h - 1FFFFFh (3) (4)
004000h - 1FFFFFh (3) (4)
008000h - 1FFFFFh (4)
008000h - 1FFFFFh (4)
NONE
NONE
* When the 32 kB Erase command is used, the protected region is 0x00_0000 - 0x1F_7FFF.
** When the 64 kB Erase command is used, the protected region is 0x00_0000 - 0x1E_FFFF.
*** When the 32 kB Erase command is used, the protected region is 0x00_8000 - 0x1F_FFFF.
**** When the 64 kB Erase command is used, the protected region is 0x01_0000 - 0x1F_FFFF.
Datasheet
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© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
3.8.2 Individual Block Lock and Unlock
Also to the standard protection scheme described in the previous subsection, the AT25FF161A device also provides the ability
to lock individual memory locations. Protection of memory locations can be applied individually using the Individual Block Lock
(36h) command and the Individual Block Unlock (39h) command. Note that in the AT25FF161A device all lock bits are set by
default, making all memory locations protected. The user must execute a series of one or more Individual Block Unlock (39h)
commands to unlock the desired memory locations.
The individual memory protection scheme is invoked by setting bit 2 (WPS) of status register 3. When this bit is set, the
AT25FF161A uses the Individual Block Lock (36h) command that provides the address of the 4 kB or 64 kB block to be locked.
See Table 15 for more information on the WPS bit.
Figure 18 above shows the address ranges for each 4 kB block corresponding to the top and bottom 64 kB blocks of the memory
map. The appropriate 24-bit address is driven on the SI pin after the 36h command. After decoding the command, hardware reads
the address and sets the appropriate lock bit for that 4 kB block.
Note that the ability to lock 4 kB blocks only applies to the top and bottom 64 kB blocks of the map. This corresponds to blocks
0 and 31. For 64 kB blocks 1 - 30, the blocks can only be locked on the 64 kB boundary (1 lock bit per 64 kB). This equates to a
total of 62 lock bits;
16 bits, one per 4 kB sub-block in the top 64 kB block
16 bits, one per 4 kB sub-block in the bottom 64 kB block
30 bits, one each for 64 kB blocks 1 - 30
See Section 5.17, Individual Block Lock (36h) and Section 5.18, Individual Block Unlock (39h) for more information.
3.8.3 Global Block Lock and Unlock
In addition to individual block protection of memory locations as described in the previous subsection, the AT25FF161A also
allows for the blocks to be locked and unlocked globally using the Global Block Lock (7Eh) and the Global Block Unlock (98h)
commands. Note that in the AT25FF161A device all lock bits are set by default, making all memory locations protected. The user
must execute a Global Unlock Block command to unlock the memory locations.
See Section 5.20, Global Block Lock (7Eh) and Section 5.21, Global Block Unlock (98h) for more information.
3.8.4 Reading the State of the Lock Bits
In addition to globally or individually locking and unlocking selected memory blocks as described above, the AT25FF161A device
allows the user to poll any block in memory to determine if it has been locked. This is accomplished by executing either the 3Ch
or 3Dh command, along with the 24-bit address. Both of these commands perform the exact same operation and can be used
interchangeably.
Once this information is decoded, hardware fetches the 8-bit lock field from the requested location and outputs this information
onto the SO pin. The most significant bit (MSB) of the value is transferred first, and the least significant bit (LSB) is transferred
last. If the LSB is 1, the corresponding block is locked and no erase or program operation can be executed to that block. If the
LSB is 0, the block or section is unlocked and program/erase operations are allowed. See Section 5.19, Read Block Lock (3Ch/
3Dh) for more information.
3.9 POWER DOWN CONSIDERATIONS
The AT25FF161A device supports the Deep Power Down (B9h) and Ultra Deep Power Down (79h/B9h) modes. Also, bit 7 (PDM)
of Status register 4 (SR4) can be used to select either of these modes using the B9h command. The 79h command is provided
for backward compatibility.
There are three ways to enter power down mode:
1. Set the PDM bit in SR4 (logic 1) and execute the B9h command to place the device into Deep Power Down (DPD) mode.
In this mode it is possible to execute the Resume from Power Down (ABh) command or Enable Reset (66h) and Reset
Device (99h) commands in order to exit DPD mode. The device could also be reset by JEDEC reset, hardware reset, or
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power-on-reset in order to exit DPD mode. The exit from DPD mode time is defined by the tRDPD timing parameter in the
AC specifications section of this document. See Section 3.9.2 below. Note that in the AT25FF161A device, simply deas-
serting CS as in other devices does not exit DPD mode.
2. Clear the PDM bit in SR4 (logic 0) and execute the B9h command to place the device into Ultra Deep Power Down (UDPD)
mode. To exit this mode, it is necessary to execute the Resume from Ultra-Deep Power Down (ABh) command or a JEDEC
reset, hardware reset, or power-on-reset to initiate an internal reset of the device. The resume from UDPD mode recovery
time is defined by the tRUDPD timing parameter in the AC specifications section of this document. See Section 3.9.2 below.
Note that in the AT25FF161A device, simply deasserting CS as in other devices does NOT exit UDPD mode.
3. Execute the 79h command to place the device into Ultra Deep Power Down (UDPD) mode. If this command is used, the
state of the PDM bit in SR4 is ignored. This mode allows for software backward compatibility. A device reset is required
to exit UPDP mode. In this mode it is necessary to execute the Resume from Ultra-Deep Power Down (ABh) command
or a JEDEC reset, hardware reset or power-on-reset to initiate an internal reset of the device. The exit from UDPD mode
recovery time is defined by the tRUDPD timing parameter in the AC specifications section of this document. See Section
3.9.2 below for more information on exiting power down mode.
3.9.1 Entering Power Down Mode
The conditions for entering DPD or UDPD mode are shown in the Table 5. The PDM column indicates the state of the Power
Down Mode bit in Status Register 4.
Table 5: Entering DPD or UDPD Mode
Power Down Exit
Recovery Time
Command
PDM bit
Power Down Mode
B9h
B9h
79h
1
0
x
Deep Power Down
Ultra Deep Power Down
Ultra Deep Power Down
Short
Long
Long
3.9.2 Exiting Power Down Mode
The following methods can be used to exit DPD or UDPD mode.
Table 6: Exiting DPD or UDPD Mode
Terminate
Power Down
Mode
Exit
Command
Power On JEDEC
Reset
Hardware
66h/99h
Status
After Exit
Command PDM bit
Reset Reset Pin 1 Command
(F0h)
B9h
B9h
79h
1
0
x
DPD
UDPD
UDPD
ABh 2
ABh 3
ABh 3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
Idle
N
Idle
N
Idle
1. Hardware reset function must be enabled by software before entering the Power Down mode. See bit 7 of Status Register 3.
2. Executing the ABh command in DPD mode returns the device to an idle state. The SRAM contents are retained.
3. Executing the ABh command in UDPD mode causes the device to initiate an internal reset sequence.The SRAM contents are undefined.
3.9.3 ABh Command
Executing the ABh command while in the Deep Power Down (DPD) mode causes the device to exit DPD and return back to an
idle state. This command does not reset the device and no data is lost. Executing the ABh command while in the Ultra-Deep
Power Down (UDPD) mode causes the device to perform an internal reset.
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3.9.4 Device Resets
In addition to theABh command described above, performing a Power On Reset (POR), a JEDEC reset, or asserting the hardware
reset pin (RESET) also causes the device to exit DPD or UDPD mode.
3.9.5 Enable Reset (66h) / Reset (99h) Command
As shown in Table 6, the 66h/99h reset command is accepted in DPD mode. The device does not exit UDPD mode, regardless
of whether the device entered UDPD mode using the B9h command or the 79h command. To exit UDPD mode, the device must
be reset as described in the previous subsections.
3.9.6 Terminate Command (F0h)
The Terminate (F0) command does not cause exit from DPD or UDPD modes. To exit DPD or UDPD mode still requires either
the ABh command, or resetting the device as described in the previous subsections.
3.9.7 Reset During Program and Erase Commands
The AT25FF161A device supports the following program and erase operations.
Program operations include:
Byte/Page Program (02h)
Sequential Program (AFh/ADh)
Dual Output Byte/Page Program (A2h)
Quad Output Byte/Page Program (32h)
Program Security Register (9Bh)
Erase operations include:
4 kB Block Erase (20h)
32 kB Block Erase (52h)
64 kB Block Erase (D8h)
Chip Erase (60h/C7h)
These commands are affected when resetting the device, as shown in Table 7. In this table, a ‘Y’ entry indicates that the device
is reset when that type of reset occurs during the corresponding command. A ‘N’ entry indicates that the operation is terminated,
but the device is not reset. For example, when the F0h command is executed during a program or erase operation, the operation
is halted, but the device is not reset.
Table 7: Resetting the Device During a Program or Erase Operation
Hardware
Command Type
Power On Reset
JEDEC Reset
66h/99h Command Terminate (F0h)
Reset Pin
Program
Erase
Y
Y
Y
Y
Y
Y
Y
Y
N
N
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3.10 ERASE/PROGRAM SUSPEND CONSIDERATIONS AND NESTED OPERATIONS
The AT25FF161A device provides three status register bits to manage program and erase suspend operations.
SUSP — Status Register 2, bit 7. The SUSP bit is set by hardware and indicates that the program or erase operation has
been suspended.
ES — Status Register 5, bit 3. The ES bit is set by hardware whenever an erase operation is suspended.
PS — Status Register 5, bit 2. The PS bit is set by hardware whenever a program operation is suspended.
These three bits work in conjunction to define the state of a suspend operation, as shown in Table 8.
In this table, the SUSP is a logical OR of the ES and PS bits. When either the ES or PS bit is set, the SUSP bit is set. When both
of the ES and PS bits are cleared, the SUSP bit is cleared.
These bits relate to the flow diagram in Figure 20 below as follows: when the erase operation is suspended, hardware sets the
ES bit. When the program operation is suspended, hardware sets the PS bit. Once the program operation is complete, hardware
clears the PS bit. Finally, when the erase operation is completed, hardware clears the ES bit.
Table 8: Encoding of Erase/Program Suspend Operations
SUSP
ES
0
PS
0
Status
0
1
1
1
No suspend operation in progress.
0
1
Program suspend operation in progress.
Erase suspend operation in progress.
Nested erase/program suspend operation in progress.
1
0
1
1
3.10.1 Nested Operations
The AT25FF161A device supports nested erase and program suspend operations. An erase operation can be suspended and a
program operation started. This operation can then also be suspended and another operation commenced, such as a read. After
the read operation is complete, the program operation can be resumed. Once the program operation is completed, the erase
operation can be resumed. Nested operations adhere to the following constraint:
Suspending an erase operation followed by a program operation is supported
Suspending a program operation followed by an erase operation is NOT supported
The erase operation must be suspended first, followed by suspension of the program operation.
Figure 20 shows an example flow diagram of a nested operation.
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Execute D8h
Execute the D8h command to
64 KB Block Erase
initiate a 64 KB erase operation.
Execute 75h
64 KB Block Erase Suspend
Execute the 75h command to suspend
the 64 KB block erase operation.
Execute 02h
Byte/Page Program
Execute the 02h command to initiate a
byte/page program operation.
Execute 75h
Byte/Page Program Suspend
Execute the 75h command to suspend
the byte/page program operation.
Execute 03h
Read Array Operation
Execute the 03h command to initiate a
read array operation.
Check to see if the read array operation
is complete. The suspended page
program operation cannot be resumed
until the 03h command has completed.
N
Is 03h Done?
Y
Once the 03h read array command has
completed, the suspended program
operation can be resumed using the 7Ah
command.
Execute 7Ah
Program Resume Operation
Check to see if the byte/page program
operation is complete. The suspended
64 KB erase operation cannot be
resumed until the 02h command has
completed.
N
Is Program
Op Done?
Y
Once the 02h byte/page program
command has completed, the
Execute 7Ah
suspended erase operation can be
resumed using the 7Ah command.
Erase Resume Operation
Check to see if the 64 KB erase
operation is complete.
N
Is Erase Op
Done?
Y
Nested
Operation
Complete
Figure 20: Flow Diagram of Nested Operations Example
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3.10.2 Program and Erase Errors
The AT25FF161A device provides two Status register bits to indicate program and erase errors.
EE — Status Register 4, bit 4. The EE bit is set by hardware whenever an error occurs during an erase operation
PE — Status Register 4, bit 5. The PE bit is set by hardware whenever an error occurs during a program operation
When a new program or erase command is accepted by the device, hardware clears the EE or PE bits respectively depending
on the command. The device clears the EE bit when a new Block Erase or Chip Erase command is accepted. The device clears
the PE bit when a new Byte/Page Program, Sequential Programming, Program OTP Security Register, Write Status Register, or
Status Register Lock command is accepted. If an error is detected during the command execution, then the EE or PE flag is set.
These flags hold their contents even if the program/erase operation is suspended. Note that the Resume command does not
change the state of the EE and PE bits. If a Terminate command is issued while the device is busy (executing program/erase),
then the PE or EE flag is set.
The PE and EE bits are volatile, meaning that any reset operation clears these bits. The ABh command is used to exit Deep
Power Down (DPD) or Ultra-Deep Power Down (UDPD) mode. If the device is in DPD mode and the user issues the ABh
command, then the device exits DPD mode but does not change the state of the PE and EE bits. However, if the ABh command
is executed and the device exits from UDPD mode, then the device initiates a reset, which causes both the PE and EE bits to be
cleared.
When an error occurs during a given command, the EE and PE bits are set, as shown in Table 9. Note that for any of the commands
where a ‘Yes’ appears in the EE or PE columns, when a new command is issued, the EE or PE bit is cleared. Therefore, when
the bit is set initially due to an error being detected, it is incumbent on software to detect when these bits are set and take the
necessary steps to determine the exact error.
Table 9: Command Errors and Their Effect on the EE and PE Bits
Command Name
Command Code
Sets the EE Bit
Sets the PE Bit
Read Array
03h, 3Bh, 6Bh, EBh, E7h
No
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
No
No
No
No
No
No
No
No
No
No
Yes
No
No
No
Yes
Yes
Block Erase
20h, 52h, D8h
60h, C7h
02h, A2h, 32h
ADh, AFh
B0h, 75h
D0h, 7Ah
06h
Chip Erase
Byte/Page Program
Sequential Programming
Program/Erase Suspend
Program/Erase Resume
Write Enable
Write Disable
04h
Volatile Write Enable
Individual Block Lock
Individual Block Unlock
Global Block Lock
50h
36h
39h
7Eh
Global Block Unlock
Read Block Lock Status
Program OTP Security Register
Read OTP Security Register
Read Status Registers (direct)
Read Status Registers (indirect)
Write Status Registers (direct)
Write Status Registers (indirect)
98h
3Ch, 3Dh
9Bh
4Bh
05h, 35h, 15h
65h
01h, 31h, 11h
71h
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Table 9: Command Errors and Their Effect on the EE and PE Bits (continued)
Command Name
Command Code
Sets the EE Bit
Sets the PE Bit
Status Register Lock
6Fh
No
Yes
Yes
Yes
Terminate
F0h
(if Erase command is
terminated)
(if Program command is
terminated)
Enable Reset
66h
99h
No
No
Reset Device
Cleared on POR
Cleared on POR
Read Mfg ID and Device ID
Deep Power Down
9Fh, 90h, 94h
B9h
No
No
No
No
No
No
Resume from Deep Power Down
ABh
Resume from Ultra Deep
Power Down
ABh
Cleared on POR
Cleared on POR
Ultra Deep Power Down
Read SFDP
79h
5Ah
77h
No
No
No
No
No
No
Set Burst with Wrap
3.10.3 Suspending and Terminating a Program or Erase Operation
Program Operation
A self-timed program operation can be suspended using the Suspend (75h) command and terminated using the Terminate (F0h)
command. The device responds to either of these commands by initiating a sequence which completes some internal sub-
operations, brings the internal voltage supplies to their quiescent state, saves the intermediate address counters and states, and
sets either the PS (Program Suspend) bit in status register 4 in the case of a Suspend command, or the PE (Program Error) bit
in status register 5 in case of the Terminate command.
When the user issues the Suspend command, the device requires a period of time equal to tSUS before the BUSY flag goes low
and the PS flag goes high. Similarly, when the user issues the Terminate command the device requires a period of time equal to
tSWTERM before the BUSY flag goes low and the PE flag goes high.
If the user issues the Suspend command, and then issues the Terminate command before the device has completed the internal
suspend operation, the device honors the Terminate command and sets the PE flag. The PS flag is not set, and the BUSY flag
is cleared. At this point the self-timed command that was terminated cannot be resumed, and the region of the memory that was
being programmed/erased is left in an intermediate state.
Erase Operation
A self-timed erase operation can be suspended using the Suspend (75h) command and terminated using the Terminate (F0h)
command. The device responds to either of these commands by initiating a sequence which completes some internal sub-
operations, brings the internal voltage supplies to their quiescent state, saves the intermediate address counters and states, and
sets either the ES (Erase Suspend) bit in status register 4 in the case of a Suspend command, or the EE (Erase Error) bit in status
register 5 in case of the Terminate command.
When the user issues the Suspend command the device requires a period of time equal to tSUS before the BUSY flag goes low
and the PE flag goes high. Similarly, when the user issues the Terminate command the device requires a period of time equal to
tSWTERM before the BUSY flag goes low and the EE flag goes high.
If the user issues the Suspend command, and then issues the Terminate command before the device has completed the internal
suspend operation, the device honors the Terminate command and sets the EE flag. The ES flags is not set, and the BUSY flag
is cleared. At this point the self-timed command that was terminated cannot be resumed, and the region of the memory that was
being programmed/erased is left in an intermediate state.
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This concept is shown in Figure 21.
BUSY
CSB
Terminate
Suspe
Command
Stop
EE/PE
ES/PS
Figure 21: Issuing a Terminate Command Before the Suspend Command has Completed
Terminate After Suspend
If the time between the Suspend command and the Terminate command is large enough, then the device may finish the internal
suspend operation before the Terminate command is received. In this case, the device clears the BUSY bit in Status register 1,
and the ES/PS flag in Status register 5 is set. Now when the device receives the Terminate command, it is ignored by the hardware.
This concept is shown in Figure 22.
BUSY
CSB
Terminate
Command
Suspend
Stop
EE/PE
ES/PS
Figure 22: Allowing Enough Time for the Suspend Operation to Complete
If the user wishes to perform another program operation, they must check the status of both the PS and PE flags in Status registers
4 and 5 respectively to determine the next action.
If the PS bit is cleared and the PE bit is set, the user can issue a new Program command. Note that previous Program command
that was terminated leaves that region of memory in an intermediate state, and it is recommended to erase this region of memory
before attempting to reprogram it.
If the ES/PS bit is set, then the user cannot issue another Program/Erase command. The user must first issue a Resume command
to re-start the suspended program operation, then either allow it to run to completion or terminate it using the Terminate command.
The user can now issue a new Program/Erase command.
3.10.4 Terminating a Non-Volatile Operation in Progress
The Terminate (F0h) command, the Software Reset command (66h + 99h), the hardware reset (RESET) pin, and the JEDEC
Reset are ways to terminate any on-going internal self-timed program/erase operation (and in some cases reset the device).
However, abruptly terminating a Status Register Write, Status Register Lock, or OTP Security Register Program command is not
desirable as this may leave these non-volatile registers in an indeterminate state.
Therefore when the device is busy executing the Status Register Write, the Status Register Lock or the OTP Security Register
Program command, then the Terminate command is ignored. The software reset, hardware reset, and JEDEC reset actions are
delayed until after the internal self-timed operations are completed; once the internal operation is completed the device is reset.
See Section 3.12 for more information on how to perform a JEDEC hardware reset.
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3.11 OTP SECURITY REGISTER LOCK
The AT25FF161A device supports four 128-byte OTP security registers. One register is programmed by Dialog Semiconductor
at the factory and is always locked. The other three OTP registers can be programmed by the user and become locked whenever
any bit in the most significant byte of that register is written. In response to this write operation, hardware writes bits 5:3 (SL3:SL1)
of Status register 2 to indicate that the corresponding register has been locked. Software can read this field to determine which
registers have been locked.
Each byte of each register can be written using address bits 8:0 that are driven with the Program OTP Security register command
(9Bh). See Table 24 in Section 5.22, Program Security Register (9Bh) for an exact encoding of these address bits.
This concept is shown in Figure 23. In this figure, A[8:7] are used to select between the four OTP Security registers, and A[6:0]
are used to select one of the 128 bytes within that register. A value of 7’b1111111 on A[6:0] indicates an access to the MSB of
that register, as shown below.
Software programs any bit in
the most significant byte of
OTP Security register 3.
Software programs any bit in
the most significant byte of
OTP Security register 2.
No programming allowed. OTP
register 0 is programmed by
Adesto at the factory. The value
in this register can be read by
executing the 4Bh command.
Software programs any bit in
the most significant byte of
OTP Security register 1.
A[8:0] = 111111111
A[8:0] = 101111111
A[8:0] = 011111111
Byte number
Byte number
Byte number
Byte number
511
510:385
384
383
382:257
256
255
254:129
128
127
126:1
0
OTP Register 3
User-Defined
OTP Register 2
User-Defined
OTP Register 1
User-Defined
OTP Register 0
Factory Programmed by Adesto
Hardware sets
bit 4 of SR2
Hardware sets
bit 5 of SR2
Hardware sets
bit 3 of SR2
SL3 SL2 SL1
7
5
4
3
0
Status Register 2
Figure 23: OTP Security Register Program and Lock
3.12 STANDARD JEDEC HARDWARE RESET
The JEDEC hardware reset sequence does not use the SCK pin. The SCK pin must be held low (mode 0) or high (mode 3)
through the entire reset sequence. This prevents any confusion with a command, as no command bits are transferred.
A reset is commanded when the data on the SI pin is 0101 on four consecutive positive edges of the CS pin with no edge on the
SCK pin throughout. This is a sequence where
1. CS is driven active low to select the device
2. Clock (SCK) remains stable in either a high or low state
3. SI is driven low by the bus master, simultaneously with CS going active low. No SPI bus slave drives SI during CS low
before a transition of SCK
4. CS is driven inactive. The slave captures the state of SI on the rising edge of CS
The above steps are repeated 4 times, each time alternating the state of SI.
After the fourth CS pulse, the slave triggers its internal reset. SI is low on the first CS, high on the second, low on the third, high
on the fourth. This provides a value of 5h, unlike random noise. Any activity on SCK during this time halts the sequence and a
Reset is not generated.
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After a JEDEC hardware reset while the device is in Ultra-Deep Power Down (UDPD) mode, the SRAM buffer resets to an
undefined value. Hardware resets all volatile status registers, including the block protection bits, to their default values.
After a JEDEC hardware reset while the device is in any other mode than UDPD mode, the SRAM buffer keeps the values it had
prior to Reset, with the following exception: If the reset sequence is initiated during an update of the SRAM buffer, the contents
of the SRAM buffer may be corrupted. Hardware resets all volatile status registers, including the block protection bits, reset to
their default values.
All non-volatile status registers keep the value they had prior to reset, with the following exception: If the reset sequence is initiated
during a write to a non-volatile status register, the value of that register may be corrupted.
The device always reverts to standard SPI mode after JEDEC hardware reset. Figure 24 illustrates the timing for the JEDEC
hardware reset operation.
tRUDPD
Figure 24: JEDEC Standard Hardware Reset
3.13 CHIP SELECT RESTRICTIONS
The CS pin is used to start and end operations in the device. Once the CS pin is asserted and the operation begins, it can only
be deasserted on a byte boundary. If the CS pin is deasserted on a non-byte boundary, the operation is ignored.
For example, when executing the ABh command to exit power down mode, only the command is required. No address and data
are required to perform this operation. Therefore, only eight clocks are required to transfer the command. If the CS pin is raised
after the 8th clock (most significant bit of the command is transferred), hardware performs the operation. If the CS pin is raised
after the 9th or 10th clock (not a byte boundary), the operation is ignored and no ABh command is executed.
Similarly, if the ABh command is used to fetch the device ID, once the CS pin is asserted, 40 clock cycles are required: 8 clocks
for the command, 24 dummy clocks, and 8 clocks to shift out the device ID. If the CS pin is raised after the 40th clock, hardware
transfers the ID information, exits power down mode, and completes the operation. However, if the CS pin is raised on the 41st
or 42nd clock (not a byte boundary), the ID information is still returned as that occurred in clocks 32 - 40, but the device does not
exit power down mode.
3.14 HOLD / RESET FUNCTION
The AT25FF161A device provides a configurable HOLD/RESET pin. This pin can be configured to operate as either a HOLD pin,
or as a device RESET pin, by programming bit 7 (HOLD/RESET) of Status register 3. When this bit is cleared, the HOLD/RESET
pin functions as an active low HOLD pin. When this bit is set, the HOLD/RESET pin functions as a active low device RESET pin.
The HOLD/RESET function is only valid in the SPI and dual output mode of operation. When bit 1 (QE) of Status register 2 is set,
indicating the device is in either Quad Output, quad I/O mode, or XiP mode. In this case the HOLD/RESET functions are not
available and the pin functions as the I/O3 data pin.
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When configured as a RESET pin, no commands are accepted while the pin is low and the device is in reset.
Configuring the pin for the HOLD function allows an operation to be paused, then resumed when the HOLD pin is deasserted.
Once the HOLD pin is asserted (with CS low), the HOLD function takes effect on the next falling edge of SCK. Conversely, once
the HOLD pin is deasserted, the HOLD function is removed on the next falling edge of SCK. Note that the CS pin must be low
for the entire time in which the HOLD operation is in progress.
The HOLD function can be used in situations where the clock and data signals of the AT25FF161A device are shared with other
external agents, allowing the device to share the bus with other high priority events such as interrupts or other events that need
immediate attention. Once the condition is resolved, the HOLD pin can be deasserted, allowing the operation to resume.
During the time the HOLD pin is asserted, the Serial Output (SO) pin is forced to the high-impedance state. The state of the Serial
Input (SI) and Serial Clock (SCK) pins are ignored. Note that the CS pin must be low for the entire time in which the HOLD
operation is in progress.
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4
Status Registers
The device contains five Status registers (SR) described in the following subsections. The Status registers can be read to deter-
mine the device's ready/busy status, as well as the status of many other functions such as hardware locking and software
protection.
4.1 REGISTER STRUCTURE AND UPDATES
In the AT25FF161A device there are two sets of Status registers. One set is implemented in hardware and is accessed as Status
registers 1 - 5. These are known as volatile registers as they lose their data during a device reset. Also, the device keeps a copy
of the Status registers in memory. These are known as non-volatile registers because they are stored in the Flash and are not
affected by a device reset. On power up, the non-volatile contents of the memory are copied to the Status registers. See Section
4.2.2 for more information on volatile and non-volatile register types.
The AT25FF161A provides two methods for updating the Status Registers. When the Write to Status Register command is
preceded by the Volatile Status Register Write Enable (50h) command, only the flip-flops holding the Status register bits are
updated; the non-volatile memory dedicated to the Status registers is not updated. When the Write to Status Register command
is preceded with a Write Enable (06h) command, then both the flip-flops holding the Status register bits and the non-volatile
memory dedicated to the Status registers are updated. This concept is shown in Figure 25.
The main difference between these two commands is the time required to execute them. Accesses to memory are much slower
by default. So for the 50h command, the write is to the volatile Status registers only which is very fast. For the 06h command, the
write is not only to the Status registers, but also to non-volatile memory which is much slower.
50h
Status
Registers
06h
Power Up
Memory
Figure 25: AT25FF161A Register Structure
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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4.2 REGISTER ACCESSES
This section describes the various ways to access the AT25FF161A Status registers. The AT25FF161A incorporates five Status
registers. Each of these registers can be written or read using both the direct and indirect addressing methods as described in
Section 4.2.1. Also, the device supports both volatile and non-volatile registers as described in Section 4.2.2.
4.2.1 Direct and Indirect Addressing
The AT25FF161A device supports both direct and indirect addressing for accessing the Status registers. The indirect addressing
method can be used for all five Status registers, and the direct addressing for the first three Status registers. This means that
Status registers 4 - 5 can only be accessed using the indirect addressing method.
Historically, Dialog Semiconductor products have supported at most three Status registers. These registers have been accessed
using the direct addressing method, where every register has a specific command used to access it and perform read or write
operations. An example of these commands is as follows:
05h: Read Status Register 1
35h: Read Status Register 2
15h: Read Status Register 3
01h: Write Status Register 1
31h: Write Status Register 2
11h: Write Status Register 3
The above commands have been retained to provide backward compatibility with existing software. In addition to the direct
method, the AT25FF161A device also provides an indirect method. In the indirect method, a single command (65h) is used to
execute a read operation on all of the Status registers. Another command (71h) is used to execute a write operation on all of the
Status registers. Once the command is provided, an 8-bit address field is used to determine which register to access. The
encoding of the address field is shown in Table 10.
Table 10: Address Field Encoding
Command
Address
Action
01h
02h
03h
04h
05h
01h
02h
03h
04h
05h
Read Status Register 1
Read Status Register 2
Read Status Register 3
Read Status Register 4
Read Status Register 5
Write Status Register 1
Write Status Register 2
Write Status Register 3
Write Status Register 4
Write Status Register 5
65h
71h
Note that by using the indirect address method, an address width of 8 bits indicates that up to 256 registers can be accessed,
allowing for future expansion without requiring additional commands or associated hardware complexity.
4.2.2 Volatile and Non-Volatile Register Accesses
As shown in Figure 25, the AT25FF161A device supports both volatile and non-volatile register accesses. Volatile register ac-
cesses are to the Status registers implemented in hardware. Non-volatile register accesses are to the Status registers stored in
memory. During power-up, the contents of the registers in memory are copied to the hardware Status registers.
The preceding 50h or 06h command determines if the Write Status Register command is to the volatile or non-volatile register set.
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4.3 STATUS REGISTER 1
Table 11 shows the bit assignments for Status register 1.
Table 11: Status Register 1 Format
Bit # Acronym Name
Type
Default Description
The SRP0 bit works in conjunction with the SRP1 bit in Status
Register 1 and the WP pin to control write protection. Types of
protection include software protection, hardware protection, one-
time programmable (OTP) protection, and power supply lock-down
protection. See Table 13 for an encoding of these bits.
Status Register
Protect 0
7
6
SRP0
R/W
0
The BPSIZE bit controls the size of the blocks protected by the
Block Protect Bits (BP2, BP1, BP0 in bits 4:2 of this register).
Block Protect
Size
0: 64 kB block size
1: 4 kB block size
BPSIZE
R/W
R/W
0
The blocks can also be protected from the bottom up or from the top
down as described in the TB bit of this register.
This controls the direction of the blocks to be protected by the Block
Protect Bits (BP2, BP1, BP0 in bits 4:2 of this register).
0: Protect from bottom up
1: Protect from top down
5
TB
Top/Bottom
0
The size of the protected blocks can also be selected as described
in the BPSIZE bit of this register.
The 3-bit Block Protect field provides write protection control and
status. These bits are set using the Write Status register 1 (01h)
command. This field can be programmed to protect all, none, or a
portion of the memory array. When that portion of the memory is
selected, it is protected from the Program and Erase commands as
described in the Memory Protection table.
4:2
BP2:0
Block Protect
R/W
000
The default is 3’b000 (none of the memory array is protected).
The WEL bit indicates the current status of the internal Write Enable
Latch. When the WEL bit is in the logic “0” state, the device does not
accept any program, erase, memory protection, or Write Status
Register commands. The WEL bit defaults to the logic “0” state after
a device power-up or reset.
This bit is encoded as follows:
0: Device is not write enabled (default).
1: Device is write enabled.
Write Enable
Latch Status
If the WEL bit is in the logic “1” state, it is not reset to a logic “0” if an
operation aborts due to an incomplete or unrecognized command
being clocked into the device before the CS pin is deasserted.
1
WEL
R
0
In order for the WEL bit to be reset when an operation aborts
prematurely, the entire command for a program, erase, memory
protection, or Write Status Register command must have been
clocked into the device.
When the Write Enable (06h) command is executed, the WEL bit is
set. Conversely, when the Volatile Status Register Write Enable
(50h) command is executed, the WEL bit is not set.
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Table 11: Status Register 1 Format (continued)
Bit # Acronym Name
Type
Default Description
The RDY/BSY bit is used to determine whether or not an internal
operation, such as a program or erase, is in progress. To poll the
RDY/BSY bit to detect the completion of a program or erase cycle,
new Status Register data must be continually clocked out of the
device until the state of the RDY/BSY bit changes from a logic “1” to
a logic “0”.
Ready/Busy
Status
0
RDY/BSY
R
0
This bit is encoded as follows:
0: Device is ready.
1: Device is busy with an internal operation.
4.4 STATUS REGISTER 2
The following table shows the bit assignments for Status register 2.
Table 12: Status Register 2 Format
Bit # Acronym
Name
Type Default Description
This bit is set by hardware and indicates that the program or erase
operation has been suspended. This bit is set after software
executes an Erase/Program Suspend (75h) command. Hardware
clears this bit when it detects that any of the following events have
occurred:
7
SUSP
Suspend Status
R
0
Erase/Program Resume (7Ah) command
Hardware Reset, JEDEC Hardware Reset
66h / 99h Reset command
The CMPRT is used in conjunction with BPSIZE, TB, and BP2:BP0
bits to provide additional memory array protection. This bit is en-
coded as follows:
0: Current protection mechanism is unchanged
1: Current protection mechanism is reversed
6
CMPRT Complement Protect R/W
0
When this bit is set, unprotected areas of memory become protect-
ed, and protected areas of memory become unprotected. For ex-
ample, when CMPRT = 0, a top 64 kB block can be protected while
the rest of the array is not; when CMP = 1, the same 64 kB block
would become unprotected while the rest of the array becomes
read-only.
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Table 12: Status Register 2 Format (continued)
Bit # Acronym
Name
Type Default Description
The 3-bit SL3:SL1 field provides a One-Time- Program (OTP) lock
status of Security registers 1 - 3. This field is used by software to
determine which of these Security registers have been locked.
Note that Security register 0 is always locked as the value is
programmed by Dialog Semiconductor at the factory.
The default state of SL[3:1] is 0, indicating that all registers are
unlocked. Each bit corresponds to a Status register as follows:
SL3 (bit 5): Security register 3
SL2 (bit 4): Security register 2
SL1 (bit 3): Security register 1
5:3
SL3:SL1
Security Lock 3:1
R
000
Each bit in this field is set by hardware when the most significant
byte of the corresponding Security register (the 128th byte) is
programmed.
For example, when the most significant byte of Security register 1
is set, bit 3 (SL1) of this field is set. Conversely, when the most
significant byte of Security register 3 is set, bit 5 (SL3) of this field
is set. Each time a bit is set, it indicates that the corresponding
128-Byte Security register has become read-only permanently.
2
R
Reserved
R
0
Reserved
The QE bit enables Quad SPI and XiP operation.This bit is
encoded as follows:
0: QE mode is disabled
1: QE mode is enabled
When the QE bit is cleared (logic 0), the WP and HOLD/RESET
pins are enabled and perform their respective functions.
When the QE bit is set (logic 1), the WP and HOLD/RESET pins
function as the IO2 and IO3 pins respectively, and the WP and
HOLD/RESET pins functions are disabled.
1
QE
Quad Enable
R/W
0
This bit only pertains to the following commands:
6Bh: Quad Output Read
EBh: XiP Mode Read
E7h: XiP Mode Read with Double-word Aligned Address
32h: Quad Output Page Program
77h: Set Burst with Wrap
94h: Quad I/O Read Manufacturer/Device ID
The SRP1 bit works in conjunction with the SRP0 bit in Status
Register 0 and the WP pin to control write protection. Types of
protection include software protection, hardware protection, one-
time programmable (OTP) protection, and reset lock-down
protection. See Table 13 for an encoding of these bits.
Status Register
Protect 1
0
SRP1
R/W
0
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Table 13 shows the operation of the SRP[1:0] volatile Status register bits during normal operation.
Table 13: Status Register Protection During Normal Operation
SRP1 SRP0 SRLOCK WP Type of Protection
Description
When both the SRP0 and SRP1 bits are 0, the Status registers
can be written by executing a Write Status Register command
(01h, 31h, 11h, 71h) and setting the WEL bit of this register.
Note that the WP pin has no meaning during this type of
operation.
Software Protected
(protection is controlled by
the CMPRT, BPSIZE, TB,
BP[2:0], or WPS bits)
0
0
x
x
Hardware Protected
When the SRP[1:0] bits are 0, 1 respectively, and the WP pin is
0
0
1
1
x
x
0
1
low, the registers are hardware protected and cannot be written
to.
(protection is controlled
by the WP pin)
Hardware Unprotected
When the SRP[1:0] bits are 0, 1 respectively, and the WP pin is
high, the registers are not hardware protected and can be
written to by executing a Write Status Register command (01h,
31h, 11h, 71h) and setting the WEL bit of this register.
(protection is controlled by
the CMPRT, BPSIZE, TB,
BP[2:0], or WPS bits)
When the SRP[1:0] bits are 1, 0 respectively, the Status
registers are write protected and cannot be written until the
device is reset (caused by a power-cycle, hardware reset, or
software reset). After reset, hardware changes the state of the
SRP[1:0] bits, as shown in Table 14.
1
0
x
x
Reset Lockdown
When the SRP[1:0] bits are 1,1 respectively, and the SRLOCK
bit is 0, the Status registers are write protected and cannot be
written until the device is reset (caused by a power-cycle,
hardware reset or software reset). After reset, hardware
changes the state of SRP[1:0] bits, as shown in Table 14.
1
1
1
1
0
1
x
x
Reset Lockdown
OTP
When the SRP[1:0] bits are 1,1 respectively, and the SRLOCK
bit is 1, the Status registers are permanently write protected.
Table 14 shows the behavior of the SRP1 and SRP0 bits after a reset condition.
Table 14: Status Register Protection During Reset
VolatileRegister
Bits
Non-Volatile Memory Bits
Type of
Description
Protection
SRP1 SRP0 SRLOCK
SRP1 SRP0
Software
Protected
The reset operation maintains the volatile SRP1 and SRP0 at
0,0.
0
0
1
1
0
1
0
1
x
x
x
0
0
0
0
0
0
1
0
1
Hardware
Protected
The reset operation maintains the volatile SRP1 and SRP0 at
0,1.
Reset
Lockdown to 0,0.
The reset operation changes the volatile SRP1 and SRP0 bits
Reset
Lockdown to 0,1.
The reset operation changes the volatile SRP1 and SRP0 bits
The reset operation maintains the volatile SRP1 and SRP0 at
1,1. This makes the Status registers permanently write
protected.
One-Time
Program (OTP)
1
1
1
1
1
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4.5 STATUS REGISTER 3
Table 15 shows the bit assignments for Status Register 3.
Table 15: Status Register 3 Format
Bit # Acronym
Name
Type
Default Description
Dialog Semiconductor provides a variety of packages for the
AT25FF161A, as shown in Section 2. Each of these packages
provides a dedicated HOLD/RESET pin that can be configured as
a RESET pin, or as a HOLD pin, depending on the programming of
this bit. This bit is encoded as follows:
HOLD/
RESET
HOLD or RESET
Function
7
R/W
0
0: HOLD function is enabled
1: RESET function is enabled
Note that this pin can only be configured as HOLD or RESET when
the QE bit (see bit 1 of Status register 2) is cleared (logic 0). If the
QE bit is set, the pin functions as a dedicated data pin and the
HOLD/RESET functionality is disabled.
The DRV1 and DRV0 bits are used to determine the output driver
strength during read operations. The driver strength is
automatically adjusted with VCC level. The driver strength is
encoded as following:
6:5
4:3
DRV1:0
Drive Level
Reserved
R/W
01*
00: Reserved
01: 100% (increase 1.66X at low VCC)
10: 66% (increase 2X at low VCC)
11: 33% (increase 3X at low VCC)
R
R
0
Reserved
The WPS bit selects the Write Protect scheme. This bit is encoded
as follows:
0: The AT25FF161A uses a combination of CMPRT, BPSIZE, TB,
and BP[2:0] bits in Status register 1 to protect a specific area of the
memory array.
Write Protection
Select
1: The AT25FF161A uses the individual block locks to protect any
individual block. The default value for all individual block lock bits is
1 upon device power on or after reset.
2
WPS
R/W
0
When this bit is set, software uses the Block Lock (36h) and Block
Unlock (39h) commands to lock and unlock blocks of memory.
For more information on this functionality, see Section 3.8, Memory
Protection.
1:0
R
Reserved
R
0
Reserved
* Default driver strength was used for device test and characterization. In order to achieve optimal performance in user system, it is recommended to adjust
driver strength setting to match user system load under application specific environmental conditions.
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4.6 STATUS REGISTER 4
Table 16 shows the bit assignments for Status register 4.
Table 16: Status Register 4 Format
Bit # Acronym
Name
Type
Default Description
This bit is used in conjunction with the Deep Power Down command
(B9h) to place the device into either Deep Power Down mode, or Ultra
Deep Power Down mode. This bit is encoded as follows:
0: Execution of the B9h command invokes Ultra Deep Power Down
mode. This is the same as executing the UDPD command 79h. In this
mode the SRAM buffer contents are not preserved.
Power Down
Mode
7
PDM
R/W
0
1: Execution of the B9h command invokes Deep Power Down mode. In
this mode the SRAM buffer contents are preserved.
In both modes, the ABh command is required to exit the corresponding
Power Down mode. Simply toggling the CS pin does not result in exiting
from Power Down mode. For more information, see Section 3.9, Power
Down Considerations.
The SPM bit indicates whether the device is in the Byte/Page Program
mode or the Sequential Program Mode. The default state after power-up
or device reset is the Byte/Page Program mode.
This bit is encoded as follows:
Sequential
Program
Mode Status
0: Byte/Page Programming Mode (default)
1: Sequential Programming Mode entered
6
SPM
R
0
If this bit is 1, the address is only required for the first transfer of the
sequential operation. Thus, on the first transfer, command, address, and
data are required. If there are subsequent operations, the address is not
required. Software need only supply the command and data (on a write).
Program
Error
This is set by hardware whenever an error occurs during a program
operation.
5
4
PE
EE
R
R
0
0
This is set by hardware whenever an error occurs during an erase
operation.
Erase Error
This bit determines whether a command is required each time a read
operation is executed using the E7h or EBh (Quad Read) commands.
This bit is encoded as follows:
0: XiP mode (continuous read mode) is disabled
1: XiP mode (continuous read mode) is enabled
If this bit is set and either the E7h or EBh commands are executed, the
command is only required for the first access (1-4-4). In this case, the
command is transferred on the SI pin, and the address and data are
transferred on the SI (I/O0), SO (I/O1), WP (I/O2), and HOLD (I/O3) pins.
Subsequent accesses require only address and data (0-4-4).
XiP Mode
Select
3
XiP
R/W
0
Note that if either this bit or the QE bit (see bit 1 of Status register 2) is 0,
the device can never be placed into 0-4-4 mode, and a command is
required for each access.
This 3-bit field maps to the W6:W4 bits of the Set Burst Wrap command
(77h) to determine the burst wrap status and the wrap length. See
Section 5.13 for more information on the Set Burst Wrap command and
an encoding of this field.
Burst Wrap
Settings
2:0 BWS[2:0]
R
001
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4.7 STATUS REGISTER 5
Table 17 shows the bit assignments for Status register 5.
Table 17: Status Register 5 Format
Bit # Acronym
Name
Type Default Description
Hardware sets this bit when the user executes the Status
Register Lock (6Fh) command, immediately followed by two
verification bytes, 4Dh and 67h. Once this action occurs, the
Status registers can be permanently locked.
7
SRLOCK Status Register Lock
R
0
This field indicates the number of dummy clocks to be inserted
between the address and data transactions for the EBh and E7h
commands. Note that the dummy clocks include the 2 clocks
required to clock in the M[7:0] bits.
000: 2 clocks
001: 4 clocks
6:4
DC[2:0]
Dummy Clocks
R/W
000
010: 6 clocks
011: 8 clocks
100: 10 clocks
101 - 111: Reserved
This bit is set by hardware whenever an erase operation is
suspended.
3
2
ES
PS
Erase Suspend
R
R
0
0
This bit is set by hardware whenever a program operation is
suspended.
Program Suspend
The TERE bit is used to enable or disable the Terminate
command. This bit is encoded as follows:
0: Terminate command is disabled
1: Terminate command is enabled
When the TERE bit is cleared (the default state after power-up),
the Terminate command is disabled and any attempts to reset the
device using the Terminate command are ignored. When the
TERE bit is set, the Terminate command is enabled.
1
TERE
Terminate Enable
R/W
0
The TERE bit retains its state as long as power is applied to the
device. Once set, the TERE bit remains in that state until it is
modified using the Write Status Register Byte 5 command or until
the device has been power cycled.
Setting the DWA bit indicates that the devices adheres to double-
word aligned addressing. This bit is only used when the EBh (XiP
DWA Read) command is executed and is encoded as follows:
0
DWA
Doubleword Aligned R/W
0
0: Double-word addressing is disabled
1: Double-word addressing is enabled
When this bit is set, the lower 2 bits of address are ignored and
assumed to be 00.
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5
Commands and Addressing
A valid command or operation must always be started by first asserting the CS pin. After the CS pin has been asserted, the host
controller must then clock out a valid 8-bit command on the SPI bus. Following the command, information such as address and
data bytes would then be clocked out by the host controller. All command, address, and data bytes are transferred with the most-
significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Commands not supported by the AT25FF161A are ignored by the device and no operation is started. The device continues to
ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted). Also,
if the CS pin is deasserted before the complete command and address information are sent to the device, then no operation is
performed and the device simply returns to the idle state and waits for the next operation.
Depending on the command, up to three bytes of information may be required, representing address bits A23 - A0. Since the
upper address limit of the AT25FF161A memory array is 1FFFFFh, address bits A23 - A21 are always ignored by the device.
Table 18: Command Listing
1
Transfer Type
Command
Address
Dummy
Data
Section
in Doc.
Hex
Cmd
Command Name
Read Commands
2
Mode
Format Bytes Clocks
Bytes
Clocks
Bytes
Clocks
Bytes
Clocks
Read Array
5.1
5.1
03h
0Bh
SPI
SPI
1-1-1
1-1-1
1
1
8
8
3
3
24
24
0
1
0
8
Var.
Var.
Var. x 8
Var. x 8
Fast Read Array
Dual
Output
Dual Output Read Array
Quad Output Read Array
5.2
5.3
5.4
5.4
5.4
5.4
3Bh
6Bh
EBh
---
1-1-2
1-1-4
1-4-4
0-4-4
1-4-4
0-4-4
1
1
1
0
1
0
8
8
8
0
8
0
3
3
3
3
3
3
24
24
6
1
8
Var.
Var.
Var.
Var.
Var.
Var.
Var. x 4
Var, x 2
Var. x 2
Var. x 2
Var. x 2
Var. x 2
Quad
Output
1
8
XiP Mode Read Array (initial
transfer)
XiP
XiP
XiP
XiP
Var.
Var.
Var.
Var.
Var. x 2
Var. x 2
Var. x 2
Var. x 2
XiP Mode Read Array
(subsequent transfers)
6
XiP Mode Read Array - DWA
addr (initial transfer)
E7h
---
6
XiP Mode Read Array - DWA
addr, subsequent transfers
6
Program/Erase Commands
Block Erase (4 Kbytes)
Block Erase (32 Kbytes)
Block Erase (64 Kbytes)
5.5
5.5
5.5
5.6
20h
52h
D8h
60h
SPI
SPI
SPI
SPI
1-1-0
1-1-0
1-1-0
1-0-0
1
1
1
1
8
8
8
8
3
3
3
0
24
24
24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Chip Erase
5.6
5.7
C7h
02h
SPI
SPI
1-0-0
1-1-1
1
1
8
8
0
3
0
0
0
0
0
0
0
Byte/Page Program
(1 - 256 bytes)
Var.
(1 - 256)
24
Var. x 8
3
Sequential Program Mode
(first command)
ADh/
AFh
5.8
5.8
5.9
SPI
SPI
1-1-1
1-0-1
1-1-2
1
1
1
8
8
8
3
0
3
24
0
0
0
0
0
0
0
1
8
8
Sequential Program Mode
(subsequent commands)
ADh/
AFh
1
Dual Output Byte/Page
Program
Dual
Output
Var.
(1 - 256)
A2h
24
Var. x 4
Datasheet
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© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Table 18: Command Listing (continued)
1
Transfer Type
Command
Address
Dummy
Data
Section
in Doc.
Hex
Cmd
Command Name
2
Mode
Format Bytes Clocks
Bytes
Clocks
Bytes
Clocks
Bytes
Clocks
Quad Output Byte/Page
Program
Quad
Output
Var.
(1 - 256)
5.10
5.11
32h
1-1-4
1-0-0
1
1
8
8
3
0
0
24
0
0
0
Var. x 2
75h/
B0h
Erase/Program Suspend
Erase/Program Resume
SPI
0
0
0
0
7Ah/
D0h
5.12
5.13
SPI
1-0-0
1-4-4
1
1
8
8
0
6
0
0
0
0
0
0
2
4
5
Set Burst with Wrap
77h
Quad I/O
3
1
Protection Commands
Write Enable
Write Disable
5.14
5.15
06h
04h
SPI
SPI
1-0-0
1-0-0
1
1
8
8
0
0
0
0
0
0
0
0
0
0
0
0
Volatile Status Register Write
Enable
5.16
50h
SPI
1-0-0
1
8
0
0
0
0
0
0
Individual Block Lock
5.17
5.18
36h
39h
SPI
SPI
1-1-0
1-1-0
1
1
8
8
3
3
24
24
0
0
0
0
0
0
0
0
Individual Block Unlock
3Ch/
3Dh
6
Read Block Lock
5.19
SPI
1-1-1
1
8
3
24
0
0
1
8
Global Block Lock
5.20
5.21
7Eh
98h
SPI
SPI
1-0-0
1-0-0
1
1
8
8
0
0
0
0
0
0
0
0
0
0
0
0
Global Block Unlock
Security Register Commands
Program OTP Security
Register
Var.
(1 - 128)
7
5.22
5.23
9Bh
4Bh
SPI
SPI
1-1-1
1-1-1
1
1
8
8
3
3
24
24
0
1
0
8
Var. x 8
Var. x 8
Var.
(1 - 128)
7
Read OTP Security Register
Status Register Commands
Read Status Register 1
Read Status Register 2
Read Status Register 3
Read Status Register 4
Read Status Register 5
Write Status Register 1
Write Status Register 2
Write Status Register 3
Write Status Register 4
Write Status Register 5
5.24
5.24
5.24
5.25
5.25
5.26
5.26
5.26
5.27
5.27
05h
35h
15h
65h
65h
01h
31h
11h
71h
71h
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
1-0-1
1-0-1
1-0-1
1-1-1
1-1-1
1-0-1
1-0-1
1-0-1
1-1-1
1-1-1
1
1
1
1
1
1
1
1
1
1
8
8
8
8
8
8
8
8
8
8
0
0
0
0
8
8
0
0
0
8
8
0
0
0
1
1
0
0
0
0
0
0
0
0
8
8
0
0
0
0
0
1
1
1
1
1
8
8
8
8
8
8
8
8
8
8
0
0
1
1
0
0
0
1
1
8
1
1
1
1
1
10
Var.
9
Read Status Registers
5.25
65h
SPI
1-1-1
1
8
1
1
8
1
8
Var. x 8
(1 - 5)
9
Write Status Registers
Status Register Lock
5.27
5.28
71h
6Fh
SPI
SPI
1-1-1
1-0-1
1
1
8
8
8
0
0
0
0
0
1
2
8
0
16
Power Down Commands
11
Deep Power-Down
5.29
B9h
SPI
1-0-0
1
8
0
0
0
0
0
0
Datasheet
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© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Table 18: Command Listing (continued)
1
Transfer Type
Command
Address
Dummy
Data
Section
in Doc.
Hex
Cmd
Command Name
2
Mode
Format Bytes Clocks
Bytes
Clocks
Bytes
Clocks
Bytes
Clocks
79h/
B9h
12
Ultra Deep Power-Down
5.31
5.30
5.30
5.30
SPI
1-0-0
1-0-0
1-1-1
1-0-0
1
1
1
1
8
8
8
8
0
0
3
0
0
0
0
0
0
0
0
0
Resume from Deep Power-
Down
ABh
ABh
ABh
SPI
SPI
SPI
0
24
0
0
0
0
0
1
0
0
8
0
Resume from Deep Power-
Down with Device ID
Resume from Ultra Deep
Power-Down
Reset Commands
13
Enable Reset
Reset Device
Terminate
5.32
5.32
5.33
66h
99h
SPI
SPI
SPI
1-0-0
1-0-0
1-0-1
1
1
1
8
8
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
8
13
F0h
Manufacturer/Device Commands
14
2
Manufacturer/Device ID
Manufacturer/Device ID
JEDEC ID
5.34
90h
94h
9Fh
SPI
Quad I/O
SPI
1-1-1
1-4-4
1-0-1
1
1
1
8
8
8
3
3
0
24
6
0
1
0
0
2
0
16
4
14
2
5.35
5.36
15
5
0
40
Miscellaneous Commands
16
Read SFDP
5.37
5Ah
SPI
1-1-1
1
8
3
24
1
8
Var.
Var. x 8
1. Indicates command, address, and data, and the number of pins each type is driven on. For example, 1-1-2 indicates that the command is driven on one pin
(SI), address is driven on one pin (SI), and data is driven on two pins (SI and SO).
2. Var = Variable
3. For the initial transfer of the ADh/AFh command, the command, address, and data are required. For all subsequent command, only the command and data
are necessary. The address field is not required and increments automatically within the device.
4. For the 77h command, 24 bits are transferred in the address field, but these bits are don’t care and are not used in the operation.
5. For the 77h command, the data byte consists of wrap bits W[7:0]. Bits 6:4 of this value are the only valid bits of the byte and are used to set the wrap mode.
6. For the 3Ch/3Dh command, the data byte returned provides the lock status for the 4 kB block relative to the address provided.
7. For the 9Bh and 4Bh commands, only the lower 9 bits of address (A[8:0]) are valid. Address bits 23:9 are don’t care.
8. For compatibility with legacy devices, command 01h can also be used with 2 bytes of data. In such case, the second byte is written to Status Register 2.
9. The 65h and 71h commands require only one byte of address.
10. For the 65h command, if the initial value in the address field is 01h, pointing to SR1, all of the Status registers can be read in one operation as long as the
CS pin is held low. Once the data for SR1 is fetched, hardware increments the address automatically and fetches the contents of SR2, etc., until all five
registers have been read.
11. Deep Power-Down mode can be entered by executing the B9h command with bit 7 (PDM) of Status Register 4 set.
12. Ultra Deep Power-Down mode can be entered by either executing the 79h command, or by executing the B9h command with bit 7 (PDM) of Status Register
4 cleared.
13. The 66h and 99h commands are used together and form back-to-back 1-0-0 sequences on the bus.
14. For the 90h and 94h commands, two data bytes are output. The first byte is the manufacturer ID, and the second byte is the device ID.
15. For the 9Fh command, five bytes are output. First byte is the manufacturer ID, second byte is Device ID 1, third byte is Device ID 2, fourth byte is the extended
string length, and the fifth byte is the extended string value.
16. For the 5Ah command, hardware outputs the data associated with the address provided, then increments the address automatically and continues to output
successive locations as long as the CS pin remains asserted. To read the entire SFDP value, software programs the initial address as 000000h to access
the first address, then leave CS asserted until the entire SFDP is read out.
Datasheet
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
5.1 READ ARRAY (03H, 0BH)
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply providing the
clock signal once the initial starting address is specified. The device incorporates an internal address counter that automatically
increments every time one byte of data is output by the device.
Two commands (0Bh and 03h) can be used to read the memory array. The use of each command depends on the maximum
clock frequency that is used to read data from the device. The 0Bh command can be used at any clock frequency up to the
maximum specified by fSCK, and the 03h command can be used for lower frequency read operations up to the maximum specified
by fRDLF
.
5.1.1 Command Prerequisites
None.
5.1.2 Transfer Format
The 03h/0Bh command follows the 1-1-1 transfer format described in Section 3.2, where the command and address are trans-
ferred on the SI pin, and data is transferred on the SO pin. See Figure 7 for timing diagram of a 1-1-1 transfer showing the toggling
of external bus signals for a read operation without dummy bytes. Figure 8 shows a read operation with dummy bytes.
5.1.3 Transfer Sequence
To perform the Read Array command, the CS pin is asserted and the information transferred as follows:
Assert the CS pin.
The appropriate command (0Bh or 03h) is clocked into the device. Eight clocks are required to transfer the command. The
most significant bit of the command is transferred first.
Three address bytes are clocked in to specify the starting address location of the first byte to read within the memory array.
A total of 24 clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
Following the three address bytes, an additional dummy byte must be clocked into the device if the 0Bh command is used.
Data is output on the SO pin. Each byte transfer requires eight clock cycles. The number of bytes transferred is determined
by software. The transfer can be anywhere from a single byte to the entire memory array. The most significant bit of each
data byte is transferred first.
Deasserting the CS pin terminates the read operation and puts the SO pin into high-impedance state. The CS pin can be
deasserted at any time and does not require a full byte of data be read.
See Table 18 for more information on the transfer sequence for this command.
When the last byte (1FFFFFh) of the memory array has been read, the device loops back and continues reading at the beginning
of the array (000000h). No delays are incurred when wrapping around from the end of the array to the beginning of the array.
5.1.4 Programming Restrictions
None
Datasheet
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
5.2 DUAL OUTPUT READ ARRAY (3BH)
The Dual Output Read Array command is similar to the standard Read Array (03h/0Bh) command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been
specified. Unlike the standard Read Array command, however, the Dual Output Read Array command allows two bits of data to
be clocked out of the device on every clock cycle, rather than just one.
5.2.1 Command Prerequisites
None.
5.2.2 Transfer Format
The 3Bh command follows the 1-1-2 transfer format described in Section 3.3, where the command and address are transferred
on the SI pin, and output data is transferred on the SI and SO pin. To facilitate this transfer, hardware switches the SI pin to an
output as soon as the command has been decoded and the address transferred. See Figure 10 for a timing diagram of this
command.
5.2.3 Transfer Sequence
To perform the Dual Output Read Array operation, the CS pin is asserted and the information transferred as follows:
The 3Bh command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three address bytes are clocked in to specify the starting address location of the first byte to read within the memory array.
A total of 24 clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
Following the three address bytes, an additional dummy byte must be clocked into the device. This requires eight clock
cycles to complete.
Data is output on the SI and SO pins. As a result, each byte transfer requires four clock cycles, half that of the 03h/0Bh
commands. The data is always output with the most significant bit of the byte transferred first. The number of bytes trans-
ferred is determined by software. The transfer can be anywhere from a single byte to the entire memory array. The data is
driven onto the bus as follows:
- 1st data clock: bit 7 is output on the SO pin
- 1st data clock: bit 6 is output on the SI pin
- 2nd data clock: bit 5 is output on the SO pin
- 2nd data clock: bit 4 is output on the SI pin
- 3rd data clock: bit 3 is output on the SO pin
- 3rd data clock: bit 2 is output on the SI pin
- 4th data clock: bit 1 is output on the SO pin
- 4th data clock: bit 0 is output on the SI pin
- Subsequent bytes are output with each additional 4 clocks. The sequence above continues with each byte of data being
output after every four clock cycles.
Deasserting the CS pin terminates the read operation and puts the SO and SI pins into a high-impedance state. The CS pin
can be deasserted at any time and does not require that a full byte of data be read.
When the last byte (1FFFFFh) of the memory array has been read, the device continues reading from the beginning of the array
(000000h). No delays are incurred when wrapping around from the end of the array to the beginning of the array.
5.2.4 Programming Restrictions
None
5.3 QUAD OUTPUT READ ARRAY (6BH)
The Quad Output Read Array command is similar to the Dual Output Read Array command, except that the Quad Output Read
Array command allows four bits of data to be clocked out of the device on every clock cycle, rather than just one or two. Note that
Datasheet
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
the Quad Enable bit (QE) in Status Register 2 (SR2) must be set to enable this command. The Quad Output Read Array command
can be used at any clock frequency, up to the maximum specified by fSCK
.
5.3.1 Command Prerequisites
None.
5.3.2 Transfer Format
The 6Bh command follows the 1-1-4 transfer format described in Section 3.4, where the command and address are transferred
on the SI pin, and data is transferred on the HOLD, WP, SO, and SI pins. See Figure 14 for a timing diagram of this transaction.
5.3.3 Transfer Sequence
To perform the Quad Output Read Array operation, the CS pin is asserted and the information transferred as follows:
The 6Bh command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three address bytes are clocked in to specify the starting address location of the first byte to read within the memory array.
A total of 24 clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
Following the three address bytes, an additional dummy byte must be clocked into the device. This requires eight clock
cycles to complete.
Following transfer of the dummy byte, hardware switches the HOLD, WP, and SI pins to outputs.
Data is output on the HOLD, WP, SO, and SI pins. As a result, each byte transfer requires two clock cycles, one-fourth
that of the 03h/0Bh commands. The data is always output with the most significant bit of the byte transferred first. The
number of bytes transferred is determined by software. The transfer can be anywhere from a single byte to the entire mem-
ory array. Each data byte is shifted out of the device as follows:
- First data clock: bit 7 is output on the HOLD pin
- First data clock: bit 6 is output on the WP pin
- First data clock: bit 5 is output on the SO pin
- First data clock: bit 4 is output on the SI pin
- Second data clock: bit 3 is output on the HOLD pin
- Second data clock: bit 2 is output on the WP pin
- Second data clock: bit 1 is output on the SO pin
- Second data clock: bit 0 is output on the SI pin
Deasserting the CS pin terminates the read operation and puts the HOLD, WP, SO, SI pins into a high-impedance state.
The CS pin can be deasserted at any time and does not require that a full byte of data be read.
When the last byte (1FFFFFh) of the memory array has been read, the device continues reading from the beginning of the array
(000000h). No delays are incurred when wrapping around from the end of the array to the beginning of the array.
5.3.4 Programming Restrictions
None
Datasheet
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
5.4 XIP READ (EBH), XIP READ WITH DOUBLE-WORD ALIGNED ADDRESS (E7H)
The XiP Read command (EBh) is similar to the Quad Output Read Array command, except that four bits of address are clocked
into the device on every clock cycle, rather than just one. The E7h command is similar to the EBh command but works only on
double-word aligned (DWA) addresses. As such, the E7h command ignores address bits A[1:0] and internally assumes that these
two bits are always 2'b00. This allows us to run the E7h command at faster clock speeds or fewer dummy clock cycles compared
to the EBh command.
The EBh command can operate in either DWA mode or non-DWA mode depending on the state of the DWA bit in Status Register
5. See Section 4.7, Status Register 5 for more information.
5.4.1 Command Prerequisites
None.
5.4.2 Transfer Format
The initial EBh/E7h command follows the 1-4-4 transfer format described in Section 3.6, where the command is transferred on
the SI pin, and the address and data are transferred on the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins. See Figure 15 for
a timing diagram of this command.
Subsequent EBh/E7h commands follow the 0-4-4 transfer format described in Section 3.6, where the address and data are
transferred on the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins. No command transfer is required. See Figure 16 for a timing
diagram of this command.
5.4.3 Mode Bits
The EBh and E7h commands follow the 1-4-4 and 0-4-4 transfer formats as described above. During the initial transfer, an 8-bit
mode field is transferred immediately following the last address byte and is decoded by hardware to determine if the device is to
be placed into XiP continuous read mode. If so, then subsequent transfers do not require the command field, resulting in a 0-4-
4 transfer type. This mode increases performance by saving 8 clocks cycles per transfer. For more information on this mode, see
Section 3.6, XiP Mode Operation.
5.4.4 Transfer Sequence — Initial Transfer
To perform the initial XiP Mode Read operation, the CS pin is asserted and the information transferred as follows:
The EBh/E7h command is clocked into the device. Eight clocks are required to transfer the command. The most significant
bit of the command is transferred first. This field is transferred on the SI pin.
Three address bytes are clocked in to specify the starting address location of the first byte to read within the memory array.
A total of 6 clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
Each address byte is shifted out of the device as follows:
- First clock: address bit 23 is input on the HOLD pin
- First clock: address bit 22 is input on the WP pin
- First clock: address bit 21 is input on the SO pin
- First clock: address bit 20 is input on the SI pin
- Second clock: address bit 19 is input on the HOLD pin
- Second clock: address bit 18 is input on the WP pin
- Second clock: address bit 17 is input on the SO pin
- Second clock: address bit 16 is input on the SI pin
- Third and fourth clocks: A15:A8 are shifted in same as above
- Fifth and sixth clocks: A7:A0 are shifted in same as above
Following the three address bytes, a programmable number of dummy bytes must be clocked into the device. See Section
5.4.6 below for more information. Note that the Mode bits are treated as part of the dummy bytes and must be clocked in to
the device.
Datasheet
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Following transfer of the dummy bytes, hardware switches the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins to out-
puts.
Data is output on the HOLD, WP, SO, and SI pins. As a result, each byte transfer requires two clock cycles. The data is
always output with the most significant bit of the byte transferred first. Each data byte is shifted out of the device as follows:
- First clock: bit 7 is output on the HOLD pin
- First clock: bit 6 is output on the WP pin
- First clock: bit 5 is output on the SO pin
- First clock: bit 4 is output on the SI pin
- Second clock: bit 3 is output on the HOLD pin
- Second clock: bit 2 is output on the WP pin
- Second clock: bit 1 is output on the SO pin
- Second clock: bit 0 is output on the SI pin
Deasserting the CS pin terminates the read operation and puts the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins into
a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.
When the last byte (1FFFFFh) of the memory array has been read, the device continues reading from the beginning of the
array (000000h). No delays are incurred when wrapping around from the end of the array to the beginning of the array.
5.4.5 Transfer Sequence — Subsequent Transfers
To perform subsequent XiP Mode Read operations, the CS pin is asserted and the information transferred as follows:
Three address bytes are clocked in to specify the starting address location of the first byte to read within the memory array.
A total of 6 clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
The address is transferred on the bus in the same manner described in Section 5.4.4 above.
Following the three address bytes, a programmable number of dummy bytes must be clocked into the device. See Section
5.4.6 below for more information. Note that the Mode bits are treated as part of the dummy bytes and must be clocked in to
the device.
Data is output on the HOLD, WP, SO, and SI pins. As a result, each byte transfer requires two clock cycles. The data is
always output with the most significant bit of the byte transferred first. Data is shifted out onto the bus in the same manner
described in Section 5.4.4 above.
Deasserting the CS pin terminates the read operation and puts the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins into
a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.
When the last byte (1FFFFFh) of the memory array has been read, the device continues reading from the beginning of the array
(000000h). No delays are incurred when wrapping around from the end of the array to the beginning of the array.
5.4.6 Programmable Number of Dummy Clocks
The number of dummy clocks required differs depending on the frequency, the type of command being performed, and the state
of bit 0 (DWA) of Status register 5. This relationship is shown in the table below. The number of Dummy clocks is set using bits
6:4 (DC[2:0]) of Status register 5. See Section 4.7, Status Register 5 for more information. Note that the number of dummy clocks
includes the 2 SCK clock periods required to clock in the M[7:0] mode bits.
Datasheet
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DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Table 19: Frequency and Number of Dummy Clocks Based on Command Type in Non-Wrap Mode (default)
XiP enabled (044) XiP enabled (044) XiP disabled (144) XiP disabled (144)
DWA
Bit
Dummy
Clocks
Cmd
DC[2:0]
(1.65 V - 3.6 V)
(2.7 V - 3.6 V)
(1.65 V - 3.6 V)
(2.7 V - 3.6 V)
SCK Frequency (MHz)
0
0
0
0
0
1
1
1
1
1
x
x
x
x
x
000
001
010
011
100
000
001
010
011
100
000
001
010
011
100
2
4
30
50
35
60
30
50
35
55
6
80
80
75
85
8
104
104
50
104
104
60
96
96
10
2
108
65
108
65
EBh
4
108
120
120
120
40
133
133
133
133
50
120
120
120
120
45
133
133
133
133
45
6
8
10
2
4
96
96
104
108
108
108
104
108
108
108
E7h
6
108
108
108
108
108
108
8
10
As shown in Table 19, the EBh command can operate on both doubleword aligned (DWA = 1) and non-doubleword aligned (DWA
= 0) addresses. The E7h command works only on doubleword aligned addresses, so the state of the DWA bit is ignored.
Datasheet
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© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Table 20: Frequency and Number of Dummy Clocks Based on Command Type in Wrap Mode (77h)
XiP enabled (044) XiP enabled (044) XiP disabled (144)
XiP disabled
(144)
DWA
Bit
Dummy
Clocks
Cmd
DC[2:0]
(1.65 V - 3.6 V)
(2.7 V - 3.6 V)
(1.65 V - 3.6 V)
(2.7 V - 3.6 V)
SCK Frequency (MHz)
0
0
0
0
0
1
1
1
1
1
x
x
x
x
x
000
001
010
011
100
000
001
010
011
100
000
001
010
011
100
2
4
30
45
30
50
30
55
80
80
85
55
80
85
90
90
55
80
85
90
90
30
55
6
75
75
85
8
90
108
120
50
96
10
2
96
100
55
EBh
45
4
85
104
120
120
120
50
90
6
104
108
108
45
96
8
104
104
55
10
2
4
90
108
120
120
120
96
E7h
6
104
108
108
100
104
104
8
10
As shown in the above table, the EBh command can operate on both doubleword aligned (DWA = 1) and non-doubleword aligned
(DWA = 0) addresses. The E7h command works only on doubleword aligned addresses, so the state of the DWA bit is ignored.
5.4.7 Programming Restrictions
None
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
5.5 BLOCK ERASE (20H, 52H, D8H)
A block of 4-, 32-, or 64-kBytes (kB) can be erased (all bits set to the logical “1” state) in a single operation by using one of three
different forms of the Block Erase command.
The 20h command is used for a 4 kB erase
The 52h command is used for a 32 kB erase
The D8h command is used for a 64 kB erase
5.5.1 Command Prerequisites
Before a Block Erase command can be issued, the Write Enable (06h) command must have been previously issued to the device
to set the WEL bit of Status Register 1.
5.5.2 Transfer Format
The 20h/52h/D8h command follows the 1-1-0 transfer format described in Section 3.2, where the command and address are
transferred on the SI pin. The address represents the block to be erased. No data is transferred for this command.
5.5.3 Transfer Sequence
To perform the Block Erase operation, the CS pin is asserted and the information transferred as follows:
The appropriate command is clocked into the device. Eight clocks are required to transfer the command. The most signifi-
cant bit of the command is transferred first.
Three address bytes are clocked in to specify the address location within the 4-, 32-, or 64-kByte block to be erased. A
total of 24 clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
See Table 18 for more information on the transfer sequence for this command.
5.5.4 Erase Operation
When the CS pin is deasserted, the device starts the erase of the appropriate block. The erasing of the block is internally self-
timed and takes place in time tBLKE. Since the Block Erase command erases a region of bytes, the lower order address bits do
not need to be decoded by the device. Depending on the command issued, the address is treated as follows:
For a 4 kB erase, address bits A11 - A0 are ignored by the device and their values can be either a logical “1” or “0”.
For a 32 kB erase, address bits A14 - A0 are ignored by the device.
For a 64 kB erase, address bits A15 - A0 are ignored by the device.
5.5.5 Command Status
While the device is executing a successful erase cycle, bit 0 in Status Register 1 (SR1) indicates that the device is busy. For faster
throughput, it is recommended that Status Register 1 be polled rather than waiting the tBLKE time to determine if the device has
finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register is reset back to the logical
“0” state.
5.5.6 Programming Restrictions
The Block Erase commands adhere to the following programming restrictions. The following events can cause the block erase
operation to be aborted. If any of these events occur, the WEL bit in Status Register 1 is reset back to the logic ‘0’ state.
The CS pin must be deasserted on a byte boundary (multiples of eight bits). Otherwise, the device aborts the operation and
no erase operation is performed.
Despite the lower order address bits not being decoded by the device, the complete three address bytes must still be
clocked into the device before the CS pin is deasserted. If the address is incomplete, the operation is aborted.
If the memory is in the protected state, the Block Erase command cannot be executed and the device returns to the idle
state once the CS pin has been deasserted.
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
5.5.7 Error Reporting
The device incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If an erase
error occurs, it is indicated by the EE and PE bits in Status Register 4. See Section 4.6, Status Register 4 for more information.
5.6 CHIP ERASE (60H, C7H)
The entire memory array can be erased in a single operation by using the Chip Erase command. Two commands (60h and C7h)
can be used for the Chip Erase command. There is no difference in device functionality when utilizing these two commands, so
they can be used interchangeably.
5.6.1 Command Prerequisites
Before a Chip Erase command can be issued, the Write Enable (06h) command must have been previously issued to the device
to set the WEL bit of Status Register 1.
The Chip Erase command is not executed if any memory region is protected by either the block protect bits or the individual block
locks. For more information on the block protect bits, see bits 4:2 (BP[2:0]) of Section 4.3, Status Register 1. For more information
on enabling individual lock bits, see bit 2 (WPS) of Section 4.5, Status Register 3.
5.6.2 Transfer Format
The 60h/C7h commands follow the 1-0-0 transfer format described in Section 3.2, where the command is transferred on the SI
pin. No address or data are transferred for this command. See Figure 3 for a timing diagram of this operation.
5.6.3 Transfer Sequence
To perform the Chip Erase operation, the CS pin is asserted and the information transferred as follows:
The 60h/C7h command is clocked into the device. Eight clocks are required to transfer the command. The most significant
bit of the command is transferred first.
When the CS pin is deasserted, the device begins to erase the entire memory array. The erasing of the device is internally
self-timed and takes place in time tCHPE
.
See Table 18 for more information on the transfer sequence for this command.
5.6.4 Device Status
While the device is executing a successful erase cycle, the RDY/BSY bit in Status Register 1 can be read and indicates the device
is busy. For faster throughput, it is recommended that Status Register 1 be polled rather than waiting the tCHPE time to determine
if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in SR1 is reset back to the logical
“0” state.
5.6.5 Programming Restrictions
The Chip Erase command adheres to the following programming restrictions. The following events can cause the chip erase
operation to be aborted. If either one occurs, the WEL bit in Status Register 1 is reset back to the logical “0” state.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no erase operation is performed.
If any block in the memory is in the protected state, the Chip Erase command cannot be executed and the device returns to
the idle state once the CS pin has been deasserted.
A Chip Erase command cannot be suspended by executing the Program/Erase Suspend (75h) command. Hardware
ignores the Program/Erase Suspend command if it is issued during a Chip Erase.
5.6.6 Error Reporting
The device incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If an erase
error occurs, it is indicated by the EE and PE bits in Status Register 4. For more information, see Section 4.6, Status Register 4.
Datasheet
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
5.7 BYTE/PAGE PROGRAM (02H)
The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into
previously erased memory locations. An erased memory location is one that has all eight bits set to the logical “1” state (a byte
value of FFh).
5.7.1 Command Prerequisites
Before a Byte/Page Program command can be issued, the Write Enable (06h) command must have been previously issued to
the device to set the WEL bit of Status Register 1.
5.7.2 Transfer Format
The 02h command follows the 1-1-1 transfer format described in Section 3.2, where the command, address, and data are all
transferred on the SI pin. See Figure 9 for a timing diagram of this transaction.
5.7.3 Transfer Sequence
To perform the Byte/Page Program operation, the CS pin is asserted and the information transferred as follows:
The 02h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three address bytes are clocked in to specify the starting address location of the first byte to read within the memory array.
A total of 24 clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
Each byte transfer requires eight clock cycles. The data is always input with the most significant bit of the byte transferred
first. The number of bytes transferred is determined by software. The transfer can be anywhere from a single byte to the
entire buffer. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page are not
programmed and remain in the erased state (FFh).
Once the CS pin is deasserted, hardware moves the data from the buffer to the memory. The programming of the data
bytes is internally self-timed and takes place in time tPP or tBP if only programming a single byte.
See Table 18 for more information on the transfer sequence for this command.
5.7.4 Device Status
While the data is being transferred, bit 0 (RDY/BSY) of Status Register 1 can be read and indicates that the device is busy. For
faster throughput, it is recommended that Status Register 1 be polled rather than waiting the tBP or tPP time to determine if the
data bytes have finished programming.
5.7.5 Programming Restrictions
The Byte/Page Program command adheres to the following programming restrictions. If any of the following conditions occur, the
programming cycle is aborted and the WEL bit in Status Register 1 is reset back to the logic ‘0’ state.
Deassertion of the CS Pin
The CS pin must be deasserted on even byte boundaries (multiples of eight bits). Otherwise, the device aborts the operation and
no data is programmed into the memory array.
Protected Memory
If the memory is in a protected state, then the Byte/Page Program command is not executed, and the device returns to the idle
state once the CS pin has been deasserted.
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Page Address Boundary
If the starting memory address denoted by A[23:0] does not fall on an even 256-byte page boundary (A[7:0] are not all 0), then
special circumstances regarding which memory locations to be programmed apply. In this situation, any data sent to the device
that exceeds the page size wraps around back to the beginning of the same page.
For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then the first
two bytes of data is programmed at addresses 0000FEh and 0000FFh while the last byte of data is programmed at address
000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) are not programmed and remain in the current
state. Also, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent are latched into the internal
buffer.
Incomplete Address or Data
If the device receives either an incomplete address, or an incomplete data byte, the operation is aborted and hardware clears the
WEL bit is Status Register 1.
5.8 SEQUENTIAL PROGRAM MODE (ADH/AFH)
The Sequential Program Mode improves throughput over the Byte/Page Program command when the Byte/Page Program com-
mand is used to program single bytes only into consecutive address locations. For example, some systems may be designed to
program only a single byte of information at a time and cannot utilize a buffered Page Program operation due to design restrictions.
In such a case, the system would normally have to perform multiple Byte Program operations in order to program data into
sequential memory locations. This approach can add considerable system overhead and SPI bus traffic.
The Sequential Programming Mode helps reduce system overhead and bus traffic by incorporating an internal address counter
that keeps track of the byte location to program, thereby eliminating the need to supply an address sequence to the device for
every byte being programmed.
5.8.1 Command Prerequisites
Before a Sequential Program command can be issued, the Write Enable (06h) command must have been previously issued to
the device to set the WEL bit of Status Register 1.
When using the Sequential Program mode, all address locations to be programmed must be in the erased state.
5.8.2 Transfer Format
The initial ADh/AFh command follows the 1-1-1 transfer format described in Section 3.2, where the command, address, and data
are all transferred on the SI pin. See Figure 9 for a timing diagram of this transaction.
All subsequent ADh/AFh commands follow the 1-0-1 transfer format described in Section 3.2, where the command and data are
both transferred on the SI pin. Subsequent accesses do not require an address. See Figure 6 for a timing diagram of this
transaction.
5.8.3 Transfer Sequence — Initial Transfer
To perform the initial Sequential Program operation, the CS pin is asserted and the information transferred as follows:
The AFh/ADh command is clocked into the device. Eight clocks are required to transfer the command. The most significant
bit of the command is transferred first.
Three address bytes are clocked in to specify the starting address location of the first byte to written to within the device
(typically the memory array). A total of 24 clocks are required to transfer the address. The most significant bit of the
address (A[23]) is transferred first.
Transfer the first byte of data. This requires eight clock cycles. The data is always input with the most significant bit of the
byte transferred first.
Deasserting the CS pin starts the internally self-timed program operation, and the byte of data is programmed into the
memory location specified by the A23:A0.
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
See Table 18 for more information on the transfer sequence for this command.
5.8.4 Transfer Sequence — Subsequent Transfers
To perform subsequent Sequential Program operations, the CS pin is asserted and the information transferred as follows:
The AFh/ADh command is clocked into the device. Eight clocks are required to transfer the command. The most significant
bit of the command is transferred first.
Because the initial transfer has already occurred and hardware knows already knows the location of the next byte to be
programmed, the address field is not necessary. The command can be followed by the next data byte.
Transfer the next byte of data. This requires eight clock cycles. The data is always input with the most significant bit of the
byte transferred first.
Deasserting the CS pin starts the internally self-timed program operation, and the byte of data is programmed into the
memory location specified by the internal address counter. There is no need to reissue the Write Enable command once
the Sequential Program Mode has been entered.
When the last desired byte has been programmed into the memory array, the Sequential Program Mode operation can be
terminated by reasserting the CS pin and sending the Write Disable command to the device to reset the WEL bit in Status
Register 1.
5.8.5 Program Status
While the device is programming a byte, the RDY/BSY bit in Status Register 1 can be read to determine if the device is busy. The
programming of the data bytes is internally self-timed and takes place in time tPP (page) or tBP (single byte).
For faster throughput, it is recommended that the Status Register be polled at the end of each program cycle rather than waiting
the tBP or tPP time to determine if the byte has finished programming before starting the next operation.
5.8.6 Commands Allowed and Not Allowed in Sequential Program Mode
When the device is busy executing a self-timed program/erase operation (RDY/BSY bit in SR1 = 1), then it normally ignores most
commands from the user. However, there are a handful of commands which are accepted by the device.
Similarly, if the device is not busy (RDY/BSY bit in SR1 = 0), but is in Sequential Programming mode, only some commands are
accepted, and others are rejected by the device.
Table 21 shows which commands can and cannot be executed with the device is in Sequential Program mode.
Table 21: Command Behavior During Sequential Programming Mode
During Sequential Programming Mode
Command Name
Command Code(s)
(RDY/BUSY = 0, SPM = 1)
Read Array
03h, 3Bh, 6Bh, EBh, E7h, 0Bh
Not allowed
Not allowed
Not allowed
Not allowed
Allowed
Block Erase
20h, 52h, D8h
60h, C7h
02h, A2h, 32h
ADh, AFh
B0h, 75h
D0h, 7Ah
06h
Chip Erase
Byte/Page Program
Sequential Programming
Program/Erase Suspend
Program/Erase Resume
Write Enable
Not Allowed
Not allowed
Allowed
Write Disable
04h
Allowed
Volatile Write Enable
50h
Not allowed
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Table 21: Command Behavior During Sequential Programming Mode (continued)
During Sequential Programming Mode
(RDY/BUSY = 0, SPM = 1)
Command Name
Command Code(s)
Individual Block Lock
Individual Block Unlock
Global Block Lock
36h
39h
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Allowed
7Eh
Global Block Unlock
98h
Read Block Lock Status
Program OTP Security Register
Read OTP Security Register
Read Status Registers (direct)
Read Status Registers (indirect)
Write Status Registers (direct)
Write Status Registers (indirect)
Status Register Lock
3Ch, 3Dh
9Bh
4Bh
05h, 35h, 15h
65h
Allowed
01h, 31h, 11h
71h
Not allowed
Not allowed
Not allowed
Allowed
6Fh
Terminate
F0h
Enable Reset
66h
Allowed
Reset Device
99h
Allowed
Read Mfg ID and Device ID
Deep Power Down
9Fh, 90h, 94h
B9h
Allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Resume from Deep Power Down
Ultra Deep Power Down
Read SFDP
ABh
79h
5Ah
Set Burst with Wrap
77h
5.8.7 Programming Restrictions
The Sequential Program mode adheres to the following programming restrictions.
Multiple Data Bytes per Program Cycle
If more than one byte of data is clocked in during a program cycle, then only the last byte of data sent on the SI pin is stored in
the internal latches. The programming of each byte is internally self-timed and takes place in time tBP
.
Deasserting the CS Pin
For each program cycle, a complete byte of data must be clocked into the device before the CS pin is deasserted, and the CS
pin must be deasserted on even byte boundaries (multiples of eight bits). Otherwise, the device abort the operation and the byte
of data is not programmed into the memory array. Also, hardware resets the WEL bit in Status Register 1.
Protected Memory
If the address initially specified by A[23:0] points to a memory location within a block that is in the protected state, then the
Sequential Program Mode command is not executed, and the device returns to the idle state once the CS pin has been deassert-
ed. The WEL bit in the Status Register is also reset back to the logical “0” state.
Sequential Program mode does not automatically skip over protected blocks. Therefore, once the highest unprotected memory
location in a programming sequence has been programmed, the device automatically exits the Sequential Program mode and
resets the WEL bit in Status Register 1.
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AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
For example, if block 1 was protected and block 0 was currently being programmed, once the last byte of block 0 was programmed,
the Sequential Program mode would automatically end. To continue programming with block 2, the Sequential Program mode
would have to be restarted by supplying the ADh or AFh command, the three address bytes, and the first byte of block 2 to
program.
Address Wrapping
There is no address wrapping when using the Sequential Program Mode. Therefore, when the last byte (1FFFFFh) of the memory
array has been programmed, the device automatically exits the Sequential Program mode and resets the WEL bit in Status
Register 1.
64 kB Block Accesses
If during a Sequential Program operation, the address increments into a 64 kB block where an erase operation has been sus-
pended, hardware exits Sequential Program mode.
Clearing the WEL Bit in Status Register 1
If the WEL bit in Status register 1 is cleared at any time during a sequential programming operation, hardware exits Sequential
Program mode.
5.8.8 Error Reporting
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly.
If a programming error arises, it is indicated by the EE and PE bits in Status Register 4.
5.9 DUAL OUTPUT BYTE/PAGE PROGRAM (A2H)
The Dual Output Byte/Page Program (A2h) command is similar to the standard Byte/Page Program command (02h) and can be
used to program anywhere from a single byte of data up to 256 bytes of data into previously erased memory locations. Unlike the
standard Byte/Page Program command, however, the Dual Output Byte/Page Program command allows two bits of data to be
clocked into the device on every clock cycle rather than just one.
5.9.1 Command Prerequisites
Before the Dual Output Byte/Page Program command can be executed, the Write Enable command (06h) must have been
previously issued to set the Write Enable Latch (WEL) bit in Status Register 1.
5.9.2 Transfer Format
The A2h command follows the 1-1-2 transfer format described in Section 3.3, where the command and address are transferred
on the SI pin, and input data is transferred on the SI and SO pins. To facilitate this transfer, hardware switches the SO pin to an
input as soon as the command has been decoded and the address transferred. See Figure 11 for a timing diagram of this
transaction.
5.9.3 Transfer Sequence
To perform a Dual Output Page Program operation, the CS pin is asserted and the information transferred as follows:
The A2h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three address bytes are clocked in to specify the starting address location of the first byte to written. A total of 24 clocks
are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
The first byte of data is transferred on the SI and SO pins. This requires four clock cycles. The data is always input with the
most significant bit on the SO pin during each clock, as shown below. Like the standard Byte/Page Program command,
all data clocked into the device is stored to an internal buffer.
- First data clock: bit 7 is input on the SO pin
- First data clock: bit 6 is input on the SI pin
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
- Second data clock: bit 5 is input on the SO pin
- Second data clock: bit 4 is input on the SI pin
- Third data clock: bit 3 is input on the SO pin
- Third data clock: bit 2 is input on the SI pin
- Fourth data clock: bit 1 is input on the SO pin
- Fourth data clock: bit 0 is input on the SI pin
- Subsequent data bytes are transmitted in the same sequence as above
5.9.4 Program Status
While the device is programming a byte, Status Register 1 can be read to determine if the device is busy. The programming of
the data bytes is internally self-timed and takes place in time tPP (page) or tBP (single byte).
For faster throughput, it is recommended that the Status Register be polled at the end of each program cycle rather than waiting
the tBP or tPP time to determine if the byte has finished programming before starting the next operation.
5.9.5 Programming Restrictions
The Dual Output Byte/Page Program operation adheres to the following programming restrictions.
Page Address Boundary
If the starting memory address denoted by A[23:0] does not fall on a 256-byte page boundary (A[7:0] are not all 0), then special
circumstances regarding which memory locations are to be programmed apply. In this situation, any data sent to the device that
exceeds the end of the page wraps around to the beginning of the same page.
For Example: If the starting address denoted by A[23:0] is 0000FEh and three bytes of data are sent to the device, then the first
two bytes of data is programmed at addresses 0000FEh and 0000FFh, while the last byte of data is programmed at address
000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) are not programmed and remain in the erased
state (FFh).
Data Transfers
When the CS pin is deasserted, the device programs the data stored in the internal buffer into the appropriate memory array
locations based on the starting address specified by A[23:0] and the number of data bytes sent to the device. If fewer than 256
bytes of data is sent to the device, then the remaining bytes within the page are not programmed and remains in the erased state
(FFh). Conversely, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent are latched into the
internal buffer.
Deassertion of the CS Pin
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin can be
deasserted. Also, the CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the
operation and no data is programmed into the memory array.
Protected Memory
If the address specified by A[23:0] points to a memory location within a block that is in the protected state, then the Byte/Page
Program command is not executed, and the device returns to the idle state once the CS pin has been deasserted. The WEL bit
in the Status Register is reset back to the Logical 0 state if the program cycle is aborted
5.9.6 Error Reporting
The device incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a
programming error arises, it is indicated by the EE and PE bits in Status Register 4.
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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5.10 QUAD OUTPUT PAGE PROGRAM (32H)
This command allows between 1 to 256 bytes of data to be programmed at previously erased memory locations.
5.10.1 Command Prerequisites
Before a Sequential Program command can be issued, the Write Enable (06h) command must have been previously issued to
the device to set the WEL bit of Status Register 1. For more information on the QE bit, see Section 4.3, Status Register 1. Also,
the Quad Enable bit (QE bit in Status Register 2) must be set. For more information on the QE bit, see Section 4.4, Status Register
2.
5.10.2 Transfer Format
The 32h command follows the 1-1-4 transfer format described in Section 3.4, Quad Output Operation (1-1-4), where the command
and address are transferred on the SI pin, and data is transferred on the HOLD, WP, SO, and SI pins. See Figure 13 for a timing
diagram of this operation.
5.10.3 Transfer Sequence
To perform the Quad Output Page Program operation, the CS pin is asserted and the information transferred as follows:
The 32h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three address bytes are clocked in to specify the starting address location of the first byte to read within the memory array.
A total of 24 clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
Following transfer of the last address byte, hardware switches the SO pin to an input.
Data is input on the HOLD, WP, SO, and SI pins. As a result, each byte transfer requires only two clock cycles to com-
plete. The data is always input with the most significant bit of the byte transferred first. The number of bytes transferred is
determined by software. The transfer can be anywhere from a single byte to the entire memory array. Each data byte is
shifted into the device as follows:
- First data clock: bit 7 is input on the HOLD pin
- First data clock: bit 6 is input on the WP pin
- First data clock: bit 5 is input on the SO pin
- First data clock: bit 4 is input on the SI pin
- Second data clock: bit 3 is input on the HOLD pin
- Second data clock: bit 2 is input on the WP pin
- Second data clock: bit 1 is input on the SO pin
- Second data clock: bit 0 is input on the SI pin
- Additional data bytes are transferred on the four pins in the same manner, as shown above.
5.10.4 Programming Restrictions
The Quad Output Byte/Page Program command adheres to the following programming restrictions
The CS pin must be deasserted on a byte boundary (multiples of eight bits). Otherwise, the device aborts the operation and
no action is taken.
If the memory is in a protected state, then the Byte/Page Program command is not executed, and the device returns to the
idle state once the CS pin has been deasserted.
If the starting memory address denoted by A[23:0] does not fall on an even 256-byte page boundary (A[7:0] are not all 0),
then special circumstances regarding which memory locations to be programmed apply. In this situation, any data sent to
the device that exceeds the page size wraps around back to the beginning of the same page.
For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then
the first two bytes of data is programmed at addresses 0000FEh and 0000FFh while the last byte of data is programmed at
address 000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) are not programmed and
remain in the current state. Also, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent are
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latched into the internal buffer.
If the device receives either an incomplete address, or an incomplete data byte, the operation is aborted and hardware
clears the WEL bit is Status Register 1.
5.10.5 Error Reporting
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly.
If a programming error arises, it is indicated by the EE and PE bits in Status Register 4.
5.11 PROGRAM/ERASE SUSPEND (75H/B0H)
The device supports two Program/Erase Suspend commands, 75h and B0h, that perform the exact same function. The 75h
command can be used for legacy software, and the B0h command is used for compatibility with future implementations.
In some code plus data storage applications, it is often necessary to process certain high-level system interrupts that require
relatively immediate reading of code or data from the Flash memory. In such an instance, it may not be possible for the system
to wait the microseconds or milliseconds required for the Flash memory to complete a program or erase cycle. The Program/
Erase Suspend command allows a program or erase operation in progress to be suspended so that other device operations can
be performed. For example, by suspending an erase operation to a particular block, the system can perform functions such as a
program or read to a different block.
5.11.1 Command Prerequisites
None.
5.11.2 Transfer Format
The 75h and B0h commands follow the 1-0-0 transfer format described in Section 3.2, where the command is transferred on the
SI pin. No address or data are transferred for this command. See Figure 3 for a timing diagram of this operation.
5.11.3 Transfer Sequence
To perform the Program Erase/Suspend operation, the CS pin is asserted and the information transferred as follows:
The 75h or B0h command is clocked into the device. Eight clocks are required to transfer the command. The most signifi-
cant bit of the command is transferred first.
When the CS pin is deasserted, the device suspends the program.
See Table 18 for more information on the transfer sequence for this command.
5.11.4 Command Behavior During a Program/Erase Operation
If an attempt is made to perform an operation that is not allowed during a program or erase suspend, such as a Write Status
Register operation, then the device simply ignores the command and no operation is performed. The state of the WEL bit in Status
Register 1 is not affected. Note that in the table below, the RDY/BSY bit is located in Status Register 1. The PS and ES bits are
located in Status Register 5.
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Table 22: Command Behavior During Program/Erase or Program/Erase Suspend Operations
During Program
During Program or Erase
(RDY/BSY = 1, PS = x,
ES = x)
During Erase Suspend
(RDY/BSY = 0, PS = 0,
ES = 1)
Suspend
(RDY/BSY = 0, PS = 1,
ES = x)
Command
Code(s)
Command
03h, 0Bh,
3Bh, 6Bh,
EBh, E7h
Read Array
Block Erase
Not allowed
Not allowed
Allowed
Allowed
20h, 52h,
D8h
Not allowed
Not allowed
Chip Erase
60h, C7h
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Allowed 1
02h, A2h,
32h
Byte/Page Program
Sequential
Programming
ADh, AFh
B0h, 75h
D0h, 7Ah
Not allowed
Allowed
Not allowed
Not allowed
Allowed
Allowed 1
Not allowed
Allowed
Program/Erase
Suspend
Program/Erase
Resume
Not allowed
Write Enable
06h
04h
50h
36h
Not allowed
Not allowed
Not allowed
Not allowed
Allowed
Allowed
Allowed
Allowed
Write Disable
Volatile Write Enable
Individual Block Lock
Allowed
Allowed
Not allowed
Not allowed
Individual Block
Unlock
39h
Not allowed
Not allowed
Not allowed
Global Block Lock
7Eh
98h
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Global Block Unlock
Read Block Lock
Status
3Ch, 3Dh
9Bh
Not allowed
Not allowed
Not allowed
Allowed
Allowed
Not allowed
Allowed
Allowed
Not allowed
Allowed
Program OTPSecurity
Register
Read OTP Security
Register
4Bh
Read Status Registers
(direct)
05h, 35h,
15h
Allowed
Allowed
Read Status Registers
(indirect)
65h
Allowed
Allowed
Allowed
Write Status Registers
(direct)
01h, 31h,
11h
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Write Status Registers
(indirect)
71h
Status Register Lock
Terminate
6Fh
F0h
66h
Not allowed
Allowed
Not allowed
Allowed
Not allowed
Allowed
Enable Reset
Allowed
Allowed
Allowed
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
Table 22: Command Behavior During Program/Erase or Program/Erase Suspend Operations (continued)
During Program
During Program or Erase
(RDY/BSY = 1, PS = x,
ES = x)
During Erase Suspend
(RDY/BSY = 0, PS = 0,
ES = 1)
Suspend
(RDY/BSY = 0, PS = 1,
ES = x)
Command
Code(s)
Command
Reset Device
99h
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Read Mfg ID and
Device ID
9Fh, 90h,
94h
Deep Power Down
B9h
ABh
Not allowed
Allowed
Not allowed
Allowed
Not allowed
Allowed
Resume from Deep
Power Down
Ultra Deep Power
Down
79h
Not allowed
Not allowed
Not allowed
Read SFDP
5Ah
77h
Not allowed
Not allowed
Allowed
Allowed
Allowed
Allowed
Set Burst with Wrap
1. The operation is allowed in a different 64 kB block.
5.11.5 Device Status
When the CS pin is deasserted, the program or erase operation currently in progress suspends within a time of tSUSE. Hardware
sets the Suspend (SUSP) bit in Status Register 2 and the ES or PS bits in Status Register 5 to indicate that the program or erase
operation has been suspended. Also, hardware clears the RDY/BSY bit in Status Register 1 to indicate that the device is ready
for another operation.
5.11.6 Programming Restrictions
The Erase/Program Suspend command adheres to the following programming restrictions.
The following commands cannot be suspended:
Write Status Register 1 (01h)
Write Status Register 2 (31h)
Write Status Register 3 (11h)
Write Status Registers (71h)
Status Register Lock (6Fh)
Program OTP Security Registers (9Bh)
Chip Erase (60h/C7h)
Sequential Programming (AFh/ADh)
Hardware ignores the Program/Suspend command if it is issued while these commands are in progress.
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Erase Suspend and Program Suspend Ordering
Aprogram operation can be performed while an erase operation is suspended. However, that operation must be completed before
the erase operation can be resumed. Also, an erase operation cannot be performed while a program operation is suspended.
Other device operations, such as a Read Status Register, can also be performed while a program or erase operation is suspended.
Write Enable Latch Ignored
Since the need to suspend a program or erase operation is immediate, the Write Enable command does not need to be issued
prior to the Program/Erase Suspend command being issued. Therefore, the Program/Erase Suspend command operates inde-
pendently of the state of the WEL bit in the Status Register.
Deasserting the CS Pin
The complete command must be clocked into the device before the CS pin is deasserted. Also, the CS pin must be deasserted
on a byte boundary (multiples of eight bits). Otherwise, no suspend operation is performed.
Accessing a Suspended Area
If a read operation is attempted to a suspended area (page for programming or block for erasing), then the device outputs
undefined data. Therefore, when performing a Read Array operation to an unsuspended area and the device's internal address
counter increments and crosses into the suspended area, the device starts outputting undefined data until the internal address
counter crosses to an unsuspended area.
5.12 PROGRAM/ERASE RESUME (7AH/D0H)
The device supports two Program/Erase Resume commands, 7Ah and D0h, that perform the exact same function. The 7Ah
command can be used for legacy software, and the D0h command is used for compatibility with future implementations.
The Program/Erase Resume command allows a suspended program or erase operation to be resumed and continue program-
ming a Flash page or erasing a Flash memory block where it left off.
5.12.1 Command Prerequisites
Hardware accepts the Program/Erase Resume command only if the ES bit (set when an erase operation is suspended) or PS bit
(set when a program operation is suspended) in Status Register 5 is set and the RDY/BSY bit in Status Register 1 is cleared. If
the ES/PS bit is cleared or the RDY/BSY bit is set, the Program/Erase Resume command is ignored by the device. See Section
4.3, Status Register 1 and Section 4.7, Status Register 5.
Note that the Write Enable command does not need to be issued prior to the Program/Erase Resume command being issued.
Therefore, the Program/Erase Resume command operates independently of the state of the WEL bit in Status Register 1.
5.12.2 Transfer Format
The 7Ah and D0h commands follow the 1-0-0 transfer format described in Section 3.2, where the command is transferred on the
SI pin. No address or data are transferred for this command. See Figure 3 for a timing diagram of this operation.
5.12.3 Transfer Sequence
To perform the Program/Erase Resume operation, the CS pin is asserted and the information transferred as follows:
The 7Ah or D0h command is clocked into the device. Eight clocks are required to transfer the command. The most signifi-
cant bit of the command is transferred first. No address of data are required for this command.
When the CS pin is deasserted, the device resumes the program.
See Table 18 for more information on the transfer sequence for this command.
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5.12.4 Command Behavior
When the command is executed, hardware performs the following:
Hardware clears either the PS or the ES bits in Status Register 5 depending on whether a program or erase operation has
been suspended. If both of these bits are cleared, hardware clears the SUSP bit in Status Register 2.
Hardware sets the RDY/BSY bit in Status Register 1 to indicate that the device is busy.
When the CS pin is deasserted, the program or erase operation currently suspended resumes within a time of tRES
.
5.12.5 Programming Restrictions
The Program/Erase Resume command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
The CS pin must be deasserted on a byte boundary (multiples of eight bits). Otherwise, no resume operation is performed.
While the device is busy resuming a program or erase operation, any attempts at issuing the Program/Erase Suspend
command are ignored. Therefore, if a resumed program or erase operation needs to be subsequently suspended again,
the system must either wait the entire tRES time before issuing the Program/Erase Suspend command, or it can check the
status of the RDY/BSY bit in Status Register 1, or the ES/PS bits in Status Register 5 to determine if the previously sus-
pended program or erase operation has resumed.
During a simultaneous Erase Suspend/Program Suspend condition, issuing the Program/Erase Resume command results
in the program operation resuming first. After the program operation has been completed, the Program/Erase Resume
command must be issued again in order for the erase operation to be resumed. For more information, see Section 3.10.1,
Nested Operations.
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5.13 SET BURST WRAP (77H)
The Set Burst with Wrap (77h) command is used in conjunction with the EBh and E7h commands to support a cache line fill,
regardless of the starting address. This type of operation, known as ‘address wrapping’, is an MCU-friendly feature that allows
the Microcontroller Unit (MCU) cache controller to fill a cache line in one operation starting from a specific address (known as the
critical byte) within the cache line, proceeding to the end of the line, then wrapping around the start of the cache line to complete
the fill.
For example, if the wrap size is 16 bytes and the starting address is 0x1004, then the read sequence would be as follows: 0x1004,
0x1005, 0x1006, 0x1007, 0x1008, 0x1009, 0x100A, 0x100B, 0x100C, 0x100D, 0x100E, 0x100F, 0x1000, 0x1001, 0x1002,
0x1003. As shown in this sequence, the fill starts at address 0x1004, proceeds to the end of the cache line (0x100F), then wraps
around to 0x1000 to complete the fill.
The wrap feature can improve code execution performance in the MCU system, as the MCU first receives the command or data
it requires at that instant, and then fetches the remainder of the cache line without requiring additional commands or addresses
to be sent.
The 77h command is used to both enable/disable the wrap-around feature, and determine the size of the wrap. The 77h command
sets the state of bits W6, W5, and W4, as shown in Table 23.
5.13.1 Command Prerequisites
None.
5.13.2 Transfer Format
The 77h command follows the 1-4-4 transfer format described in Section 3.6, where the command is transferred on the SI pin,
and the address and data are transferred on the HOLD, WP, SO, and SI pins. See Figure 17 for a timing diagram of this command.
5.13.3 Transfer Sequence
To perform the Set Burst with Wrap operation, the CS pin is asserted and the information transferred as follows:
The 77h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three address bytes are clocked in. A total of 6 clocks are required to transfer the address. The most significant bit of the
address (A[23]) is transferred first. Even though the address must be clocked in, the address is treated as a don’t care field
internally.
Following transfer of the last address byte, eight Wrap bits are transferred which indicate the length of the wrap operation
as described in the table below.
5.13.4 Wrap Bits
After the last address byte is transferred, the device transfers eight wrap bits (W7-0), which indicate the wrap length. Note that
only wrap bits W6:W4 are used during this operation. The W7 and W3:W0 bits are not used. This is shown in Table 23.
Table 23: Encoding of Burst Wrap Bits
W4 = 0
W4 = 1
W6
W5
Wrap Length
8-byte
Wrap Around
Wrap Length
Wrap Around
0
0
1
1
0
1
0
1
Yes
Yes
Yes
Yes
N/A
N/A
N/A
N/A
No
No
No
No
16-byte
32-byte
64-byte
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Once the 77h command is executed and the W6:W4 bits are set, the subsequent EBh or E7h command uses these bits to
determine what section size to access within a given page. As shown in the table, returning to the normal read operation requires
the execution of another 77h command with the W4 bit driven high (W4 = 1).
5.13.5 Programming Restrictions
The Set Burst with Wrap command adheres to the following programming restrictions.
The CS pin must be deasserted on a byte boundary (multiples of eight bits). Otherwise, the device aborts the operation and
no action is taken.
5.14 \WRITE ENABLE (06H)
The Write Enable command is used to set the Write Enable Latch (WEL) bit in Status Register 1. The WEL bit must be set for
any of the following commands to be executed:
Byte/Page Program (02h)
Dual Output Byte/Page Program (A2h)
Quad Output Byte/Page Program (32h)
Sequential Program Mode (AFh/ADh)
Any Erase command (20h, 52h, D8h, 60h/C7h)
Program OTP Security Register (9Bh)
Write Status Register (01h, 31h, 11h, 71h)
This makes the issuance of the above commands a two step process, thereby reducing the chances of a command being
accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to the issuance of one of these
commands, that command is not executed.
5.14.1 Command Prerequisites
None.
5.14.2 Transfer Format
The 06h command follows the 1-0-0 transfer format described in Section 3.2, where the command is transferred on the SI pin.
No address or data are transferred for this command. See Figure 3 for a timing diagram of this operation.
5.14.3 Transfer Sequence
To perform the Write Enable operation, the CS pin is asserted and the information transferred as follows:
The 06h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first. No address or data are required for this command.
When the CS pin is deasserted, hardware sets the WEL bit in Status Register 1.
See Table 18 for more information on the transfer sequence for this command.
5.14.4 Programming Restrictions
The Write Enable command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no action is taken.
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5.15 WRITE DISABLE (04H)
The Write Disable command is used to clear the Write Enable Latch (WEL) bit in Status Register 1. When the WEL bit is cleared,
the following commands cannot be executed:
Byte/Page Program (02h)
Dual Output Byte/Page Program (A2h)
Quad Output Byte/Page Program (32h)
Sequential Program Mode (AFh/ADh)
Any Erase command (20h, 52h, D8h, 60h/C7h)
Program OTP Security Register (9Bh)
Write Status Register (01h, 31h, 11h, 71h)
Other conditions can also cause the WEL bit to be cleared. For more information, see Table 11.
5.15.1 Command Prerequisites
None.
5.15.2 Transfer Format
The 04h command follows the 1-0-0 transfer format described in Section 3.2, where the command is transferred on the SI pin.
No address or data are transferred for this command. See Figure 3 for a timing diagram of this operation.
5.15.3 Transfer Sequence
To perform the Write Disable operation, the CS pin is asserted and the information transferred as follows:
The 04h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first. No address or data are required for this command.
When the CS pin is deasserted, hardware clears the WEL bit in Status Register 1.
See Table 18 for more information on the transfer sequence for this command.
5.15.4 Programming Restrictions
The Write Disable command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no action is taken.
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5.16 VOLATILE STATUS REGISTER WRITE ENABLE (50H)
To write the volatile version of the Status Register bits, the Write Enable for Volatile Status Register (50h) command must be
issued prior to each Write Status Register (01h) command. The Write Enable for the Volatile Status Register command does not
set the Write Enable Latch (WEL) bit in Status Register 1. It is only valid for the next following Write Status Register command,
to change the volatile Status Register bit values.
5.16.1 Command Prerequisites
None.
5.16.2 Transfer Format
The 50h command follows the 1-0-0 transfer format described in Section 3.2, where the command is transferred on the SI pin.
No address or data are transferred for this command. See Figure 3 for a timing diagram of this operation.
5.16.3 Transfer Sequence
To perform the Write Disable operation, the CS pin is asserted and the information transferred as follows:
The 50h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first. No address or data are required for this command.
When the CS pin is deasserted, hardware performs the operation.
See Table 18 for more information on the transfer sequence for this command.
5.16.4 Programming Restrictions
The Volatile Status Register Write Enable command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no action is taken.
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5.17 INDIVIDUAL BLOCK LOCK (36H)
The Individual Block Lock command can be used to protect individual pages in the memory array from being programmed or
erased via one of the Program or Erase commands. To enable the individual block lock function, the WPS bit in Status Register
3 must be set. If the WPS bit is cleared, write protection is then determined by the combination of the CMPRT, BPSIZE, TB, and
BP[2:0] bits in the Status Register 1. The default value for each individual lock bit is 1 at power-up or reset, so the entire memory
array is protected.
5.17.1 Command Prerequisites
The Write Enable (06h) command must be executed before the device can accept the Individual Block Lock command. This is
required to set the WEL bit in Status Register 1.
5.17.2 Transfer Format
The 36h command follows the 1-1-0 transfer format described in Section 3.2, where the command and address are transferred
on the SI pin. The address represents the individual block to be locked. Hence no data is transferred for this command.
5.17.3 Transfer Sequence
To perform the Individual Block Lock operation, the CS pin is asserted and the information transferred as follows:
The 36h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three address bytes are clocked in to specify the address location to be locked within the memory array. A total of 24
clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
When the CS pin is deasserted, hardware performs the operation and clears the WEL bit in Status Register 1.
See Table 18 for more information on the transfer sequence for this command.
5.17.4 Programming Restrictions
The Individual Block Lock command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no action is taken.
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5.18 INDIVIDUAL BLOCK UNLOCK (39H)
The Individual Block Unlock command can be used to unlock individual pages in the memory array to allow them to be pro-
grammed or erased via one of the Program or Erase commands. To enable the individual block unlock function, the WPS bit in
Status Register 3 must be set. If WPS is cleared, write protection is then determined by the combination of the CMP, SEC, TB,
and BP[2:0] bits in Status Register 1. The default value for each individual lock bit is 1 at power-up or reset, so the entire memory
array is being protected.
5.18.1 Command Prerequisites
The Write Enable (06h) command must be executed before the device can accept the Individual Block Unlock command. This is
required to set the WEL bit in Status Register 1.
5.18.2 Transfer Format
The 39h command follows the 1-1-0 transfer format described in Section 3.2, where the command and address are transferred
on the SI pin. The address represents the individual block to be unlocked. Hence no data is transferred for this command. See
Figure 4 for a timing diagram of this transaction.
5.18.3 Transfer Sequence
To perform the individual block unlock operation, the CS pin is asserted and the information transferred as follows:
The 39h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three address bytes are clocked in to specify the address location to be unlocked within the memory array. A total of 24
clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
When the CS pin is deasserted, hardware performs the operation and clears the WEL bit in Status Register 1.
See Table 18 for more information on the transfer sequence for this command.
5.18.4 Programming Restrictions
The Individual Block Unlock command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no action is taken.
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5.19 READ BLOCK LOCK (3CH/3DH)
The Read Block Lock commands allow the user to read the status of the lock bits in each block. The individual block locks
are used to protect any individual block. The default value for all individual block lock bits is 1 upon device power on or after reset.
The 3Ch and 3Dh commands perform the exact same operation. These two commands are identical and are provided for
backward compatibility purposes.
5.19.1 Command Prerequisites
The WPS bit in Status Register 3 must be set. When WPS is set, software uses the Block Lock (36h) and Block Unlock (39h)
commands to lock and unlock blocks of memory. If the WPS bit is cleared, write protection is determined by the combination of
CMP, SEC, TB, BP[2:0] bits in the Status Registers. The Read Block Lock command must not be used to determine the protection
status of any region of the memory. See Section 3.8.1 for more information on the protection scheme.
5.19.2 Transfer Format
The 3Ch and 3Dh commands follow the 1-1-1 transfer format described in Section 3.2, where the command and address are
transferred on the SI pin, and data is transferred on the SO pin. Figure 7 shows a timing diagram for this transaction.
5.19.3 Transfer Sequence
To perform the Read Block Lock operation, the CS pin is asserted and the information transferred as follows:
The 3dh or 3Dh command is clocked into the device. Eight clocks are required to transfer the command. The most signifi-
cant bit of the command is transferred first.
Three address bytes are clocked in to specify the starting address location of the first byte to read within the buffer. A total
of 24 clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
Data is output on the SO pin and requires eight clock cycles. The MSB of the lock value is driven onto the SO pin first,
and the LSB is driven out last. If the LSB is 1, the corresponding block is locked and no erase or program operation
can be executed to that block. If the LSB is 0, the block is unlocked, indicating that program/erase operations are
allowed. The remaining bits 7:1 of this value are undefined.
If CS is kept low and additional data is clocked out, the device simply repeats the same byte over and over again until CS
goes high. Out of the 8 bits in this byte, the LSB (bit 0) has the lock bit information, the rest of the are undefined. The lock
bit information corresponds to the region of memory that encapsulates the 20-bit address provided by the user. So for
example:
- If the user provides an address of 0x000000, the device returns the lock status of the 4 kB region from 0x000000 -
0x000FFF.
- If the user provides an address of 0x001234, the device returns the lock status of the 4 kB region 0x001000 - 0x001FFF.
5.19.4 Programming Restrictions
The Read Block Lock command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
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5.20 GLOBAL BLOCK LOCK (7EH)
The Global Block Lock command is used to set all of the block bits to 1 with one operation.
5.20.1 Command Prerequisites
The Write Enable command (06h) must be executed to set WEL bit in Status Register 1 before the Global Block Lock command
can be executed. See Section 5.14, \Write Enable (06h) for more information.
5.20.2 Transfer Format
The 7Eh command follows the 1-0-0 transfer format described in Section 3.2, where the command is transferred on the SI pin.
No address or data are transferred for this command. See Figure 3 for a timing diagram of this operation.
5.20.3 Transfer Sequence
To perform the Global Block Lock operation, the CS pin is asserted and the information transferred as follows:
The 7Eh command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first. No address or data are required for this command.
When the CS pin is deasserted, hardware performs the operation and clears the WEL bit in Status Register 1.
See Table 18 for more information on the transfer sequence for this command.
5.20.4 Programming Restrictions
The Global Block Lock command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no action is taken.
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5.21 GLOBAL BLOCK UNLOCK (98H)
The Global Block UnLock command is used to reset all of the block bits to 0 with one operation.
5.21.1 Command Prerequisites
The Write Enable command (06h) must be executed to set WEL bit in Status Register 1 before the Global Block Unlock command
can be executed. See Section 5.14, \Write Enable (06h) for more information.
5.21.2 Transfer Format
The 98h command follows the 1-0-0 transfer format described in Section 3.2, where the command is transferred on the SI pin.
No address or data are transferred for this command. See Figure 3 for a timing diagram of this operation.
5.21.3 Transfer Sequence
To perform the Global Block Unlock operation, the CS pin is asserted and the information transferred as follows:
The 98h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first. Since all blocks are unlocked with this command, no address or data are required.
When the CS pin is deasserted, hardware performs the operation and clears the WEL bit in Status Register 1.
See Table 18 for more information on the transfer sequence for this command
5.21.4 Programming Restrictions
The Global Block Unlock command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no action is taken.
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5.22 PROGRAM SECURITY REGISTER (9BH)
There are four specialized 128-byte OTP (One-Time Programmable) Security Registers that can be used for purposes such as
unique device serialization and locked key storage.
5.22.1 Command Prerequisites
Before the Program OTP Security Register command can be issued, the Write Enable command (06h) must be executed to set
WEL bit in Status Register 1. See Section 5.14, \Write Enable (06h) for more information.
5.22.2 OTP Security Register Layout
The OTP Security Registers are independent of the main Flash memory array. The four registers are organized as follows:
Table 24: OTP Security Register 0 Bit Assignments
Security Register Byte Number
127
126
125
.....
2
1
0
Factory Programmed by Dialog Semiconductor
Table 25: OTP Security Register 1 Bit Assignments
Security Register Byte Number
255
254
253
.....
130
258
386
129
257
385
128
256
384
User Security OTP Register
Table 26: OTP Security Register 2 Bit Assignments
Security Register Byte Number
383
382
381
.....
User Security OTP Register
Table 27: OTP Security Register 3 Bit Assignments
Security Register Byte Number
511
510
509
.....
User Security OTP Register
5.22.3 Transfer Format
The 9Bh command follows the 1-1-1 transfer format described in Section 3.2, where the command and address are transferred
on the SI pin, and data is transferred on the SO pin. See Figure 9 for timing diagram of this transfer.
5.22.4 Transfer Sequence
To perform the Program OTP Register operation, the CS pin is asserted and the information transferred as follows:
The 9Bh command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three address bytes are clocked in to specify the starting address location of the first byte to read within the memory array.
A total of 24 clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
For this command, address bits 23:9 are don’t care. Only bits 8:0 are used to address the appropriate Security register.
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See Table 28 for an encoding of the address.
Data is input on the SI pin. Each byte transfer requires eight clock cycles. The data is always input with the most significant
bit of the byte transferred first. The number of bytes transferred is determined by software. The transfer can be anywhere
from a single byte to the entire OTP register array. Additional data bytes are transferred every eight clocks as long as the
CS pin is asserted. The programming of the data bytes is internally self-timed and takes place in a time of tOTPP if the
entire 128-byte register is programmed at once.
When the CS pin is deasserted, the device takes the data stored in the internal buffer and programs it into the appropriate
OTP Security Register locations based on the starting address specified by A8-A0 and the number of data bytes sent to the
device.
Note that the Program OTP Security Register command utilizes an internal 256-buffer for processing. Therefore, the contents of
the buffer is altered from its previous state when this command is issued.
See Table 18 for more information on the transfer sequence for this command.
5.22.5 Addressing the OTP Security Registers
Each byte within the four OTP security registers can be accessed using bits 8:0 of the address. Bits 23:9 of the address are
ignored. The lower 7 bits (6:0) are used to select a byte within a given 128-byte OTP register. The next two bits (8:7) are used to
select one of the four OTP registers. This is shown in Table 28.
Table 28: OTP Register Access Address Map
Address
23:9
A8
0
A7
0
A6
A5
A4
A3
A2
A1
A0
OTP Security Register 0 (Factory Programmed by Dialog Semiconductor)
A[6:0] = 0000000 - byte 0, A[6:0] = 1111111 - byte 127
Don’t care
User defined OTP Security Register 1
A[6:0] = 0000000 - byte 128, A[6:0] = 1111111 - byte 255
Don’t care
Don’t care
Don’t care
0
1
1
1
0
1
User defined OTP Security Register 2
A[6:0] = 0000000 - byte 256, A[6:0] = 1111111 - byte 383
User defined OTP Security Register 3
A[6:0] = 0000000 - byte 384, A[6:0] = 1111111 - byte 511
5.22.6 Programming Status
While the device is programming the OTP Security Register, the RDY/BSY bit in Status Register 1 can be read to determine if
the operation is still in progress. For faster throughput, it is recommended that the Status Register be polled rather than waiting
the tOTPP time to determine if the data bytes have finished programming. At some point before the OTP Security Register
programming completes, hardware clears the WEL bit in the Status Register.
5.22.7 Locking OTP Registers 1 - 3
The tables above show the bytes associated with each OTP register. OTP register 0 is locked by default as the value is pro-
grammed by Dialog Semiconductor at the factory and cannot be changed. For OTP registers 1 - 3, the most significant byte is as
follows:
OTP Register 1: MSB = byte 255
OTP Register 2: MSB = byte 383
OTP Register 3: MSB = byte 511
For OTP registers 1 - 3, bit-level programming is allowed for the first 127 bytes of the registers. However, the register is locked
whenever one or more bits of the most significant byte are programmed. For example, if any bit of byte 255 in OTP register 1 is
programmed, that register is locked by hardware can cannot be programmed further.
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5.22.8 Verifying the Locked Status of a Security Register
As described in the previous subsection, once any bit in the MSB of Security registers 1 - 3 is written, the register is locked and
not further programming is allowed. Software can determine the Locked status of each register by reading bits 5:3 (SL3:SL1) of
Status Register 2. Each bit corresponds to one of the user defined OTP security registers. If the corresponding bit is cleared, the
register is not locked. If the corresponding bit is set, the register is locked and cannot be programmed. See Section 4.4, Status
Register 2 for more information.
5.22.9 Programming Restrictions
The Program OTP Register command adheres to the following program restrictions.
Early Power Down
If the device is powered-down during the OTP Security Register program cycle, then the contents of the 128-byte user program-
mable portion of the OTP Security Register cannot be guaranteed and may not be programmed again.
Deasserting the CS Pin
The CS pin must be deasserted on a byte boundary (multiples of eight bits). Otherwise, the device aborts the operation and the
user-programmable portion of the OTP Security Register is not programmed.
Incomplete Address or Data
The WEL bit in the Status Register is cleared if the OTP Security Register program cycle aborts due to an incomplete address
being sent or an incomplete byte of data being sent.
Register Previously Programmed
Prior to programming an OTP register, hardware checks the state of the SL3:1 field in Status Register 2. For example, if an attempt
is made to program OTP register 1, and the register was previously programmed as indicated by the SL1 bit in Status Register
2 being set, the operation is aborted.
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5.23 READ OTP SECURITY REGISTER (4BH)
The Read OTP Security Register command accesses the four specialized OTP security registers. Any portion of the value can
be read out depending on when the CS pin is deasserted.
5.23.1 Command Prerequisites
None.
5.23.2 Transfer Format
The 4Bh command follows the 1-1-1 transfer format described in Section 3.2, where the command and address are transferred
on the SI pin, and data is transferred on the SO pin. See Figure 7 for a timing diagram of this transaction. In this diagram a single
byte of data is shown.
5.23.3 Transfer Sequence — Single Register
To perform the Read OTP Security register operation of a single register, the CS pin is asserted and the information transferred
as follows:
The 4Bh command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three address bytes are clocked in to specify the starting address location of the first byte to read within the memory array.
A total of 24 clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
The address breakdown is as follows:
- A[23:9] are don’t care
- A[8:0] indicate the byte address
Following the three address bytes, an additional dummy byte must be clocked into the device.
Data is output on the SO pin. Each byte transfer requires eight clock cycles. The data is always output with the most signif-
icant bit of the byte transferred first. The number of bytes transferred depends on how long the CS pin remains asserted. A
total of 1024 clocks would be required to shift out all 128 bytes of data.
5.23.4 Transfer Sequence — All Registers
To perform the Read OTP Security register operation of all four register, the transfer sequence is the same as above, except that
the CS pin remains asserted until all registers are read. As noted above, a total of 1024 clocks would be required to read one
register. Therefore, a total of 4096 clocks would be required to read out the contents of all four registers.
See Table 18 for more information on the transfer sequence for this command.
5.23.5 Programming Restrictions
None.
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5.24 READ STATUS REGISTERS 1 - 3 (05H, 35H, 15H)
Three Read Status Register commands are used to perform a direct read of Status registers 1 - 3. These registers can also be
indirectly accessed using the 65h command as described in the following section. In the direct method, a specific command is
executed. Hardware decodes this command and retrieves data from the appropriate Status register. No address field is required.
Status registers 1 - 3 are accessed by the following commands.
Read Status Register 1: 05h
Read Status Register 2: 35h
Read Status Register 3: 15h
5.24.1 Command Prerequisites
None.
5.24.2 Transfer Format
The 05h/35h/15h commands follow the 1-0-1 transfer format described in Section 3.2, where the command is transferred on the
SI pin, and data is transferred on the SO pin. No address is required for this command. See Figure 5 for a timing diagram of this
transaction.
5.24.3 Transfer Sequence
To perform the Read Status Register register operation, the CS pin is asserted and the information transferred as follows:
The 05h/35h/15h command is clocked into the device. Eight clocks are required to transfer the command. The most signif-
icant bit of the command is transferred first.
Data is output on the SO pin. Each byte transfer requires eight clock cycles. The data is always output with the most signif-
icant bit of the byte transferred first. After the last bit (0) of the Status Register has been clocked out, the sequence repeats
itself, starting again with bit 7 of the selected register byte. This continues as long as the CS pin remains asserted and the
clock pin is being pulsed. The data in the Status Register is constantly being updated, so each repeating sequence may
output new data.
Deasserting the CS pin terminates the Read Status Register operation and put the SO pin into a high-impedance state.
The CS pin can be deasserted at any time and does not require that a full byte of data be read.
See Table 18 for more information on the transfer sequence for this command.
5.24.4 Programming Restrictions
None.
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5.25 READ STATUS REGISTERS (65H)
The Read Status Register command works in conjunction with an 8-bit address field to perform an indirect read of Status registers
1 - 5. Registers 1 - 3 can also be directly accessed as described in the previous section. In the indirect method, a Read Status
register command (65h) is executed. Hardware decodes this command and retrieves data from the appropriate Status register
as directed by the 8-bit address field, which follows the command in the sequence. Status registers 1 - 5 are read in the following
manner.
Table 29: Indirect Addressing of the Status Registers
Byte 0
Command
65h
Byte 1
Address
01h
Byte 2
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Byte 3
Output
S[7:0]
Action
Read Status Register 1
Read Status Register 2
Read Status Register 3
Read Status Register 4
Read Status Register 5
65h
02h
S[15:8]
S[23:16]
S[31:24]
S[39:32]
65h
03h
65h
04h
65h
05h
5.25.1 Command Prerequisites
None.
5.25.2 Transfer Format
The 65h command follows the 1-1-1 transfer format described in Section 3.2, where the command and address are transferred
on the SI pin, and data is transferred on the SO pin. Figure 7 shows a timing diagram for this operation.
5.25.3 Transfer Sequence
To perform the Read Status Register operation, the CS pin is asserted and the information transferred as follows:
The 65h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
One address byte is clocked in to specify the address the register to be written. A total of 8 clocks are required to transfer
the address. The most significant bit of the address (A[7]) is transferred first.
Following the one address byte, one dummy byte is clocked into the device.
Data is output on the SO pin. Each byte transfer requires eight clock cycles. The data is always output with the most signif-
icant bit of the byte transferred first. The number of bytes transferred is determined by software. The transfer can be any-
where from a single register to all five registers.
Deasserting the CS pin terminates the read operation and puts the SO pin into high-impedance state. The CS pin can be
deasserted at any time and does not require a full byte of data be read.
See Table 18 for more information on the transfer sequence for this command.
5.25.4 Reading a Single Status Register
To read a specific Status Register, the CS pin must first be asserted and the corresponding command of 65h must be clocked
into the device. After the command has been clocked in, the 8-bit address of the register to be read is clocked into the device, as
shown in the above table. Once the address is decoded, hardware begins outputting Status Register data on the SO pin during
every subsequent clock cycle.
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5.25.5 Continuous Read of All Status Registers
To read all five Status registers in sequence, execute a 65h command with the address field equivalent to 01h. Once the contents
of Status Register 1 are read out, the hardware increments the address automatically and begins reading the contents of Status
Register 2. This continues until all five Status registers have been read out as long as the CS pin remains asserted and the clock
pin is being pulsed. Once the process is started, data is input and output from the device as follows:
Table 30: Indirect Status Register Read Sequence
Clocks
0 - 7
Action
Command 65h. Clocks 0 - 3 = 0110, and clocks 4 - 7 = 0101.
Address 01h. Clocks 8 - 11 = 0000, and clocks 12 - 15 = 0001.
Dummy byte on clocks 16 - 23.
8 - 15
16 - 23
24 - 31
32 - 39
40 - 47
48 - 55
56 - 63
64 - xx
Status Register 1 data. Clock 24 = bit 7, and clock 31 = bit 0.
Status Register 2 data. Clock 32 = bit 7, and clock 39 = bit 0.
Status Register 3 data. Clock 40 = bit 7, and clock 47 = bit 0.
Status Register 4 data. Clock 48 = bit 7, and clock 55 = bit 0.
Status Register 5 data. Clock 56 = bit 7, and clock 63 = bit 0.
Data is undefined.
5.25.6 Transfer Diagram
Figure 26 shows the bus signals during an indirect register read operation. This type of command requires only a single 8-bit
address, as shown below.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SCK
SI
COMMAND
ADDRESS BITS A7-A0
DUMMY
0
1
1
0
0
1
0
1
A
A
A
A
A
A
A
A
X
X
X
X
X
X
X
X
MSB
MSB
MSB
DATA OUT 1
HIGH-IMPEDANCE
D
D
D
D
D
D
D
D
D
D
SO
MSB
MSB
Figure 26: Status Register Read Operation Showing 8-bit Address Field
5.25.7 Programming Restrictions
The Read Status Register command adheres to the following programming restrictions.
Reading Register Addresses 7 Through 255
As the address is an 8-bit value, the device continues to read up to 255 register bytes as long as the CS pin remains asserted,
even though only five registers are implemented at this time. Starting with a read of register 6 through register 255, the device
returns undefined data. If the CS pin remains asserted and all 255 bytes are read out, the address wraps around from FFh to 00h.
This continues until the CS pin is deasserted.
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5.26 WRITE STATUS REGISTERS 1 - 3 — DIRECT (01H, 31H, 11H)
The Write Status Register commands are used to perform a direct write of Status registers 1 - 3. These registers can also be
indirectly accessed as described in the following section. In the direct method, a specific command is executed. Hardware
decodes this command and writes the data to the appropriate Status register. No address field is required. Status registers 1 - 3
are accessed by the following commands.
Write Status Register 1: 01h
Write Status Register 2: 31h
Write Status Register 3: 11h
5.26.1 Command Prerequisites
To write the volatile version of the Status Register bits, the Write Enable for Volatile Status Register (50h) command must be
issued prior to each Write Status Register (01h/31h/11h) command. The Write Enable for the Volatile Status Register command
does not set the Write Enable Latch (WEL) bit in Status Register 1. It is only valid for the next following Write Status Register
command, to change the volatile Status Register bit values.
To write the non-volatile version of the Status Register bits, the Write Enable (06h) command must be issued prior to each Write
Status Register (01h/31h/11h) command.
5.26.2 Transfer Format
The 01h/31h/11h commands follow the 1-0-1 transfer format described in Section 3.2, where the command and data are trans-
ferred on the SI pin. No address is required for this command. See Figure 6 for a timing diagram of this transaction.
5.26.3 Transfer Sequence
To perform the Write Status Register register operation, the CS pin is asserted and the information transferred as follows:
The 01h/31h/11h command is clocked into the device. Eight clocks are required to transfer the command. The most signif-
icant bit of the command is transferred first.
Data is input on the SI pin. Each byte transfer requires eight clock cycles. The data is always input with the most significant
bit of the byte transferred first.
When the CS pin is deasserted, hardware clears the WEL bit in Status Register 1.
See Table 18 for more information on the transfer sequence for this command.
5.26.4 Programming Restrictions
The Write Status Register command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no action is taken.
For compatibility with legacy devices, command 01h can also be used with 2 bytes of data. In such case, the second byte
is written to Status Register 2.
To ensure that only Status Register 1 is written, command 01h is used with one data byte only.
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5.27 WRITE STATUS REGISTERS — INDIRECT (71H)
The Write Status Register command works in conjunction with an 8-bit address field to perform an indirect write of Status registers
1 - 5. Registers 1 - 3 can also be directly accessed as described in the previous section. In the indirect method, a Write Status
register command (71h) is executed. Hardware decodes this command and writes data to the appropriate Status register using
the 8-bit address field, which follows the command in the sequence. Status registers 1 - 5 are written in the following manner.
Table 31: Indirect Addressing of the Status Registers
Byte 0
Command
71h
Byte 1
Address
01h
Byte 2
Write Data
S[7:0]
Action
Write Status Register 1
Write Status Register 2
Write Status Register 3
Write Status Register 4
Write Status Register 5
71h
02h
S[15:8]
71h
03h
S[23:16]
S[31:24]
S[39:32]
71h
04h
71h
05h
5.27.1 Command Prerequisites
The Write Enable command (06h) must be executed to set WEL bit in Status Register 1 before the Write Status Register (71h)
command can be executed. See Section 5.14, \Write Enable (06h) for more information.
To write the volatile version of the Status Register bits, the Write Enable for Volatile Status Register (50h) Command must be
issued prior to each Write Status Register (71h) command. The Write Enable for the Volatile Status Register command does not
set the Write Enable Latch (WEL) bit in Status Register 1. It is only valid for the next following Write Status Register command,
to change the volatile Status Register bit values.
To write the non-volatile version of the Status Register bits, the Write Enable (06h) command must be issued prior to each Write
Status Register (01h/31h/11h) command.
5.27.2 Transfer Format
The 71h command follows the 1-1-1 transfer format described in Section 3.2, where the command, address, and data are
transferred on the SI pin. Figure 7 shows a timing diagram for this operation.
5.27.3 Transfer Sequence
To perform the Write Status Register operation, the CS pin is asserted and the information transferred as follows:
The 71h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
One address byte is clocked in to specify the address of the register to be written. A total of 8 clocks are required to transfer
the address. The most significant bit of the address (A[7]) is transferred first.
Data is input on the SI pin. Each byte transfer requires eight clock cycles. The data is always input with the most significant
bit of the byte transferred first. If more than one byte of data is provided before the CS pin is deasserted, no register is writ-
ten.
See Table 18 for more information on the transfer sequence for this command.
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
5.27.4 Writing to a Status Register
To write a specific Status Register, the CS pin must first be asserted and the corresponding command of 71h must be clocked
into the device. After the command has been clocked in, the 8-bit address of the register to be written is clocked into the device,
as shown in the above table. Once the address is decoded, hardware begins writing to the Status Register with the data on the
SI pin. This sequence in Table 32 shows a write to Status Register 1.
Table 32: Indirect Status Register Write Sequence
Clocks
0 - 7
Action
Command 71h. Clocks 0 - 3 = 0111, and clocks 4 - 7 = 0001.
Address 01h. Clocks 8 - 11 = 0000, and clocks 12 - 15 = 0001.
Status Register 1 write data. Clock 16 = bit 7, and clock 23 = bit 0.
8 - 15
16 - 23
5.27.5 Transfer Diagram
Figure 27 shows the bus signals during an indirect register write operation. This type of command requires only a single 8-bit
address.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
COMMAND
ADDRESS BITS A7-A0
DATA IN
0
1
1
1
0
0
0
1
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
MSB
MSB
MSB
HIGH-IMPEDANCE
SO
Figure 27: Status Register Write Operation Showing 8-bit Address Field
5.27.6 Programming Restrictions
The Write Status Registers command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no action is taken.
The AT25FF161A device implements Status registers 1 - 5 at addresses 0x01 through 0x05. If the user attempts to write to
a register that is not defined or reserved (addresses 0x00, or 0x06 - 0xFF), then the device does not write to any Status
register byte. Instead the operation is aborted and hardware clears the WEL bit in Status register 1 once the CS pin is
deasserted.
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5.28 STATUS REGISTER LOCK (6FH)
The Status Register Lock command is used to explicitly lock the Status registers when the SRP1 and SRP0 bits in Status Registers
2 and 1 are set. Once this occurs, they can no longer be programmed. This command is provided to eliminate the possibility of
inadvertently locking the registers by accidentally setting the SRP1 and SRP0 bits in Status Registers 2 and 1. Even if these two
bits are set to 2’b11, this command, along with two verification bytes, is required in order for hardware to lock the Status registers.
5.28.1 Command Prerequisites
The Write Enable command (06h) must be executed to set the WEL bit in Status Register 1 before the Status Register Lock
command can be executed. See Section 5.14, \Write Enable (06h) for more information.
5.28.2 Transfer Format
The 6Fh command follows a special 1-0-1 transfer format described in Section 3.2, where the command, address, and data are
transferred on the SI pin. However, for this command, two verification bytes are transferred. Figure 28 shows a timing diagram
for this operation.
5.28.3 Transfer Sequence
To perform the Status Register Lock operation, the CS pin is asserted and the information transferred as follows:
The 6Fh command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Data is input on the SI pin. The first verification byte of 4Dh is transferred, followed by a second verification byte of 67h.
Each byte transfer requires eight clock cycles. The data is always input with the most significant bit of the byte transferred
first. Note that these values must be transferred in the correct order. If a value other than 4Dh followed by 67h is trans-
ferred, the operation is aborted.
See Table 18 for more information on the transfer sequence for this command.
5.28.4 Transfer Diagram
Figure 28 shows the bus signals during a Status Register Lock operation. In this transfer the command is followed by two
verification bytes.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
COMMAND
VERIFICATION BYTE 1
VERIFICATION BYTE 2
0
1
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
MS B
MSB
MSB
HIGH-IMPEDANCE
SO
Figure 28: Status Register Lock Operation with Two Verification Bytes
5.28.5 Programming Restrictions
The Write Status Registers command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no action is taken.
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5.29 DEEP POWER DOWN (B9H)
The Deep Power-Down command is used in conjunction with bit 7 (PDM) in Status register 4 to place the device into Deep Power-
Down mode. When the PDM bit is set and the B9h command is executed, the device enters Deep Power Down mode.
When the device is in Deep Power-Down mode, most commands, including the Read Status Register command, are ignored.
The only commands that are accepted while in this mode are the Resume from Deep Power-Down command (ABh), the Enable
Reset command (66h), and the Reset Device (99h) commands. Since all other commands are ignored, the mode can be used
as an extra protection mechanism against program and erase operations. When the CS pin is deasserted, the device enters the
Deep Power-Down mode within the maximum time of tEDPD
5.29.1 Command Prerequisites
None.
.
5.29.2 Transfer Format
The B9h command follows the 1-0-0 transfer format described in Section 3.2, where the command is transferred on the SI pin.
No address or data are transferred for this command. See Figure 3 for a timing diagram of this operation.
5.29.3 Transfer Sequence
To perform the Deep Power Down operation, the CS pin is asserted and the information transferred as follows:
The B9h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
When the CS pin is deasserted, the device begins the power down operation.
See Table 18 for more information on the transfer sequence for this command.
5.29.4 Programming Restrictions
The Deep Power Down command adheres to the following programming restrictions.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation.
The B9h command is ignored if an internally self-timed operation such as a program or erase cycle is in progress. In this
case, the B9h command must be reissued after the internally self-timed operation has been completed. Software can mon-
itor the RDY/BSY bit in Status Register 1 to determine when the program or erase operation has completed.
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5.30 RESUME FROM ULTRA-DEEP POWER DOWN / DEEP POWER DOWN WITH DEVICE ID (ABH)
In order to exit the Deep Power Down (DPD) mode and resume normal device operation, the Resume from Deep Power-Down
(ABh) command must be issued. This command, along with the 66h/99h Reset Enable/Reset command, are the only commands
that the device recognizes while in the Deep Power-Down mode. This command allows both the exit from DPD mode, as well as
a fetch of the Device ID. Which operation is executed depends on the way in which CS is used as described below.
The ABh command can also be used to exit from Ultra-Deep Power Down (UDPD) mode. Execution of this command while in
Ultra-Deep Power Down causes the device to initialize, and then enters standby mode, where it is ready to accept commands.
5.30.1 Command Options
As mentioned above, the ABh command can be used to exit both DPD and UDPD modes. In DPD mode, execution of the ABh
command causes the device to exit the DPD state, and also fetch the device ID, as described in Section 5.30.4 below. In UDPD
mode, the ABh command is used to exit the UDPD state as described in Section 5.30.5 below. Table 33 shows how to exit the
DPD and UDPD modes.
Table 33: Options for Exiting DPD and UDPD Modes
Currently in
DPD Mode?
Currently in
UDPD Mode?
Command
Exit DPD Mode
Exit UDPD Mode
Fetch Device ID
No
Yes
No
No
No
No
Yes
No
No
No
Yes
Yes
No
ABh
Yes
Yes
5.30.2 Command Prerequisites
None.
5.30.3 Transfer Format — Resume from Deep Power Down
For this operation, theABh command follows the 1-0-0 transfer format described in Section 3.2, where the command is transferred
on the SI pin. No address or data are transferred for this command. See Figure 3 for a timing diagram of this operation.
5.30.4 Transfer Format — Resume from Deep Power Down and Obtain Device ID
For this operation, theABh command follows the 1-1-1 transfer format described in Section 3.2, where the command is transferred
on the SI pin and address and data on the SO pin. See Figure 7 for a timing diagram of this operation. Note that no address is
transferred for this command. Rather, three dummy bytes are transferred in place of the address.
5.30.5 Transfer Sequence — Resume from Deep Power Down
To perform the Resume from Deep Power Down operation, the CS pin is asserted and the information transferred as follows:
The ABh command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit
of the command is transferred first.
For this operation, the CS pin must be deasserted on the 8th clock, immediately after the command is issued. This causes
the device begins the resume from power down operation. When the CS pin is deasserted after the 8th clock, the device
exits the Deep Power-Down mode within the maximum time of tRDPD and returns to the standby mode. After the device has
returned to the standby mode, normal command operations such as Read Array can be resumed.
See Table 18 for more information on the transfer sequence for this command.
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5.30.6 Transfer Sequence — Resume from Deep Power Down and Obtain Device ID
To perform the Resume from Deep Power Down operation, the CS pin is asserted and the information transferred as follows:
The ABh command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit
of the command is transferred first.
Three dummy bytes are then clocked in for the address. These clocks are required to provide time for the device to exit
power down mode and fetch the device ID. A total of 24 clocks are required to transfer the three dummy bytes.
For this operation, the CS pin continues to be asserted after the 8th clock. In this operation, the CS pin is held low for the
time it takes to transfer the Device ID. Therefore, 40 clocks are required to complete this operation; 8 for the command, 24
for the dummy bytes, and 8 clocks for the device ID.
The device ID is shifted out on the SO pin, with the most significant bit of the value being transmitted first. The device ID is
read out continuously until the CS pin is deasserted.
5.30.7 Transfer Sequence — Resume from Ultra-Deep Power Down
To perform the resume from Ultra-Deep Power Down operation, the CS pin is asserted and the information transferred as follows:
The ABh command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit
of the command is transferred first.
Once CS is deasserted, hardware initiates an internal reset of the device and the SRAM contents are lost.
The device exits the Ultra Deep Power-Down mode within the time tRUDPD as defined in Section 6.5.
Figure 29 shows a timing diagram of this timing parameter.
CS
tRDPD
t
RUDPD
0
1
2
3
4
5
6
7
SCK
SI
OPCODE
1
MSB
0
1
0
1
0
1
1
HIGH-IMPEDANCE
Active Current
SO
I
CC
Deep Power Down mode or
Standby Mode Current
de Current
Ultra-Deep Power Down mode current
Figure 29: Resume from Deep Power Down or Ultra-Deep Power Down
5.30.8 Programming Restrictions
The Resume from Deep Power Down command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no action is taken.
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5.31 ULTRA-DEEP POWER DOWN (79H)
The Ultra-Deep Power-Down (UDPD) mode allows the device to further reduce energy consumption compared to Deep Power-
Down mode by shutting down additional internal circuitry. The UDPD mode can be entered by either executing the 79h command,
or by executing the B9h command with bit 7 (PDM) of Status Register 4 cleared. When the device is in the Ultra-Deep Power-
Down mode, all commands except the ABh command are ignored.
Execution of the ABh command allows the device to exit from Ultra-Deep Power Down mode. Execution of this command while
in Ultra-Deep Power Down causes the device to initialize, and then enters standby mode.
5.31.1 Command Prerequisites
None.
5.31.2 Transfer Format
The 79h command follows the 1-0-0 transfer format described in Section 3.2, where the command is transferred on the SI pin.
No address or data are transferred for this command. See Figure 3 for a timing diagram of this operation.
5.31.3 Transfer Sequence
To perform the Ultra-Deep Power Down operation, the CS pin is asserted and the information transferred as follows:
The 79h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
When the CS pin is deasserted, the device enters the Ultra-Deep Power-Down mode within the maximum time
of t
. Any additional data clocked into the device after this command is ignored.
EUDPD
Figure 30 shows a diagram with this timing parameter.
CS
tEUDPD
0
1
2
3
4
5
6
7
SCK
SI
Opcode
0
MSB
1
1
1
1
0
0
1
High-impedance
SO
Active Current
I
CC
Standby Mode Current
Ultra-Deep Power-Down Mode Current
Figure 30: Entering Ultra-Deep Power Down State
See Table 18 for more information on the transfer sequence for this command.
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5.31.4 Programming Restrictions
The following events can cause the Ultra-Deep Power Down operation to be aborted.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
return to the standby mode once the CS pin is deasserted. Also, the device defaults to the standby mode after a power
cycle.
The 79h command is ignored if an internally self-timed operation such as a program or erase cycle is in progress. The 79h
command must be reissued after the internally self-timed operation has been completed. Software can monitor the RDY/
BSY bit in Status Register 1 to determine when the program or erase operation has completed.
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5.32 ENABLE RESET (66H) AND RESET DEVICE (99H)
Executing the Reset (66h/99h) command terminates all internal operations and causes the device to initialize. After reset, the
device is set to its default parameters and all previous register settings are lost.
5.32.1 Command Prerequisites
None.
5.32.2 Transfer Format
The 66h/99h commands are issued as two back-to-back 1-0-0 commands described in Section 3.2. The first command (66h)
enables the reset function and is transferred on the SI pin. The second command (99h) immediately follows the 66h command
and initiates a reset of the device. This command is also transferred on the SI pin. No address or data are transferred for this
command. See Figure 3 for a timing diagram of this operation.
5.32.3 Transfer Sequence
To perform a device reset operation, the CS pin is asserted and the information transferred as follows:
The 66h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Deassert the CS pin for one clock cycle.
Reassert the CS pin.
The 99h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first. Note that no other command can be issued in between the 66h command and the 99h
command.
When the CS pin is deasserted after the 99h command, the device initiates the reset operation within a time of tSWRST
.
During the reset sequence, no other command can be accepted by the device.
See Table 18 for more information on the transfer sequence for this command.
Figure 31 shows an example of the back-to-back command sequence.
CS
SI
66h
99h
8 clocks
8 clocks
Figure 31: Enable Reset and Reset Command Sequence (SPI Mode)
5.32.4 Programming Restrictions
The Enable Reset command adheres to the following programming restrictions.
The complete command must be clocked into the device before the CS pin is deasserted.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no action is taken.
If an erase or program operation has been suspended (75h command has been executed prior to the 66h/99h command)
and the device reset sequence is initiated, the data is corrupted. To prevent this from happening, check the RDY/BSY in
Status Register 1 and the SUSP bit in Status Register 2 to make sure each bit is cleared before issuing the 66h/99h Reset
command sequence.
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5.33 TERMINATE (F0H)
In some applications, it may be necessary to prematurely terminate a program or erase operation rather than wait for the program
or erase operation to complete normally. The Terminate command immediately aborts any operation in progress and returns the
device to an idle state.
Since the need to terminate the operation is immediate, the Write Enable command does not need to be issued prior to the
Terminate command. Therefore, the Terminate command operates independently of the state of the WEL bit in Status Register 1.
Once this command is issued, the operation in progress cannot be continued. To suspend and then continue an operation, use
the Program/Erase Suspend (75h) and Program/Erase Resume (7Ah) commands.
5.33.1 Command Prerequisites
The Terminate command can be executed only if the command has been enabled by setting the Reset Enabled (RSTE) bit in
Status Register 5 using the Write Status Register 5 command (71h + 05h address offset). This command must be executed before
the Terminate command is executed. If the Reset command has not been enabled (the RSTE bit in is cleared), then any attempt
at executing the Terminate command is ignored.
5.33.2 Transfer Format
The F0h command follows the 1-0-1 transfer format described in Section 3.2, where the command and data are transferred on
the SI pin. Immediately after the command is transferred, a confirmation data byte is transferred. This byte is required by the
hardware before the Terminate command can be executed. A timing diagram of this operation is shown in Figure 6.
5.33.3 Transfer Sequence
To perform device reset operation, the CS pin is asserted and the information transferred as follows:
The F0h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
The D0h confirmation byte is clocked into the device. Eight clocks are required to transfer the command. The most signifi-
cant bit of the command is transferred first. Note that is the confirmation byte is any value other than D0h, the entire com-
mand is ignored and the device returns to the idle state.
When the CS pin is deasserted after the D0h confirmation byte, the device initiates the terminate operation within a time of
tSWTERM. During the terminate sequence, no other command can be accepted by the device.
See Table 18 for more information on the transfer sequence for this command.
5.33.4 Programming Restrictions
The F0h Terminate command adheres to the following programming restrictions.
If a program or erase operation is in progress and cannot complete before the operation is terminated via the F0h com-
mand, the contents of the page being programmed or erased cannot be guaranteed to be valid.
The F0h command does not reset the device configuration registers in volatile mode. If a reset of the internal state is
desired, perform a 66h/99h command. This command resets the device and all programmable parameters and all volatile
register contents are lost.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
returns to the standby mode once the CS pin is deasserted. Also, the device defaults to the standby mode after a power
cycle.
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5.34 READ MANUFACTURER/DEVICE ID (90H)
The Read Manufacturer/Device ID (90h) command provides both the JEDEC assigned manufacturer ID, and the specific device
ID.
5.34.1 Command Prerequisites
None.
5.34.2 Transfer Format
The 90h command follows the 1-1-1 transfer format described in Section 3.2, where the command and address are transferred
on the SI pin, and data is transferred on the SO pin. See Figure 7 for timing diagram of this operation.
5.34.3 Transfer Sequence
To perform the Read Array operation, the CS pin is asserted and the information transferred as follows:
The 90h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three dummy bytes are clocked in during the address phase. A total of 24 clocks are required. These three dummy bytes
are not used
Data is output on the SO pin. Two bytes are transferred, requiring a total of 16 clock cycles. The data is driven onto the bus
as follows:
- 1st data clock: bit 7 of the manufacturer ID is output on the SO pin
- 2nd data clock: bit 6 of the manufacturer ID is output on the SO pin
- .........
- 8th data clock: bit 0 of the manufacturer ID is output on the SO pin
- 9th data clock: bit 7 of the device ID is output on the SO pin
- 10th data clock: bit 6 of the device ID is output on the SO pin
- .........
- 16th data clock: bit 0 of the device ID is output on the SO pin
Deasserting the CS pin terminates the read operation and puts the SO pin into high-impedance state. If the CS pin remains
asserted, the device continues to shift out the manufacturer ID followed by the device ID.
See Table 18 for more information on the transfer sequence for this command.
5.34.4 Programming Restrictions
None.
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5.35 QUAD I/O READ MANUFACTURER/DEVICE ID (94H)
The Read Manufacturer/Device ID command operates in quad I/O mode, where the SI, SO, WP, and HOLD pins are all bidirec-
tional, to allow the manufacturer and device ID information to be transmitted at four times the speed of the Read Manufacturer/
Device ID command (90h).
5.35.1 Command Prerequisites
None.
5.35.2 Transfer Format
The 94h command follows the 1-4-4 transfer format described in Section 3.6, where the command is transferred on the SI pin,
and the address and data are transferred on the SI, SO, WP, and HOLD pins. See Figure 5 for a timing diagram of this transaction.
5.35.3 Transfer Sequence
To perform the Quad Read Manufacturer/Device ID command, the CS pin is asserted and the information transferred as follows:
The 94h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three dummy address bytes are clocked in during the address phase. A total of 6 clocks are required. These three dummy
bytes are ignored.
The mode byte is clocked into the device. Two clocks are required to transfer the command. The one dummy byte is
ignored.
Four dummy clocks are driven to the device prior to the output of data.
Data is output on the SI, SO, WP, and HOLD pins. Each byte transfer requires two clock cycles. The data is always output
with the most significant bit of the byte transferred first. The first byte transferred is the manufacturer ID. The second byte
transferred is the device ID. As long as CS is asserted, hardware continues to shift these two bytes out onto the bus. Each
data byte is shifted out of the device as follows:
- First data clock: bit 7 of the manufacturer ID is output on the HOLD pin
- First data clock: bit 6 of the manufacturer ID is output on the WP pin
- First data clock: bit 5 of the manufacturer ID is output on the SO pin
- First data clock: bit 4 of the manufacturer ID is output on the SI pin
- Second data clock: bit 3 of the manufacturer ID is output on the HOLD pin
- Second data clock: bit 2 of the manufacturer ID is output on the WP pin
- Second data clock: bit 1 of the manufacturer ID is output on the SO pin
- Second data clock: bit 0 of the manufacturer ID is output on the SI pin
- In clocks 3 and 4, the device ID is shifted out on byte 2 in the same manner as above
5.35.4 Programming Restrictions
None.
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5.36 READ JEDEC ID (9FH)
The Read JEDEC ID command allows software to identify the manufacturer and device ID information for the device while it is in
the system. This command allows the ID information to be read out a relatively low clock frequency to ensure the device can be
identified. Once the identification process is complete, the application can increase the clock frequency as necessary. For more
information, see the Serial Flash Discoverable Parameters (SFDP) JEDEC specification, edition JESD216C.
5.36.1 Command Prerequisites
None.
5.36.2 Transfer Format
The 9Fh command follows the 1-0-1 transfer format described in Section 3.2, where the command is transferred on the SI pin,
and data is transferred on the SO pin. See Figure 32 for timing diagram of this operation. Note that no address is required for this
type of read operation.
5.36.3 Transfer Sequence
To perform the JEDEC ID operation, the CS pin is asserted and the information transferred as follows:
The 9Fh command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first. No address is required for this transaction.
Data is output on the SO pin. Five bytes are transferred, requiring a total of 40 clock cycles. The data is driven onto the bus
as follows:
- 1st data clock: bit 7 of the manufacturer ID is output on the SO pin
- .........
- 8th data clock: bit 0 of the manufacturer ID is output on the SO pin
- 9th data clock: bit 7 of the device ID byte 1 is output on the SO pin
- .........
- 16th data clock: bit 0 of the device ID byte 1 is output on the SO pin
- 17th data clock: bit 7 of the device ID byte 2 is output on the SO pin
- .........
- 24th data clock: bit 0 of the device ID byte 2 is output on the SO pin
- 25th data clock: bit 7 of the extended device string length byte is output on the SO pin
- .........
- 32nd data clock: bit 0 of the extended device string length byte is output on the SO pin
- 33rd data clock: bit 7 of the extended device string value byte is output on the SO pin
- .........
- 40th data clock: bit 0 of the extended device string value byte is output on the SO pin
Deasserting the CS pin terminates the read operation and puts the SO pin into high-impedance state. If the CS pin remains
asserted, the device continues to shift out the manufacturer ID followed by the device ID.
See Table 18 for more information on the transfer sequence for this command.
The following tables below show the exact contents of each data byte.
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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Table 34: Manufacturer and Device ID Details
Hex
Value
Data Type
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Details
JEDEC Assigned Code
JEDEC Code: 0001 1111 (1Fh for Dialog
Semiconductor)
Manufacturer ID
1Fh
46h
08h
01h
0xh
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
x
Family Code
Density Code
1
Family Code: 010 (4h)
Density Code: 00110 (6h)
Device ID (Part 1)
Device ID (Part 2)
1
Sub Code
0
0
0
1
Sub-family Code
Revision Code
0 0
Sub Code: 000
Sub-family Code: 01
Revision Code: 000
0
1
Number of Extended Device ID Bytes to Follow
Device ID (Part 3)
(EDI String Length)
Bytes to follow: 1
0
0
0
0
0
0
Extended device Identity Value
Device ID (Part 4)
(EDI String Value)
x: Device Variant/Option. See table below.
0
0
0
x
x
x
Table 35: Device ID Part 4 Variants — EDI String Value
EDI String Value
Variant
Initial device
TBD
00h
01h
02h
TBD
03h
TBD
04h
TBD
05h
TBD
06h
TBD
07h
TBD
08h - 0Fh
Reserved
5.36.4 Transfer Diagram
Figure 32 shows the bus signals during an indirect register read operation. This type of command requires only a single 8-bit
address.
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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CS
0
6
7
8
14 15 16
22 23 24
30 31 32
38 39 40
46
SCK
SI
OPCODE
9Fh
HIGH-IMPEDANCE
08h
01h
1Fh
46h
0x
SO
MANUFACTURER ID
DEVICE ID
BYTE1
DEVICE ID
BYTE2
EXTENDED
DEVICE
INFORMATION
STRING LENGTH
EXTENDED
DEVICE
INFORMATION
STRING VALUE
Note: Each transition
shown for SI and SO represents one byte (8 bits)
Figure 32: Read JEDEC ID
5.36.5 Programming Restrictions
None.
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5.37 SERIAL FLASH DISCOVERABLE PARAMETERS (5AH)
The device contains a 256-byte Serial Flash Discoverable Parameter (SFDP) register. The SFDP register can be sequentially
read in a similar fashion to the Read Array operation up to the maximum clock frequency specified by fSCK
.
5.37.1 Command Prerequisites
None.
5.37.2 Transfer Format
The 5Ah command follows the 1-1-1 transfer format described in Figure 3.2.4, where the command, address, and dummy bytes
are transferred on the SI pin, and data is transferred on the SO pin. Figure 8 shows a timing diagram of a read operation with
dummy bytes. In this diagram one byte of data is transferred. Additional bytes can be transferred as long as the CS pin is asserted.
5.37.3 Transfer Sequence
To perform the SFDP operation, the CS pin is asserted and the information transferred as follows:
The 5Ah command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three address bytes are clocked in to specify the starting address location of the first byte to read within the memory array.
A total of 24 clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first.
Following the three address bytes, an additional dummy byte must be clocked into the device.
Data is output on the SO pin. Each byte transfer requires eight clock cycles. The data is always output with the most signif-
icant bit of the byte transferred first. The number of bytes transferred is determined by software. The transfer can be any-
where from a single byte to the entire SFDP value. The most significant bit of each data byte is transferred first.
Deasserting the CS pin terminates the read operation and puts the SO pin into high-impedance state. The CS pin can be
deasserted at any time and does not require a full byte of data be read. The format of the SFDP re ister follows the format
provided in JEDEC Standard No. 216 Rev B.
5.37.4 Programming Restrictions
When the last byte (0000FFh) of the SFDP Security Register has been read, the device continues reading back at the beginning
of the register (000000h). No delays are incurred when wrapping around from the end of the register to the beginning of the
register.
5.37.5 SFDP Organization
Contact Dialog Semiconductor for SFDP table information.
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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6
Electrical Specifications
6.1 ABSOLUTE MAXIMUM RATINGS
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions beyond those
indicated in the operational sections of this
specification is not implied. Exposure to
Temperature under bias . . . . . . -55 °C to +125 °C
Storage Temperature . . . . . . . . -65 °C to +150 °C
All input voltages
(including NC pins)
with respect to ground. . . . .-0.6 V to (VCC + 0.5 V)
absolute maximum rating conditions for
extended periods may affect device reliability.
All output voltages
with respect to ground. . . . .-0.6 V to (VCC + 0.5 V)
6.2 DC AND AC OPERATING RANGE
Parameter
AT25FF161A
-40 °C to 85 °C
1.65 V to 3.6 V
Operating Temperature (Case)
VCC Power Supply
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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6.3 DC CHARACTERISTICS FOR 1.65V TO 3.6V
1.65 V to 3.6 V
Typ 1
Symbol
Parameter
Condition
Units
Min
Max
Ultra-Deep Power-Down
Current
CS = VCC. All other inputs at
0V or VCC
2
IUDPD
5 - 7
8.2
30
400
nA
µA
µA
CS, RESET, WP = VCC. All
other inputs at 0V or VCC
IDPD
Deep Power-Down Current
Standby Current
17.5
50
CS, RESET, WP = VCC. All
other inputs at 0V or VCC
3
ISB
SPI (33 MHz)
IOUT = 0 mA
IOUT = 0 mA
IOUT = 0 mA
IOUT = 0 mA
5.5
8.6
9.0
mA
mA
mA
mA
SPI (104MHz)
Dual (104 MHz)
Quad (104 MHz)
13.0
15.0
18.0
4
ICC1
10.7
13.0
Active Current,
Program Operation
5
ICC3
CS = VCC
CS = VCC
9.2
13.0
15.5
mA
mA
Active Current,
Erase Operation
ICC4
10.2
6
ILI
Input Load Current
Output Leakage Current
Input Low Voltage
All inputs at CMOS levels
All inputs at CMOS levels
±2
±2
µA
µA
V
ILO
VIL
VCC x 0.2
VIH
VOL
VOH
Input High Voltage
Output Low Voltage
Output High Voltage
VCC x 0.8
VCC - 0.2
V
IOL = 100 µA
IOH = -100 µA
0.2
V
V
1. Typical values measured at 1.8 V @ 25 °C for the 1.65 V to 3.6 V range.
2. I value is estimated. Not 100% tested.
UDPD
3. During continuous read mode (0-4-4), I may exceed maximum limit.
SB
4. Checkerboard pattern.
5. WP (IO ) and HOLD/RESET (IO ) pins have an internal pull-up resistor. Its input load current is +2 / -40 μA.
2
3
6.4 AC CHARACTERISTICS - MAXIMUM CLOCK FREQUENCIES
1.65V to 3.6V
Min Typ
Max1
2.7V to 3.6V
Typ Max
Symbol
Parameter
Units
Min
Maximum clock frequency for all operations
(except 03h, 0Bh, 3Bh, 6Bh, EBh, and E7h
commands)
108
133
MHz
Maximum clock frequency for 0Bh and 3Bh
commands
108
108
108
108
108
133
MHz
MHz
MHz
fSCK
Maximum clock frequency for 6Bh command
Maximum clock frequency for EBh and E7h
commands
Maximum clock frequency for 03h command (Read
Array – Low Frequency)
fRDLF
40
40
MHz
1. See Table 19 and Table 20 for the maximum frequency of EBh/E7h commands in various modes.
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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6.5 AC CHARACTERISTICS – ALL OTHER PARAMETERS
1.65V to 3.6V
Typ
Symbol 1
Parameter
Units
Min
4.5
4.5
0.75
0.75
35
6
Max
tCLKH
tCLKL
tCLKR
tCLKF
tCSH
SCK High Time
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
SCK Low Time
Clock Rise Time, Peak-to-Peak (Slew Rate)
Clock Fall Time, Peak-to-Peak (Slew Rate)
Minimum CS High Time
tCSLS
tCSLH
tCSHS
tCSHH
tDS
CS Low Setup Time (relative to clock)
CS Low Hold Time (relative to clock)
CS High Setup Time (relative to clock)
CS High Hold Time (relative to clock)
Data In Setup Time
6
6
6
2
tDH
Data In Hold Time
1
tDIS
Output Disable Time
8
8
tV
Output Valid Time
tOH
Output Hold Time
0
6
6
6
6
tHLS
HOLD Low Setup Time (relative to clock)
HOLD Low Hold Time (relative to clock)
HOLD High Setup Time (relative to clock)
HOLD High Hold Time (relative to clock)
HOLD Low to Output High-Z
tHLH
tHHS
tHHH
tHLQZ
tHHQX
tWPS
tWPH
tEDPD
tEUDPD
tSWTERM
tSWRST
7
7
HOLD High to Output Low-Z
Write Protect Setup Time
20
Write Protect Hold Time
100
CS High to Deep Power-Down
CS High to Ultra Deep Power-Down
Resume from Terminate Command Time
Resume from Software Reset Time
Resume form Ultra Deep Power-Down Time
Resume from Deep Power-Down Time
3
3
50
200
200
35
2
tRUDPD
160
tRDPD
1. Not 100% tested (value guaranteed by design and characterization).
2. The maximum spec is valid for UDPD hold time (duration of Ultra-Deep Power-Down state) of >550 ms. For the shorter UDPD hold times, T
might reach
RUDPD
1200 μs under some conditions.
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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6.6 PROGRAM AND ERASE CHARACTERISTICS
Symbol Parameter
1.65V - 3.6V
2.7V - 3.6V
Typ 1
4.5
Units
Min
Typ 1
4.0
Max 2
Min
Max 2
tPP
Page Program Time (256 Bytes)
Byte Program Time
7.0
7.0
ms
µs
3
tBP
32
32
4 kB
32 kB
64 kB
90
125
900
85
125
900
ms
ms
ms
sec
µs
tBLKE
Block Erase Time
620
1200
37
550
1600
1100
34
1600
tCHPE
Chip Erase Time (16M density)
Suspend Time (Program)
Suspend Time (Erase)
50
50
12
10
50
50
12
10
tSUS
µs
Resume Time (Program)
Resume Time (Erase)
10
8
10
8
µs
tRES
µs
OTP Security Register Program Time
(<= 10K)
tOTPP
5
6
5
6
ms
ms
tWRSR
Write Status Register Time
8.0
15
7.5
15
o
o
1. Typical values measured at 1.8 V at 25 C for 1.65 V - 3.6 V, and at 3.3 V at 25 C for 2.7 V - 3.6 V.
2. Unless otherwise specified, maximum is worst case measurement at cycling conditions after 100K cycles.
3. Program time after the first byte varies.
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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6.7 POWER ON TIMING
When power is first applied to the device, or when recovering from a reset condition, the output pin (SO) is in a high-impedance
state, and a high-to-low transition on the CS pin is required to start a valid instruction. The SPI mode (Mode 3 or Mode 0) is
automatically selected on every falling edge of CS by sampling the inactive clock state.
As the device initializes, there is a transient current demand. The system needs to be capable of providing this current to ensure
correct initialization. During power-up, the device must not be accessed for at least the minimum tVCSL time after the supply
voltage reaches the minimum VCC level (VCC min). While the device is being powered-up, the internal Power-On Reset (POR)
circuitry keeps the device in a reset mode until the supply voltage rises above the minimum VCC. During this time, all operations
are disabled and the device does not respond to any commands. (the tVCSL time is measured from when VCC reaches VCC min.)
If Power On Reset (POR) has not been properly completed by the end of tVCSL, the execution of a JEDEC Reset sequence restarts
the POR process. This ensures the device can complete POR sequence, even if some aspect of system Power-On voltage ramp-
up causes the POR to not initiate or complete correctly.
Figure 33 shows the AC timing during power-up.
Vcc
VCCmin
tVCSL
Full Operation
Permitted
tVR
0V
Figure 33: AC Timing During Device Power Up
Table 36: Power On Timing Requirements
1.65V - 3.6V
Typ
Symbol
Parameter
Units
Min
Max
200
tVCSL
tVR
Minimum VCC to full operation permitted
VCC rise time (from 0V to VCCmin)
VCC brown-out low time
µs
µs/V
µs
1
6000 1
tPWD
300
VPWDMAX
Maximum VCC brown-out
0.2
V
o
o
1. 30000 µs/V at -15 C to 85 C.
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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Figure 34 shows the AC power-up timing after a brown-out condition.
Vcc
VCCmin
tVCSL
Full Operation
Permitted
VPWDMAX
tVR
tPWD
Figure 34: AC Power-up Timing After a Brown-Out
6.8 AC TIMING DIAGRAMS
W&6+
&6
W&6/6
W&6/+
W&/./
W&6++
W&/.+
W&6+6
6&.
W'6
W'+
06%
/6%
06%
6,ꢎ62ꢎ:3ꢎ+2/'
Figure 35: Serial Input Timing
CS
SCK
SI
tCLKH
tCLKL
tDIS
tOH
tV
tV
SI/SO/WP/HOLD
Figure 36: Serial Output Timing
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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CS
tWPS
tWPH
WP
SCK
SI
0
0
0
X
MSB
MSB OF
WRITE STATUS REGISTER
OPCODE
LSB OF
WRITE STATUS REGISTER
DATA BYTE
MSB OF
NEXT OPCODE
HIGH-IMPEDANCE
SO
Figure 37: WP Timing for Write Status Register Command
CS
SCK
HOLD
SI
tHHH
tHLS
tHLH
tHHS
HIGH-IMPEDANCE
SO
Figure 38: HOLD Timing – Serial Input
CS
SCK
HOLD
SI
tHHH
tHLS
tHLH
tHHS
tHLQZ
tHHQX
SO
Figure 39: HOLD Timing – Serial Output
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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7
Ordering Information
AT 25FF 161 A - SS H N - B
Shipping
B = Bulk
Designator
T = Tape
Product Family
Operating Voltage
N = 1.65 V - 3.6 V
Device Density
161 = 16 Mbit
Device Grade
H = Green, NiPdAu finish
U = Green, MatteSn or Sn alloy
Revision
Industrial Temperature Range
(-40 C - +85 C)
o
o
P = Green NiPdAu lead finish,
non-conductive silver-free
die attach material
o
o
(-40 C - +85 C)
Package Options
SS = 8-lead 0.150” narrow SOIC
S = 8-lead 0.208” wide SOIC
MA = 8-pad 2 x 3 x 0.6 mm UDFN
U = 8-ball WLCSP
Note: Contact Dialog Semiconductor for more
information on die/wafer options.
Table 37: Valid Ordering Codes for Operating Voltage 1.65 V to 3.6 V
Available to
Order
Mechanical
Drawing
Lead
Finish
Temperature
Range
Valid Part Number
Description
AT25FF161A-SSHN-B
AT25FF161A-SSHN-T
8-lead, 0.150" Narrow Plastic Gull Wing
Small Outline Package (JEDEC SOIC)
Yes
Yes
Yes
Yes
8S1
8S2
NiPdAu
AT25FF161A-SHN-B
AT25FF161A-SHN-T
8-lead, 0.208” Wide Plastic Gull Wing
Small Outline Package (EIAJ SOIC)
Industrial
(-40°C to +85°C)
8-pad, 2 x 3 x 0.6 mm, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
AT25FF161A-MAHN-T
AT25FF161A-UUN-T
AT25FF161A-DWF
8MA3
NiPdAu
SnAgCu
--
8-ball, 3 x 2 x 3 mm Ball Matrix, 0.35 mm Z-
Height
8-WLCSP
Contact Dialog Contact Dialog
Semiconductor Semiconductor
Die in Wafer Form
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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8
Packaging Information
The AT25FF161A device supports the following package types:
8S1, 8-lead 0.150 narrow body JEDEC SOIC
8S2, 8-lead 0.208 wide body EIAJ
8MA3, 2 x 3 x 0.6 mm UDFN
8-WLCSP, 8-ball 3 x 2 x 3 array WLCSP
Each of these packages is described in the following subsections.
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8.1 8S1 – JEDEC SOIC
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8.2 8S2 – 8-LEAD EIAJ SOIC
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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8.3 8MA3 – 2 X 3 UDFN
E
Pin 1 ID
D
SIDE VIEW
A3
A1
TOP VIEW
A
COMMON DIMENSIONS
(Unit of Measure = mm)
K
Option A
0.45
SYMBOL
MIN
0.45
0.00
NOM
MAX
0.60
0.06
Pin #1
Chamfer
(C 0.35)
8
7
6
5
1
2
Pin #1 Notch
(0.20 R)
A
(Option B)
A1
A3
0.150 REF
D2
e
b
D
D2
E
0.20
1.50
0.30
1.70
3
4
2.00 BSC 0.1
1.60
3.00 BSC 0.1
0.50 BSC
0.50
e
b
L
0.40
0.60
L
BOTTOM VIEW
Notes:
1. This package conforms to JEDEC reference MO-229, Saw Singulation.
2. The terminal #1 ID is a Laser-marked Feature.
TITLE
GPC
REV.
D
DRAWING NO.
8MA3, 8-pad (2 x 3 x 0.6 mm Body), Thermally
Enhanced Plastic Ultra Thin Dual Flat No Lead
Package (UDFN)
YFG
8MA3
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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8.4 8-WLCSP — 8-BALL 3 X 2 X 3 WLCSP
TOP VIEW
BOTTOM VIEW
PIN A1 MARK
PIN A1 MARK
1
2
3
3
2
1
A
B
C
D
A
200
B
400
C
D
E
400
800
200
E
350
700
1767
BSL
SIDE VIEW
25
All dimensions in micrometers (μm)
250
440 21
210 31
165 17
TITLE
Revision
A
Ordering Part
Internal Package
Identifier
Number Identifier
8-ball (3 x 2 x 3 Array)
Wafer Level Chip Scale Package (WLCSP)
UD
DEC
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16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
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9
Revision History
Revision
Date
3/2020
Change History
A
Initial release of AT25FF161A 16 Mbit data sheet.
Updated timing in Section 8.6, Program and Erase Characteristics.
Updated Table 7-2, Frequency and Number of Dummy Clocks Based on Command Type.
Added footnotes 3 and 4 to Section 8.6.
B
6/2020
Added 2.7V - 3.6V voltage option to Table 8-4.
Added 2.7V - 3.6V voltage option to Table 8-6.
Updated frequency information on page 1.
Changed data sheet status from ADVANCED to PRELIMINARY.
Updated Table 7-2, Frequency and Number of Dummy Clocks Based on Command Type.
Updated numbers in Table 8-3.
Updated numbers in Table 8-4.
Updated numbers in Table 8-6.
Updated frequency information on page 1.
Updated power dissipation information on page 1.
C
D
9/2020
Changed Table 8-19 to indicate temperature dependency.
Updated Table 7-2 and added Table 7-3 in Section 7.4, XiP Mode Read Command.
Updated Section 8.3, Maximum Clock Frequencies.
Changed value in second footnote of Section 8.5, AC Characteristics - All Other Parameters.
Deleted tPE row from table in Section 8.6, Program and Erase Characteristics.
Removed footnote 4 from Section 8.3, DC Characteristics.
01/2021
Applied Dialog Semiconductor format.
In section 6.2, changed Vcc Power Supply to 1.65 V to 3.75 V.
Added section 6.4 with 1.65 V to 3.75 V characteristics.
Added ordering code AT25FF161A-SSPN-T.
Added device grade P to ordering info.
E
F
04/2021
06/2021
Removed all references to the 1.65 V to 3.75 V version of the device.
Added tolerance of +/-0.1 mm to rows D and E of the table in Section 8.3, 8MA3 - 2 X 3 UDFN.
Corrected the N option in the Ordering Information figure.
Corrected title to Table 37.
Removed original Table 6.4.
G
H
07/2021
08/2021
Removed “Preliminary” designation.
Changed values in Tables 19 and 20, the tables sections 6.3 - 6.6, and Table 36.
Updated UDFN package drawing in Section 8.3.
Datasheet
2021-08-13
Revision H
119
DS-AT25FF161A-182
© 2021 Dialog Semiconductor
AT25FF161A
16-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory
with Multi-I/O Support
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Datasheet
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Revision H
120
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