AT45DB161E-SHF2B-T_技术文档

AT45DB161E

16-Mbit DataFlash (with Extra 512-kbits)

2.3 V or 2.5 V Minimum SPI Serial Flash Memory

Features



Single 2.3 V - 3.6 V or 2.5 V - 3.6 V supply

Serial Peripheral Interface (SPI) compatible

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Supports SPI modes 0 and 3

Supports RapidS^™operation



Continuous read capability through entire array

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Up to 85 MHz

Low-power read option up to 15 MHz

Clock-to-output time (t_V) of 6 ns maximum

User-configurable page size

-

512 bytes per page

528 bytes per page (default)

Page size can be factory pre-configured for 512 bytes



Two fully independent SRAM data buffers (512/528 bytes)

Allows receiving data while reprogramming the main memory array

Flexible programming options

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Byte/Page Program (1 to 512/528 bytes) directly into main memory

Buffer Write

Buffer to Main Memory Page Program



Flexible erase options

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Page Erase (512/528 bytes)

Block Erase (4 kB)

Sector Erase (128 kB)

Chip Erase (16 Mbits)

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Program and Erase Suspend/Resume

Advanced hardware and software data protection features

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Individual sector protection

Individual sector lockdown to make any sector permanently read-only

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128-byte, One-Time Programmable (OTP) Security Register

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64 bytes factory programmed with a unique identifier

64 bytes user programmable

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Hardware and software controlled reset options

JEDEC Standard Manufacturer and Device ID Read

Low-power dissipation

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400 nA Ultra-Deep Power-Down current (typical)

3 µA Deep Power-Down current (typical)

25 µA Standby current (typical)

7 mA Active Read current (typical @ 15 MHz))



Endurance: 100,000 program/erase cycles per page minimum

Data retention: 20 years

Complies with full industrial temperature range

Green (Pb/Halide-free/RoHS compliant) packaging options

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8-lead SOIC (0.150" wide and 0.208" wide)

8-pad Ultra-thin DFN (5 x 6 x 0.6mm)

11-ball Wafer Level Chip Scale Package

Die in Wafer Form (contact factory for availability)

DS-AT45DB161E–8782N–03/2021

Table of Contents

1. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2. Pin Configurations and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4. Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

5. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

6. Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

6.1 Continuous Array Read (Legacy Command: E8h Opcode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.2 Continuous Array Read (High-Frequency Mode: 1Bh Opcode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.3 Continuous Array Read (High-Frequency Mode: 0Bh Opcode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.4 Continuous Array Read (Low-Frequency Mode: 03h Opcode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.5 Continuous Array Read (Low Power Mode: 01h Opcode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.6 Main Memory Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.7 Buffer Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7. Program and Erase Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

7.1 Buffer Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.2 Buffer to Main Memory Page Program with Built-In Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.3 Buffer to Main Memory Page Program without Built-In Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.4 Main Memory Page Program through Buffer with Built-In Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.5 Main Memory Byte/Page Program through Buffer 1 without Built-In Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.6 Read-Modify-Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.7 Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.8 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.9 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.10 Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.11 Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.12 Program/Erase Resume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8. Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

8.1 Software Sector Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.1.1 Enable Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

8.1.2 Disable Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

8.2 Hardware Controlled Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.3 Sector Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.3.1 Erase Sector Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

8.3.2 Program Sector Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

8.3.3 Read Sector Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

8.3.4 About the Sector Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

9. Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

9.1 Sector Lockdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9.1.1 Read Sector Lockdown Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

9.1.2 Freeze Sector Lockdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

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9.2 Security Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.2.1 Programming the Security Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

9.2.2 Reading the Security Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

10. Additional Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

10.1 Main Memory Page to Buffer Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.2 Main Memory Page to Buffer Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.3 Auto Page Rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.4 Status Register Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.4.1 RDY/BUSY Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

10.4.2 COMP Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

10.4.3 DENSITY Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

10.4.4 PROTECT Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

10.4.5 PAGE SIZE Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

10.4.6 EPE Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

10.4.7 SLE Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

10.4.8 PS2 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

10.4.9 PS1 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

10.4.10The ES bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

11. Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

11.1 Resume from Deep Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

11.2 Ultra-Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

11.3 Exit Ultra-Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12. Buffer and Page Size Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

13. Manufacturer and Device ID Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

14. Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

15. Operation Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

16. Command Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

17. Power-On/Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

17.1 Initial Power-Up Timing Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

18. System Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

19. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

19.1 Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

19.2 DC and AC Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

19.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

19.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

19.5 Program and Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

20. Input Test Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

21. Output Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

22. Using the RapidS Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

23. AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

24. Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

25. Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

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26. Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

27. Auto Page Rewrite Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

27.1 Entire Array Sequentially . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

27.2 Entire Array Randomly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

28. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

28.1 Ordering Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

28.2 Ordering Codes (Standard Page Size). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

28.3 Ordering Codes (Binary Page Size). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

28.4 Ordering Codes (Reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

29. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

29.1 8S1 – 8-lead JEDEC SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

29.2 8S2 – 8-lead EIAJ SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

29.3 8MA1 – 8-pad UDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

29.4 CS16-11A – 11-ball WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

30. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

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1

Description

The Adesto^®AT45DB161E is a 2.3 V or 2.5 V minimum, serial-interface sequential access Flash memory ideally

suited for a wide variety of digital voice, image, program code, and data storage applications. The AT45DB161E

also supports the RapidS serial interface for applications requiring very high speed operation. Its 17,301,504 bits of

memory are organized as 4,096 pages of 512 bytes or 528 bytes each. In addition to the main memory, the

AT45DB161E also contains two SRAM buffers of 512/528 bytes each. The buffers allow receiving of data while a

page in the main memory is being reprogrammed. Interleaving between both buffers can dramatically increase a

system's ability to write a continuous data stream. Also, the SRAM buffers can be used as additional system

scratch pad memory, and E²PROM emulation (bit or byte alterability) can be easily handled with a self-contained

three step read-modify-write operation.

Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel

interface, the Adesto DataFlash^®uses a serial interface to sequentially access its data. The simple sequential

access dramatically reduces active pin count, facilitates simplified hardware layout, increases system reliability,

minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and

industrial applications where high-density, low-pin count, low-voltage, and low-power are essential.

To allow for simple in-system re-programmability, the AT45DB161E does not require high input voltages for

programming. The device operates from a single 2.3 V to 3.6 V or 2.5 V to 3.6 V power supply for the erase and

program and read operations. The AT45DB161E is enabled through the Chip Select pin (CS) and accessed via a

three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).

All programming and erase cycles are self-timed.

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2

Pin Configurations and Pinouts

WLCSP⁽²⁾

8-pad UDFN⁽¹⁾

8-lead SOIC

Bottom View

Top View

(through package)

NC

SI

SCK

RESET

CS

1

2

3

4

8

7

6

5

SO

SI

SCK

1

2

3

4

8

7

6

5

SO

GND

V_CC

WP

SI

SCK

RESET

CS

SO

GND

RESET

CS

V

CC

GND

V_CC

WP

NC

Pin 1

1. The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential. This pad can be a “no connect” or connected to GND.

2. Contact Dialog Semiconductor for manufacturing flow and availability.

Figure 2-1. Pinouts

Table 2-1. Pin Configurations

Asserted

State

Symbol

Name and Function

Type

Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the

device is deselected and normally be placed in the standby mode (not Deep Power-Down

mode), and the output pin (SO) is in a high-impedance state. When the device is deselected,

data is not accepted on the input pin (SI).

CS

Low

Input

A high-to-low transition on the CS pin is required to start an operation and a low-to-high

transition is required to end an operation. When ending an internally self-timed operation such

as a program or erase cycle, the device does not enter the standby mode until the operation is

done.

Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of

data to and from the device. Command, address, and input data present on the SI pin is

always latched on the rising edge of SCK, while output data on the SO pin is always clocked

out on the falling edge of SCK.

SCK

—

Input

Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input

including command and address sequences. Data on the SI pin is always latched on the rising

edge of SCK. Data present on the SI pin is ignored whenever the device is deselected (CS is

deasserted).

SI

—

Input

Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is

always clocked out on the falling edge of SCK. The SO pin is in a high-impedance state

whenever the device is deselected (CS is deasserted).

SO

Output

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Table 2-1. Pin Configurations (continued)

Asserted

State

Symbol

Name and Function

Type

Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector

Protection Register are protected against program and erase operations regardless of whether

the Enable Sector Protection command has been issued or not. The WP pin functions

independently of the software controlled protection method. After the WP pin goes low, the

contents of the Sector Protection Register cannot be modified.

If a program or erase command is issued to the device while the WP pin is asserted, the device

ignores the command and perform no operation. The device returns to the idle state once the

CS pin has been deasserted. The Enable Sector Protection command and the Sector

Lockdown command, however, are recognized by the device when the WP pin is asserted.

WP

Low

Input

The WP pin is internally pulled-high and can be left floating if hardware controlled protection is

not used. However, it is recommended that the WP pin also be externally connected to V_CC

whenever possible.

Reset: A low state on the reset pin (RESET) terminates the operation in progress and reset the

internal state machine to an idle state. The device remains in the reset condition as long as a

low level is present on the RESET pin. Normal operation can resume once the RESET pin is

brought back to a high level.

RESET

Low

Input

The device incorporates an internal power-on reset circuit, so there are no restrictions on the

RESET pin during power-on sequences. If this pin and feature is not used, then it is

recommended that the RESET pin be driven high externally.

Device Power Supply: The V_CCpin is used to supply the source voltage to the device.

Operations at invalid V_CCvoltages can produce spurious results; do not attempted this.

V_CC

—

Power

GND

Ground: The ground reference for the power supply. Connect GND to the system ground.

Ground

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3

Block Diagram

WP

Flash Memory Array

Page (512/528 bytes)

Buffer 1 (512/528 bytes)

Buffer 2 (512/528 bytes)

SCK

CS

RESET

V_CC

I/O Interface

GND

SI

SO

Figure 3-1. Block Diagram

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4

Memory Array

To provide optimal flexibility, the AT45DB161E memory array is divided into three levels of granularity comprising

of sectors, blocks, and pages. Figure 4-1 illustrates the breakdown of each level and details the number of pages

per sector and block. Program operations to the DataFlash can be done at the full page level or at the byte level (a

variable number of bytes). The erase operations can be performed at the chip, sector, block, or page level.

Sector Architecture

Block Architecture

Page Architecture

Block 0

Block 1

Block 2

8 Pages

Page 0

Sector 0a

Sector 0a = 8 pages

4,096/4,224 bytes

Page 1

Sector 0b = 248 pages

126,976/130,944 bytes

Page 6

Page 7

Page 8

Page 9

Block 30

Block 31

Block 32

Block 33

Sector 1 = 256 pages

131,072 /135,168 bytes

Sector 2 = 256 pages

131,072/135,168 bytes

Page 14

Page 15

Page 16

Page 17

Page 18

Block 62

Block 63

Block 64

Block 65

Sector 14 = 256 pages

131,072/135,168 bytes

Sector 15 = 256 pages

131,072/135,168 bytes

Block 510

Block 511

Page 4,094

Page 4,095

Block = 4,096/4,224 bytes

Page = 512/528 bytes

Figure 4-1. Memory Architecture Diagram

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5

Device Operation

The device operation is controlled by instructions from the host processor. The list of instructions and their

associated opcodes are contained in Table 16-1, on page 45, through Table 16-4, on page 46. A valid instruction

starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory

address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired

buffer or main memory address location through the SI (Serial Input) pin. All instructions, addresses, and data are

transferred with the Most Significant Bit (MSB) first.

Three address bytes are used to address memory locations in either the main memory array or in one of the SRAM

buffers. The three address bytes are comprised of a number of dummy bits and a number of actual device address

bits, with the number of dummy bits varying depending on the operation being performed and the selected device

page size. Buffer addressing for the standard DataFlash page size (528 bytes) is referenced in the datasheet using

the terminology BFA9 - BFA0 to denote the 10 address bits required to designate a byte address within a buffer.

The main memory addressing is referenced using the terminology PA11 - PA0 and BA9 - BA0, where PA11 - PA0

denotes the 12 address bits required to designate a page address, and BA9 - BA0 denotes the 10 address bits

required to designate a byte address within the page. Therefore, when using the standard DataFlash page size, a

total of 22 address bits are used.

For the “power of 2” binary page size (512 bytes), the buffer addressing is referenced in the datasheet using the

conventional terminology BFA8 - BFA0 to denote the nine address bits required to designate a byte address within

a buffer. Main memory addressing is referenced using the terminology A20 - A0, where A20 - A9 denotes the 12

address bits required to designate a page address, and A8 - A0 denotes the nine address bits required to

designate a byte address within a page. Therefore, when using the binary page size, a total of 21 address bits are

used.

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6

Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM

data buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. See the diagrams in Section 26 for

details on the clock cycle sequences for each mode.

6.1

Continuous Array Read (Legacy Command: E8h Opcode)

By supplying an initial starting address for the main memory array, the Continuous Array Read command can be

used to sequentially read a continuous stream of data from the device by providing a clock signal; no additional

addressing information or control signals need to be provided. The DataFlash incorporates an internal address

counter that automatically increments on every clock cycle, allowing one continuous read from memory to be

performed without the need for additional address sequences. To perform a Continuous Array Read using the

standard DataFlash page size (528 bytes), an opcode of E8h must be clocked into the device followed by three

address bytes (which comprise the 22-bit page and byte address sequence) and four dummy bytes. The first 12

bits (PA11 - PA0) of the 22-bit address sequence specify which page of the main memory array to read and the last

10 bits (BA9 - BA0) of the 22-bit address sequence specify the starting byte address within the page. To perform a

Continuous Array Read using the binary page size (512 bytes), an opcode of E8h must be clocked into the device

followed by three address bytes and four dummy bytes. The first 12 bits (A20 - A9) of the 21-bit address sequence

specify which page of the main memory array to read and the last nine bits (A8 - A0) of the 21-bit address

sequence specify the starting byte address within the page. The dummy bytes that follow the address bytes are

needed to initialize the read operation. Following the dummy bytes, additional clock pulses on the SCK pin results

in data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the

reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the

device continues reading at the beginning of the next page with no delays incurred during the page boundary

crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main

memory array has been read, the device continues reading back at the beginning of the first page of memory. As

with crossing over page boundaries, no delays are incurred when wrapping around from the end of the array to the

beginning of the array.

A low-to-high transition on the CS pin terminates the read operation and tri-state the output pin (SO). The

maximum SCK frequency allowable for the Continuous Array Read is defined by the f_CAR1specification. The

Continuous Array Read bypasses the data buffers and leaves the contents of the buffers unchanged.

Warning:

This command is not recommended for new designs.

6.2

Continuous Array Read (High-Frequency Mode: 1Bh Opcode)

This command can be used to read the main memory array sequentially at the highest possible operating clock

frequency up to the maximum specified by f_CAR4. To perform a Continuous Array Read using the standard

DataFlash page size (528 bytes), the CS pin must first be asserted, and then an opcode of 1Bh must be clocked

into the device followed by three address bytes and two dummy bytes. The first 12 bits (PA11 - PA0) of the 22-bit

address sequence specify which page of the main memory array to read and the last 10 bits (BA9 - BA0) of the 22-

bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using

the binary page size (512 bytes), the opcode 1Bh must be clocked into the device followed by three address bytes

(A20 - A0) and two dummy bytes. Following the dummy bytes, additional clock pulses on the SCK pin results in

data being output on the SO (Serial Output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the

reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the

device continues reading at the beginning of the next page with no delays incurred during the page boundary

crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main

memory array has been read, the device continues reading back at the beginning of the first page of memory. As

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with crossing over page boundaries, no delays are incurred when wrapping around from the end of the array to the

beginning of the array.

A low-to-high transition on the CS pin terminates the read operation and tri-state the output pin (SO). The

maximum SCK frequency allowable for the Continuous Array Read is defined by the f_CAR1specification. The

Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.

6.3

Continuous Array Read (High-Frequency Mode: 0Bh Opcode)

This command can be used to read the main memory array sequentially at higher clock frequencies up to the

maximum specified by f_CAR1. To perform a Continuous Array Read using the standard DataFlash page size (528

bytes), the CS pin must first be asserted, and then an opcode of 0Bh must be clocked into the device followed by

three address bytes and one dummy byte. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify

which page of the main memory array to read and the last 10 bits (BA9 - BA0) of the 22-bit address sequence

specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size

(512 bytes), the opcode 0Bh must be clocked into the device followed by three address bytes (A20 - A0) and one

dummy byte. Following the dummy byte, additional clock pulses on the SCK pin results in data being output on the

SO pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading

of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device

continues reading at the beginning of the next page with no delays incurred during the page boundary crossover

(the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory

array has been read, the device continues reading back at the beginning of the first page of memory. As with

crossing over page boundaries, no delays are incurred when wrapping around from the end of the array to the

beginning of the array.

A low-to-high transition on the CS pin terminates the read operation and tri-state the output pin (SO). The

maximum SCK frequency allowable for the Continuous Array Read is defined by the f_CAR1specification. The

Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.

6.4

Continuous Array Read (Low-Frequency Mode: 03h Opcode)

This command can be used to read the main memory array sequentially at lower clock frequencies up to maximum

specified by f_CAR2. Unlike the previously described read commands, this Continuous Array Read command for the

lower clock frequencies does not require the clocking in of dummy bytes after the address byte sequence. To

perform a Continuous Array Read using the standard DataFlash page size (528 bytes), the CS pin must first be

asserted, and then an opcode of 03h must be clocked into the device followed by three address bytes. The first 12

bits (PA11 - PA0) of the 22-bit address sequence specify which page of the main memory array to read and the last

10 bits (BA9 - BA0) of the 22-bit address sequence specify the starting byte address within the page. To perform a

Continuous Array Read using the binary page size (512 bytes), the opcode 03h must be clocked into the device

followed by three address bytes (A20 - A0). Following the address bytes, additional clock pulses on the SCK pin

results in data being output on the SO pin.

The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When

the end of a page in the main memory is reached during a Continuous Array Read, the device continues reading at

the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the

end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the

device continues reading back at the beginning of the first page of memory. As with crossing over page

boundaries, no delays are incurred when wrapping around from the end of the array to the beginning of the array.

A low-to-high transition on the CS pin terminates the read operation and tri-state the output pin (SO). The

maximum SCK frequency allowable for the Continuous Array Read is defined by the f_CAR2specification. The

Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.

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6.5

Continuous Array Read (Low Power Mode: 01h Opcode)

This command is ideal for applications that want to minimize power consumption and do not need to read the

memory array at high frequencies. Like the 03h opcode, this Continuous Array Read command allows reading the

main memory array sequentially without the need for dummy bytes to be clocked in after the address byte

sequence. The memory can be read at clock frequencies up to maximum specified by f_CAR3. To perform a

Continuous Array Read using the standard DataFlash page size (528 bytes), the CS pin must first be asserted, and

then an opcode of 01h must be clocked into the device followed by three address bytes. The first 12 bits (PA11 -

PA0) of the 22-bit address sequence specify which page of the main memory array to read and the last 10 bits

(BA9 - BA0) of the 22-bit address sequence specify the starting byte address within the page. To perform a

Continuous Array Read using the binary page size (512 bytes), the opcode 01h must be clocked into the device

followed by three address bytes (A20 - A0). Following the address bytes, additional clock pulses on the SCK pin

results in data being output on the SO pin.

The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When

the end of a page in the main memory is reached during a Continuous Array Read, the device continues reading at

the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the

end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the

device continues reading back at the beginning of the first page of memory. As with crossing over page

boundaries, no delays are incurred when wrapping around from the end of the array to the beginning of the array.

A low-to-high transition on the CS pin terminates the read operation and tri-state the output pin (SO). The

maximum SCK frequency allowable for the Continuous Array Read is defined by the f_CAR3specification. The

Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.

6.6

Main Memory Page Read

A Main Memory Page Read allows the reading of data directly from a single page in the main memory, bypassing

both of the data buffers and leaving the contents of the buffers unchanged. To start a page read using the standard

DataFlash page size (528 bytes), an opcode of D2h must be clocked into the device followed by three address

bytes (which comprise the 22-bit page and byte address sequence) and four dummy bytes. The first 12 bits (PA11

- PA0) of the 22-bit address sequence specify the page in main memory to be read and the last 10 bits (BA9 - BA0)

of the 22-bit address sequence specify the starting byte address within that page. To start a page read using the

binary page size (512 bytes), the opcode D2h must be clocked into the device followed by three address bytes and

four dummy bytes. The first 12 bits (A20 - A9) of the 21-bit address sequence specify which page of the main

memory array to read, and the last nine bits (A8 - A0) of the 21-bit address sequence specify the starting byte

address within that page. The dummy bytes that follow the address bytes are sent to initialize the read operation.

Following the dummy bytes, the additional pulses on SCK result in data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the

reading of data. Unlike the Continuous Array Read command, when the end of a page in main memory is reached,

the device continues reading back at the beginning of the same page rather than the beginning of the next page.

A low-to-high transition on the CS pin terminates the read operation and tri-state the output pin (SO). The

maximum SCK frequency allowable for the Main Memory Page Read is defined by the f_SCKspecification. The Main

Memory Page Read bypasses both data buffers and leaves the contents of the buffers unchanged.

6.7

Buffer Read

The SRAM data buffers can be accessed independently from the main memory array, and using the Buffer Read

command allows data to be sequentially read directly from either one of the buffers. Four opcodes, D4h or D1h for

Buffer 1 and D6h or D3h for Buffer 2, can be used for the Buffer Read command. The use of each opcode depends

on the maximum SCK frequency that is used to read data from the buffers. The D4h and D6h opcode can be used

at any SCK frequency up to the maximum specified by f_CAR1while the D1h and D3h opcode can be used for lower

frequency read operations up to the maximum specified by f_CAR2

.

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To perform a Buffer Read using the standard DataFlash buffer size (528 bytes), the opcode must be clocked into

the device followed by three address bytes comprised of 14 dummy bits and 10 buffer address bits (BFA9 - BFA0).

To perform a Buffer Read using the binary buffer size (512 bytes), the opcode must be clocked into the device

followed by three address bytes comprised of 15 dummy bits and nine buffer address bits (BFA8 - BFA0).

Following the address bytes, one dummy byte must be clocked into the device to initialize the read operation if

using opcodes D4h or D6h. The CS pin must remain low during the loading of the opcode, the address bytes, the

dummy byte (if using opcodes D4h or D6h), and the reading of data. When the end of a buffer is reached, the

device continues reading back at the beginning of the buffer. A low-to-high transition on the CS pin terminates the

read operation and tri-state the output pin (SO).

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7

Program and Erase Commands

7.1

Buffer Write

Using the Buffer Write command allows data clocked in from the SI pin to be written directly into either one of the

SRAM data buffers.

To load data into a buffer using the standard DataFlash buffer size (528 bytes), an opcode of 84h for Buffer 1 or

87h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 14 dummy bits and

10 buffer address bits (BFA9 - BFA0). The 10 buffer address bits specify the first byte in the buffer to be written.

To load data into a buffer using the binary buffer size (512 bytes), an opcode of 84h for Buffer 1 or 87h for Buffer 2,

must be clocked into the device followed by 15 dummy bits and nine buffer address bits (BFA8 - BFA0). The nine

buffer address bits specify the first byte in the buffer to be written.

After the last address byte has been clocked into the device, data can then be clocked in on subsequent clock

cycles. If the end of the data buffer is reached, the device wraps around back to the beginning of the buffer. Data

continues to be loaded into the buffer until a low-to-high transition is detected on the CS pin.

7.2

Buffer to Main Memory Page Program with Built-In Erase

The Buffer to Main Memory Page Program with Built-In Erase command allows data that is stored in one of the

SRAM buffers to be written into an erased or programmed page in the main memory array. It is not necessary to

pre-erase the page in main memory to be written because this command automatically erases the selected page

prior to the program cycle.

To perform a Buffer to Main Memory Page Program with Built-In Erase using the standard DataFlash page size

(528 bytes), an opcode of 83h for Buffer 1 or 86h for Buffer 2 must be clocked into the device followed by three

address bytes comprised of two dummy bits, 12 page address bits (PA11 - PA0) that specify the page in the main

memory to be written, and 10 dummy bits.

To perform a Buffer to Main Memory Page Program with Built-In Erase using the binary page size (512 bytes), an

opcode of 83h for Buffer 1 or 86h for Buffer 2 must be clocked into the device followed by three address bytes

comprised of three dummy bits, 12 page address bits (A20 - A9) that specify the page in the main memory to be

written, and nine dummy bits.

When a low-to-high transition occurs on the CS pin, the device first erases the selected page in main memory (the

erased state is a logic 1) and then program the data stored in the appropriate buffer into that same page in main

memory. Both erasing and programming the page are internally self-timed and take a maximum time of t_EP. During

this time, the RDY/BUSY bit in the Status Register indicates that the device is busy.

The device also incorporates an intelligent erase and program algorithm that can detect when a byte location fails

to erase or program properly. If an erase or programming error arises, it is indicated by the EPE bit in the Status

Register.

7.3

Buffer to Main Memory Page Program without Built-In Erase

The Buffer to Main Memory Page Program without Built-In Erase command allows data that is stored in one of the

SRAM buffers to be written into a pre-erased page in the main memory array. It is necessary that the page in main

memory to be written be previously erased in order to avoid programming errors.

To perform a Buffer to Main Memory Page Program without Built-In Erase using the standard DataFlash page size

(528 bytes), an opcode of 88h for Buffer 1 or 89h for Buffer 2 must be clocked into the device followed by three

address bytes comprised of two dummy bits, 12 page address bits (PA11 - PA0) that specify the page in the main

memory to be written, and 10 dummy bits.

To perform a Buffer to Main Memory Page Program using the binary page size (512 bytes), an opcode of 88h for

Buffer 1, or 89h for Buffer 2, must be clocked into the device followed by three address bytes comprised of three

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dummy bits, 12 page address bits (A20 - A9) that specify the page in the main memory to be written, and nine

dummy bits.

When a low-to-high transition occurs on the CS pin, the device programs the data stored in the appropriate buffer

into the specified page in the main memory. The page in main memory that is being programmed must have been

previously erased using one of the erase commands (Page Erase, Block Erase, Sector Erase, or Chip Erase).

Programming the page is internally self-timed and takes a maximum time of t_P. During this time, the RDY/BUSY bit

in the Status Register indicates that the device is busy.

The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to

program properly. If a programming error arises, it is indicated by the EPE bit in the Status Register.

7.4

Main Memory Page Program through Buffer with Built-In Erase

The Main Memory Page Program through Buffer with Built-In Erase command combines the Buffer Write and

Buffer to Main Memory Page Program with Built-In Erase operations into a single operation to help simplify

application firmware development. With the Main Memory Page Program through Buffer with Built-In Erase

command, data is first clocked into either Buffer 1 or Buffer 2, the addressed page in memory is then automatically

erased, and then the contents of the appropriate buffer are programmed into the just-erased main memory page.

To perform a Main Memory Page Program through Buffer using the standard DataFlash page size (528 bytes), an

opcode of 82h for Buffer 1 or 85h for Buffer 2 must first be clocked into the device followed by three address bytes

comprised of two dummy bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory to be

written, and 10 buffer address bits (BFA9 - BFA0) that select the first byte in the buffer to be written.

To perform a Main Memory Page Program through Buffer using the binary page size (512 bytes), an opcode of 82h

for Buffer 1 or 85h for Buffer 2 must first be clocked into the device followed by three address bytes comprised of

three dummy bits, 12 page address bits (A20 - A9) that specify the page in the main memory to be written, and nine

buffer address bits (BFA8 - BFA0) that select the first byte in the buffer to be written.

After all address bytes have been clocked in, the device takes data from the input pin (SI) and store it in the

specified data buffer. If the end of the buffer is reached, the device wraps around back to the beginning of the

buffer. When there is a low-to-high transition on the CS pin, the device first erases the selected page in main

memory (the erased state is a logic 1) and then program the data stored in the buffer into that main memory page.

Erasing and programming the page are internally self-timed and take a maximum time of t_EP. During this time, the

RDY/BUSY bit in the Status Register indicates that the device is busy.

The device also incorporates an intelligent erase and programming algorithm that can detect when a byte location

fails to erase or program properly. If an erase or program error arises, it is indicated by the EPE bit in the Status

Register.

7.5

Main Memory Byte/Page Program through Buffer 1 without Built-In Erase

The Main Memory Byte/Page Program through Buffer 1 without Built-In Erase command combines both the Buffer

Write and Buffer to Main Memory Program without Built-In Erase operations to allow any number of bytes (1 to

512/528 bytes) to be programmed directly into previously erased locations in the main memory array. With the

Main Memory Byte/Page Program through Buffer 1 without Built-In Erase command, data is first clocked into Buffer

1, and then only the bytes clocked into the buffer are programmed into the pre-erased byte locations in main

memory. Multiple bytes up to the page size can be entered with one command sequence.

To perform a Main Memory Byte/Page Program through Buffer 1 using the standard DataFlash page size (528

bytes), an opcode of 02h must first be clocked into the device followed by three address bytes comprised of two

dummy bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory to be written, and 10

buffer address bits (BFA9 - BFA0) that select the first byte in the buffer to be written. After all address bytes are

clocked in, the device takes data from the input pin (SI) and store it in Buffer 1. Any number of bytes (1 to 528) can

be entered. If the end of the buffer is reached, then the device wraps around back to the beginning of the buffer.

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To perform a Main Memory Byte/Page Program through Buffer 1 using the binary page size (512 bytes), an opcode

of 02h for Buffer 1 using must first be clocked into the device followed by three address bytes comprised of three

dummy bits, 12 page address bits (A20 - A9) that specify the page in the main memory to be written, and nine

buffer address bits (BFA8 - BFA0) that selects the first byte in the buffer to be written. After all address bytes are

clocked in, the device takes data from the input pin (SI) and store it in Buffer 1. Any number of bytes (1 to 512) can

be entered. If the end of the buffer is reached, then the device wraps around back to the beginning of the buffer.

When using the binary page size, the page and buffer address bits correspond to a 21-bit logical address (A20-A0)

in the main memory.

After all data bytes have been clocked into the device, a low-to-high transition on the CS pin starts the program

operation in which the device programs the data stored in Buffer 1 into the main memory array. Only the data bytes

that were clocked into the device are programmed into the main memory.

Example: If only two data bytes were clocked into the device, then only two bytes are programmed into main memory

and the remaining bytes in the memory page remains in their previous state.

The CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the operation is aborted

and no data are programmed. Programming the data bytes is internally self-timed and takes a maximum time of t_P

(the program time is a multiple of the t_BPtime depending on the number of bytes being programmed). During this

time, the RDY/BUSY bit in the Status Register indicates that the device is busy.

The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to

program properly. If a programming error arises, it is indicated by the EPE bit in the Status Register.

7.6

Read-Modify-Write

A completely self-contained read-modify-write operation can be performed to reprogram any number of sequential

bytes in a page in the main memory array without affecting the rest of the bytes in the same page. This command

allows the device to easily emulate an EEPROM by providing a method to modify a single byte or more in the main

memory in a single operation, without the need for pre-erasing the memory or the need for any external RAM

buffers. The Read-Modify-Write command is essentially a combination of the Main Memory Page to Buffer

Transfer, Buffer Write, and Buffer to Main Memory Page Program with Built-in Erase commands.

To perform a Read-Modify-Write using the standard DataFlash page size (528 bytes), an opcode of 58h for Buffer

1 or 59h for Buffer 2 must be clocked into the device followed by three address bytes comprised of two dummy bits,

12 page address bits (PA11 - PA0) that specify the page in the main memory to be written, and 10 byte address

bits (BA9 - BA0) that designate the starting byte address within the page to reprogram.

To perform a Read-Modify-Write using the binary page size (512 bytes), an opcode of 58h for Buffer 1 or 59h for

Buffer 2 must be clocked into the device followed by three address bytes comprised of three dummy bits, 12 page

address bits (A20 - A9) that specify the page in the main memory to be written, and 9 byte address bits (A8 - A0)

designate the starting byte address within the page to reprogram.

After the address bytes have been clocked in, any number of sequential data bytes from one to 512/528 bytes can

be clocked into the device. If the end of the buffer is reached when clocking in the data, then the device wraps

around back to the beginning of the buffer. After all data bytes have been clocked into the device, a low-to-high

transition on the CS pin starts the self-contained, internal read-modify-write operation. Only the data bytes that

were clocked into the device are reprogrammed in the main memory.

Example: If only one data byte was clocked into the device, then only one byte in main memory is reprogrammed and

the remaining bytes in the main memory page remain in their previous state.

The CS pin must be deasserted on a byte boundary (multiples of 8 bits); otherwise, the operation is aborted and no

data are programmed. Reprogramming the data bytes is internally self-timed and takes a maximum time of t_P.

During this time, the RDY/BUSY bit in the Status Register indicates that the device is busy.

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The device also incorporates an intelligent erase and programming algorithm that can detect when a byte location

fails to erase or program properly. If an erase or program error arises, it is indicated by the EPE bit in the Status

Register.

The Read-Modify-Write command uses the same opcodes as the Auto Page Rewrite command. If no data bytes

are clocked into the device, then the device performs an Auto Page Rewrite operation. See the Auto Page Rewrite

command description on page 26 for more details.

7.7

Page Erase

The Page Erase command can be used to individually erase any page in the main memory array allowing the

Buffer to Main Memory Page Program without Built-In Erase command or the Main Memory Byte/Page Program

through Buffer 1 command to be used at a later time.

To perform a Page Erase with the standard DataFlash page size (528 bytes), an opcode of 81h must be clocked

into the device followed by three address bytes comprised of two dummy bits, 12 page address bits (PA11 - PA0)

that specify the page in the main memory to be erased, and 10 dummy bits.

To perform a Page Erase with the binary page size (512 bytes), an opcode of 81h must be clocked into the device

followed by three address bytes comprised of three dummy bits, 12 page address bits (A20 - A9) that specify the

page in the main memory to be erased, and nine dummy bits.

When a low-to-high transition occurs on the CS pin, the device erases the selected page (the erased state is a

logic 1). The erase operation is internally self-timed and takes a maximum time of t_PE. During this time, the

RDY/BUSY bit in the Status Register indicates that the device is busy.

The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase

properly. If an erase error arises, it is indicated by the EPE bit in the Status Register.

7.8

Block Erase

The Block Erase command can be used to erase a block of eight pages at one time. This command is useful when

needing to pre-erase larger amounts of memory and is more efficient than issuing eight separate Page Erase

commands.

To perform a Block Erase with the standard DataFlash page size (528 bytes), an opcode of 50h must be clocked

into the device followed by three address bytes comprised of two dummy bits, nine page address bits (PA11 -

PA3), and 13 dummy bits. The nine page address bits are used to specify which block of eight pages is to be

erased.

To perform a Block Erase with the binary page size (512 bytes), an opcode of 50h must be clocked into the device

followed by three address bytes comprised of three dummy bits, nine page address bits (A20 - A12), and 12

dummy bits. The nine page address bits are used to specify which block of eight pages is to be erased.

When a low-to-high transition occurs on the CS pin, the device erases the selected block of eight pages. The erase

operation is internally self-timed and takes a maximum time of t_BE. During this time, the RDY/BUSY bit in the Status

Register indicates that the device is busy.

The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase

properly. If an erase error arises, it is indicated by the EPE bit in the Status Register.

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Table 7-1. Block Erase Addressing

PA11/

A20

PA10/

A19

PA9/

A18

PA8/

A17

PA7/

A16

PA6/

A15

PA5/

A14

PA4/

A13

PA3/

A12

PA2/

A11

PA1/

A10

PA0/

A9

Block

0

1

0

1

0

1

X

0

1

2

3

•

1

0

1

0

1

0

1

X

508

509

510

511

7.9

Sector Erase

The Sector Erase command can be used to individually erase any sector in the main memory.

The main memory array is comprised of 17 sectors. Only one sector can be erased at a time. To erase Sector 0a

or Sector 0b with the standard DataFlash page size (528 bytes), opcode 7Ch must be clocked into the device,

followed by three address bytes comprised of two dummy bits, nine page address bits (PA11 - PA3), and 13

dummy bits. To erase Sector 1-15, opcode 7Ch must be clocked into the device, followed by three address bytes

comprised of two dummy bits, four page address bits (PA11 - PA8), and 18 dummy bits.

To erase Sector 0a or Sector 0b with the binary page size (512 bytes), opcode 7Ch must be clocked into the device

followed by three address bytes comprised of three dummy bits, nine page address bits (A20 - A12), and 12

dummy bits. To erase Sector 1-15 erase, opcode 7Ch must be clocked into the device, followed by three dummy

bits, four page address bits (A20 - A17), and 17 dummy bits.

The page address bits are used to specify any valid address location within the sector to be erased. When the CS

pin transitions from low-to high, the device erases the selected sector. This operation is internally timed and takes

a maximum time of t_SE. During this time, the RDY/BUSY bit in the Status Register indicates that the device is busy.

The device also incorporates an intelligent algorithm that can detect when a byte location fails to erase properly. If

an erase error arises, it is indicated by the EPE bit in the Status Register.

Table 7-2. Sector Erase Addressing

PA11/ PA10/

PA9/

A18

PA8/

A17

PA7/

A16

PA6/

A15

PA5/

A14

PA4/

A13

PA3/

A12

PA2/

A11

PA1/

A10

PA0/

A9

Sector

A20

A19

0

1

0

1

0

1

X

0a

0b

1

X

2

•

1

0

1

0

1

0

1

X

12

13

14

15

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7.10 Chip Erase

The Chip Erase command allows the entire main memory array to be erased can be erased at one time.

To execute the Chip Erase command, a four-byte command sequence of C7h, 94h, 80h, and 9Ah must be clocked

into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the

device, and any data clocked in after the opcode are ignored. After the last bit of the opcode sequence has been

clocked in, the CS pin must be deasserted to start the erase process. The erase operation is internally self-timed

and takes a time of t_CE. During this time, the RDY/BUSY bit in the Status Register indicates that the device is busy.

The Chip Erase command does not affect sectors that are protected or locked down; the contents of those sectors

remains unchanged. Only those sectors that are not protected or locked down are erased.

The WP pin can be asserted while the device is erasing, but protection is not activated until the internal erase cycle

completes.

The device also incorporates an intelligent algorithm that can detect when a byte location fails to erase properly. If

an erase error arises, it is indicated by the EPE bit in the Status Register.

Table 7-3. Chip Erase Command

Command

Byte 1

Byte 2

Byte 3

Byte 4

Chip Erase

C7h

94h

80h

9Ah

CS

C7h

94h

80h

9Ah

Each transition represents eight bits

Figure 7-1. Chip Erase

7.11 Program/Erase Suspend

In some code and data storage applications, it might not be possible for the system to wait the milliseconds

required for the Flash memory to complete a program or erase cycle. The Program/Erase Suspend command

allows a program or erase operation in progress to a particular 128-kB sector of the main memory array to be

suspended so that other device operations can be performed.

Example: By suspending an erase operation to a particular sector, the system can perform functions such as a

program or read operation within a different 128-kB sector. Other device operations, such as Read Status

Register, can also be performed while a program or erase operation is suspended.

To perform a Program/Erase Suspend, an opcode of B0h must be clocked into the device. No address bytes need

to be clocked into the device, and any data clocked in after the opcode are ignored. When the CS pin is

deasserted, the program or erase operation currently in progress is suspended within a time of t_SUSP. One of the

Program Suspend bits (PS1 or PS2) or the Erase Suspend bit (ES) in the Status Register is then set to the logic 1

state. Also, the RDY/BUSY bit in the Status Register indicates that the device is ready for another operation.

Read operations are not allowed to a 128-kB sector that has had its program or erase operation suspended. If a

read is attempted to a suspended sector, then the device outputs undefined data. Therefore, when performing a

Continuous Array Read operation and the device's internal address counter increments and crosses the sector

boundary to a suspended sector, the device then starts outputting undefined data continuously until the address

counter increments and crosses a sector boundary to an unsuspended sector.

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A program operation is not allowed to a sector that has been erase suspended. If a program operation is attempted

to an erase suspended sector, then the program operation aborts.

During an Erase Suspend, a program operation to a different 128-kB sector can be started and subsequently

suspended. This results in a simultaneous Erase Suspend/Program Suspend condition and is indicated by the

states of both the ES and PS1 or PS2 bits in the Status Register being set to a logic 1.

If a Reset command is performed, or if the RESET pin is asserted while a sector is erase suspended, then the

suspend operation is aborted and the contents of the sector are left in an undefined state. However, if a reset is

performed while a page is program or erase suspended, the suspend operation aborts, but only the contents of the

page being programmed or erased are undefined; the remaining pages in the 128-kB sector retain their previous

contents.

Table 7-4. Operations Allowed and Not Allowed During Suspend

Operation During

Program Suspend in

Buffer 1 (PS1)

Operation During

Program Suspend in

Buffer 2 (PS2)

Operation During

Erase Suspend (ES)

Command

Read Commands

Read Array (All Opcodes)

Read Buffer 1 (All Opcodes)

Read Buffer 2 (All Opcodes)

Program and Erase Commands

Buffer 1 Write

Allowed

Not Allowed

Allowed

Buffer 2 Write

Not Allowed

Buffer 1 to Memory Program w/ Erase

Buffer 2 to Memory Program w/ Erase

Buffer 1 to Memory Program w/o Erase

Buffer 2 to Memory Program w/o Erase

Memory Program through Buffer 1 w/ Erase

Memory Program through Buffer 2 w/ Erase

Memory Program through Buffer 1 w/o Erase

Auto Page Rewrite

Not Allowed

Allowed

Not Allowed

Allowed

Not Allowed

Page Erase

Block Erase

Sector Erase

Chip Erase

Protection and Security Commands

Enable Sector Protection

Not Allowed

Disable Sector Protection

Erase Sector Protection Register

Program Sector Protection Register

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Table 7-4. Operations Allowed and Not Allowed During Suspend (continued)

Operation During

Program Suspend in

Buffer 1 (PS1)

Operation During

Program Suspend in

Buffer 2 (PS2)

Operation During

Erase Suspend (ES)

Command

Read Sector Protection Register

Sector Lockdown

Allowed

Not Allowed

Allowed

Not Allowed

Allowed

Not Allowed

Allowed

Read Sector Lockdown

Freeze Sector Lockdown State

Program Security Register

Not Allowed

Allowed

Not Allowed

Allowed

Not Allowed

Allowed

Read Security Register

Additional Commands

Main Memory to Buffer 1 Transfer

Main Memory to Buffer 2 Transfer

Main Memory to Buffer 1 Compare

Main Memory to Buffer 2 Compare

Enter Deep Power-Down

Not Allowed

Allowed

Not Allowed

Allowed

Not Allowed

Allowed

Not Allowed

Allowed

Not Allowed

Allowed

Not Allowed

Allowed

Resume from Deep Power-Down

Enter Ultra-Deep Power-Down mode

Read Configuration Register

Read Status Register

Allowed

Read Manufacturer and Device ID

Reset (via Hardware or Software)

Allowed

7.12 Program/Erase Resume

The Program/Erase Resume command allows a suspended program or erase operation to be resumed and

continue where it left off.

To perform a Program/Erase Resume, an opcode of D0h must be clocked into the device. No address bytes need

to be clocked into the device, and any data clocked in after the opcode are ignored. When the CS pin is

deasserted, the program or erase operation currently suspended is resumed within a time of t_RES. The PS1 bit, PS2

bit, or ES bit in the Status Register is then reset back to a logic 0 state to indicate that the program or erase

operation is no longer suspended. Also, the RDY/BUSY bit in the Status Register indicates that the device is busy

performing a program or erase operation.

During a simultaneous Erase Suspend/Program Suspend condition, issuing the Program/Erase Resume command

results in the program operation resuming first. After the program operation has been completed, the

Program/Erase Resume command must be issued again in order for the erase operation to be resumed.

While the device is busy resuming a program or erase operation, any attempts at issuing the Program/Erase

Suspend command is ignored. Therefore, if a resumed program or erase operation needs to be subsequently

suspended again, the system must either wait the entire t_REStime before issuing the Program/Erase Suspend

command, or it must check the status of the RDY/BUSY bit or the appropriate PS1, PS2, or ES bit in the Status

Register to determine if the previously suspended program or erase operation has resumed.

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8

Sector Protection

Two protection methods, hardware and software controlled, are provided for protection against inadvertent or

erroneous program and erase cycles. The software controlled method relies on the use of software commands to

enable and disable sector protection while the hardware controlled method employs the use of the Write Protect

(WP) pin. The selection of which sectors that are to be protected or unprotected against program and erase

operations is specified in the Nonvolatile Sector Protection Register. The status of whether or not sector protection

has been enabled or disabled by either the software or the hardware controlled methods can be determined by

checking the Status Register.

8.1

Software Sector Protection

Software controlled protection is useful in applications in which the WP pin is not or cannot be controlled by a host

processor. In such instances, the WP pin can be left floating (the WP pin is internally pulled high) and sector

protection can be controlled using the Enable Sector Protection and Disable Sector Protection commands.

If the device is power cycled, then the software controlled protection is disabled. Once the device is powered up,

the Enable Sector Protection command must be reissued if sector protection is wanted and if the WP pin is not

used.

8.1.1 Enable Sector Protection

Sectors specified for protection in the Sector Protection Register can be protected from program and erase

operations by issuing the Enable Sector Protection command. To enable the sector protection, a four-byte

command sequence of 3Dh, 2Ah, 7Fh, and A9h must be clocked into the device. After the last bit of the opcode

sequence has been clocked in, the CS pin must be deasserted to enable the Sector Protection.

Table 8-1. Enable Sector Protection Command

Command

Byte 1

Byte 2

Byte 3

Byte 4

Enable Sector Protection

3Dh

2Ah

7Fh

A9h

CS

SI

3Dh

2Ah

7Fh

A9h

Each transition represents eight bits

Figure 8-1. Enable Sector Protection

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8.1.2 Disable Sector Protection

To disable the sector protection, a four-byte command sequence of 3Dh, 2Ah, 7Fh, and 9Ah must be clocked into

the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to disable

the sector protection.

Table 8-2. Disable Sector Protection Command

Command

Byte 1

Byte 2

Byte 3

Byte 4

Disable Sector Protection

3Dh

2Ah

7Fh

9Ah

CS

3Dh

2Ah

7Fh

A9h

SI

Each transition represents eight bits

Figure 8-2. Disable Sector Protection

8.2

Hardware Controlled Protection

Sectors specified for protection in the Sector Protection Register and the Sector Protection Register itself can be

protected from program and erase operations by asserting the WP pin and keeping the pin in its asserted state.

The Sector Protection Register and any sector specified for protection cannot be erased or programmed as long as

the WP pin is asserted. In order to modify the Sector Protection Register, the WP pin must be deasserted. If the

WP pin is permanently connected to GND, then the contents of the Sector Protection Register cannot be changed.

If the WP pin is deasserted or permanently connected to V_CC, then the contents of the Sector Protection Register

can be modified.

The WP pin overrides the software controlled protection method but only for protecting the sectors.

Example: If the sectors are not previously protected by the Enable Sector Protection command, then asserting the WP

pin enables the sector protection within the maximum specified t_WPEtime. When the WP pin is deasserted,

however, the sector protection is no longer be enabled (after the maximum specified t_WPDtime) as long as

the Enable Sector Protection command was not issued while the WP pin was asserted. If the Enable Sector

Protection command was issued before or while the WP pin was asserted, then deasserting the WP pin

does not disable the sector protection. In this case, the Disable Sector Protection command must be issued

while the WP pin is deasserted to disable the sector protection. The Disable Sector Protection command is

also ignored whenever the WP pin is asserted.

A noise filter is incorporated to help protect against spurious noise that might inadvertently assert or deassert the

WP pin.

Figure 8-3 and Table 8-3 detail the sector protection status for various scenarios of the WP pin, the Enable Sector

Protection command, and the Disable Sector Protection command.

1

2

3

WP

Figure 8-3. WP Pin and Protection Status

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Table 8-3. WP Pin and Protection Status

Time

Sector

Protection

Status

Sector

Protection

Register

Disable Sector

Protection Command

WP Pin

Enable Sector Protection Command

Period

Command Not Issued Previously

X

Disabled

Enabled

Disabled

Enabled

Read/Write

Read

1

2

3

High

Low

High

—

Issue Command

—

X

Command Issued During Period 1 or 2

Not Issued Yet

Issue Command

—

Read/Write

—

Issue Command

8.3

Sector Protection Register

The nonvolatile Sector Protection Register specifies which sectors are to be protected or unprotected with either

the software or hardware controlled protection methods. The Sector Protection Register contains 16 bytes of data,

of which byte locations 0 through 15 contain values that specify whether Sectors 0 through 15 are protected or

unprotected. The Sector Protection Register is user modifiable and must be erased before it can be

reprogrammed. Table 8-4 illustrates the format of the Sector Protection Register.

Table 8-4. Sector Protection Register

Sector Number

Protected

0 (0a, 0b)

1 to 15

FFh

See Table 8-5

Unprotected

00h

Note: The default values for bytes 0 through 15 are 00h when shipped from Adesto.

Table 8-5. Sector 0 (0a, 0b) Sector Protection Register Byte Value

Bit 7:6

Bit 5:4

Bit 3:2

N/A

Bit 1:0

N/A

Data

Value

Sector Protection

Sector 0a

(Page 0-7)

Sector 0b

(Page 8-255)

Sectors 0a and 0b Unprotected

Protect Sector 0a

00

11

00

11

00

11

XX

0xh

Cxh

3xh

Fxh

Protect Sector 0b

Protect Sectors 0a and 0b

Note: x = Don’t care.

8.3.1 Erase Sector Protection Register

In order to modify and change the values of the Sector Protection Register, it must first be erased using the Erase

Sector Protection Register command.

To erase the Sector Protection Register, a four-byte command sequence of 3Dh, 2Ah, 7Fh, and CFh must be

clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be

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deasserted to initiate the internally self-timed erase cycle. Erasing the Sector Protection Register takes a maximum

time of t_PE. During this time, the RDY/BUSY bit in the Status Register indicates that the device is busy. If the device

is powered-down before the erase cycle is done, then the contents of the Sector Protection Register cannot be

guaranteed.

The Sector Protection Register can be erased with sector protection enabled or disabled. Since the erased state

(FFh) of each byte in the Sector Protection Register is used to indicate that a sector is specified for protection,

leaving the sector protection enabled during the erasing of the register allows the protection scheme to be more

effective in the prevention of accidental programming or erasing of the device. If an erroneous program or erase

command is sent to the device immediately after erasing the Sector Protection Register and before the register can

be reprogrammed, then the erroneous program or erase command is not processed because all sectors are

protected.

Table 8-6. Erase Sector Protection Register Command

Command

Byte 1

Byte 2

Byte 3

Byte 4

Erase Sector Protection Register

3Dh

2Ah

7Fh

CFh

CS

SI

3Dh

2Ah

7Fh

CFh

Each transition represents eight bits

Figure 8-4. Erase Sector Protection Register

8.3.2 Program Sector Protection Register

Once the Sector Protection Register has been erased, it can be reprogrammed using the Program Sector

Protection Register command.

To program the Sector Protection Register, a four-byte command sequence of 3Dh, 2Ah, 7Fh, and FCh must be

clocked into the device followed by 16 bytes of data corresponding to Sectors 0 through 15. After the last bit of the

opcode sequence and data have been clocked in, the CS pin must be deasserted to initiate the internally self-timed

program cycle. Programming the Sector Protection Register takes a maximum time of t_P. During this time, the

RDY/BUSY bit in the Status Register indicates that the device is busy. If the device is powered-down before the

erase cycle is done, then the contents of the Sector Protection Register cannot be guaranteed.

If the proper number of data bytes is not clocked in before the CS pin is deasserted, then the protection status of

the sectors corresponding to the bytes not clocked in cannot be guaranteed.

Example: If only the first two bytes are clocked in instead of the complete 16 bytes, then the protection status of the

last 14 sectors cannot be guaranteed. Furthermore, if more than 16 bytes of data is clocked into the device,

then the data wraps back around to the beginning of the register. For instance, if 17 bytes of data are

clocked in, then the 17th byte is stored at byte location 0 of the Sector Protection Register.

The data bytes clocked into the Sector Protection Register need to be valid values (0xh, 3xh, Cxh, and Fxh for

Sector 0a or Sector 0b, and 00h or FFh for other sectors) in order for the protection to function correctly. If a non-

valid value is clocked into a byte location of the Sector Protection Register, then the protection status of the sector

corresponding to that byte location cannot be guaranteed.

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Example: If a value of 17h is clocked into byte location 2 of the Sector Protection Register, then the protection status

of Sector 2 cannot be guaranteed.

The Sector Protection Register can be reprogrammed while the sector protection is enabled or disabled. Being

able to reprogram the Sector Protection Register with the sector protection enabled allows the user to temporarily

disable the sector protection to an individual sector rather than disabling sector protection completely.

The Program Sector Protection Register command uses Buffer 1 for processing. Therefore, the contents of Buffer

1 are altered from their previous state when this command is issued.

Table 8-7. Program Sector Protection Register Command

Command

Byte 1

Byte 2

Byte 3

Byte 4

Program Sector Protection Register

3Dh

2Ah

7Fh

FCh

CS

Data Byte

n + 1

Data Byte

n + 15

3Dh

2Ah

7Fh

FCh

SI

n

Each transition represents eight bits

Figure 8-5. Program Sector Protection Register

8.3.3 Read Sector Protection Register

To read the Sector Protection Register, an opcode of 32h and three dummy bytes must be clocked into the device.

After the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the SCK pin

results in the Sector Protection Register contents being output on the SO pin. The first byte (byte location 0)

corresponds to Sector 0 (0a and 0b), the second byte corresponds to Sector 1, and the last byte (byte location 15)

corresponds to Sector 15. Once the last byte of the Sector Protection Register has been clocked out, any

additional clock pulses results in undefined data being output on the SO pin. The CS pin must be deasserted to

terminate the Read Sector Protection Register operation and put the output into a high-impedance state.

Table 8-8. Read Sector Protection Register Command

Command

Byte 1

Byte 2

Byte 3

Byte 4

Read Sector Protection Register

32h

XXh

Note: XX = Dummy byte.

CS

32h

XX

SI

Data

n

Data

n + 1

Data

SO

n + 15

Each transition represents eight bits

Figure 8-6. Read Sector Protection Register

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8.3.4 About the Sector Protection Register

The Sector Protection Register is subject to a limit of 10,000 erase/program cycles. Carefully evaluate the number

of times the Sector Protection Register must be modified during the course of the application’s life cycle. If the

application requires that the Security Protection Register be modified more than the specified limit of 10,000 cycles

because the application needs to temporarily unprotect individual sectors (sector protection remains enabled while

the Sector Protection Register is reprogrammed), then the application needs to limit this practice. Instead, a

combination of temporarily unprotecting individual sectors along with disabling sector protection completely needs

to be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded.

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9

Security Features

9.1

Sector Lockdown

The device incorporates a sector lockdown mechanism that allows each individual sector to be permanently locked

so that it becomes read-only (ROM). This is useful for applications that require the ability to permanently protect a

number of sectors against malicious attempts at altering program code or security information.

Warning:

Once a sector is locked down, it can never be erased or programmed, and it can never be unlocked.

To issue the sector lockdown command, a four-byte command sequence of 3Dh, 2Ah, 7Fh, and 30h must be

clocked into the device followed by three address bytes specifying any address within the sector to be locked

down. After the last address bit has been clocked in, the CS pin must be deasserted to initiate the internally self-

timed lockdown sequence. The lockdown sequence takes a maximum time of t_P. During this time, the RDY/BUSY

bit in the Status Register indicates that the device is busy. If the device is powered-down before the lockdown

sequence is done, then the lockdown status of the sector cannot be guaranteed. In this case, it is recommended

that the user read the Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or

bytes and re-issue the Sector Lockdown command if necessary.

Table 9-1. Sector Lockdown Command

Command

Byte 1

Byte 2

Byte 3

Byte 4

Sector Lockdown

3Dh

2Ah

7Fh

30h

CS

SI

Address

byte

Address

byte

Address

byte

3Dh

2Ah

7Fh

30h

Each transition represents eight bits

Figure 9-1. Sector Lockdown

9.1.1 Read Sector Lockdown Register

The nonvolatile Sector Lockdown Register specifies which sectors in the main memory are currently unlocked or

have been permanently locked down. The Sector Lockdown Register is a read-only register and contains 16 bytes

of data which correspond to Sectors 0 through 15. To read the Sector Lockdown Register, an opcode of 35h must

be clocked into the device followed by three dummy bytes. After the opcode and dummy bytes have been clocked

in, the data for the contents of the Sector Lockdown Register are clocked out on the SO pin. The first byte (byte

location 0) corresponds to Sector 0 (0a and 0b), the second byte corresponds to Sector 1, and the last byte (byte

location 15) corresponds to Sector 15. After the last byte of the Sector Lockdown Register has been read,

additional pulses on the SCK pin results in undefined data being output on the SO pin.

Deasserting the CS pin terminates the Read Sector Lockdown Register operation and put the SO pin into a high-

impedance state. Table 9-2 details the format the Sector Lockdown Register.

Table 9-2. Sector Lockdown Register

Sector Number

Locked

0 (0a, 0b)

1 to 15

FFh

See Table 9-3

Unlocked

00h

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Table 9-3. Sector 0 (0a and 0b) Sector Lockdown Register Byte Value

Bit 7:6

Bit 5:4

Bit 3:2

N/A

00

Bit 1:0

N/A

00

Data

Value

Sector Protection

Sector 0a (Page 0-7)

Sector 0b (Page 8-255)

Sectors 0a and 0b Unlocked

Sector 0a Locked

00

11

00

11

00

11

00h

C0h

30h

F0h

00

Sector 0b Locked

00

Sectors 0a and 0b Locked

00

Table 9-4. Read Sector Lockdown Register Command

Command

Byte 1

Byte 2

XXh

Byte 3

XXh

Byte 4

Read Sector Lockdown Register

35h

XXh

CS

32h

XX

SI

Data

n

Data

n + 1

Data

SO

n + 15

Each transition represents eight bits

Figure 9-2. Read Sector Lockdown Register

9.1.2 Freeze Sector Lockdown

The Sector Lockdown command can be permanently disabled, and the current sector lockdown state can be

permanently frozen so that no additional sectors can be locked down aside from those already locked down. Any

attempt to issue the Sector Lockdown command after the Sector Lockdown State has been frozen is ignored.

To issue the Freeze Sector Lockdown command, the CS pin must be asserted and the opcode sequence of 34h,

55h, AAh, and 40h must be clocked into the device. Any additional data clocked into the device are ignored. When

the CS pin is deasserted, the current sector lockdown state is permanently frozen within a time of t_LOCK. Also, the

SLE bit in the Status Register is permanently reset to a logic 0 to indicate that the Sector Lockdown command is

permanently disabled.

Table 9-5. Freeze Sector Lockdown

Command

Byte 1

Byte 2

Byte 3

Byte 4

Freeze Sector Lockdown

34h

55h

AAh

40h

CS

34h

55h

AAh

40h

SI

Each transition represents eight bits

Figure 9-3. Freeze Sector Lockdown

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9.2

Security Register

The device contains a specialized Security Register that can be used for purposes such as unique device

serialization or locked key storage. The register is comprised of a total of 128 bytes that is divided into two portions.

The first 64 bytes (byte locations 0 through 63) of the Security Register are allocated as a One-Time

Programmable space. Once these 64 bytes have been programmed, they cannot be erased or reprogrammed.

The remaining 64 bytes of the register (byte locations 64 through 127) are factory programmed by Adesto and

contains a unique value for each device. The factory programmed data is fixed and cannot be changed.

Table 9-6. Security Register

Security Register Byte Number

0

1

· · ·

63

64

65

· · ·

127

Data Type

One-Time User Programmable

Factory Programmed by Adesto

9.2.1 Programming the Security Register

The user programmable portion of the Security Register does not need to be erased before it is programmed.

To program the Security Register, a four-byte opcode sequence of 9Bh, 00h, 00h, and 00h must be clocked into

the device. After the last bit of the opcode sequence has been clocked into the device, the data for the contents of

the 64-byte user programmable portion of the Security Register must be clocked in.

After the last data byte has been clocked in, the CS pin must be deasserted to initiate the internally self-timed

program cycle. Programming the Security Register takes a time of t_P, during which time the RDY/BUSY bit in the

Status Register indicates that the device is busy. If the device is powered-down during the program cycle, then the

contents of the 64-byte user programmable portion of the Security Register cannot be guaranteed.

If the full 64 bytes of data are not clocked in before the CS pin is deasserted, then the values of the byte locations

not clocked in cannot be guaranteed.

Example: If only the first two bytes are clocked in instead of the complete 64 bytes, then the remaining 62 bytes of the

user programmable portion of the Security Register cannot be guaranteed. Furthermore, if more than 64

bytes of data is clocked into the device, then the data wraps back around to the beginning of the register.

For example, if 65 bytes of data are clocked in, then the 65th byte is stored at byte location 0 of the Security

Register.

Warning:

The user programmable portion of the Security Register can only be programmed one time.

Therefore, it is not possible, for example, to only program the first two bytes of the register and then program

the remaining 62 bytes at a later time.

The Program Security Register command uses Buffer 1 for processing. Therefore, the contents of Buffer 1

are altered from their previous state when this command is issued.

CS

SI

Data

n

Data

n + 1

Data

n + x

9Bh

00h

Each transition represents eight bits

Figure 9-4. Program Security Register

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9.2.2 Reading the Security Register

To read the Security Register, an opcode of 77h and three dummy bytes must be clocked into the device. After the

last dummy bit has been clocked in, the contents of the Security Register can be clocked out on the SO pin. After

the last byte of the Security Register has been read, additional pulses on the SCK pin results in undefined data

being output on the SO pin.

Deasserting the CS pin terminates the Read Security Register operation and put the SO pin into a high-impedance

state.

CS

SI

77h

XX

Data

n

Data

n + 1

Data

n + x

SO

Each transition represents eight bits

Figure 9-5. Read Security Register

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10 Additional Commands

10.1 Main Memory Page to Buffer Transfer

A page of data can be transferred from the main memory to either Buffer 1 or Buffer 2. To transfer a page of data

using the standard DataFlash page size (528 bytes), an opcode of 53h for Buffer 1 or 55h for Buffer 2 must be

clocked into the device followed by three address bytes comprised of two dummy bits, 12 page address bits (PA11

- PA0) which specify the page in main memory to be transferred, and 10 dummy bits. To transfer a page of data

using the binary page size (512 bytes), an opcode of 53h for Buffer 1 and 55h for Buffer 2 must be clocked into the

device followed by three address bytes comprised of three dummy bits, 12 page address bits (A20 - A9) which

specify the page in the main memory to be transferred, and nine dummy bits.

The CS pin must be low while toggling the SCK pin to load the opcode and the three address bytes from the input

pin (SI). The transfer of the page of data from the main memory to the buffer begins when the CS pin transitions

from a low to a high state. During the page transfer time (t_XFR), the RDY/BUSY bit in the Status Register can be

read to determine whether or not the transfer has been completed.

10.2 Main Memory Page to Buffer Compare

A page of data in main memory can be compared to the data in Buffer 1 or Buffer 2 as a method to ensure that data

was successfully programmed after a Buffer to Main Memory Page Program command. To compare a page of data

with the standard DataFlash page size (528 bytes), an opcode of 60h for Buffer 1 or 61h for Buffer 2 must be

clocked into the device followed by three address bytes comprised of two dummy bits, 12 page address bits (PA11

- PA0) which specify the page in the main memory to be compared to the buffer, and 10 dummy bits. To compare

a page of data with the binary page size (512 bytes), an opcode of 60h for Buffer 1 or 61h for Buffer 2 must be

clocked into the device followed by three address bytes comprised of three dummy bits, 12 page address bits (A20

- A9) which specify the page in the main memory to be compared to the buffer, and nine dummy bits.

The CS pin must be low while toggling the SCK pin to load the opcode and the address bytes from the input pin

(SI). On the low-to-high transition of the CS pin, the data bytes in the selected Main Memory Page are compared

with the data bytes in Buffer 1 or Buffer 2. During the compare time (t_COMP), the RDY/BUSY bit in the Status

Register indicates that the part is busy. When the compare operation is done, bit 6 of the Status Register is

updated with the result of the compare.

10.3 Auto Page Rewrite

This command only needs to be used if the possibility exists that static (non-changing) data is stored in a page or

pages of a sector and the other pages of the same sector are erased and programmed a large number of times.

Applications that modify data in a random fashion within a sector can fall into this category. To preserve data

integrity of a sector, each page within a sector must be updated/rewritten at least once within every 50,000

cumulative page erase/program operations within that sector. The Auto Page Rewrite command provides a simple

and efficient method to “refresh” a page in the main memory array in a single operation.

The Auto Page Rewrite command is a combination of the Main Memory Page to Buffer Transfer and Buffer to Main

Memory Page Program with Built-In Erase commands. With the Auto Page Rewrite command, a page of data is

first transferred from the main memory to Buffer 1 or Buffer 2 and then the same data (from Buffer 1 or Buffer 2) is

programmed back into the same page of main memory, essentially “refreshing” the contents of that page. To start

the Auto Page Rewrite operation with the standard DataFlash page size (528 bytes), a one-byte opcode, 58H for

Buffer 1 or 59H for Buffer 2, must be clocked into the device followed by three address bytes comprised of two

dummy bits, 12 page address bits (PA11-PA0) that specify the page in main memory to be rewritten, and 10

dummy bits.

To initiate an Auto Page Rewrite with the a binary page size (512 bytes), the opcode 58H for Buffer 1 or 59H for

Buffer 2, must be clocked into the device followed by three address bytes consisting of three dummy bits, 12 page

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address bits (A20 - A9) that specify the page in the main memory that is to be rewritten, and nine dummy bits.

When a low-to-high transition occurs on the CS pin, the part first transfers data from the page in main memory to a

buffer and then program the data from the buffer back into same page of main memory. The operation is internally

self-timed and takes a maximum time of t_EP. During this time, the RDY/BUSY Status Register indicates that the

part is busy.

If a sector is programmed or reprogrammed sequentially page by page and the possibility does not exist that there

is a page or pages of static data, then the programming algorithm shown in Figure 27-1, on page 68, is

recommended. Otherwise, if there is a chance that there are one or more pages of a sector that contain static data,

then the programming algorithm shown in Figure 27.2, on page 69, is recommended.

Please contact Adesto for availability of devices that are specified to exceed the 50,000 cycle cumulative limit.

10.4 Status Register Read

The two-byte Status Register can be used to determine the device's ready/busy status, page size, a Main Memory

Page to Buffer Compare operation result, the sector protection status, Freeze Sector Lockdown status,

erase/program error status, Program/Erase Suspend status, and the device density. The Status Register can be

read at any time, including during an internally self-timed program or erase operation.

To read the Status Register, the CS pin must first be asserted and then the opcode D7h must be clocked into the

device. After the opcode has been clocked in, the device begins outputting Status Register data on the SO pin

during every subsequent clock cycle. After the second byte of the Status Register has been clocked out, the

sequence repeats itself, starting again with the first byte of the Status Register, as long as the CS pin remains

asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated, so each

repeating sequence can output new data. The RDY/BUSY status is available for both bytes of the Status Register

and is updated for each byte.

Deasserting the CS pin terminates the Status Register Read operation and put the SO pin into a high-impedance

state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

Table 10-1. Status Register Format – Byte 1

Type ¹

Bit

Name

Description

0

1

0

1

Device is busy with an internal operation.

7

RDY/BUSY Ready/Busy Status

R

Device is ready.

Main memory page data matches buffer data.

Main memory page data does not match buffer data.

6

5:2

1

COMP

Compare Result

R

101

1

DENSITY

PROTECT

Density Code

16-Mbit

0

1

0

1

Sector protection is disabled.

Sector Protection Status

Sector protection is enabled.

Device is configured for standard DataFlash page size (528 bytes).

Device is configured for “power of 2” binary page size (512 bytes).

0

PAGE SIZE Page Size Configuration

R

1. R = Readable only.

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Table 10-2. Status Register Format – Byte 2

Type ¹

Bit

7

Name

Description

Device is busy with an internal operation.

0

1

0

1

0

1

0

1

0

1

0

1

RDY/BUSY Ready/Busy Status

R

Device is ready.

6

RES

EPE

RES

SLE

Reserved for Future Use

Erase/Program Error

Reserved for future use.

Erase or program operation was successful.

Erase or program error detected.

5

4

Reserved for Future Use

Sector Lockdown Enabled

Reserved for future use.

Sector Lockdown command is disabled.

Sector Lockdown command is enabled.

No program operation has been suspended while using Buffer 2.

A sector is program suspended while using Buffer 2.

No program operation has been suspended while using Buffer 1.

A sector is program suspended while using Buffer 1.

No sectors are erase suspended.

3

Program Suspend Status

(Buffer 2)

2

1

0

PS2

PS1

ES

R

Program Suspend Status

(Buffer 1)

Erase Suspend

A sector is erase suspended.

1. R = Readable only.

10.4.1 RDY/BUSY Bit

The RDY/BUSY bit is used to determine whether or not an internal operation, such as a program or erase, is in

progress. To poll the RDY/BUSY bit to detect if an internally timed operation is done, new Status Register data

must be continually clocked out of the device until the state of the RDY/BUSY bit changes from a logic 0 to a logic

1.

10.4.2 COMP Bit

The result of the most recent Main Memory Page to Buffer Compare operation is indicated using the COMP bit. If

the COMP bit is a logic 1, then at least one bit of the data in the Main Memory Page does not match the data in the

buffer.

10.4.3 DENSITY Bits

The device density is indicated using the DENSITY bits. For the AT45DB161E, the four bit binary value is 1011.

The decimal value of these four binary bits does not actually equate to the device density; the four bits represent a

combinational code relating to differing densities of DataFlash devices. The DENSITY bits are not the same as the

density code indicated in the JEDEC Device ID information. The DENSITY bits are provided only for backward

compatibility to older generation DataFlash devices.

10.4.4 PROTECT Bit

The PROTECT bit provides information to the user on whether or not the sector protection has been enabled or

disabled, either by the software-controlled method or the hardware-controlled method.

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10.4.5 PAGE SIZE Bit

The PAGE SIZE bit indicates whether the buffer size and the page size of the main memory array is configured for

the “power of 2” binary page size (512 bytes) or the standard DataFlash page size (528 bytes).

10.4.6 EPE Bit

The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one

byte during the erase or program operation did not erase or program properly, then the EPE bit is set to the logic 1

state. The EPE bit is not set if an erase or program operation aborts for any reason, such as an attempt to erase or

program a protected region or a locked down sector or an attempt to erase or program a suspended sector. The

EPE bit is updated after every erase and program operation.

10.4.7 SLE Bit

The SLE bit indicates whether or not the Sector Lockdown command is enabled or disabled. If the SLE bit is a logic

1, then the Sector Lockdown command is still enabled and sectors can be locked down. If the SLE bit is a logic 0,

then the Sector Lockdown command has been disabled and no further sectors can be locked down.

10.4.8 PS2 Bit

The PS2 bit indicates if a program operation has been suspended while using Buffer 2. If the PS2 bit is a logic 1,

then a program operation has been suspended while Buffer 2 was being used, and any command attempts that

can modify the contents of Buffer 2 are ignored.

10.4.9 PS1 Bit

The PS1 bit indicates if a program operation has been suspended while using Buffer 1. If the PS1 bit is a logic 1,

then a program operation has been suspended while Buffer 1 was being used, and any command attempts that

can modify the contents of Buffer 1 are ignored.

10.4.10 The ES bit

The ES bit indicates whether or not an erase has been suspended. If the ES bit is a logic 1, then an erase

operation (page, block, sector, or chip) has been suspended.

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11

Deep Power-Down

During normal operation, the device is placed in the standby mode to consume less power as long as the CS pin

remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to

place the device into an even lower power consumption state called the Deep Power-Down mode.

When the device is in the Deep Power-Down mode, all commands including the Status Register Read command

are ignored with the exception of the Resume from Deep Power-Down command. Since all commands are ignored,

the mode can be used as an extra protection mechanism against program and erase operations.

Entering the Deep Power-Down mode is done by asserting the CS pin, clocking in the opcode B9h, and then

deasserting the CS pin. Any additional data clocked into the device after the opcode is ignored. When the CS pin is

deasserted, the device enters the Deep Power-Down mode within the maximum time of t_EDPD

.

The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on

an even byte boundary (multiples of eight bits); otherwise, the device aborts the operation and return to the

standby mode once the CS pin is deasserted. Also, the device defaults to the standby mode after a power cycle.

The Deep Power-Down command is ignored if an internally self-timed operation such as a program or erase cycle

is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has

been completed in order for the device to enter the Deep Power-Down mode.

CS

t_EDPD

0

1

2

3

4

5

6

7

SCK

SI

Opcode

1

MSB

0

1

0

1

High-impedance

Active Current

SO

I_CC

Standby Mode Current

Deep Power-Down Mode Current

Figure 11-1. Deep Power-Down Timing

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11.1 Resume from Deep Power-Down

In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-

Down command must be issued. The Resume from Deep Power-Down command is the only command that the

device recognizes while in the Deep Power-Down mode.

To resume from the Deep Power-Down mode, the CS pin must first be asserted and then the opcode ABh must be

clocked into the device. Any additional data clocked into the device after the opcode is ignored. When the CS pin is

deasserted, the device exits the Deep Power-Down mode and return to the standby mode within the maximum

time of t_RDPD. After the device has returned to the standby mode, normal command operations such as Continuous

Array Read can be resumed.

If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an

even byte boundary (multiples of eight bits), then the device aborts the operation and return to the Deep Power-

Down mode.

CS

t_RDPD

0

1

2

3

4

5

6

7

SCK

SI

Opcode

1

MSB

0

1

0

1

0

1

High-impedance

Active Current

SO

I_CC

Standby Mode Current

Deep Power-Down Mode Current

Figure 11-2. Resume from Deep Power-Down Timing

11.2 Ultra-Deep Power-Down

The Ultra-Deep Power-Down mode allows the device to consume far less power compared to the standby and

Deep Power-Down modes by shutting down additional internal circuitry. Since almost all active circuitry is

shutdown in this mode to conserve power, the contents of the SRAM buffers cannot be maintained. Therefore, any

data stored in the SRAM buffers is lost once the device enters the Ultra-Deep Power-Down mode.

When the device is in the Ultra-Deep Power-Down mode, all commands including the Status Register Read and

Resume from Deep Power-Down commands are ignored. Since all commands are ignored, the mode can be used

as an extra protection mechanism against program and erase operations.

Entering the Ultra-Deep Power-Down mode is done by asserting the CS pin, clocking in the opcode 79h, and then

deasserting the CS pin. Any additional data clocked into the device after the opcode is ignored. When the CS pin is

deasserted, the device enters the Ultra-Deep Power-Down mode within the maximum time of t_EUDPD

.

The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on

an even byte boundary (multiples of eight bits); otherwise, the device aborts the operation and return to the

standby mode once the CS pin is deasserted. Also, the device defaults to the standby mode after a power cycle.

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The Ultra-Deep Power-Down command is ignored if an internally self-timed operation such as a program or erase

cycle is in progress. The Ultra-Deep Power-Down command must be reissued after the internally self-timed

operation has been completed in order for the device to enter the Ultra-Deep Power-Down mode.

CS

t_EUDPD

0

1

2

3

4

5

6

7

SCK

SI

Opcode

0

MSB

1

0

1

High-impedance

Active Current

SO

I_CC

Standby Mode Current

Ultra-Deep Power-Down Mode Current

Figure 11-3. Ultra-Deep Power-Down Timing

11.3 Exit Ultra-Deep Power-Down

To exit from the Ultra-Deep Power-Down mode, the CS pin must be pulsed by asserting the CS pin, waiting the

minimum necessary t_CSLUtime, and then deasserting the CS pin again. To facilitate simple software development,

a dummy byte opcode can also be entered while the CS pin is being pulsed just as in a normal operation like the

Program Suspend operation; the dummy byte opcode is ignored by the device in this case. After the CS pin has

been deasserted, the device exits from the Ultra-Deep Power-Down mode and return to the standby mode within a

maximum time of t_XUDPD. If the CS pin is reasserted before the t_XUDPDtime has elapsed in an attempt to start a new

operation, then that operation is ignored and nothing is performed. The system must wait for the device to return to

the standby mode before normal command operations such as Continuous Array Read can be resumed.

Since the contents of the SRAM buffers cannot be maintained while in the Ultra-Deep Power-Down mode, the

SRAM buffers contains undefined data when the device returns to the standby mode.

CS

t

CSLU

t_XUDPD

High-impedance

SO

I_CC

Active Current

Standby Mode Current

Ultra-Deep Power-Down Mode Current

Figure 11-4. Exit Ultra-Deep Power-Down

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12 Buffer and Page Size Configuration

The memory array of DataFlash devices is actually larger than other Serial Flash devices in that extra user-

accessible bytes are provided in each page of the memory array. For the AT45DB161E, there are an extra 16

bytes of memory in each page for a total of an extra 64 kB (512 kbits) of user-accessible memory. Therefore, the

device density is actually 16.5 Mbits instead of 16 Mbits.

Some designers, however, might not want to take advantage of this extra memory and instead architect their

software to operate on a “power of 2” binary, logical addressing scheme. To allow this, the DataFlash can be

configured so that the buffer and page sizes are 512 bytes instead of the standard 528 bytes. Also, the

configuration of the buffer and page sizes is reversible and can be changed from 528 bytes to 512 bytes or from

512 bytes to 528 bytes. The configured setting is stored in an internal nonvolatile register so that the buffer and

page size configuration is not affected by power cycles. The nonvolatile register has a limit of 10,000

erase/program cycles; therefore, be careful not to switch between the size options more than 10,000 times.

Devices are initially shipped from Adesto with the buffer and page sizes set to 528 bytes. Devices can be ordered

from Adesto pre-configured for the “power of 2” binary size of 512 bytes. For details, see Section 28, Ordering

Information, on page 70.

To configure the device for “power of 2” binary page size (512 bytes), a four-byte opcode sequence of 3Dh, 2Ah,

80h, and A6h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the

CS pin must be deasserted to initiate the internally self-timed configuration process and nonvolatile register

program cycle. Programming of the nonvolatile register takes a time of t_EP, during which time the RDY/BUSY bit in

the Status Register indicates that the device is busy. The device does not need to be power cycled after the

configuration process and register program cycle in order for the buffer and page size to be configured to 512

bytes.

To configure the device for standard DataFlash page size (528 bytes), a four-byte opcode sequence of 3Dh, 2Ah,

80h, and A7h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the

CS pin must be deasserted to initial the internally self-timed configuration process and nonvolatile register program

cycle. Programming of the nonvolatile register takes a time of t_EP, during which time the RDY/BUSY bit in the

Status Register indicates that the device is busy. The device does not need to be power cycled after the

configuration process and register program cycle in order for the buffer and page size to be configured to 528

bytes.

Table 12-1. Buffer and Page Size Configuration Commands

Command

Byte 1

3Dh

Byte 2

2Ah

Byte 3

80h

Byte 4

A6h

“Power of 2” binary page size (512 bytes)

DataFlash page size (528 bytes)

3Dh

2Ah

80h

A7h

CS

SI

Opcode

Byte 4

3Dh

2Ah

80h

Each transition represents eight bits

Figure 12-1. Buffer and Page Size Configuration

AT45DB161E

DS-AT45DB161E–8782N–03-2021

40

13 Manufacturer and Device ID Read

Identification information can be read from the device to enable systems to electronically query and identify the

device while it is in the system. The identification method and the command opcode comply with the JEDEC

Standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory

Devices”. The type of information that can be read from the device includes the JEDEC-defined Manufacturer ID,

the vendor-specific Device ID, and the vendor-specific Extended Device Information.

The Read Manufacturer and Device ID command is limited to a maximum clock frequency of f_CLK. Since not all

Flash devices are capable of operating at very high clock frequencies, design applications to read the identification

information from the devices at a reasonably low clock frequency to ensure that all devices to be used in the

application can be identified properly. Once the identification process is complete, the application can then

increase the clock frequency to accommodate specific Flash devices that are capable of operating at the higher

clock frequencies.

To read the identification information, the CS pin must first be asserted and then the opcode 9Fh must be clocked

into the device. After the opcode has been clocked in, the device begins outputting the identification data on the

SO pin during the subsequent clock cycles. The first byte to be output is the Manufacturer ID, followed by two bytes

of the Device ID information. The fourth byte output is the Extended Device Information (EDI) String Length, which

is 01h indicating that one byte of EDI data follows. After the one byte of EDI data is output, the SO pin goes into a

high-impedance state; therefore, additional clock cycles have no affect on the SO pin and no data is output. As

indicated in the JEDEC Standard, reading the EDI String Length and any subsequent data is optional.

Deasserting the CS pin terminates the Manufacturer and Device ID Read operation and put the SO pin into a high-

impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

Table 13-1. Manufacturer and Device ID Information

Byte No.

Data Type

Value

1Fh

26h

00h

01h

00h

1

2

3

4

5

Manufacturer ID

Device ID (Byte 1)

Device ID (Byte 2)

Extended Device Information (EDI) String Length

[Optional to Read] Extended Device Information Byte 1

Table 13-2. Manufacturer and Device ID Details

Bit

7

Bit

6

Bit

5

Bit

4

Bit

3

Bit

2

Bit

1

Bit

0

Hex

Value

Data Type

Details

JEDEC Assigned Code

Manufacturer ID

1Fh

26h

00h

JEDEC code: 0001 1111 (1Fh for Adesto)

0

1

0

1

0

1

0

Family Code

Density Code

1

Family code: 001 (AT45Dxxx Family)

Density code: 00110 (16-Mbit)

Device ID (Byte 1)

Device ID (Byte 2)

0

Sub Code

0

1

Product Variant

Sub code:

000 (Standard Series)

Product variant:00000

0

AT45DB161E

DS-AT45DB161E–8782N–03-2021

41

Table 13-3. EDI Data

Bit

Hex

Valu

e

Bit

6

Bit

5

Bit

3

Bit

2

Bit

1

Bit

0

Byte Number

7

Bit 4

Details

RFU

0

Device Revision

RFU:

Reserved for Future Use

1

00h

Device revision:00000 (Initial Version)

0

CS

SCK

SI

0

6

7

8

14 15 16

22 23 24

30 31 32

38 39 40

46

Opcode

9Fh

High-impedance

1Fh

26h

00h

01h

EDI

00h

EDI

SO

Manufacturer ID

Device ID

Byte 1

Device ID

Byte 2

String Length

Data Byte 1

Note: Each transition

shown for SI and SO represents one byte (8 bits)

Figure 13-1. Read Manufacturer and Device ID Timing

AT45DB161E

DS-AT45DB161E–8782N–03-2021

42

14 Software Reset

In some applications, it might be necessary to prematurely terminate a program or erase cycle early rather than

wait the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete

normally. The Software Reset command allows a program or erase operation in progress to be ended abruptly and

returns the device to an idle state.

To perform a Software Reset, the CS pin must be asserted and a four-byte command sequence of F0h, 00h, 00h,

and 00h must be clocked into the device. Any additional data clocked into the device after the last byte is ignored.

When the CS pin is deasserted, the program or erase operation currently in progress is terminated within a time

t_SWRST. Since the program or erase operation might not complete before the device is reset, the contents of the

page being programmed or erased cannot be guaranteed to be valid.

The Software Reset command has no effect on the states of the Sector Protection Register, the Sector Lockdown

Register, or the buffer and page size configuration. The PS2, PS1, and ES bits of the Status Register, however,

are reset back to their default states. If a Software Reset operation is performed while a sector is erase suspended,

the suspend operation aborts and the contents of the page or block being erased in the suspended sector is left in

an undefined state. If a Software Reset is performed while a sector is program suspended, the suspend operation

aborts and the contents of the page that was being programmed and subsequently suspended is undefined. The

remaining pages in the sector retain their previous contents.

The complete four-byte opcode must be clocked into the device before the CS pin is deasserted, and the CS pin

must be deasserted on a byte boundary (multiples of eight bits); otherwise, no reset operation is performed.

Table 14-1. Software Reset

Command

Byte 1

Byte 2

Byte 3

Byte 4

Software Reset

F0h

00h

CS

SI

F0h

00h

Each transition represents eight bits

Figure 14-1. Software Reset

AT45DB161E

DS-AT45DB161E–8782N–03-2021

43

15 Operation Mode Summary

The commands described previously can be grouped into four different categories to better describe which

commands can be executed at what times.

Group A commands consist of:

1. Main Memory Page Read

2. Continuous Array Read (SPI)

3. Read Sector Protection Register

4. Read Sector Lockdown Register

5. Read Security Register

6. Buffer 1 (or 2) Read

Group B commands consist of:

1. Page Erase

2. Block Erase

3. Sector Erase

4. Chip Erase

5. Main Memory Page to Buffer 1 (or 2) Transfer

6. Main Memory Page to Buffer 1 (or 2) Compare

7. Buffer 1 (or 2) to Main Memory Page Program with Built-In Erase

8. Buffer 1 (or 2) to Main Memory Page Program without Built-In Erase

9. Main Memory Page Program through Buffer 1 (or 2) with Built-In Erase

10. Main Memory Byte/Page Program through Buffer 1 without Built-In Erase

11. Auto Page Rewrite

Group C commands consist of:

1. Buffer 1 (or 2) Write

2. Status Register Read

3. Manufacturer and Device ID Read

Group D commands consist of:

1. Erase Sector Protection Register

2. Program Sector Protection Register

3. Sector Lockdown

4. Program Security Register

5. Buffer and Page Size Configuration

6. Freeze Sector Lockdown

If a Group A command is in progress (not fully completed), then another command in Group A, B, C, or D must not

be started. However, during the internally self-timed portion of Group B commands, any command in Group C can

be executed. The Group B commands using Buffer 1 must use Group C commands with Buffer 2, and vice versa.

Finally, during the internally self-timed portion of a Group D command, execute only the Status Register Read

command.

Most of the commands in Group B can be suspended and resumed, except the Buffer Transfer, Buffer Compare,

and Auto Page Rewrite operations. If a Group B command is suspended, all of the Group A commands can be

executed. See Table 7-4 to determine which of the Group B, Group C, and Group D commands are allowed.

AT45DB161E

DS-AT45DB161E–8782N–03-2021

44

16 Command Tables

Table 16-1. Read Commands

Command

Opcode

D2h

01h

Main Memory Page Read

Continuous Array Read (Low-Power Mode)

Continuous Array Read (Low-Frequency)

Continuous Array Read (High-Frequency)

Continuous Array Read (Legacy Command – Not Recommended for New Designs)

Buffer 1 Read (Low-Frequency)

03h

0Bh

1Bh

E8h

D1h

D3h

D4h

D6h

Buffer 2 Read (Low-Frequency)

Buffer 1 Read (High-Frequency)

Buffer 2 Read (High-Frequency)

Table 16-2. Program and Erase Commands

Command

Opcode

Buffer 1 Write

84h

Buffer 2 Write

87h

Buffer 1 to Main Memory Page Program with Built-In Erase

Buffer 2 to Main Memory Page Program with Built-In Erase

Buffer 1 to Main Memory Page Program without Built-In Erase

Buffer 2 to Main Memory Page Program without Built-In Erase

Main Memory Page Program through Buffer 1 with Built-In Erase

Main Memory Page Program through Buffer 2 with Built-In Erase

Main Memory Byte/Page Program through Buffer 1 without Built-In Erase

Page Erase

83h

86h

88h

89h

82h

85h

02h

81h

Block Erase

50h

Sector Erase

7Ch

Chip Erase

C7h + 94h + 80h + 9Ah

Program/Erase Suspend

B0h

D0h

58h

59h

Program/Erase Resume

Read-Modify-Write through Buffer 1

Read-Modify-Write through Buffer 2

AT45DB161E

DS-AT45DB161E–8782N–03-2021

45

Table 16-3. Protection and Security Commands

Command

Opcode

3Dh + 2Ah + 7Fh + A9h

3Dh + 2Ah + 7Fh + 9Ah

3Dh + 2Ah + 7Fh + CFh

3Dh + 2Ah + 7Fh + FCh

32h

Enable Sector Protection

Disable Sector Protection

Erase Sector Protection Register

Program Sector Protection Register

Read Sector Protection Register

Sector Lockdown

3Dh + 2Ah + 7Fh + 30h

35h

Read Sector Lockdown Register

Freeze Sector Lockdown

Program Security Register

Read Security Register

34h + 55h + AAh + 40h

9Bh + 00h + 00h + 00h

77h

Table 16-4. Additional Commands

Command

Opcode

Main Memory Page to Buffer 1 Transfer

Main Memory Page to Buffer 2 Transfer

Main Memory Page to Buffer 1 Compare

Main Memory Page to Buffer 2 Compare

Auto Page Rewrite through Buffer 1

Auto Page Rewrite through Buffer 2

Deep Power-Down

53h

55h

60h

61h

58h

59h

B9h

Resume from Deep Power-Down

Ultra-Deep Power-Down

ABh

79h

Status Register Read

D7h

Manufacturer and Device ID Read

Configure “Power of 2” (Binary) Page Size

Configure Standard DataFlash Page Size

Software Reset

9Fh

3Dh + 2Ah + 80h + A6h

3Dh + 2Ah + 80h + A7h

F0h + 00h + 00h + 00h

AT45DB161E

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46

Table 16-5. Legacy Commands^(Note:)

Command

Opcode

54H

Buffer 1 Read

Buffer 2 Read

56H

Main Memory Page Read

Continuous Array Read

Status Register Read

52H

68H

57H

Note: Legacy commands are not recommended for new designs.

Table 16-6. Detailed Bit-level Addressing Sequence for Binary Page Size (512 bytes)

Page Size = 512 bytes

Address Byte

Added

Dummy

Bytes

Opcode

Hex

Opcode

Binary

N/A

1

01h

02h

03h

0Bh

1Bh

32h

35h

50h

53h

55h

58h ¹

59h ¹

59h ²

60h

61h

77h

79h

7Ch

81h

82h

83h

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

2

N/A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

AT45DB161E

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47

Table 16-6. Detailed Bit-level Addressing Sequence for Binary Page Size (512 bytes) (continued)

Page Size = 512 bytes Address Byte Address Byte Address Byte

Added

Dummy

Bytes

Opcode

Hex

Opcode

Binary

N/A

4

84h

85h

86h

87h

88h

89h

9Fh

B9h

ABh

B0h

D0h

D1h

D2h

D3h

D4h

D6h

D7h

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

N/A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

X

A

N/A

1

N/A

1.Shown to indicate when Auto Page Rewrite Operation is executed.

2. Shown to indicate when Read Modify Write Operation is executed.

Note:

X = Dummy Bit

Table 16-7. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (528 bytes)

Page Size = 528-bytes Address Byte Address Byte Address Byte

Added

Dummy

Bytes

Opcode

01h

02h

03h

0Bh

1Bh

32h

0

1

0

1

0

1

0

1

0

1

0

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

N/A

1

2

N/A

AT45DB161E

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48

Table 16-7. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (528 bytes) (continued)

Page Size = 528-bytes Address Byte Address Byte Address Byte

Added

Dummy

Bytes

Opcode

35h

50h

53h

55h

58 ¹

58h ¹

59h ¹

59h ²

60h

61h

77h

79h

7Ch

81h

82h

83h

84h

85h

86h

87h

88h

89h

9Fh

B9h

ABh

B0h

D0h

D1h

D2h

D3h

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

N/A

4

N/A

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

B

X

P

X

P

X

P

X

P

X

P

X

B

X

B

X

B

X

N/A

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

P

X

B

P

X

P

X

B

N/A

AT45DB161E

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49

Table 16-7. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (528 bytes) (continued)

Page Size = 528-bytes Address Byte Address Byte Address Byte

Added

Dummy

Bytes

Opcode

D4h

D6h

D7h

1

0

1

0

1

0

1

0

1

X

B

1

N/A

1. Shown to indicate when Auto Page Rewrite Operation is executed.

2. Shown to indicate when Read Modify Write Operation is executed.

Note:

P = Page Address bit; B = Byte/Buffer Address bit; X = Dummy bit.

AT45DB161E

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50

17 Power-On/Reset State

When power is first applied to the device, or when recovering from a reset condition, the device defaults to SPI

Mode 3. Also, the output pin (SO) is in a high impedance state, and a high-to-low transition on the CS pin is

required to start a valid instruction. The SPI mode (Mode 3 or Mode 0) is automatically selected on every falling

edge of CS by sampling the inactive clock state.

17.1 Initial Power-Up Timing Restrictions

As the device initializes, there is a transient current demand. The system needs to be capable of providing this

current to ensure correct initialization. During power-up, the device must not be accessed for at least the minimum

t_VCSLtime after the supply voltage reaches the minimum V_CClevel. While the device is being powered-up, the

internal Power-On Reset (POR) circuitry keeps the device in a reset mode until the supply voltage rises above the

maximum POR threshold value (V_POR). During this time, all operations are disabled and the device does not

respond to any commands. After power-up, the device is in the standby mode.

If the first operation to the device after power-up is a program or erase operation, then the operation cannot be

started until the supply voltage reaches the minimum V_CClevel and an internal device delay has elapsed. This

delay is a maximum time of t_PUW

.

Table 17-1. Power-Up Timing

Symbol

t_VCSL

Parameter

Min

Max

Units

µs

Minimum V_CCto Chip Select Low Time

70

t_PUW

Power-Up Device Delay Before Program or Erase Allowed

Power-On Reset (POR) Voltage

3

ms

V

V_POR

1.5

2.2

V

CC

Read Operation Permitted

V_CC(min)

V_POR(max)

V_POR(min)

t_VCSL

t_PUW

Do Not Attempt

Device Access

During this Time

Program/Erase Operations Permitted

Time

Figure 17-1. Power-Up Timing

AT45DB161E

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51

18 System Considerations

The serial interface is controlled by the Serial Clock (SCK), Serial Input (SI), and Chip Select (CS) pins. These

signals must rise and fall monotonically and be free from noise. Excessive noise or ringing on these pins can be

misinterpreted as multiple edges and cause improper operation of the device. PCB traces must be kept to a

minimum distance or appropriately terminated to ensure proper operation. If necessary, decoupling capacitors can

be added on these pins to provide filtering against noise glitches.

As system complexity continues to increase, voltage regulation is becoming more important. A key element of any

voltage regulation scheme is its current sourcing capability. Like all Flash memories, the peak current for

DataFlash devices occurs during the programming and erasing operations. The supply voltage regulator needs to

be able to supply this peak current requirement. An under specified regulator can cause current starvation. Besides

increasing system noise, current starvation during programming or erasing can lead to improper operation and

possible data corruption.

AT45DB161E

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52

19 Electrical Specifications

19.1 Absolute Maximum Ratings*

Notice: Stresses beyond those listed under “Absolute

Maximum Ratings” can cause permanent

Temperature under Bias . . . . . . . -55°C to +125°C

damage to the device. This is a stress rating only

and functional operation of the device at these or

any other conditions beyond those indicated in

the operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods can affect device

reliability. Voltage extremes referenced in the

“Absolute Maximum Ratings” are intended to

accommodate short duration

Storage Temperature. . . . . . . . . . -65°C to +150°C

Absolute Maximum V_cc. . . . . . . . . . . . . . . . 3.96 V

All Output Voltages with Respect to Ground

undershoot/overshoot conditions and does not

imply or guarantee functional device operation at

these levels for any extended period of time.

. . . . . . -0.6 V to 4.2 V (Max V_CCof 3.6 V + 0.6 V)

All Input Voltages with Respect to Ground

(excluding V_CCpin, including NC pins)

. . . . . . -0.6 V to 4.2 V (Max V_CCof 3.6 V + 0.6 V)

19.2 DC and AC Operating Range

ATx

2.3 V Version

2.5 V Version

Operating Temperature (Case)

V_CCPower Supply

Industrial

-40°C to 85°C

2.3 V to 3.6 V

2.5 V to 3.6 V

AT45DB161E

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19.3 DC Characteristics

Symbol Parameter

Condition

Min

Typ

Max

Units

Ultra-Deep Power-Down

Current

CS= V_CC. All other inputs at 0 V or

V_CC

I_UDPD

I_DPD

I_SB

0.4

1

µA

CS= V_CC. All other inputs at 0 V or

V_CC

Deep Power-Down Current

5

12

50

µA

CS= V_CC. All other inputs at 0 V or

V_CC

Standby Current

25

f = 1 MHz; I_OUT= 0 mA

f = 15 MHz; I_OUT= 0 mA

f = 50 MHz; I_OUT= 0 mA

f = 85 MHz; I_OUT= 0 mA

6

7

9

mA

Active Current, Low Power

Read (01h) Operation

I_CC1

11

17

22

12

16

Active Current,

Read Operation

(1)

I_CC2

Active Current,

Program Operation

I_CC3

CS=V_CC

12

18

mA

Active Current,

Erase Operation

I_CC4

I_LI

Input Load Current

All inputs at CMOS levels

1

µA

I_LO

Output Leakage Current

V_CC

0.3

x

V_IL

Input Low Voltage

V

V_CC

0.7

x

V_CC

0.6

+

V_IH

Input High Voltage

Output Low Voltage

Output High Voltage

V

V_OL

V_OH

I_OL= 100 µA

I_OH= -100 µA

0.4

V_CC

0.2V

-

Notes: 1. Typical values measured at 3.0 V at 25°C.

AT45DB161E

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19.4 AC Characteristics

ATx

2.3 V Version

2.5 V Version

Symbol

Parameter

Units

Min

Max

70

Min

Max

70

f_SCK

SCK Frequency

MHz

f_CAR1

SCK Frequency for Continuous Read (0x0B)

85

SCK Frequency for Continuous Read (0x03)

(Low Frequency)

f_CAR2

f_CAR3

f_CAR4

50

15

50

15

MHz

SCK Frequency for Continuous Read

(Low Power Mode – 01h Opcode)

SCK Frequency for Continuous Read

(0x1B)

104

t_WH

t_WL

SCK High Time

4

ns

SCK Low Time

1

t_SCKR

SCK Rise Time, Peak-to-peak

SCK Fall Time, Peak-to-peak

Minimum CS High Time

0.1

20

5

0.1

20

5

V/ns

ns

1

t_SCKF

t_CS

t_CSS

t_CSH

t_SU

t_H

CS Setup Time

ns

CS Hold Time

5

ns

Data In Setup Time

2

ns

Data In Hold Time

1

ns

t_HO

Output Hold Time

0

ns

1

t_DIS

Output Disable Time

6

7

6

7

ns

t_V

Output Valid

ns

t_WPE

t_WPD

t_LOCK

WP Low to Protection Enabled

WP High to Protection Disabled

Freeze Sector Lockdown Time (from CS High)

CS High to Ultra-Deep Power-Down

Minimum CS Low Time to Exit Ultra-Deep Power-Down

Exit Ultra-Deep Power-Down Time

CS High to Deep Power-Down

Resume from Deep Power-Down Time

Page to Buffer Transfer Time

Page to Buffer Compare Time

RESET Pulse Width

1

µs

ns

1

100

4

100

4

1

t_EUDPD

t_CSLU

20

t_XUDPD

180

2

180

2

µs

1

t_EDPD

t_RDPD

t_XFR

t_COMP

t_RST

35

200

10

t_REC

RESET Recovery Time

1

t_SWRST

Software Reset Time

35

1. Values are based on device characterization, not 100% tested in production.

AT45DB161E

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19.5 Program and Erase Characteristics

Symbol

t_EP

Parameter

Min

Typ

17

3

Max

25*

4

Units

ms

µs

Page Erase and Programming Time (512/528 bytes)

Page Programming Time

Byte Programming Time

Page Erase Time

t_P

t_BP

8

t_PE

12

45

1.4

22

10

20

10

20

200

35

100

2*

ms

s

t_BE

Block Erase Time

t_SE

Sector Erase Time

t_CE

Chip Erase Time

40

s

Program

15

t_SUSP

Suspend Time

µs

Erase

30

Program

Erase

15

t_RES

Resume Time

µs

30

t_OTPP

OTP Security Register Program Time

500

Notes: 1. Specification waiver for legacy inventory might apply.

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20 Input Test Waveforms and Measurement Levels

0.9V_CC

AC

Driving

Levels

V_CC/2

Measurement

Level

0.1V_CC

t_R, t_F< 2ns (10% to 90%)

21 Output Test Load

Device

Under

Test

30pF

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22 Using the RapidS Function

To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be

used to transmit data back and forth across the serial bus. The DataFlash is designed to always clock its data out

on the falling edge of the SCK signal and clock data in on the rising edge of SCK.

For full clock cycle operation to be achieved, when the DataFlash is clocking data out on the falling edge of SCK,

the host controller must wait until the next falling edge of SCK to latch the data in. Similarly, the host controller must

clock its data out on the rising edge of SCK in order to give the DataFlash a full clock cycle to latch the incoming

data in on the next rising edge of SCK.

Slave CS

1

8

1

8

1

2

3

4

5

6

7

2

3

4

5

6

7

SCK

MOSI

MISO

B

E

A

C

D

MSB

LSB

BYTE-MOSI

H

G

I

F

MSB

LSB

BYTE-SO

MOSI = Master Out, Slave In

MISO = Master In, Slave Out

The Master is the host controller and the Slave is the DataFlash.

The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.

The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.

A. Master clocks out first bit of BYTE-MOSI on the rising edge of SCK

B. Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK

C. Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK

D. Last bit of BYTE-MOSI is clocked out from the Master

E. Last bit of BYTE-MOSI is clocked into the slave

F. Slave clocks out first bit of BYTE-SO

G. Master clocks in first bit of BYTE-SO

H. Slave clocks out second bit of BYTE-SO

I. Master clocks in last bit of BYTE-SO

Figure 22-1. RapidS Mode Timing

SI (INPUT)

MSB

CMD

8-bits

X X X X X X X X X X X X X X X X

X X X X X X X X

LSB

3 Dummy Bits

Page Address

(A20 - A9)

Byte/Buffer Address

(A8 - A0/BFA8 - BFA0)

Figure 22-2. Command Sequence for Read/Write Operations for Page Size 512 bytes

(Except Status Register Read, Manufacturer and Device ID Read)

SI (INPUT)

MSB

CMD

8-bits

X X X X X X X X X X X X X X X X

X X X X X X X X

LSB

2

Page Address

(PA11 - PA0)

Byte/Buffer Address

(BA9 - BA0/BFA9 - BFA0)

Dummy Bits

Figure 22-3. Command Sequence for Read/Write Operations for Page Size 528 bytes

(Except Status Register Read, Manufacturer and Device ID Read)

AT45DB161E

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23 AC Waveforms

Four different timing waveforms are shown in Figure 23-1 through Figure 23-4. Waveform 1 shows the SCK signal

being low when CS makes a high-to-low transition and Waveform 2 shows the SCK signal being high when CS

makes a high-to-low transition. In both cases, output SO becomes valid while the SCK signal is still low (SCK low

time is specified as t_WL). Timing Waveforms 1 and 2 conform to RapidS serial interface but for frequencies up to 85

MHz. Waveforms 1 and 2 are compatible with SPI Mode 0 and SPI Mode 3, respectively.

Waveform 3 and 4 illustrate general timing diagram for RapidS serial interface. These are similar to Waveform 1

and 2, except that output SO is not restricted to become valid during the t_WLperiod. These timing waveforms are

valid over the full frequency range (maximum frequency = 85 MHz) of the RapidS serial case.

t_CS

CS

t_CSS

t_WH

t_WL

t_CSH

SCK

SO

SI

t_V

t_HO

t_DIS

High-impedance

t_SU

High-impedance

Valid Out

t_H

Valid In

Figure 23-1. Waveform 1 = SPI Mode 0 Compatible

t_CS

CS

SCK

SO

t_CSS

t_WL

t_WH

t_CSH

t_V

t_HO

t_DIS

High Z

High-impedance

Valid Out

t_H

t_SU

Valid In

SI

Figure 23-2. Waveform 2 = SPI Mode 3 Compatible

AT45DB161E

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t_CS

CS

SCK

SO

t_CSS

t_WH

t_WL

t_CSH

t_V

t_HO

t_DIS

High-impedance

t_SU

High-impedance

Valid Out

t_H

SI

Valid In

Figure 23-3. Waveform 3 = RapidS Mode 0

t_CS

CS

SCK

SO

t_CSS

t_WL

t_WH

t_CSH

t_V

t_HO

t_DIS

High Z

High-impedance

Valid Out

t_H

t_SU

Valid In

Figure 23-4. Waveform 4 = RapidS Mode 3

SI

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24 Write Operations

The following block diagram and waveforms illustrate the various write sequences available.

Flash Memory Array

Page (512/528 bytes)

Buffer 1 To

Main Memory

Page Program

Buffer 2 To

Main Memory

Page Program

Buffer 1 (512/528 bytes)

Buffer 2 (512/528 bytes)

Buffer 1

Write

Buffer 2

Write

I/O Interface

SI

Figure 24-1. Block Diagram

Completes Writing into Selected Buffer

CS

Binary Page Size

15 Dummy Bits + BFA8-BFA0

CMD

X

X···X, BFA9-8

BFA7-0

n

n + 1

Last Byte

SI (Input)

Figure 24-2. Buffer Write

Starts Self-timed Erase/Program Operation

CS

Binary Page Size

A20-A9 + 9 Dummy Bits

CMD

PA11-6

PA5-0, XX

XXXX XX

SI (Input)

n

= 1st byte read

Each transition represents eight bits

n+1 = 2nd byte read

Figure 24-3. Buffer to Main Memory Page Program

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25 Read Operations

The following block diagram and waveforms illustrate the various read sequences available.

Flash Memory Array

Page (512/528 bytes)

Main Memory

Page To

Main Memory

Page To

Buffer 2

Buffer 1

Buffer 1 (512/528 bytes)

Buffer 2 (512/528 bytes)

Buffer 1

Read

Main Memory

Page Read

Buffer 2

Read

I/O Interface

SO

Figure 25-1. Block Diagram

CS

Address for Binary Page Size

A20-A16

A15-A8

A7-A0

CMD

PA11-6

PA5-0, BA9-8

BA7-0

X

SI (Input)

4 Dummy Bytes

SO (Output)

n

n + 1

Figure 25-2. Main Memory Page Read

Starts Reading Page Data into Buffer

CS

Binary Page Size

A20-A9 + 9 Dummy Bits

CMD

PA11-6

PA5-0, XX

XXXX XX

SI (Input)

SO (Output)

Figure 25-3. Main Memory Page to Buffer Transfer

Data From the selected Flash Page is read into either SRAM Buffer

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CS

Address for Binary Page Size

A20-A16

A15-A8

A7-A0

CMD

X

X... X, BFA9-8

BFA7-0

X

SI (Input)

No Dummy Byte (opcodes D1H and D3H)

1 Dummy Byte (opcodes D4H and D6H)

SO (Output)

n

n + 1

Each transition represents eight bits

Figure 25-4. Buffer Read

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26 Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34

62 63 64 65 66 67 68 69 70 71 72

SCK

SI

Opcode

Address Bits

32 Dummy Bits

1

0

1

0

A

X

MSB

Data Byte 1

High-impedance

D

SO

MSB

Bit 0 of

Page n+1

Bit 4095/4223

of Page n

Figure 26-1. Continuous Array Read Timing (Legacy Opcode E8h)

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Opcode

Address Bits A20 - A0

Dummy Bits

X

0

1

0

1

A

X

MSB

Data Byte 1

High-impedance

D

SO

MSB

Figure 26-2. Continuous Array Read Timing (Opcode 0Bh)

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40

Opcode

Address Bits A20-A0

0

1

A

MSB

Data Byte 1

High-impedance

D

SO

MSB

Figure 26-3. Continuous Array Read Timing (Opcode 01h or 03h)

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CS

SCK

SI

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34

62 63 64 65 66 67 68 69 70 71 72

Opcode

Address Bits

32 Dummy Bits

1

0

1

0

1

0

A

X

MSB

Data Byte 1

High-impedance

D

SO

MSB

Figure 26-4. Main Memory Page Read Timing (Opcode D2h)

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

SCK

Address Bits

Binary Page Size = 15 Dummy Bits + BFA8-BFA0

Standard DataFlash Page Size =

14 Dummy Bits + BFA9-BFA0

Dummy Bits

Opcode

1

0

1

0

1

0

X

A

X

SI

MSB

Data Byte 1

High-impedance

D

SO

MSB

Figure 26-5. Buffer Read Timing (Opcode D4h or D6h)

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40

SCK

Address Bits

Binary Page Size = 15 Dummy Bits + BFA8-BFA0

Standard DataFlash Page Size =

Opcode

14 Dummy Bits + BA9-BFA0

1

0

1

0

1

X

A

SI

MSB

Data Byte 1

High-impedance

D

SO

MSB

Figure 26-6. Buffer Read – Low Frequency Timing (Opcode D1h or D3h)

AT45DB161E

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CS

SCK

SI

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40

Opcode

Dummy Bits

0

1

0

1

0

X

MSB

Data Byte 1

High-impedance

D

SO

MSB

Figure 26-7. Read Sector Protection Register Timing (Opcode 32h)

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40

Opcode

Dummy Bits

0

1

0

1

0

1

X

MSB

Data Byte 1

High-impedance

D

SO

MSB

Figure 26-8. Read Sector Lockdown Register Timing (Opcode 35h)

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40

Opcode

Dummy Bits

0

1

0

1

X

MSB

Data Byte 1

High-impedance

D

SO

MSB

Figure 26-9. Read Security Register Timing (Opcode 77h)

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CS

SCK

SI

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Opcode

1

0

1

0

1

MSB

Status Register Data

High-impedance

D

SO

MSB

Figure 26-10. Status Register Read Timing (Opcode D7h)

CS

SCK

SI

0

6

7

8

14 15 16

22 23 24

30 31 32

38 39 40

46

Opcode

9Fh

High-impedance

1Fh

26h

00h

01h

EDI

00h

EDI

SO

Manufacturer ID

Device ID

Byte 1

Device ID

Byte 2

String Length

Data Byte 1

Note: Each transition

shown for SI and SO represents one byte (8 bits)

Figure 26-11. Manufacturer and Device Read Timing (Opcode 9Fh)

CS

t

CSS

REC

SCK

RESET

t

RST

High Impedance

SO (Output)

SI (Input)

Figure 26-12. Reset Timing

Note: The CS signal must be in the high state before the RESET signal is deasserted.

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27 Auto Page Rewrite Flowchart

27.1 Entire Array Sequentially

START

Provide Address

and Data

Buffer Write

(84h, 87h)

Main Memory Page Program

through Buffer

(82h, 85h)

Buffer To Main

Memory Page Program

(83h, 86h)

END

Figure 27-1. Algorithm for Programming or Re-programming of the Entire Array Sequentially

Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the

array page-by-page

2. A page can be written using either a Main Memory Page Program operation or a buffer write operation

followed by a buffer to Main Memory Page Program operation

3. The algorithm above shows the programming of a single page. The algorithm is repeated sequentially for

each page within the entire array

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27.2 Entire Array Randomly

START

Provide Address of

Page to Modify

Main Memory Page

If planning to modify multiple

bytes currently stored within

a page of the Flash array

to Buffer Transfer

(53h, 55h)

Buffer Write

(84h, 87h)

Main Memory Page Program

through Buffer

(82h, 85h)

Buffer to Main

Memory Page Program

(83h, 86h)

(2)

Auto Page Rewrite

(58h, 59h)

Increment Page

(2)

Address Pointer

END

Figure 27-2. Algorithm for Programming or Re-programming of the Entire Array Randomly

Notes: 1. To preserve data integrity, each page of an DataFlash sector must be updated/rewritten at least once within

every 50,000 cumulative page erase and program operations.

2. A page address pointer must be maintained to indicate which page is to be rewritten. The auto page rewrite

command must use the address specified by the page address pointer.

3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications can choose to

wait until 50,000 cumulative page erase and program operations have accumulated before rewriting all

pages of the sector.

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28 Ordering Information

28.1 Ordering Detail

A T 4 5 D B 1 6 1 E - S S H D 2 B - B

Designator

Shipping Carrier Option

B = Bulk (tubes)

T = Tape and reel

Y = Trays

Product Family

45DB = DataFlash

Page Size Option

“ ” = Standard (528 bytes/page)

2B = Binary (512 bytes/page)

Device Density

16 = 16 Mbit

Operating Voltage

Interface

1 = Serial

D = 2.5 V minimum (2.5 V to 3.6 V)

F = 2.3 V minimum (2.3 V to 3.6 V)

Device Grade

Device Revision

H = Green, NiPdAu lead finish,

Industrial temperature range

(–40°C to +85°C)

U = Green, Matte Sn or Sn alloy,

Industrial temperature range

(–40°C to +85°C)

Package Option

SS = 8-lead,0.150” wide SOIC

S

= 8-lead,0.208” wide SOIC

M = 8-pad, 5 x 6 x 0.6 mm UDFN

CC = 9-ball, 3 x 3 (1 mm pitch) UBGA

U

= 11-ball WLCSP

DWF = Die in Wafer Form

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28.2 Ordering Codes (Standard Page Size)

Ordering Code

Package

Lead Finish

Operating Voltage

f_SCK

Device Grade

AT45DB161E-SSHD-B ¹

AT45DB161E-SSHD-T ¹

AT45DB161E-SHD-B ¹

AT45DB161E-SHD-T ¹

AT45DB161E-MHD-Y ¹

AT45DB161E-MHD-T ¹

8S1

Industrial

8S2

NiPdAu

2.5 V to 3.6 V

85 MHz

(-40°C to 85°C)

8 MA1

AT45DB161E-SSHF-B ¹

AT45DB161E-SSHF-T ¹

AT45DB161E-SHF-B ¹

AT45DB161E-SHF-T ¹

AT45DB161E-MHF-Y ¹

AT45DB161E-MHF-T ¹

AT45DB161E-UUF-T ^1,3

AT45DB161E-DWF ²

8S1

8S2

NiPdAu

Industrial

2.3 V to 3.6 V

85 MHz

(-40°C to 85°C)

8 MA1

CS16-11A

DWF

1. The shipping carrier suffix is not marked on the device.

2. Contact Dialog Semiconductor for mechanical drawing or Die Sales information.

3. Contact Dialog Semiconductor for manufacturing flow and availability.

Package Type

8S1

8-lead 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8-lead 0.208" wide, Plastic Gull Wing Small Outline (EIAJ SOIC)

8S2

8 MA1

CS16-11A

DWF

8-pad (5 x 6 x 0.6 mm body), Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead (UDFN)

11-ball, Wafer Level Chip Scale Package

Die in Wafer Form

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28.3 Ordering Codes (Binary Page Size)

Ordering Code

Package

8S1

Lead Finish

Operating Voltage

f_SCK

Device Grade

AT45DB161E-SSHD2B-T ^1,2

AT45DB161E-SHD2B-T ^1,2

AT45DB161E-MHD2B-T ^1,2

AT45DB161E-SSHF2B-T ¹

AT45DB161E-SHF2B-T ¹

AT45DB161E-MHF2B-T ¹

AT45DB161E-UUF2B-T ^1,3

Industrial

8S2

NiPdAu

2.5 V to 3.6 V

85 MHz

(-40°C to 85°C)

8 MA1

8S1

Industrial

8S2

NiPdAu

SnAgCu

2.3 V to 3.6 V

85 MHz

(-40°C to 85°C)

8MA1

CS16-11A

1. The shipping carrier suffix is not marked on the device.

2. Not recommended for new design. Use the F (2.3 V - 3.6 V) voltage option.

3. Contact Dialog Semiconductor for manufacturing flow and availability.

Package Type

8-lead 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8-lead 0.208" wide, Plastic Gull Wing Small Outline (EIAJ SOIC)

8S1

8S2

8MA1

CS16-11A

8-pad (5 x 6 x 0.6 mm body), Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead (UDFN)

11-ball, Wafer Level Chip Scale Package

28.4 Ordering Codes (Reserved)

Ordering Code

Package

Lead Finish

Operating Voltage

f_SCK

Device Grade

AT45DB161E-SSHFHA-T ^1,2

AT45DB161E-SHFHA-T ^1,2

AT45DB161E-SSHFHC-T ^1,3

AT45DB161E-SHFHC-T ^1,3

8S1

8S2

8S1

8S2

Industrial

NiPdAu

2.3 V to 3.6 V

85 MHz

(-40°C to 85°C)

Notes: 1. The shipping carrier suffix is not marked on the device.

2. Parts ordered with suffix code ‘HA’ are shipped in tape and reel (T&R) only with the page size set to

528 bytes.

3. Parts ordered with suffix code ‘HC’ are shipped in tape and reel (T&R) only with the page size set to

512 bytes.

Package Type

8S1

8S2

8-lead 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8-lead 0.208" wide, Plastic Gull Wing Small Outline (EIAJ SOIC)

AT45DB161E

DS-AT45DB161E–8782N–03-2021

72

29 Packaging Information

29.1 8S1 – 8-lead JEDEC SOIC

C

1

E

E1

L

N

Ø

TOP VIEW

END VIEW

e

b

COMMON DIMENSIONS

(Unit of Measure = mm)

A

MIN

1.35

0.10

MAX

1.75

0.25

NOM

–

NOTE

SYMBOL

A1

A

A1

b

0.31

0.17

4.80

3.81

5.79

–

0.51

0.25

5.05

3.99

6.20

C

D

E1

E

e

–

D

–

SIDE VIEW

Notes: This drawing is for general information only.

Refer to JEDEC Drawing MS-012, Variation AA

for proper dimensions, tolerances, datums, etc.

1.27 BSC

L

0.40

0°

–

1.27

8°

Ø

6/22/11

DRAWING NO. REV.

TITLE

GPC

8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC)

SWB

8S1

G

AT45DB161E

DS-AT45DB161E–8782N–03-2021

73

29.2 8S2 – 8-lead EIAJ SOIC

C

1

E

E11

L

N

θ

TOOPP VVIEW

END VIEEWW

e

b

COMMON DIMENSIONS

(Unit of Measure = mm)

A

MIN

1.70

0.05

0.35

0.15

5.13

5.18

7.70

0.51

0°

MAX

2.16

0.25

0.48

0.35

5.35

5.40

8.26

0.85

8°

NOM

NOTE

SYMBOL

A11

A

A1

b

4

C

D

E1

E

D

2

L

SIDE VVIIEEWW

θ

e

1.27 BSC

3

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs aren't included.

3. Determines the true geometric position.

4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.

4/15/08

DRAWING NO.

REV.

GPC

TITLE

8S2, 8-lead, 0.208” Body, Plastic Small

Outline Package (EIAJ)

STN

8S2

F

AT45DB161E

DS-AT45DB161E–8782N–03-2021

74

29.3 8MA1 – 8-pad UDFN

E

C

Pin 1 ID

SIDE VIEW

D

y

TOP VIEW

A1

A

K

E2

Option A

0.45

Pin #1

8

1

2

3

Pin #1 Notch

(0.20 R)

(Option B)

Chamfer

(C 0.35)

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

MAX

NOM

NOTE

SYMBOL

7

A

0.45

0.55

0.60

e

D2

A1

b

0.00

0.35

0.02

0.40

0.152 REF

5.00

4.00

6.00

3.40

1.27

0.60

–

0.05

0.48

6

C

D

D2

E

4.90

3.80

5.90

3.20

5.10

4.20

6.10

3.60

5

4

b

BOTTOM VIEW

L

E2

e

L

0.50

0.00

0.20

0.75

0.08

–

y

K

–

4/15/08

GPC

YFG

DRAWING NO.

TITLE

REV.

8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally

Enhanced Plastic Ultra Thin Dual Flat No Lead

Package (UDFN)

8MA1

D

AT45DB161E

DS-AT45DB161E–8782N–03-2021

75

29.4 CS16-11A – 11-ball WLCSP

TOP VIEW

SIDE VIEW

BOTTOM VIEW

COMMON DIMENSIONS

(Unit of Measure = mm)

Pin Assignment Matrix

A

B

C

D

E

F

NC

1

2

SCK

GND

RESET

V_CC

SI

CS

WP

SO

3

4

NC

12/22/15

TITLE

GPC

DRAWING NO.

REV.

CS16-11A, 11-ball, Wafer Level Chip Scale

Package (WLCSP)

YFG

CS16-11A

A

AT45DB161E

DS-AT45DB161E–8782N–03-2021

76

30 Revision History

Doc. Rev.

Date

03/2012 Initial document release.

Update “Enable Sector Protection”, “Disable Sector Protection”, “Erase Sector Protection

Comments

8782A

Register”, “Program Sector Protection Register”, and “Read Sector Lockdown Register” figures.

Correct descriptions for PAGE SIZE, bit 0 in “Status Register Format – Byte 1” table.

Insert 1Bh opcode in “Detailed Bit-level Addressing Sequence for Binary Page Size (512 bytes)”

and “Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size

(528 bytes)” tables.

DC Characteristics:



Add I_CC1condition of f = 20 MHz; I_OUT= 0 mA; V_CC= 3.6 V with typical 7.5 mA and

maximum 10 mA.

Add I_CC4– Active Current, Erase Operation, V_CC= 3.6 V, typical 14 mA and maximum

20 mA.

Update I_ZPto I_UDPD– decrease typical from 0.5 µA to 0.4 µA and maximum from 2 µA to

1 µA.



Update I_DPto I_DPDand I_SPto I_SB.

Update I_CC0to I_CC1– decrease typical 7 mA to 6.5 mA.

Update I_CC1to I_CC2– 33 MHz, increase maximum from 17 mA to 19 mA;

50 MHz, decrease maximum from 20 mA to 19 mA; and at

85 MHz, increase typical 14 mA to 16 mA and maximum 23 mA to 26 mA.

Update I_CC2to I_CC3– remove erase operation, decrease typical from 15 mA to 12 mA and

maximum from 20 mA to 18 mA.



AC Characteristics:

8782B

06/2012



Remove typical columns, t_SECP, and t_SECUP

.

f_CAR3– increase 2.3 V/2.5 V maximum 10 MHz to 20 MHz.

t_WH– decrease 2.3 V minimum from 6.8 ns to 6.4 ns and 2.5 V minimum from 6.8 ns to 5.2

ns.



t_WL– decrease 2.3 V minimum from 6.8 ns to 6.4 ns and 2.5 V minimum from 6.8 ns to 5.2

ns.



t_CS– decrease 2.3 V/2.5 V minimum from 50 ns to 30 ns.

t_H– decrease 2.3 V/2.5 V minimum from 3 ns to 1 ns.

t_DIS– decrease 2.3 V maximum from 35 ns to 7 ns and 2.5 V from 35 ns to 6 ns.

t_V– decrease 2.3 V maximum from 8 ns to 7 ns.

t_COMP– decrease 2.3 V/2.5 V maximum from 250 µs to 220 µs.

Program and Erase Characteristics:



Remove 2.3 V minimum, typical, and maximum columns.

t_EP– decrease typical from 17 ms to 15 ms and maximum from 50 ms to 40 ms.

t_PE– decrease typical from 15 ms to 12 ms and maximum from 50 ms to 35 ms.

t_SE– decrease typical from 1.6 s to 1.4 s and maximum from 5 s to 3.5 s.

t_CE– decrease typical from 25 s to 22 s and maximum from 60 s to 40 s.

Update ordering code detail.

Replace package option from 9C1-CBGA to 9CC1-UBGA.

Various topographical edits throughout document.

Update template.

Updated preliminary to complete datasheet status.

Corrected pinout drawings to state top view.

8782C

07/2012

Increased t_XUDPDmaximum from 70 µs to 120 µs.

Updated ordering detail to add 2B equals factory set 512 byte binary page size option.

AT45DB161E

DS-AT45DB161E–8782N–03-2021

77

Doc. Rev.

Date

Comments

Added Legacy Commands table.

Updated to Adesto logos.

8782D

11/2012

Updated electrical and power specifications. Additional 2.3 V package options. “Buffer 1 (or 2)

Read” moved from Group C to Group A in Operation Mode Summary.

8782E

8782F

6/2013

7/2013

Updated Auto Page Rewrite cycle to 50,000 cumulative page erase/program operations. Added

reserved part order codes.Updated DC conditions for V_OL,I_CC3and I_CC4.F voltage option (2.3 V -

3.6 V) recommended for new designs.

Updated spec in Continuous Array Read (1Bh Opcode) to f_CAR4. Corrected Low Power Read

8782G

8782H

8782I

10/2013 Option (up to 15 MHz). Corrected Ultra-Deep Power-Down current (400 nA typical). Updated spec

for Input High Voltage (Max) to V_CC+ 0.6 V.

Added Die in Wafer Form package option. Added explanation of Read-Modify-Write command

(Section 6.6). Updated Table 6-4 (Main Memory to Buffer Compare). Added information on Power

Up (Section 16.1). Added footnotes to Tables 15-6 and 15-7. Updated Tables 12-1 and 12-3.

7/2015

Updated condition description for I_UDPD, I_DPD, and I_SB.

Added WLCSP package option.Updated Condition description for I_DPD, I_SB,I_{cc1 and}I_cc2

.

3/2016

Added footnote to I_cc1, t_DIS, t_EUDPD, t_EPD. Removed footnote 2 on Table 18.3. Removed footnotes

from Table 18.5.

8782J

8782K

1/2017

7/2017

Added patent information.

Added clarification of Absolute Maximum Ratings. Corrected Active Read and Standby specs on

Features page. Added footnote and updated WLCSP references.

8782L

8782M

2/2019

7/2020

Removed 9CC, 9-ball UBGA package option.

Updated format and layout. Copy edited throughout (no change to technical content).

In Table 28.2, removed original notes 2 and 3, and updated notes 4 and 5.

In Table 28.3, removed original notes 2 and 3, and updated note 5.

8782N

3/2/21

AT45DB161E

DS-AT45DB161E–8782N–03-2021

78

Corporate Office

California | USA

Adesto Headquarters

3600 Peterson Way

Santa Clara, CA 95054

Phone: (+1) 408.400.0578

Adesto, the Adesto logo, CBRAM and DataFlash are trademarks or registered trademarks of Adesto Technologies Corporation in the United States and other countries. Other company, product, and service

names may be trademarks or service marks of others. Adesto products are covered by one or more patents listed at http://www.adestotech.com/patents.

Disclaimer: Adesto Technologies Corporation (“Adesto”) makes no warranties of any kind, other than those expressly set forth in Adesto’s Terms and Conditions of Sale at

http://www.adestotech.com/terms-conditions. Adesto assumes no responsibility or obligations for any errors which may appear in this document, reserves the right to change devices or specifications

herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by Adesto

herewith or in connection with the sale of Adesto products, expressly or by implication. Adesto’s products are not authorized for use in medical applications (including, but not limited to, life support systems

and other medical equipment), weapons, military use, avionics, satellites, nuclear applications, or other high risk applications (e.g., applications that, if they fail, can be reasonably expected to result in

personal injury or death) or automotive applications, without the express prior written consent of Adesto.


型号：	AT45DB161E-SHF2B-T
厂家：	Dialog Semiconductor
描述：	16-Mbit DataFlash (with Extra 512-kbits) 2.3 V or 2.5 V Minimum SPI Serial Flash Memory 时钟光电二极管内存集成电路
文件：	总80页 (文件大小：1368K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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