CCE45035VLDO_技术文档

CCE4503

IO-Link Device IC

PLEASE NOTE: This Datasheet is preliminary. Please note the available Errata sheet at

www.dialog-semiconductor.com/products/cce4503

General Description

The CCE4503 is an easy-to-use device side IO-Link compliant transceiver. It combines IO-Link

compliant communication capability with advanced protection circuitry and additional features while

keeping the application small and simple. Controlled by an UART interface (TXD, RXD, TXEN), the

output drivers can be configured as PNP, NPN or Push-Pull. Three LDO options and an automatic

wake-up detection simplify the overall system requirements and reduce the need for additional

external circuitry. The integrated protection features such as reverse-polarity protection, overcurrent

protection, undervoltage detection and thermal protection ensure a robust functionality and

communication. With the small 3mm x 3mm DFN10 package size, it is especially suitable for space

limited sensor and actuator applications.

Key Features

■

IO-Link Compliant Transceiver

■

Small DFN 10-pin package

One IO-Link channel with up to 250 mA

permanent driving current

3 LDO Options with up to 20 mA

□

3.3V LDO output

5V LDO output

External LDO

□

350 mA peak (typ.)

■

Configurable PNP-, NPN- and

Push-Pull mode

■

Reverse-polarity protection

Overcurrent detection

■

Configurable current limit

Configurable slew rate limitation for optimized

EMC

Undervoltage detection

Overtemperature detection

■

Wake-up detection

Applications

■

IO-Link Sensors

IO-Link Actuators

■

High voltage level shifter

Industrial automation

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IO-Link Device IC

System Diagram

Figure 1: System Diagram

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IO-Link Device IC

Contents

General Description ............................................................................................................................ 1

Key Features ........................................................................................................................................ 1

Applications ......................................................................................................................................... 1

System Diagram .................................................................................................................................. 2

Contents ............................................................................................................................................... 3

Figures.................................................................................................................................................. 4

Tables ................................................................................................................................................... 4

1

2

3

Block Diagram ............................................................................................................................... 5

Pinout ............................................................................................................................................. 6

Characteristics .............................................................................................................................. 7

3.1 Absolute Maximum Ratings .................................................................................................. 7

3.2 Recommended Operating Conditions................................................................................... 8

3.3 Electrical Characteristics....................................................................................................... 8

3.4 Thermal Characteristics ...................................................................................................... 10

4

Functional Description ............................................................................................................... 11

4.1 Output stage........................................................................................................................ 11

4.2 Current limit and slew rate configuration............................................................................. 12

4.3 Automatic Recovery............................................................................................................ 12

4.4 Wake-up detection .............................................................................................................. 12

4.5 Error output handling........................................................................................................... 13

4.6 Overtemperature detection ................................................................................................. 13

4.7 Allowed Reverse polarity connections ................................................................................ 13

5

Package Information................................................................................................................... 14

5.1 Package Outlines................................................................................................................ 14

5.2 Soldering Information.......................................................................................................... 14

6

7

Ordering Information .................................................................................................................. 15

Application Information.............................................................................................................. 15

Revision History ................................................................................................................................ 16

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Figures

Figure 1: System Diagram..................................................................................................................... 2

Figure 2: Block Diagram........................................................................................................................ 5

Figure 3: DFN10 Pinout Diagram (Top View)........................................................................................ 6

Figure 4: Automatic recovery............................................................................................................... 12

Figure 5: DFN10 Package Outline Drawing ........................................................................................ 14

Figure 6: CCE4503 application ........................................................................................................... 15

Tables

Table 1: Pin Description ........................................................................................................................ 6

Table 2: Pin Type Definition .................................................................................................................. 7

Table 3: Absolute Maximum Ratings..................................................................................................... 7

Table 4: Recommended Operating Conditions ..................................................................................... 8

Table 5: Input / Output CQ .................................................................................................................... 8

Table 6: Digital I/O................................................................................................................................. 9

Table 7: 3.3V / 5V Voltage Regulator.................................................................................................. 10

Table 8: Thermal characteristics ......................................................................................................... 10

Table 9: Output stage truth table......................................................................................................... 11

Table 10: Current limit and slew rate configuration............................................................................. 12

Table 11: Ordering Information ........................................................................................................... 15

Datasheet

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1

Block Diagram

CCE4503

VDD

LDO

3.3V / 5V

Protection

/over temp

L+

NERR

/over current

/under voltage

On Chip

Oscillator

&

Protection

HV-Driver

CQ

NWUP

&

Diagnostics

Logic Core

TXEN

TXD

Protection

L-

ILIM

RXD

I/O-Link RX

Figure 2: Block Diagram

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2

Pinout

Thermal

Pad

igure 3: DFN10 Pinout Diagram (Top View)

Table 1: Pin Description

Pin No. Pin Name

Type

Reset

Description

(Table 2) State

1

2

VDD

PWR

3.3V - 5V Supply Voltage Input / Output

NERR

OD

High-Z

Error Output (Overcurrent detection, Undervoltage

detection, Overtemperature detection

3

RXD

DO

Channel signal output

4

TXD

DI, PU

DI, PD

AI

Channel signal input

5

TXEN

ILIM

Channel driver enable

6

Current Limit configuration

Ground supply (IO-Link)

7

L-

PWR

DIO

8

CQ

IO-Link data

9

L+

PWR

OD

Positive supply (IO-Link)

Wake-up detection (Channel short detection)

Thermal Pad, connect to VSS or leave open

10

PAD

NWUP

Thermal Pad

High-Z

GND

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Table 2: Pin Type Definition

Pin Type

DI

Description

Pin Type

AI

Description

Digital input

Analog input

DO

Digital output

AO

Analog output

DIO

OD

Digital input/output

Digital Output open drain

Pull-up resistor (fixed)

Pull-down resistor (fixed)

Power

AIO

Analog input/output

Back drive protection

Switchable pull-up resistor

Switchable pull-down resistor

Ground

BP

PU

SPU

SPD

GND

PD

PWR

3

Characteristics

3.1 Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to

the device. These are stress ratings only, so functional operation of the device at these or any other

conditions beyond those indicated in the operational sections of the specification are not implied.

Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

Table 3: Absolute Maximum Ratings

Parameter

Conditions

Name

Min

-40

-42

-40

Max

40

Unit

V

Supply Voltage

Static, referenced to V_L-

Dynamic (t ≤ 100 µs)

Ambient temperature

V_L+- V_L-

V_L+- V_{L-_pulse}

T_amb

42

V

Operating

+125

°C

Temperature

Storage

Temperature

T_storage

T_j

-55

-40

V_L-

+175

+150

V_L+

°C

V

Junction

Temperature

Voltage at pin CQ

Referenced to V_L-:V_CQ- V_L-

V_CQ,max

Voltage at all other Referenced to V_L-

pins

V_IOmax

-0.7

V_DD+ 0.7

V

ESD protection

JS-001-2012 HBM

JEDEC JESD78D Class1

12 s max.

V_ESD

4

kV

mA

°C

I_latchup

T_solder

Tbd

Soldering

Temperature

Tbd

6

Logic Level Supply

Voltage

VDD_max

I_OutMax

V

Output current

At pin RXD, NWUP, NERR

-5

5

mA

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3.2 Recommended Operating Conditions

Table 4: Recommended Operating Conditions

Parameter

Conditions

7, 9

9

Name

V_L+

Min

Typ

Max

36

1

Unit

V

Main Supply Voltage

Supply Voltage Ripple

7

F_ripple= DC … 100kHz

∆V_L+

V

V_L+> 12 V

Voltage CQ

Receiver mode

External Supply

8

1

V_{CQ_MAX}

VDD

V_L-

3

V_L+

5.5

V

Logic Level Supply

Voltage

LDO Output Current

3.3V LDO or 5V LDO,

1

I_VDD

20

mA

V_L+≤ 24V

ILIM External Resistor

To L-

6

1

R_ILIM

C_LDO

0

100

1.2

kΩ

LDO External

Capacitor

0.8

1

µF

3.3 Electrical Characteristics

Table 5: Input / Output CQ

Parameter

Conditions

Name

Min

Typ

Max

Unit

Output voltage low

level

active pull down,

I_OL=-200mA

8

V_OL

0

1.5

V

Output voltage high

level

active pull up,

I_OH=+200mA

8

V_OH

I_leak

V_L+

1.5

-

V_L+

2

V

Leakage current

input enabled

-2

µA

0 ≤ V_CQ≤ V_L+- 0.1 V

Maximum Permanent

Output Current

Current of CQ

channel

8

I_CQmax

I_limP

-250

250

mA

Output source current

limit

R_ILIM= 0 or hZ

300

35

350

50

400

70

R_ILIM= 100 kΩ

Output sink current

limit

R_ILIM= 0 or hZ

8

I_limN

-400

-70

-350

-50

-300

-35

mA

R_ILIM= 100 kΩ

Load capacitance

Inductive load

8

C_L

5

nF

H

L_Load

t_r,f

1.5

869

Output rise/fall time

(20% to 80%)

Open load, R_ILIM= 0

or hZ

ns

Switch On Time

Switch Off Time

8

t_{DLY_LH}

t_{DLY_HL}

T_SHORT

4

µs

Short circuit detection

time

300

Short circuit disable

time

RILIM ≠ hZ

8

T_{SHORT_DIS}

15

ms

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Parameter

Conditions

Name

T_WAKE

Min

Typ

Max

Unit

Wake-up detection

time

8

40

80

100

µs

Input threshold high

level

8

V_IH

10.5

8

11.75

13

V

Input threshold low

level

8

V_IL

9.75

2

11.5

V

Hysteresis between

input thresholds high

and low

V_Hyst

Table 6: Digital I/O

Parameter

Conditions

Name

Min

Typ

Max

1

Unit

Input

Input Voltage LOW

Input Voltage HIGH

Input Voltage LOW

Input Voltage HIGH

Input Pull-Up current

VDD = 3.3 V

VDD = 5.0 V

4, 5

V_{IN_L_3V3}

V_{IN_H_3V3}

V_{IN_L_5V}

V_{IN_H_5V}

I_{PU_5V}

V

2.3

4, 5

1.5

V

3.5

3

V

VDD - VSS = 5.0 V,

V_pin=0V

30

110

-3

µA

4, 5

Input Pull-Down

current

VDD - VSS = 5.0 V,

V_pin=5.0V

I_{PD_5V}

-110

-30

µA

Output

2, 3, 10

Output Voltage LOW

VDD - VSS = 3.3 V

I_{OUT_LOW}= 2 mA

V_{OUT_L}

V_{OUT_H}

0.7

0.8

V

2, 3, 10

VDD - VSS = 5.0 V

I_{OUT_LOW}= 2 mA

3

Output Voltage HIGH

VDD - VSS = 3.3 V

I_{OUT_HIGH}= 2 mA

2.6

4.2

VDD - VSS = 5.0 V

I_{OUT_HIGH}= 2 mA

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Table 7: 3.3V / 5V Voltage Regulator

Parameter

Conditions

1

Name

VDD_3V3

VDD_5V

V_DO

Min

3.0

4.5

Typ

3.3

5

Max

3.6

5.5

2

Unit

V

Output Voltage VDD

3.3V Regulator

5V Regulator

1

V

Voltage Drop

Load Current = 20

mA

1

V

Output Current VDD

Line regulation

1

I_VDD

20

2

mA

I_OUT= 1 mA

V_L+= 24 V

REG

mV/V

Load regulation

DC current up to 20

mA

1

%

V_L+= 24 V

Power Supply rejection 100 kHz, I_OUT= 20

1

PSRR

V_RST

40

dB

V

ratio

mA

Power-On Threshold

Only applies to the

driver without LDO

(CCE4503-0)

2.7

3.0

1

Undervoltage lockout

voltage (V_L+)

V_L+,min

V_DD,min

6

V

Undervoltage lockout

3

5

voltage (V_DD

)

Start-up time

µs

3.4 Thermal Characteristics

Table 8: Thermal characteristics

Parameter Description

Conditions

Min

Typ

Max

Unit

T_{ALARM_H}

T_{ALARM_L}

T_WARNING

R_tja

Alarm temperature (higher

threshold)

150

165

180

°C

Alarm temperature (lower

threshold)

140

125

155

140

170

155

30

°C

Warning temperature

(higher threshold)

Thermal resistance

(junction to ambient)

K/W

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4

Functional Description

CCE4503 is a fully reverse polarity protected IO-Link slave device with one IO-Link channel. The

system consists of a high voltage output stage with integrated overcurrent protection, a high voltage

input stage with a spike-tolerant filter, a logic core with UART interface, an internal oscillator and an

optional LDO. The LDO output voltage is factory programmed and needs to be specified with the

order. To simplify the IO-Link protocol handling, a wake-up detection and automatic recovery function

are implemented. Additional advance protection features such as overtemperature detection and

undervoltage detection ensure robust functionality in industrial applications. All pins are ESD-

protected.

4.1 Output stage

The output stage switches the output transistors in regard to TXD and TXEN. In IO-Link mode or

Push-Pull mode TXEN is used to enable or disable the output stage. If TXEN is set high, the output

stage is enabled and the output of CQ can be controlled by TXD (inverted). If TXEN is set low, the

output stage is disabled and put into an inactive low-power state.

TXEN and TXD can also be used to configure the device in NPN, PNP and Push-Pull mode. See

Table 9. NPN mode can be configured by setting TXD high and using TXEN as control pin. PNP

mode can be configured by setting TXD low and using TXEN as control pin.

Table 9: Output stage truth table

Mode

TXEN

TXD

0

CQ

High-Z

1

IO-Link

(regular operation)

0

1

0

1

0

1

/ Push-Pull

0

1

0

NPN

PNP

1

High-Z

0

1

0

High-Z

1

0

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4.2 Current limit and slew rate configuration

The driver slew rate as well as the current limit is configured by a resistor R_ILIMconnected to ILIM.

The value of the resistor intended for configuration is specified between 0Ω and 100 kΩ, where a

lower resistor value leads to faster switching and higher maximum currents. The automatic recovery

function is only available for R_ILIM< 1 MΩ.

Table 10: Current limit and slew rate configuration

Resistor

0Ω - 100 kΩ

Current limit

350 mA - 50 mA

350 mA

Slew rate

Fast - slow

Fast

Automatic recovery

Yes

No

Open (R_ILIM> 4 MΩ)

Note: If ILIM is left open (R_ILIM> 4 MΩ) the output driver operates as if connected to VSS (R_ILIM

0 Ω), but with automatic recovery disabled.

=

4.3 Automatic Recovery

If a short is detected, the output stage is automatically disabled after the time t_SHORT. The automatic

recovery function enables the output again after t_{SHORT_DIS}and checks if the overcurrent is still

present (see Figure 4).

Reset after t_{short_dis}

Channel

Overcurrent detected

automatically

enabled

disabled

Set

Channel

TXEN = 0

TXEN = 1

disabled

Figure 4: Automatic recovery

4.4 Wake-up detection

An overcurrent pulse of t_WAKEwill be detected as wake-up pulse. When a wake-up pulse is detected,

the output of NWUP will switch from high impedance to low until TXEN is toggled by the

microcontroller.

An overcurrent pulse > t_WAKEwill be detected as overcurrent fault condition.

An overcurrent pulse < t_WAKEwill not be detected.

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4.5 Error output handling

The error output NERR combines the indication of three error sources and will be tied low if any fault

condition is detected. The following error sources are indicated by NERR:

●

Overtemperature

Undervoltage

Overcurrent

The overtemperature and undervoltage detections are combinational outputs and keep the NERR

signal low as long as the error is present. The overcurrent detection is latched and will be reset when

the CCE4503 leaves the transmit mode (TXEN = 0).

4.6 Overtemperature detection

The overtemperature detection detects 3 thresholds:

●

At T_WARNINGthe output of NERR will be tied low. This is a combinational signal and cannot be

reset by the MCU. It will be reset once the temperature drops below T_WARNING

.

●

At T_{ALARM_H}, the chip will switch off the outputs. This cannot be reset by the MCU.

When the temperature drops again below T_{ALARM_L}, the output is released and can be controlled

by TXEN and TXD.

4.7 Allowed Reverse polarity connections

The CCE4503 is designed to handle all possible permutations of reverse polarity.

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5

Package Information

5.1 Package Outlines

Figure 5: DFN10 Package Outline Drawing

5.2 Soldering Information

Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can

be downloaded from http://www.jedec.org.

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6

Ordering Information

The ordering number consists of the part number followed by a suffix (shown as "xxxx") indicating the

package, packing method and LDO option. For details and availability, please consult Dialog

Semiconductor’s customer support portal or your local sales representative.

Table 11: Ordering Information

Part Number

Package

Size (mm)

Shipment Form

Pack Quantity

CCE4503 xx LDO

DFN10

3 x 3

T&R

4000

Part Number Legend:

7

Application Information

The CCE4503 may need to be connected to some external components depending on the desired

operating environment:

●

If an LDO is selected (5V or 3.3V), a 1 µF capacitor from VDD to L- must be provided by the

customer

Outputs NERR and NWUP are open-drain outputs. Usually the internal pull-up resistors of the

MCU can be used. If no pull-up resistors can be configured, the customer needs to connect

external resistors.

●

A resistor RLIM may be used to set the overcurrent limit and slew rate. For maximum slew rate

and overcurrent limit, the pin can be connected to VSS or left open.

Figure 6: CCE4503 application

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Revision History

Revision

2.3

Date

Description

23-Jul-2020

27-May-2020

26-May-2020

Changed Ordering Information

Corrected Electrical Characteristics (Table 5 & 6)

2.2

2.1

Corrected Electrical Characteristics (Table 6)

Added Errata sheet note

2.0

20-Feb-2020

Initial version. Preliminary

Status Definitions

Revision

Datasheet Status

Product Status

Definition

1.<n>

Target

Development

This datasheet contains the design specifications for

product development. Specifications may be changed in

any manner without notice.

2.<n>

3.<n>

Preliminary

Final

Qualification

This datasheet contains the specifications and preliminary

characterization data for products in pre-production.

Specifications may be changed at any time without notice

in order to improve the design.

Production

This datasheet contains the final specifications for products

in volume production. The specifications may be changed

at any time in order to improve the design, manufacturing

and supply. Major specification changes are

communicated via Customer Product Notifications.

Datasheet changes are communicated via www.dialog-

semiconductor.com.

4.<n>

Obsolete

Archived

This datasheet contains the specifications for discontinued

products. The information is provided for reference only.

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Dialog Semiconductor reserves the right to change without notice the information published in this document, including without limitation the

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型号：	CCE45035VLDO
厂家：	Dialog Semiconductor
描述：	IO-Link Device IC
文件：	总17页 (文件大小：530K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CCE45035VLDO [DIALOG]

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