CCG1401_CSP [DIALOG]
Programmable Transimpedance Amplifier;
| 型号： | CCG1401_CSP |
| 厂家： | 
Dialog Semiconductor |
| 描述： | Programmable Transimpedance Amplifier |
| 文件： | 总20页 (文件大小：1087K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CCG1401
Programmable Transimpedance Amplifier
General Description
The CCG1401 is a universal programmable amplifier for optical sensor applications. The chip can be
delivered in a QFN16 package or as a Chip Size Package (CSP) for very small PCB footprints.
FEATURES
•
•
•
•
•
•
•
Universal amplifier for optical sensor applications
Programmable transimpedance
Programmable upper frequency range
Programmable threshold voltages
Single supply voltage
Low current consumption
Standby mode
SCHEMATIC
Figure 1: Block Diagram
Datasheet
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CCG1401
Programmable Transimpedance Amplifier
2 Pinout
2.1 Package QFN16
1
12
11
NC
COMP
NC
2
VSS
PAD
VSS
3
4
10
9
VDD
TIN
VOUT
SIN
Figure 2: CCG1401 - QFN16 (Top View)
2.2 Chip Size Package
10
11
9
2
8
3
7
6
VDD
VSS
VOUT
COMP
Top
View
5
4
12
1
Figure 3: CCG1401 Pad configuration (CSP/Bumped Die)
Revision 2.4
Datasheet
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CCG1401
Programmable Transimpedance Amplifier
2.3 Pin Descriptions
Pin no.
QFN16
Pin.no.
CSP
Name
Type
Function
1
-
NC
-
Not connected
2
3
4
5
12
11
10
-
VSS
VDD
TIN
PWR
PWR
IN
Signal/PWR Ground
Power Supply
Input TIA
NC
-
Not connected
6
7
8
9
8
-
CEXT
TOUT
NC
IN
OUT
-
External Capacitor TIA
Output TIA
Not connected
9
7
6
-
5
4
3
2
1
SIN
VOUT
NC
COMP
CLK
CSX
DIO
IN
OUT
-
OUT
IN
IN
Input SUM Amplifier
Analog Output
Not connected
Comparator Output
Serial Interface CLOCK
Serial Interface ENABLE
Serial Interface DATA IN/OUT
Power-ON Reset Output
10
11
12
13
14
15
16
IN/OUT
OUT
POR
Table 1: CCG1401 Pin Descriptions
3 Absolute Maximum Ratings
Absolute maximum ratings are allowed for short periods of time only, otherwise product reliability degrades.
Parameter
Symbo Conditions
l
VDD
Min.
-0.60
Max.
Unit
Supply voltage
6
V
Total power dissipation
Storage temperature range
Soldering Profile
PTOT
ϑstorage
tsoldering
20
150
12
mW
°C
s
@ ϑop=125 °C
sol_max=260 °C
Human Body model JEDEC
JESD22 Method A114B
Class2
-55
2
ϑ
ESD Protection
VESD
kV
Only in case of forward
biased ESD diodes. Input
voltage above VDD or below
VSS
Permanent current into ESD-
protection diodes
IDC_ESD
MTBF
4
mA
FIT
Reliability
100
@ ϑamb=27 °C
Table 2: Absolute maximum ratings
Datasheet
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CCG1401
Programmable Transimpedance Amplifier
4 Electrical Characteristics
Electrical characteristics are valid for typical operating conditions, the whole specified temperature and
supply voltage range unless otherwise specified.
Parameter
Symbol
Conditions
Min.
Typ.
Max. Unit
Operating temperature
range
op
Ambient temperature
-40
125 C
Junction temperature
range
j,op
Junction temperature
-40
130 C
Maximum capacitance of
connected photodiode
Typical values are
Input capacitance
CID
150 pF
recommended. Change in
value could lead to
change in absolute
transimpedance and
bandwidth.
Coupling capacitor
between TOUT and SIN
Cint
0.32
nF
Smaller than minimum
values can lead to
peaking, should be
avoided. Higher than
typical values will change
bandwidth and
External capacitor @
CEXT¹ to Ground
Cext
2
5
nF
transimpedance value.
RLoad_COMP
10
kΩ
Load resistance at COMP
Load capacitance at
COMP
Load resistance at VOUT
CLoad_COMP
RLoad_VOUT
200 pF
4.7
kΩ
Load capacitance at
VOUT
CLoad_VOUT
100 pF
Table 3: General Parameters
Note 1: The transimpedance amplifier has a bandpass characteristic dependent from the external capacitor
C
ext and operating condition. The low bandpass cut-off frequency can be calculated as follows:
1
ꢀ =
ꢁ
(
)
2 ∗ ꢂ ∗ ꢃꢄꢅ,ꢆꢇ−(ꢈ∗ln ꢉ +0.06) ∗ 1800 ∗ ꢊꢋꢌꢍ ∗ ꢎꢏꢌꢐ
With:
•
IDC_in Transimpedance amplifier input current (formula valid range 1µA to specified max
value, see 4.3. Transimpedance Input Stage)
•
•
•
•
K
Input current exponent = 0.14
Transimpedance control variable
Control variable exponent = -1.2
External capacitor
M
Exp
Cext
Datasheet
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CCG1401
Programmable Transimpedance Amplifier
4.2 Power Supply
Parameter
Supply voltage
Current
Symbol
VDD
Conditions
Min.
3
Typ.
Max.
5.5
Unit
V
VDD=5.5V,
IDD
2.5
3
mA
µA
consumption
no external load currents
no external load currents,
CSX=CLK=High
Standby current
IDDstandby
15
Table 4: Power Supply
4.3 Transimpedance Input Stage / Bandwidth Limitation
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Transimpedance
control
Adjustable in three steps: 1, 8,
64
M
1
8
64
Deviation of ratio from step to
step;
IDC_IN=3µA
Transimpedance
ratio tolerance
ΔM/M
3
11
%
RT3
RT2
RT1
M=64, T=27°C, fmeas=100kHz
M=8, T=27°C, fmeas=100kHz
M=1, T=27°C, fmeas=100kHz
M=1, 8, 64;
210
26
3.3
kΩ
kΩ
kΩ
Transimpedance
Tolerance of
transimpedance
Temperature
coefficient
ΔRT/ RT
-30
30
%
T=27°C
ppm/
K
TCRT
700
900
Tolerance of
transimpedance
over IDC_IN
ΔRT/
RT_IDC
5
%
M=64 IDC_IN=0.1µA…100µA
M=1, 8, 64
3≤VDD≤3.3V
3.3≤VDD≤5.5V
Transimpedance
VDD drift
∆RT/RT_V
DD
6
1
%
Load TOUT: C=320pF and
R=10kΩ in series to ground
M=64
M=8
M=1
Input resistance
RI_TIA
IDC_IN
1.7
kΩ
100
800
1500
µA
µA
µA
DC input current @
TIN
200 kHz noise bandwidth,
6 dB SNR @ IDC_IN=1µA
pA/√H
Input noise current INOISE
2.5
z
Table 5: Transimpedance Input Stage / Bandwidth Limitation
Datasheet
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CCG1401
Programmable Transimpedance Amplifier
4.4 Programmable Amplifier / Analog Output
Parameter
Symbol Conditions
Min.
Typ.
Max.
Unit
Input resistance
Gain control resolution
RI_AMP
GA
7
10
8
13
kΩ
BIT
GA=0 minimum value
GA=15
1/16
1
Gain control range
Gain
GA=255 maximum value
GA=255, GFA=0
GA=255, GFA=1
GA=255, GFA=2
GA=255, GFA=3
RLoad_VOUT=4.7 kΩ
16
100
250
500
1000
kHz
kHz
kHz
kHz
V
3dB cut-off frequency
control
fAMP_3dB
Output voltage
VOUT
0.2
4.8
2/3
VDD
DC output voltage
VOUT_DC
3V step at pin SIN,
CLoad_VOUT=100pF, VDD=3V
GA=15, GFA=0
3V step at pin SIN,
CLoad_VOUT=100pF, VDD=3V
GA=15, GFA=1
3V step at pin SIN,
CLoad_VOUT=100pF, VDD=3V
GA=15, GFA=2
3V step at pin SIN,
CLoad_VOUT=100pF, VDD=3V
GA=15, GFA=3
|0.3|
|0.6|
|1.2|
|2.4|
V/µs
V/µs
V/µs
V/µs
Output slew rate
SRout
Table 6: Programmable Amplifier / Analog output
Datasheet
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CCG1401
Programmable Transimpedance Amplifier
4.5 Comparator
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Input offset voltage
Voffs
3σ
±8
mV
Toggle input voltage over
Noise filter gate time
tNOISE_GATE threshold, comparator output
doesn’t reach 0.7V
ns
80
Low limit threshold
voltage
Upper limit threshold
voltage
referenced to 2/3 VDD,
GSREF=31
referenced to 2/3 VDD,
GSREF=0
-186
VSREF
mV
28
Threshold voltage
deviations
Threshold voltage
resolution
Threshold voltage
step size
Gsref=0…31
Linear steps
±28
mV
BIT
mV
∆VSREF
GSREF
5
VSREF_step
5.1
After asserting CSX signal
(low->high; SPI
communication cycle)
Settling time VSREF
tsettling
10
µs
Table 7: Comparator
4.6 Overall System Data
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
M=64, Gain=1/16
@ fmeas=100kHz
M=64, Gain=16
@ fmeas=100kHz
M=8, Gain=1/16
@ fmeas=100kHz
M=8, Gain=16
@ fmeas=100kHz
M=1, Gain=1/16
@ fmeas=100kHz
M=1, Gain=16
8.5
3500
Total
transimpedance
(Vout / Ifoto)
1.0
RTT
kΩ
430
0.14
5
54.5
600
@ fmeas=100kHz
Temperature
coefficient RTT
Total
ppm/
K
TCRTT
M=1, 8, 64
transimpedance VDD
drift
3≤VDD≤3.3V
3.3≤VDD≤5.5V
%
∆RTT/RTT
2
1
100 times overdrive,
∆VOUT,DC / VOUT,DC = 1%
M=1, 8, 64, GA=15
Settling time after
overdrive input TIN
tset
30
55
µs
Bandlimiting
frequency
fl
fu
20
170
40
270
kHz
kHz
M=1, 8, 64
Datasheet
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CCG1401
Programmable Transimpedance Amplifier
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Low frequency
suppression
a100
@100Hz
-50
-70
dB
VDD=5V, IDC_IN=10µA,
GSREF=0, M=1,
Pulse current=25µA
Monitor pin VOUT
tdead consists mainly
Dead time between
input and output
response
tdead
1.2
2.8
µs
µs
of tprop
Switching time from
standby to operation
Switching time from
operation to standby
Start-up time
tsw_01
Cext = 5nF
150
200
tsw_10
tstart
Cext = 5nF
20
2
µs
After reaching VDD=3V
ms
Table 8: Overall System Data
4.7 Power on Reset
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
POR signal goes high @ VDD
= VPOR_on
Power-on threshold
VPOR_on
2.4
2.6
2.8
V
POR signal goes low @ VDD
= VPOR_off
Power-off threshold
Hysteresis
VPOR_off
2.2
2.45
160
2.7
V
VPOR_hyst
100
230
mV
Table 9: Power ON Reset
4.8 Logic Output Comp
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
IOUT=4mA, VDD=3…5V
No input signal
Low output voltage
VOL
0.8
V
IOUT=-4mA, VDD=5V
Signal detected
IOUT=-4mA, VDD=3V
Signal detected
VOH_5V
VOH_3V
4.2
V
V
High output voltage
2.2
Slew rate
SRcomp
tprop
|25|
|50|
0.5
|90|
1.5
V/µs
µs
Propagation time
Output leakage
current
IO_LEAK
-0.5
0.5
µA
Table 10: Logic Output COMP
Datasheet
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CCG1401
Programmable Transimpedance Amplifier
4.9 Logic Input (DIO, CLK, CSX)
Parameter
Symbol
VIL_3V
VIL_5V
VIH_3V
VIH_5V
Cin_d
Conditions
VDD=3.0V
VDD=5.0V
VDD=3.0V
VDD=5.0V
Min.
Typ.
Max.
0.5
0.8
Unit
V
Low input voltage
1.5
2.2
V
High input voltage
Input capacitance
Frequency at CLK
40
4
pF
MHz
fCLK
Table 11: Logic Input (DIO, CLK, CSX)
5 Functional Description
5.1 SPI and Digital Control
A synchronous serial interface receives data from an external controller via DIO, CLK and CSX. This
interface consists of a 10 bit shift register, 2 bit header and 8 bit data. Each positive slope at CLK shifts the
value at DIO into the shift register. With a positive slope at CSX the 8 databits of the shift register are
transferred to the address register or a parameter register depending on the value of the header. A data
package with header “00” selects a parameter register. Following data packages with header “01” are
intended for the previously selected register.
To read out the registers content, the header needs to be “10”. DIO changes then its functionality from input
to output and DIO pin has to be released. Data can be shifted out with the positive edge of CLK. Sampling
of data should occur on the negative edge. Maximum frequency when reading is 50 kHz. The output data
starts with the register content at address 0, followed by the one at address 1 and ends with the content of
register 4. After transfer of the last bit, when CSX goes high, DIO changes its functionality back to input
behavior. The DIO-behavior is visualized by the internal signal DOUT_EN in the timing diagram.
Standby modus of analog circuitry can be selected by register (see 0) and alternatively by setting CSX=High
and CLK=High. The SPI is not affected by standby operation.
The comparator threshold can be controlled by register content and setting DIO=High for using the register
SREF1 (see 5.4.4) or setting DIO=Low for using register SREF2 (see 5.4.5). Take into consideration that
this mechanism does not work during an SPI-transfer.
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CCG1401
Programmable Transimpedance Amplifier
5.2 SPI TIMING
Figure 4: Timing diagram
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SPI Clock Frequency
fSPI
4
MHz
SPI Clock Period
SPI Start Clock after tSPI_S
tSPI_CLK
250
125
ns
ns
Select
SPI End of Select after tSPI_E
Clock
125
250
ns
ns
SPI
Idle
between tSPI_I
Access
Table 12: SPI Timing
After Power-on all register defaults are in logical state “High”, except CIRC_DIS in CTRL-register (see 0).
5.3 SPI Protocol
10 bit shift register: 2 bit header, 8 bit data/address
Bit
Denotation
Message type 0 (SPI-Write address)
Message type 1 (SPI-Write data)
Message type 2 (SPI-Read data)
9
8
7
D7
-
D7
D7
6
D6
-
D6
D6
5
D5
-
D5
D5
4
D4
-
D4
D4
3
2
1
0
H1
‘0’
‘0’
‘1’
H0
‘0’
‘1’
‘0’
D3
A3
D3
D3
D2
A2
D2
D2
D1
A1
D1
D1
D0
A0
D0
D0
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CCG1401
Programmable Transimpedance Amplifier
5.4 REGISTER DESCRIPTION
5.4.1 Register Definitions
0x1
0x2
0x3
0x4
GAIN
SREF1
SREF2
CTRL
Table 13: Register Definitions
5.4.2 TIA – Transimpedance Register
address: 0x0
Bit
7 : 2
1 : 0
Name
Reset
-
TI
0xFF
Table 14: TIA
Address: 0x0
TI
Transimpedance range selector
0d: M=1
1d: M=8
2d: M=64
3d: default state, returns to M=64
5.4.3 GAIN – Programmable Gain Register
Bit
7 : 0
Name
Reset
GA
0xFF
Table 15: GAIN
Address: 0x1
GA
Programmable amplifier gain adjustment
Gain = (GA+1)/16
0d: Gain = 1/16
15d: Gain = 1
255d: Gain = 16 (default)
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CCG1401
Programmable Transimpedance Amplifier
5.4.4 SREF1 – Programmable threshold voltage Register #1
Bit
7 : 5
4 : 0
Name
Reset
-
SREF1
0xFF
Table 16: SREF1
Address: 0x2
SREF1 Comparator threshold voltage 1
Defines the comparator threshold voltage referenced to 2/3 VDD
Vsref ≈ SREF1 * -5.1mV
DIO = high
5.4.5 SREF2 – Programmable threshold voltage Register #2
Bit
7 : 5
4 : 0
Name
Reset
-
SREF2
0xFF
Table 17: SREF2
Address: 0x3
SREF2 Comparator threshold voltage 2
Defines the comparator threshold voltage referenced to 2/3 VDD
Vsref ≈ SREF2 * -5.1mV
DIO = low
5.4.6 CTRL – General Control Register
Bit
7
6
5 : 2
1 : 0
Name
Reset
COMP_DIS
CIRC_DIS
-
GFA
0xBF (0b10111111)
Table 18: CTRL
Address: 0x4
GFA
Programmable summing amplifier 3dB frequency control adjustment
0d -> GFA=0
1d -> GFA=1
2d -> GFA=2
3d -> GFA=3
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CCG1401
Programmable Transimpedance Amplifier
CIRC_DIS
Circuit disable (standby mode)
0d -> circuit is enabled (This is the default value! Keep in mind that this is the only bit that
is initialized with ‘0’)
1d -> circuit is disabled
COMP_DIS
Comparator output disable
0d -> comparator output is enabled
1d -> comparator output is disabled
6 Application Notes
6.1 Application with Photodiode Sensor
5V
1µF
3
4
VDD
7
9
TOUT
SIN
TIN
320pF
6
CEXT
5nF
CCG1401
VOUT
16
15
14
13
10
POR
DIO
CSX
CLK
VOUT
12 TRIG
COMP
E-PAD
VSS
2
Figure 4: Optical Application
Datasheet
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CCG1401
Programmable Transimpedance Amplifier
7 Package Outline
7.1 QFN16 Package
Symbol
Min
Nom.
Max
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
0.20
b
0.25
0.30
0.35
D
E
e
L
0.35
0.40
0.45
K
0.20
D2
2.00
2.10
2.20
E2
2.00
2.10
2.20
4.00
BSC
4.00
BSC
0.65
BSC.
-
-
REF.
UNIT : mm
Figure 5: QFN16 Package
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CCG1401
Programmable Transimpedance Amplifier
7.2 CSP 12 Package
Figure 7: CSP12 Package
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Programmable Transimpedance Amplifier
8 Tape and Reel Information
8.1 Tape QFN16 Package
Figure 8: QFN16 Tape Dimensions
8.2 Tape CSP Package
Figure 9: CSP Tape Dimensions
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Programmable Transimpedance Amplifier
8.3 Reel Information QFN16
Symbol
Min
Typ
Max
A
-
-
B
1.5
-
C
D
20.2
-
-
W1 QFN16
13.25
-
12.8
13.0
13.5
330
-
13.75
Figure 10 : Reel Dimensions QFN16
Datasheet
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CCG1401
Programmable Transimpedance Amplifier
8.4 Reel Information CSP
Figure 11: Reel Dimensions CSP
9 Ordering Information
Table 19: Ordering Information
Part
Order No.
Package
Delivery
Quantity
CCG1401 CCG1401_QFN16 QFN16
Tape & Reel
Tape & Reel
5.000 per reel
3.000 per reel
CCG1401 CCG1401_CSP
CSP
Datasheet
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CCG1401
Programmable Transimpedance Amplifier
10 Revision History
Revision
2.4
Date
Description
31-Oct-2019
07-Feb-2018
03-Apr-2017
Updated template
2.3
Added CSP outline and tape, reel drawing CSP
Updated document number
2.2
Correct Pinning in 2.1 – 2.3 and QFN pitch 0,65
Introduction of Start-up time (4.6)
Fix condition for switch time operation – standby (4.6)
2.1
13-Oct-2016
Changed description of (TI) transimpedance gain default value
(5.4.3)
Fixed description for summing amplifier gain (GFA) = 3 (5.4.6)
11 Disclaimer
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modification. Unless otherwise agreed in writing, such testing or modification is the sole responsibility of
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© 2019 Dialog Semiconductor. All rights reserved.
Datasheet
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CCG1401
Programmable Transimpedance Amplifier
Contents
1 General Description ................................................................................................................................... 1
Features ........................................................................................................................................1
Schematic......................................................................................................................................1
2 Pinout .........................................................................................................................................................2
2.1 Package QFN16..................................................................................................................................2
2.2 Chip Size Package ..............................................................................................................................2
2.3 Pin Descriptions...................................................................................................................................3
3 Absolute Maximum Ratings ...................................................................................................................... 3
4 Electrical Characteristics........................................................................................................................... 4
4.2 Power Supply ......................................................................................................................................5
4.3 Transimpedance Input Stage / Bandwidth Limitation..........................................................................5
4.4 Programmable Amplifier / Analog Output............................................................................................6
4.5 Comparator..........................................................................................................................................7
4.6 Overall System Data............................................................................................................................7
4.7 Power on Reset...................................................................................................................................8
4.8 Logic Output Comp..............................................................................................................................8
4.9 Logic Input (DIO, CLK, CSX)...............................................................................................................9
5 Functional Description................................................................................................................................ 9
5.1 SPI and Digital Control ........................................................................................................................9
5.2 SPI Timing .........................................................................................................................................10
5.4 Register Description ..........................................................................................................................11
5.4.3 GAIN – Programmable Gain Register ........................................................................................ 11
5.4.4 SREF1 – Programmable threshold voltage Register #1 ............................................................12
5.4.5 SREF2 – Programmable threshold voltage Register #2 ............................................................12
5.4.6 CTRL – General Control Register............................................................................................... 12
6 Application Notes ..................................................................................................................................... 13
6.1 Application with Photodiode Sensor..................................................................................................13
7 Package Outline....................................................................................................................................... 14
7.1 QFN16 Package................................................................................................................................14
7.2 CSP 12 Package ...............................................................................................................................15
8 Tape and Reel Information....................................................................................................................... 16
8.1 Tape QFN16 Package......................................................................................................................16
8.2 Tape CSP Package...........................................................................................................................16
8.3 Reel Information QFN16....................................................................................................................17
8.4 Reel Information CSP........................................................................................................................18
9 Ordering Information ................................................................................................................................ 18
10 Revision History ..................................................................................................................................... 19
11 Disclaimer .............................................................................................................................................. 19
Contents...................................................................................................................................................... 20
Datasheet
Revision 2.4
31-Oct-2019
CFR0011-120-00
20 of 20
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