DA14580-01UNA_技术文档

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

 42 kB System SRAM

 84 kB ROM

 8 kB Retention SRAM

General Description

The DA14580 integrated circuit has a fully integrated

radio transceiver and baseband processor for Blue-

tooth^®low energy. It can be used as a standalone

application processor or as a data pump in hosted sys-

tems.

 Power management

 Integrated Buck/Boost DC-DC converter

 P0, P1, P2 and P3 ports with 3.3 V tolerance

 Easy decoupling of only 4 supply pins

The DA14580 supports a flexible memory architecture

for storing Bluetooth profiles and custom application

code, which can be updated over the air (OTA). The

qualified Bluetooth low energy protocol stack is stored

in a dedicated ROM. All software runs on the ARM^®

Cortex^®-M0 processor via a simple scheduler.

 Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)

battery cells

 10-bit ADC for battery voltage measurement

 Digital controlled oscillators

 16 MHz crystal (±20 ppm max) and RC oscillator

 32 kHz crystal (±50 ppm, ±500 ppm max) and

RCX oscillator

The Bluetooth low energy firmware includes the

L2CAP service layer protocols, Security Manager

(SM), Attribute Protocol (ATT), the Generic Attribute

Profile (GATT) and the Generic Access Profile (GAP).

All profiles published by the Bluetooth SIG as well as

custom profiles are supported.

 General purpose, Capture and Sleep timers

 Digital interfaces

 General purpose I/Os: 14 (WLCSP34 package),

24 (QFN40 package), 32 (QFN48 package)

 2 UARTs with hardware flow control up to 1 MBd

 SPI+™ interface

The transceiver interfaces directly to the antenna and

is fully compliant with the Bluetooth 4.2 standard.

 I2C bus at 100 kHz, 400 kHz

 3-axes capable Quadrature Decoder

 Analog interfaces

 4-channel 10-bit ADC

 Radio transceiver

The DA14580 has dedicated hardware for the Link

Layer implementation of Bluetooth low energy and

interface controllers for enhanced connectivity capabili-

ties.

 Fully integrated 2.4 GHz CMOS transceiver

 Single wire antenna: no RF matching or RX/TX

switching required

Features

 Supply current at VBAT3V:

 Complies with Bluetooth V4.2, ETSI EN 300 328 and

EN 300 440 Class 2 (Europe), FCC CFR47 Part 15

(US) and ARIB STD-T66 (Japan)

 Processing power

TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)

 0 dBm transmit output power

 -20 dBm output power in “Near Field Mode”

 -93 dBm receiver sensitivity

 16 MHz 32 bit ARM Cortex-M0 with SWD inter-

face

 Dedicated Link Layer Processor

 AES-128 bit encryption Processor

 Memories

 Packages:

 WLCSP 34 pins, 2.436 mm x 2.436 mm

 QFN 40 pins, 5 mm x 5 mm

 QFN 48 pins, 6 mm x 6 mm

 KGD (wafer, dice)

 32 kB One-Time-Programmable (OTP) memory

________________________________________________________________________________________________

System Diagram

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

1 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Contents

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 8

4 System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 ARM CORTEXM0 CPU. . . . . . . . . . . . . . . . . . 9

4.2 BLUETOOTH SMART. . . . . . . . . . . . . . . . . . . . 9

4.2.1 BLE Core . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2.2 Radio Transceiver . . . . . . . . . . . . . . . . . 10

4.2.3 SmartSnippets  

4.3 MEMORIES. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.4 FUNCTIONAL MODES . . . . . . . . . . . . . . . . . . .11

4.5 POWER MODES. . . . . . . . . . . . . . . . . . . . . . . 12

4.6 INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.6.1 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.6.2 SPI+. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.6.3 I2C Interface . . . . . . . . . . . . . . . . . . . . . 12

4.6.4 General Purpose ADC. . . . . . . . . . . . . . 13

4.6.5 Quadrature Decoder . . . . . . . . . . . . . . . 13

4.6.6 Keyboard Controller. . . . . . . . . . . . . . . . 13

4.6.7 Input/Output Ports . . . . . . . . . . . . . . . . . 13

4.7 TIMERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.7.1 General Purpose Timers . . . . . . . . . . . . 13

4.7.2 Wake-Up timer. . . . . . . . . . . . . . . . . . . . 14

4.7.3 Watchdog Timer. . . . . . . . . . . . . . . . . . . 14

4.8 CLOCK/RESET. . . . . . . . . . . . . . . . . . . . . . . . 14

4.8.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.8.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.9 POWER MANAGEMENT . . . . . . . . . . . . . . . . 15

5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7 Package Information. . . . . . . . . . . . . . . . . . . . . . . 151

7.1 MOISTURE SENSITIVITY LEVEL (MSL) . . . 151

7.2 WLCSP HANDLING . . . . . . . . . . . . . . . . . . . 151

7.3 SOLDERING INFORMATION. . . . . . . . . . . . 151

7.4 PACKAGE OUTLINES . . . . . . . . . . . . . . . . . 152

Datasheet

Revision 3.4

09-Nov-2016

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DA14580

FINAL

• Quad Flat Package No Leads (QFN) with 48 pins

Bluetooth Low Energy 4.2 SoC

2

Pinout

• Quad Flat Package No Leads (QFN) with 40 pins

The DA14580 comes in three packages:

The actual pin/ball assignment is depicted in the follow-

ing figures:

• Wafer Level Chip Scale Package (WLCSP) with 34

balls

1

2

3

4

5

6

A

B

C

D

E

F

Figure 2: WLCSP34 ball assignment

P0_0

P0_1

P0_2

P0_3

P3_0

P0_4

P0_5

P2_1

P0_6

1

2

3

4

5

36

35

34

33

32

31

30

29

28

27

26

25

P3_6

XTAL16Mm

XTAL16Mp

P1_3

P1_2

DA14580

6

7

SW_CLK

SWDIO

P1_1

(Top View)

8

9

VBAT1V

10

11

12

P3_1

P0_7

P1_0

SWITCH

P3_5

P3_2

Pin 0: GND plane

Figure 3: QFN48 Pin Assignment

Datasheet

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DA14580

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Bluetooth Low Energy 4.2 SoC

1

2

P0_0

P0_1

P0_2

P0_3

NC

30

29

28

27

26

25

24

23

22

21

XTAL16Mm

XTAL16Mp

P1_3

3

4

P1_2

DA14580

5

SW_CLK

SWDIO

P1_1

6

P0_4

P0_5

P2_1

(Top View)

7

8

VBAT1V

9

P0_6

P0_7

P1_0

10

SWITCH

Pin 0: GND

plane

Figure 4: QFN40 Pin Assignment

Table 1: Pin Description

Pin Name Type

General Purpose I/Os

Drive

(mA)

Reset

State

Description

P0_0

P0_1

P0_2

P0_3

P0_4

P0_5

P0_6

P0_7

DIO

4.8

I-PD

INPUT/OUTPUT with selectable pull up/down resistor. Pull-down

enabled during and after reset. General purpose I/O port bit or

alternate function nodes. Contains state retention mechanism

during power down.

DIO

P1_0

P1_1

P1_2

P1_3

P1_4/SWCLK

P1_5/SW_DIO

DIO

4.8

I-PD

I-PU

INPUT/OUTPUT with selectable pull up/down resistor. Pull-down

enabled during and after reset. General purpose I/O port bit or

alternate function nodes. Contains state retention mechanism

during power down.

This signal is the JTAG clock by default

This signal is the JTAG data I/O by default

P2_0

P2_1

P2_2

P2_3

P2_4

P2_5

P2_6

P2_7

P2_8

P2_9

DIO

I-PD

INPUT/OUTPUT with selectable pull up/down resistor. Pull-down

enabled during and after reset. General purpose I/O port bit or

alternate function nodes. Contains state retention mechanism

during power down.

NOTE: This port is only available on the QFN40/QFN48 pack-

ages.

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

5 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 1: Pin Description

Drive

(mA)

Reset

State

Pin Name

Type

Description

P3_0

P3_1

P3_2

P3_3

P3_4

P3_5

P3_6

P3_7

DIO

4.8

I-PD

INPUT/OUTPUT with selectable pull up/down resistor. Pull-down

enabled during and after reset. General purpose I/O port bit or

alternate function nodes. Contain state retention mechanism dur-

ing power down.

NOTE: This port is only available on the QFN48 package.

Debug Interface

SWDIO/P1_5

DIO

4.8

I-PU

I-PD

INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and

control communication. Can also be used as a GPIO

SW_CLK/

P1_4

INPUT JTAG clock signal. Can also be used as a GPIO

Clocks

XTAL16Mp

XTAL16Mm

XTAL32kp

XTAL32km

AI

AO

AI

INPUT. Crystal input for the 16 MHz XTAL

OUTPUT. Crystal output for the 16 MHz XTAL

INPUT. Crystal input for the 32.768 kHz XTAL

OUTPUT. Crystal output for the 32.768 kHz XTAL

AO

Quadrature Decoder

QD_CHA_X

QD_CHB_X

QD_CHA_Y

QD_CHB_Y

QD_CHA_Z

QD_CHB_Z

SPI Bus Interface

SPI_CLK

DI

INPUT. Channel A for the X axis. Mapped on Px ports

INPUT. Channel B for the X axis. Mapped on Px ports

INPUT. Channel A for the Y axis. Mapped on Px ports

INPUT. Channel B for the Y axis. Mapped on Px ports

INPUT. Channel A for the Z axis. Mapped on Px ports

INPUT. Channel B for the Z axis. Mapped on Px ports

DI

DO

DI

INPUT/OUTPUT. SPI Clock. Mapped on Px ports

INPUT. SPI Data input. Mapped on Px ports

SPI_DI

SPI_DO

DO

DI

OUTPUT. SPI Data output. Mapped on Px ports

INPUT. SPI Clock enable (active LOW). Mapped on Px ports

SPI_EN

I2C Bus Interface

SDA

DIO/DIOD

INPUT/OUTPUT. I2C bus Data with open drain port. Mapped on

Px ports

SCL

DIO/DIOD

INPUT/OUTPUT. I2C bus Clock with open drain port. In open

drain mode, SCL is monitored to support bit stretching by a

slave. Mapped on Px ports.

UART Interface

UTX

DO

DI

OUTPUT. UART transmit data. Mapped on Px ports

INPUT. UART receive data. Mapped on Px ports

OUTPUT. UART Request to Send. Mapped on Px ports

INPUT. UART Clear to Send. Mapped on Px ports

OUTPUT. UART 2 transmit data. Mapped on Px ports

INPUT. UART 2 receive data. Mapped on Px ports

OUTPUT. UART 2 Request to Send. Mapped on Px ports

INPUT. UART 2 Clear to Send. Mapped on Px ports

URX

URTS

DO

DI

UCTS

UTX2

DO

DI

URX2

URTS2

UCTS2

DO

DI

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

6 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 1: Pin Description

Drive

(mA)

Reset

State

Pin Name

Type

Description

Analog Interface

ADC[0]

AI

INPUT. Analog to Digital Converter input 0. Mapped on P0[0]

INPUT. Analog to Digital Converter input 1. Mapped on P0[1]

INPUT. Analog to Digital Converter input 2. Mapped on P0[2]

INPUT. Analog to Digital Converter input 3. Mapped on P0[3]

ADC[1]

ADC[2]

ADC[3]

Radio Transceiver

RFIOp

AIO

RF input/output. Impedance 50 

RFIOm

RF ground

Miscellaneous

RST

DI

INPUT. Reset signal (active high). Must be connected to GND if

not used.

VBAT_RF

VDCDC_RF

VPP

AIO

AI

Connect to VBAT3V on the PCB

Connect to VDCDC on the PCB

INPUT. This pin is used while OTP programming and testing.

OTP programming: VPP = 6.7 V ± 0.1 V

OTP Normal operation: leave VPP floating

Power Supply

VBAT3V

AIO

AI

INPUT/OUTPUT. Battery connection. Used for a single coin bat-

tery (3 V). If an alkaline or a NiMH battery (1.5 V) is attached to

pin VBAT1V, this is the second output of the DC-DC converter.

VBAT1V

SWITCH

INPUT. Battery connection. Used for an alkaline or a NiMh bat-

tery (1.5 V). If a single coin battery (3 V) is attached to pin

VBAT3V,this pin must be connected to GND.

AIO

INPUT/OUTPUT. Connection for the external DC-DC converter

inductor.

VDCDC

GND

AO

Output of the DC-DC converter

Ground

AIO

-

Datasheet

Revision 3.4

09-Nov-2016

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DA14580

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Bluetooth Low Energy 4.2 SoC

3

Ordering Information

Table 2: Ordering Information (Samples)

Part Number

Package

WLCSP34

QFN48

Size (mm)

2.436 x 2.436

6 x 6

Shipment Form

Mini-reel

Tray

Pack Quantity

DA14580-01UNA

DA14580-01A31

DA14580-01AT1

50/100/1000

50

QFN40

5 x 5

Tray

Table 3: Ordering Information (Production)

Part Number

Package

WLCSP34

QFN48

QFN40

KGD

Size (mm)

2.436 x 2.436

6 x 6

Shipment Form

Mini-reel

Reel

Pack Quantity

5000

DA14580-01UNA

DA14580-01A32

DA14580-01AT2

DA14580-01WO4

DA14580-01WC4

4000

5 x 5

Reel

5000

wafer

Contact Dialog Semiconductor sales office

KGD

dice

Table 4: Ordering Information (Preprogrammed OTP)

Part Number

Package

QFN48

Shipment Form Pack Quantity

Description

DA14580-01PxA31

DA14580-01PxAT1

DA14580-01PxUNA

DA14580-01PxA32

DA14580-01PxAT2

Tray

50

Preprogrammed OTP, version x

QFN40

Tray

50

WLCSP34

QFN48

Mini-reel

Reel

5000

4000

QFN40

Reel

Part Number Legend:

DA14580-nn[ABC]XYZ

nn: chip revision number

A, AB or ABC: special version (optional)

XY: package code

Z: packing method

Datasheet

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the architecture, which the OS can use as a tick

timer or as a general timer in other applications with-

out an OS.

Bluetooth Low Energy 4.2 SoC

4

System Overview

The DA14580 contains the following internal blocks:

• SuperVisor Call (SVC) instruction with a dedicated

SVC exception and PendSV (Pendable SuperVisor

service) to support various operations in an embed-

ded OS.

4.1 ARM CORTEXM0 CPU

The Cortex-M0 processor is a 32-bit Reduced Instruc-

tion Set Computing (RISC) processor with a von Neu-

mann architecture (single bus interface). It uses an

instruction set called Thumb, which was first supported

in the ARM7TDMI processor; however, several newer

instructions from the ARMv6 architecture and a few

instructions from the Thumb-2 technology are also

included. Thumb-2 technology extended the previous

Thumb instruction set to allow all operations to be car-

ried out in one CPU state. The instruction set in

Thumb-2 includes both 16-bit and 32-bit instructions;

most instructions generated by the C compiler use the

16-bit instructions, and the 32-bit instructions are used

when the 16-bit version cannot carry out the required

operations. This results in high code density and

avoids the overhead of switching between two instruc-

tion sets.

• Architecturally defined sleep modes and instructions

to enter sleep. The sleep features allow power con-

sumption to be reduced dramatically. Defining sleep

modes as an architectural feature makes porting of

software easier because sleep is entered by a spe-

cific instruction rather than implementation defined

control registers.

• Fault handling exception to catch various sources of

errors in the system.

• Support for 24 interrupts.

• Little endian memory support.

• Wake up Interrupt Controller (WIC) to allow the pro-

cessor to be powered down during sleep, while still

allowing interrupt sources to wake up the system.

In total, the Cortex-M0 processor supports only 56

base instructions, although some instructions can have

more than one form. Although the instruction set is

small, the Cortex-M0 processor is highly capable

because the Thumb instruction set is highly optimized.

• Halt mode debug. Allows the processor activity to

stop completely so that register values can be

accessed and modified. No overhead in code size

and stack memory size.

Academically, the Cortex-M0 processor is classified as

load-store architecture, as it has separate instructions

for reading and writing to memory, and instructions for

arithmetic or logical operations that use registers.

• CoreSight technology. Allows memories and periph-

erals to be accessed from the debugger without halt-

ing the processor.

• Supports Serial Wire Debug (SWD) connections.

The serial wire debug protocol can handle the same

debug features as the JTAG, but it only requires two

wires and is already supported by a number of

debug solutions from various tools vendors.

Features

• Thumb instruction set. Highly efficient, high code

density and able to execute all Thumb instructions

from the ARM7TDMI processor.

• High performance. Up to 0.9 DMIPS/MHz (Dhrys-

tone 2.1) with fast multiplier.

• Four (4) hardware breakpoints and two (2) watch

points.

• Built-in Nested Vectored Interrupt Controller (NVIC).

This makes interrupt configuration and coding of

exception handlers easy. When an interrupt request

is taken, the corresponding interrupt handler is exe-

cuted automatically without the need to determine

the exception vector in software.

• Breakpoint instruction support for an unlimited num-

ber of software breakpoints.

• Programmer’s model similar to the ARM7TDMI pro-

cessor. Most existing Thumb code for the

ARM7TDMI processor can be reused. This also

makes it easy for ARM7TDMI users, as there is no

need to learn a new instruction set.

• Interrupts can have four different programmable pri-

ority levels. The NVIC automatically handles nested

interrupts.

• The design is configured to respond to exceptions

(e.g. interrupts) as soon as possible (minimum 16

clock cycles).

4.2 BLUETOOTH SMART

4.2.1 BLE Core

• Non maskable interrupt (NMI) input for safety critical

systems.

The BLE (Bluetooth low energy) core is a qualified

Bluetooth baseband controller compatible with the

Bluetooth low energy 4.2 specification and it is in

charge of packet encoding/decoding and frame sched-

uling.

• Easy to use and C friendly. There are only two

modes (Thread mode and Handler mode). The

whole application, including exception handlers, can

be written in C without any assembler.

Features

• Built-in System Tick timer for OS support. A 24-bit

timer with a dedicated exception type is included in

• All device classes support (Broadcaster, Central,

Observer, Peripheral)

Datasheet

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Bluetooth Low Energy 4.2 SoC

• All packet types (Advertising / Data / Control)

• Encryption (AES / CCM)

• Bit stream processing (CRC, Whitening)

• FDMA/TDMA/events formatting and synchronization

• Frequency hopping calculation

• Operating clock 16 MHz or 8 MHz

• Low power modes supporting 32.0 kHz or

32.768 kHz

• Supports power down of the baseband during the

protocol’s idle periods

• AHB Slave interface for register file access

• AHB Slave interface for Exchange Memory access

of CPU via BLE core

• AHB Master interface for direct access of BLE core

to Exchange Memory space

4.2.2 Radio Transceiver

The Radio Transceiver implements the RF part of the

Bluetooth low energy protocol. Together with the Blue-

tooth 4.2 PHY layer, this provides a 93 dB RF link

budget for reliable wireless communication.

All RF blocks are supplied by on-chip low-drop out-reg-

ulators (LDOs). The bias scheme is programmable per

block and optimized for minimum power consumption.

The Bluetooth LE radio comprises the Receiver, Trans-

mitter, Synthesizer, Rx/Tx combiner block, and Biasing

LDOs.

Figure 5: SmartSnippets Stack

Apart from the protocol stack, the Software platform

supports a Hardware Abstraction Layer (HAL) which

enables easy access to peripheral’s features from a

programmer’s point of view, as presented in the follow-

ing figure.

Features

• Single ended RFIO interface, 50  matched

• Alignment free operation

• -93 dBm receiver sensitivity

• 0 dBm transmit output power

• Ultra low power consumption

• Fast frequency tuning minimizes overhead

4.2.3 SmartSnippets

The DA14580 comes complete with Dialog’s Smart-

Snippets Bluetooth Software platform which includes

a qualified Bluetooth Smart single-mode stack on chip.

Numerous Bluetooth Smart profiles for consumer well-

ness, sport, fitness, security and proximity applications

are supplied as standard, while additional customer

profiles can be developed and added as needed.

The SmartSnippets software development environ-

ment is based on Keil’s uVision mature tools and

contains example application code for both embedded

and hosted modes.

Datasheet

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Bluetooth Low Energy 4.2 SoC

Application

Sample

Drivers

Accelerometer SPI FLASH

Battery

Driver

CORE

Drivers

EEPROM

I2C

Driver

GPIO

Driver

SPI

Driver

UART

Driver

ADC

Driver

Quadrature

Timers

Figure 6: Hardware Abstraction Layer

Core drivers are provided for each interface of the

DA14580 enabling optimized usage of the hardware’s

capabilities. These drivers provide an easy-to-use

interface towards the hardware engines without having

to interfere with the register programming directly.

Sleep mode.

4.4 FUNCTIONAL MODES

The DA14580 is optimized for deeply embedded appli-

cations such as health monitoring, sports measuring,

human interaction devices etc. Customers are able to

develop and test their own applications. Upon comple-

tion of the development, the application code can be

programmed into the OTP. In general, the system has

three functional modes of operation:

On top of the core drivers, a number of sample drivers

is also provided enabling communication with basic

Bluetooth Smart application components: accelerome-

ters, FLASH/EEPROM non-volatile memories, etc.

4.3 MEMORIES

A. Development Mode: During this phase application

code is developed using the ARM Cortex-M0 SW envi-

ronment. The compiled code is then downloaded into

the System RAM or any Retention RAMs by means of

SWD (JTAG) or any serial interface (e.g. UART).

Address 0x00 is remapped to the physical memory that

contains the code and the CPU is configured to reset

and execute code from the remapped device. This

mode is enabling application development, debugging

and on-the-fly testing.

The following memories are part of the DA14580’s

internal blocks:

ROM. This is a 84 kB ROM containing the Bluetooth

low energy protocol stack as well as the boot code

sequence.

OTP. This is a 32 kB One-Time Programmable memory

array, used to store the application code as well as

Bluetooth low energy profiles. It also contains the sys-

tem configuration and calibration data.

B. Normal Mode: After the application is ready and

verified, the code can be burned into the OTP. When

the system boots/wakes up, the DMA of the OTP con-

troller will automatically copy the program code from

the OTP into the system RAM. Next, a SW reset or a

jump to the System RAM occurs and code execution is

started. Hence, in this mode, the system is autono-

mous, contains the required SW in OTP and is ready

for integration into the final product.

System SRAM. This is a 42 kB system SRAM (Sys-

RAM) which is primarily used for mirroring the program

code from the OTP when the system wakes/powers

up. It also serves as Data RAM for intermediate varia-

bles and various data that the protocol requires.

Optionally, it can be used as extra memory space for

the BLE TX and RX data structures.

Retention RAMs. These are 4 special low leakage

SRAM cells (2 kB + 2 kB + 3 kB + 1 kB) used to store

various data of the Bluetooth low energy protocol as

well as the system’s global variables and processor

stack when the system goes into Deep Sleep mode.

Storage of this data ensures secure and quick configu-

ration of the BLE Core after the system wakes up.

Every cell can be powered on or off according to the

application needs for retention area when in Deep

C. Calibration Mode: Between Development and Nor-

mal mode, there is an intermediate stage where the

chip needs to be calibrated with respect to two impor-

tant features:

• Programming of the Bluetooth device address

• Programming of the trimming value for the external

16 MHz crystal.

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This mode of operation applies to the final product and

is performed by the customer. During this phase, cer-

tain fields in the OTP should be programmed.

• Prioritized interrupt identification

• Programmable serial data baud rate as calculated

by the following: baud rate = (serial clock frequency)/

(divisor).

4.5 POWER MODES

There are four different power modes in the DA14580:

4.6.2 SPI+

• Active mode: System is active and operates at full

speed.

This interface supports a subset of the Serial Periph-

eral Interface (SPI^TM). The serial interface can transmit

and receive 8, 16 or 32 bits in master/slave mode and

transmit 9 bits in master mode. The SPI+ interface has

enhanced functionality with bidirectional 2x16-bit word

FIFOs.

• Sleep mode: No power gating has been pro-

grammed, the ARM CPU is idle, waiting for an inter-

rupt. PD_SYS is on. PD_PER and PED_RAD

depending on the programmed enabled value.

• Extended Sleep mode: All power domains are off

except for the PD_AON, the programmed PD_RRx

and the PD_SR. Since the SysRAM retains its data,

no OTP mirroring is required upon waking up the

system.

SPI is a trademark of Motorola, Inc.

Features

• Slave and Master mode

• 8 bit, 9 bit, 16 bit or 32 bit operation

• Deep Sleep mode: All power domains are off except

for the PD_AON and the programmed PD_RRx.

This mode dissipates the minimum leakage power.

However, since the SysRAM has not retained its

data, an OTP mirror action is required upon waking

up the system.

• Clock speeds up to 16 MHz for the SPI controller.

Programmable output frequencies of SPI source

clock divided by 1, 2, 4, 8

• SPI clock line speed up to 8 MHz

• SPI mode 0, 1, 2, 3 support (clock edge and phase)

• Programmable SPI_DO idle level

4.6 INTERFACES

4.6.1 UARTs

• Maskable Interrupt generation

• Bus load reduction by unidirectional writes-only and

reads-only modes.

The UART is compliant to the industry-standard 16550

and is used for serial communication with a peripheral,

modem (data carrier equipment, DCE) or data set.

Data is written from a master (CPU) over the APB bus

to the UART and it is converted to serial form and

transmitted to the destination device. Serial data is also

received by the UART and stored for the master (CPU)

to read back.

Built-in RX/TX FIFOs for continuous SPI bursts.

4.6.3 I2C Interface

The I2C interface is a programmable control bus that

provides support for the communications link between

Integrated Circuits in a system. It is a simple two-wire

bus with a software-defined protocol for system control,

which is used in temperature sensors and voltage level

translators to EEPROMs, general-purpose I/O, A/D

and D/A converters.

There is no DMA support on the UART block since its

contains internal FIFOs. Both UARTs support hardware

flow control signals (RTS, CTS, DTR, DSR).

Features

• 16 bytes Transmit and receive FIFOs

• Hardware flow control support (CTS/RTS)

• Two-wire I2C serial interface consists of a serial data

line (SDA) and a serial clock (SCL)

• Shadow registers to reduce software overhead and

also include a software programmable reset

• Two speeds are supported:

• Standard mode (0 to 100 kbit/s)

• Fast mode (<= 400 kbit/s)

• Transmitter Holding Register Empty (THRE) inter-

rupt mode

• IrDA 1.0 SIR mode supporting low power mode.

• Functionality based on the 16550 industry standard:

• Clock synchronization

• 32 deep transmit/receive FIFOs

• Master transmit, Master receive operation

• 7 or 10-bit addressing

• Programmable character properties, such as num-

ber of data bits per character (5-8), optional

• parity bit (with odd or even select) and number of

stop bits (1, 1.5 or 2)

• 7 or 10-bit combined format transfers

• Bulk transmit mode

• Line break generation and detection

• Default slave address of 0x055

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• Interrupt or polled-mode operation

• Handles Bit and Byte waiting at both bus speeds

• Programmable SDA hold time

4.6.6 Keyboard Controller

The Keyboard controller can be used for debouncing

the incoming GPIO signals when implementing a key-

board scanning engine. It generates an interrupt to the

CPU (KEYBR_IRQ).

4.6.4 General Purpose ADC

The DA14580 is equipped with a high-speed ultra low

power 10-bit general purpose Analog-to-Digital Con-

verter (GPADC). It can operate in unipolar (single

ended) mode as well as in bipolar (differential) mode.

The ADC has its own voltage regulator (LDO) of 1.2 V,

which represents the full scale reference voltage.

In parallel, five extra interrupt lines can be triggered by

a state change on 32 selectable GPIOs (GPIOx_IRQ).

Features

• Monitors any of the 32 available GPIOs (12 in the

WLCSP package, 22 in the QFN40 and 32 in the

QFN48)

Features

• Generates a keyboard interrupt on key press or key

release

• 10-bit dynamic ADC with 65 ns conversion time

• Maximum sampling rate 3.3 Msample/s

• Implements debouncing time from 0 up to 63 ms

• Ultra low power (5 A typical supply current at

100 ksample/s)

Supports five separate interrupt generation lines from

GPIO toggling

• Single-ended as well as differential input with two

input scales

4.6.7 Input/Output Ports

• Four single-ended or two differential external input

channels

The DA14580 has software-configurable I/O pin

assignment, organized into ports Port 0, Port1, Port2

and Port 3. Port 2 is only available at the QFN40 pack-

age while ports 2 and 3 are available at the QFN48

package.

• Battery monitoring function

• Chopper function

• Offset and zero scale adjust

• Common-mode input level adjust

Features

• Port 0: 8 pins, Port 1: 6 pins (including SW_CLK and

SWDIO), Port 2: 10 pins, Port 3: 8 pins

• Fully programmable pin assignment

4.6.5 Quadrature Decoder

• Selectable 25 k pull-up, pull-down resistors per pin

This block decodes the pulse trains from a rotary

encoder to provide the step and the direction of the

movement of an external device. Three axes (X, Y, Z)

are supported.

• Pull-up voltage either VBAT3V (BUCK mode) or

VBAT1V (BOOST mode) configurable per pin

• Fixed assignment for analog pin ADC[3:0]

The integrated quadrature decoder can automatically

decode the signals for the X, Y and Z axes of a HID

input device, reporting step count and direction: the

channels are expected to provide a pulse train with 90

degrees phase difference; depending on whether the

reference channel is leading or lagging, the direction

can be determined.

• Pins retain their last state when system enters the

Extended or Deep Sleep mode.

4.7 TIMERS

4.7.1 General Purpose Timers

This block can be used for waking up the chip as soon

as there is any kind of movement from the external

device connected to it.

The Timer block contains 2 timer modules that are soft-

ware controlled, programmable and can be used for

various tasks.

Features

Timer 0

• Three 16-bit signed counters that provide the step

count and direction on each of the axes (X, Y and Z)

• 16-bit general purpose timer

• Ability to generate 2 Pulse Width Modulated signals

(PWM0 and PWM1, with common programming)

• Programmable system clock sampling at maximum

16 MHz.

• Programmable output frequency:

• APB interface for control and programming

• Programmable source from P0, P1 and P2 ports

• Digital filter on the channel inputs to avoid spikes

16, 8, 4, 2 MHz or 32 kHz

f = ------------------------------------------------------------------------

M + 1 + N + 1

16

with N = 0 to (2 -1), M = 0 to (2 -1)

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Bluetooth Low Energy 4.2 SoC

• Programmable duty cycle:

be applied to the GPIO to ensure a successful system

wake-up.

M + 1

M + 1 + N + 1

--------------------------------------------

 =

 100 %

• Separately programmable interrupt timer:

16, 8, 4, 2 MHz or 32 kHz

T = ------------------------------------------------------------------------

4.7.3 Watchdog Timer

ON + 1

The Watchdog timer is an 8-bit timer with sign bit that

can be used to detect an unexpected execution

sequence caused by a software run-away and can

generate a full system reset or a Non-Maskable Inter-

rupt (NMI).

Timer 2

• 14-bit general purpose timer

• Ability to generate 3 Pulse Width Modulated signals

(PWM2, PWM3 and PWM4)

Features

• Input clock frequency:

sys_clk

• 8 bits down counter with sign bit, clocked with a

10.24 ms clock for a maximum 2.6 s time-out.

f_IN= ------------------- with N = 1, 2, 4 or 8

N

and sys_clk = 16 MHz or 32 kHz

• Non-Maskable Interrupt (NMI) or WDOG reset.

• Programmable output frequency:

• Optional automatic WDOG reset if NMI handler fails

to update the Watchdog register.

f_IN

------

2

f_IN





















-----------------

2

f_OUT

=

to

14

• Non-maskable Watchdog freeze of the Cortex-M0

Debug module when the Cortex-M0 is halted in

Debug state.

– 1

• Three outputs with Programmable duty cycle from

0 % to 100 %

Maskable Watchdog freeze by user program. Note that

if the system is not remapped, i.e. SysRAM is at

address 0x20000000, then a watchdog fire will trigger

the BootROM code to be executed again.

• Used for white LED intensity (on/off) control

4.7.2 Wake-Up timer

The Wake-up timer can be programmed to wake up the

DA14580 from power down mode after a prepro-

grammed number of GPIO events.

4.8 CLOCK/RESET

4.8.1 Clocks

Features

• Monitors any GPIO state change

• Implements debouncing time from 0 up to 63 ms

The Digital Controlled Xtal Oscillator (DXCO) is a

Pierce configured type of oscillator designed for low

power consumption and high stability. There are two

such crystal oscillators in the system, one at 16

• Accumulates external events and compares the

number to a programmed value

MHz(XTAL16M) and

a

second at 32.768 kHz

(XTAL32K). The 32.768 kHz oscillator has no trimming

capabilities and is used as the clock of the Extended/

Deep Sleep modes. The 16 MHz oscillator can be

trimmed.

• Generates an interrupt to the CPU

The principle schematic of the two oscillators is shown

in Figure 7 below. No external components to the

DA14580 are required other than the crystal itself. If

the crystal has a case connection, it is advised to con-

nect the case to ground.

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LDO groups in the system:

1. LDO RET: This is the LDO providing power to the

Retention domain (PD_AON). It powers the Retention

RAMs and the digital part which is always on.

16 MHz

32.768 kHz

2. LDO OTP: This is the LDO powering the OTP macro

cell. This is the reason for using the step-up DC-DC

converter when running from an Alkaline battery.

3. LDO SYS: This is the LDO providing the system with

the actual VDD power required for the digital part to

operate. Note that the Power Block implements seam-

less switching from the LDO SYS to the LDO RET

when the system enters Deep Sleep mode. In the latter

case, a low voltage is applied to the PD_AON power

domain to further reduce leakage.

0-22.4 pF

clock16MHz

clock32kHz

4. LDO (various): This a group of LDOs used for the

elaborate control of the powering up/down of the

Radio, the GP ADC and the XTAL16M oscillator.

Figure 7: Crystal Oscillator Circuits

There are two ways of connecting external batteries to

the Power Block of the DA14580. They depend on the

specific battery cell used and its voltage range. Battery

cells are distinguished into Lithium coin cells (2.35 V to

3.3 V) and Alkaline cells (1.0 V to 1.8 V). The connec-

tion diagrams are presented in Figure 9 and Figure 8

respectively:

There are 3 RC oscillators in the DA14580: one provid-

ing 16 MHz (RC16M), one providing 32 kHz (RC32K)

and one providing a frequency in the range of 10.5 kHz

(RCX).

4.8.2 Reset

The DA14580 comprises an RST pad which is active

high. It contains an RC filter for spikes suppression

with 400 k and 2.8 pF for the resistor and the capaci-

tor respectively. It also contains a 25 k pull-down

resistor. This pad should be connected to ground if not

needed by the application. The typical latency of the

RST pad is in the range of 2 s.

4.9 POWER MANAGEMENT

The DA14580 has a complete power management

function integrated with Buck or Boost DC-DC con-

verter and separate LDOs for the different power

domains of the system.

Features

• On-chip LDOs, without external capacitors

• Synchronous DC-DC converter which can be config-

ured as either:

• Boost (step-up) converter, starting from 0.9 V,

when running from an Alkaline/NiMH cell.

• Buck (step-down) converter for increased effi-

ciency when running from a Lithium coin-cell or 2

Alkaline batteries down to 2.35 V.

• Battery voltage measurement ADC (multiplexed

input from general purpose ADC)

• Use of small external components (2.2 H inductor

and 1F capacitor)

The Power Block contains a DC-DC converter which

can be configured to operate as a Step-Up or a Step-

Down converter. The converter provides power to four

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2.35 V to 3.3 V

Lithium

coin-cell

LDO

analog/RF

digital

analog/RF

retention

VBAT1V

Buck Converter

DA14580

Figure 8: Supply Overview, Coin-Cell Application

0.9 V to 2.0 V

VBAT1V

SWITCH

internal supply for boost conv.

VBAT3V

VDCDC

< 0.9 V

Alkaline

or

on

NiMH

Boost Converter

VDCDC_RF

VBAT_RF

LDO

digital

analog/RF

retention

DA14580

Figure 9: Supply Overview, Alkaline-Cell Application

The usage of Boost or Buck mode with respect to the

provided voltage ranges is illustrated in the following

figure which also illustrates the efficiency of the engine

assuming a 10 mA constant load.

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DC‐DC Efficiency vs Voltage

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

0.9

1.8

2.35

0

0.5

1

1.5

2

2.5

3

3.5

Buck

Boost

Boost (Vout > 1.4 V)

Figure 10: DC-DC Efficiency in Buck/Boost Mode at

Various Voltage Levels

The X axis represents the supply voltage. BOOST

mode should be used when voltage ranges from 0.9 V

to 2.0 V to sustain a decent efficiency over 70 %. From

that point on, the power dissipation becomes quite

large.

BUCK mode can operate correctly with voltages in the

range of 2.35 V to 3.3 V.

There are two voltage areas in Figure 10 designated by

dashed lines. The first one (0 V to 0.9 V) indicates that

the DA14580 is not operational when the voltage is

below 0.9 V. This is the absolute threshold for the DC-

DC converter Boost mode.

The second area (1.8 V to 2.2 V) indicates that Deep

Sleep mode is not allowed when the DC-DC converter

is configured in BUCK mode and the voltage is within

this range, because the OTP will not be readable any

more. However, this part of the voltage range can be

covered by the BOOST mode. Furthermore, when

BUCK mode is mandatory, Extended Sleep mode can

be activated instead of Deep Sleep mode, thus not

using the OTP for the code mirroring but retain the

code in SysRAM.

Note: The system should never be cold booted when

the supply voltage is less than 2.5 V. A manual power

up with a power supply less than 2.5 V in buck mode

might create instability.

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5

Registers

This section contains a detailed view of the DA14580 registers. It is organized as follows: An overview table is pre-

sented initially, which depicts all register names, addresses and descriptions. A detailed bit level description of each

register follows.

The register file of the ARM Cortex-M0 can be found in the following documents, available on the ARM website:

Devices Generic User Guide:

DUI0497A_cortex_m0_r0p0_generic_ug.pdf

Technical Reference Manual:

DDI0432C_cortex_m0_r0p0_trm.pdf

These documents contain the register descriptions for the Nested Vectored Interrupt Controller (NVIC), the System

Control Block (SCB) and the System Timer (SysTick).

Datasheet

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Table 5: Register Map

Address

Port

Description

0x40008000

0x40008004

0x40008008

0x4000800C

0x40008010

0x40008014

0x40008018

0x4000801C

0x50000000

0x50000002

0x50000004

0x50000008

0x5000000A

0x50000010

0x50000012

0x50000014

0x50000016

0x50000020

0x50000022

0x50000024

0x50000028

0x5000002A

0x50000100

0x50000102

0x50000104

0x50000106

0x50000108

0x5000010A

OTPC_MODE_REG

OTPC_PCTRL_REG

OTPC_STAT_REG

OTPC_AHBADR_REG

OTPC_CELADR_REG

OTPC_NWORDS_REG

OTPC_FFPRT_REG

OTPC_FFRD_REG

CLK_AMBA_REG

Mode register

Bit-programming control register

Status register

AHB master start address

Macrocell start address

Number of words

Ports access to fifo logic

Latest read data from the OTPC_FFPRT_REG

HCLK, PCLK, divider and clock gates

Xtal frequency trimming register

Peripheral divider register

Radio PLL control register

Clock control register

CLK_FREQ_TRIM_REG

CLK_PER_REG

CLK_RADIO_REG

CLK_CTRL_REG

PMU_CTRL_REG

Power Management Unit control register

System Control register

SYS_CTRL_REG

SYS_STAT_REG

System status register

TRIM_CTRL_REG

CLK_32K_REG

Control trimming of the XTAL16M

32 kHz oscillator register

16 MHz RC-oscillator register

20 kHz RXC-oscillator control register

Bandgap trimming

CLK_16M_REG

CLK_RCX20K_REG

BANDGAP_REG

ANA_STATUS_REG

WKUP_CTRL_REG

WKUP_COMPARE_REG

WKUP_RESET_IRQ_REG

WKUP_COUNTER_REG

WKUP_RESET_CNTR_REG

WKUP_SELECT_P0_REG

Status bit of analog (power management) circuits

Control register for the wakeup counter

Number of events before wakeup interrupt

Reset wakeup interrupt

Actual number of events of the wakeup counter

Reset the event counter

Select which inputs from P0 port can trigger wkup

counter

0x5000010C

0x5000010E

0x50000110

WKUP_SELECT_P1_REG

WKUP_SELECT_P2_REG

WKUP_SELECT_P3_REG

Select which inputs from P1 port can trigger wkup

counter

Select which inputs from P2 port can trigger wkup

counter

Select which inputs from P3 port can trigger wkup

counter

0x50000112

0x50000114

0x50000116

0x50000118

0x50000200

0x50000202

0x50000204

0x50000206

0x50000208

WKUP_POL_P0_REG

WKUP_POL_P1_REG

WKUP_POL_P2_REG

WKUP_POL_P3_REG

QDEC_CTRL_REG

Select the sensitivity polarity for each P0 input

Select the sensitivity polarity for each P1 input

Select the sensitivity polarity for each P2 input

Select the sensitivity polarity for each P3 input

Quad Decoder control register

QDEC_XCNT_REG

QDEC_YCNT_REG

QDEC_CLOCKDIV_REG

QDEC_CTRL2_REG

Counter value of the X Axis

Counter value of the Y Axis

Clock divider register

Quad Decoder control register

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Table 5: Register Map

Address

Port

Description

0x5000020A

0x50001000

0x50001004

0x50001008

0x5000100C

0x50001010

0x50001014

0x50001018

0x5000101C

0x50001020

0x50001024

0x50001030

0x50001034

0x50001038

0x5000103C

0x50001040

0x50001044

0x50001048

0x5000104C

0x50001050

0x50001054

0x50001058

0x5000105C

0x50001060

0x50001064

0x50001068

0x5000106C

0x5000107C

0x50001080

0x50001084

0x50001088

0x5000108C

0x50001090

0x50001094

0x50001098

0x5000109C

0x500010A0

0x500010A4

0x500010F4

0x500010F8

0x500010FC

0x50001100

0x50001104

0x50001108

QDEC_ZCNT_REG

Z_counter

UART_RBR_THR_DLL_REG

UART_IER_DLH_REG

UART_IIR_FCR_REG

UART_LCR_REG

Receive Buffer Register

Interrupt Enable Register

Interrupt Identification Register/FIFO Control Register

Line Control Register

UART_MCR_REG

Modem Control Register

UART_LSR_REG

Line Status Register

UART_MSR_REG

Modem Status Register

UART_SCR_REG

Scratchpad Register

UART_LPDLL_REG

Low Power Divisor Latch Low

Low Power Divisor Latch High

Shadow Receive/Transmit Buffer Register

UART Status register.

UART_LPDLH_REG

UART_SRBR_STHR0_REG

UART_SRBR_STHR1_REG

UART_SRBR_STHR2_REG

UART_SRBR_STHR3_REG

UART_SRBR_STHR4_REG

UART_SRBR_STHR5_REG

UART_SRBR_STHR6_REG

UART_SRBR_STHR7_REG

UART_SRBR_STHR8_REG

UART_SRBR_STHR9_REG

UART_SRBR_STHR10_REG

UART_SRBR_STHR11_REG

UART_SRBR_STHR12_REG

UART_SRBR_STHR13_REG

UART_SRBR_STHR14_REG

UART_SRBR_STHR15_REG

UART_USR_REG

UART_TFL_REG

Transmit FIFO Level

UART_RFL_REG

Receive FIFO Level.

UART_SRR_REG

Software Reset Register.

UART_SRTS_REG

Shadow Request to Send

UART_SBCR_REG

Shadow Break Control Register

Shadow DMA Mode

UART_SDMAM_REG

UART_SFE_REG

Shadow FIFO Enable

UART_SRT_REG

Shadow RCVR Trigger

UART_STET_REG

Shadow TX Empty Trigger

UART_HTX_REG

Halt TX

UART_CPR_REG

Component Parameter Register

Component Version

UART_UCV_REG

UART_CTR_REG

Component Type Register

UART2_RBR_THR_DLL_REG

UART2_IER_DLH_REG

UART2_IIR_FCR_REG

Receive Buffer Register

Interrupt Enable Register

Interrupt Identification Register/FIFO Control Register

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Table 5: Register Map

Address

Port

Description

0x5000110C

0x50001110

0x50001114

0x50001118

0x5000111C

0x50001120

0x50001124

0x50001130

0x50001134

0x50001138

0x5000113C

0x50001140

0x50001144

0x50001148

0x5000114C

0x50001150

0x50001154

0x50001158

0x5000115C

0x50001160

0x50001164

0x50001168

0x5000116C

0x5000117C

0x50001180

0x50001184

0x50001188

0x5000118C

0x50001190

0x50001194

0x50001198

0x5000119C

0x500011A0

0x500011A4

0x500011F4

0x500011F8

0x500011FC

0x50001200

0x50001202

0x50001204

0x50001206

0x50001208

0x50001300

0x50001304

UART2_LCR_REG

Line Control Register

UART2_MCR_REG

Modem Control Register

UART2_LSR_REG

Line Status Register

UART2_MSR_REG

Modem Status Register

UART2_SCR_REG

Scratchpad Register

UART2_LPDLL_REG

UART2_LPDLH_REG

UART2_SRBR_STHR0_REG

UART2_SRBR_STHR1_REG

UART2_SRBR_STHR2_REG

UART2_SRBR_STHR3_REG

UART2_SRBR_STHR4_REG

UART2_SRBR_STHR5_REG

UART2_SRBR_STHR6_REG

UART2_SRBR_STHR7_REG

UART2_SRBR_STHR8_REG

UART2_SRBR_STHR9_REG

UART2_SRBR_STHR10_REG

UART2_SRBR_STHR11_REG

UART2_SRBR_STHR12_REG

UART2_SRBR_STHR13_REG

UART2_SRBR_STHR14_REG

UART2_SRBR_STHR15_REG

UART2_USR_REG

Low Power Divisor Latch Low

Low Power Divisor Latch High

Shadow Receive/Transmit Buffer Register

UART Status register.

UART2_TFL_REG

Transmit FIFO Level

UART2_RFL_REG

Receive FIFO Level.

UART2_SRR_REG

Software Reset Register.

UART2_SRTS_REG

Shadow Request to Send

UART2_SBCR_REG

UART2_SDMAM_REG

UART2_SFE_REG

Shadow Break Control Register

Shadow DMA Mode

Shadow FIFO Enable

UART2_SRT_REG

Shadow RCVR Trigger

UART2_STET_REG

Shadow TX Empty Trigger

UART2_HTX_REG

Halt TX

UART2_CPR_REG

Component Parameter Register

Component Version

UART2_UCV_REG

UART2_CTR_REG

Component Type Register

SPI_CTRL_REG

SPI control register 0

SPI_RX_TX_REG0

SPI RX/TX register0

SPI_RX_TX_REG1

SPI RX/TX register1

SPI_CLEAR_INT_REG

SPI_CTRL_REG1

SPI clear interrupt register

SPI control register 1

I2C_CON_REG

I2C Control Register

I2C_TAR_REG

I2C Target Address Register

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

21 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 5: Register Map

Address

Port

Description

0x50001308

0x50001310

0x50001314

0x50001318

0x5000131C

0x50001320

0x5000132C

0x50001330

0x50001334

0x50001338

0x5000133C

0x50001340

0x50001344

0x50001348

0x5000134C

0x50001350

0x50001354

0x50001358

0x5000135C

0x50001360

0x50001364

0x50001368

0x5000136C

0x50001370

0x50001374

0x50001378

0x5000137C

0x50001380

0x50001394

0x50001398

0x5000139C

0x500013A0

0x50001400

0x50001402

0x50001404

0x50001406

0x50001408

0x5000140C

0x5000140E

0x50001410

0x50001412

0x50001414

0x50001416

0x50001500

I2C_SAR_REG

I2C Slave Address Register

I2C Rx/Tx Data Buffer and Command Register

I2C_DATA_CMD_REG

I2C_SS_SCL_HCNT_REG

I2C_SS_SCL_LCNT_REG

I2C_FS_SCL_HCNT_REG

I2C_FS_SCL_LCNT_REG

I2C_INTR_STAT_REG

Standard Speed I2C Clock SCL High Count Register

Standard Speed I2C Clock SCL Low Count Register

Fast Speed I2C Clock SCL High Count Register

Fast Speed I2C Clock SCL Low Count Register

I2C Interrupt Status Register

I2C_INTR_MASK_REG

I2C_RAW_INTR_STAT_REG

I2C_RX_TL_REG

I2C Interrupt Mask Register

I2C Raw Interrupt Status Register

I2C Receive FIFO Threshold Register

I2C Transmit FIFO Threshold Register

Clear Combined and Individual Interrupt Register

Clear RX_UNDER Interrupt Register

Clear RX_OVER Interrupt Register

Clear TX_OVER Interrupt Register

Clear RD_REQ Interrupt Register

I2C_TX_TL_REG

I2C_CLR_INTR_REG

I2C_CLR_RX_UNDER_REG

I2C_CLR_RX_OVER_REG

I2C_CLR_TX_OVER_REG

I2C_CLR_RD_REQ_REG

I2C_CLR_TX_ABRT_REG

I2C_CLR_RX_DONE_REG

I2C_CLR_ACTIVITY_REG

I2C_CLR_STOP_DET_REG

I2C_CLR_START_DET_REG

I2C_CLR_GEN_CALL_REG

I2C_ENABLE_REG

Clear TX_ABRT Interrupt Register

Clear RX_DONE Interrupt Register

Clear ACTIVITY Interrupt Register

Clear STOP_DET Interrupt Register

Clear START_DET Interrupt Register

Clear GEN_CALL Interrupt Register

I2C Enable Register

I2C_STATUS_REG

I2C Status Register

I2C_TXFLR_REG

I2C Transmit FIFO Level Register

I2C_RXFLR_REG

I2C Receive FIFO Level Register

I2C_SDA_HOLD_REG

I2C_TX_ABRT_SOURCE_REG

I2C_SDA_SETUP_REG

I2C_ACK_GENERAL_CALL_REG

I2C_ENABLE_STATUS_REG

I2C_IC_FS_SPKLEN_REG

GPIO_IRQ0_IN_SEL_REG

GPIO_IRQ1_IN_SEL_REG

GPIO_IRQ2_IN_SEL_REG

GPIO_IRQ3_IN_SEL_REG

GPIO_IRQ4_IN_SEL_REG

GPIO_DEBOUNCE_REG

GPIO_RESET_IRQ_REG

GPIO_INT_LEVEL_CTRL_REG

KBRD_IRQ_IN_SEL0_REG

KBRD_IRQ_IN_SEL1_REG

KBRD_IRQ_IN_SEL2_REG

GP_ADC_CTRL_REG

I2C SDA Hold Time Length Register

I2C Transmit Abort Source Register

I2C SDA Setup Register

I2C ACK General Call Register

I2C Enable Status Register

I2C SS and FS spike suppression limit Size

GPIO interrupt selection for GPIO_IRQ0

GPIO interrupt selection for GPIO_IRQ1

GPIO interrupt selection for GPIO_IRQ2

GPIO interrupt selection for GPIO_IRQ3

GPIO interrupt selection for GPIO_IRQ4

debounce counter value for GPIO inputs

GPIO interrupt reset register

high or low level select for GPIO interrupts

GPIO interrupt selection for KBRD_IRQ for P0

GPIO interrupt selection for KBRD_IRQ for P1 and P2

GPIO interrupt selection for KBRD_IRQ for P3

General Purpose ADC Control Register

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

22 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 5: Register Map

Address

Port

Description

0x50001502

0x50001504

0x50001506

0x50001508

0x5000150A

0x5000150C

0x5000150E

0x50001600

0x50001602

0x50001604

0x50001606

0x50003000

0x50003002

0x50003004

0x50003006

0x50003008

0x5000300A

0x5000300C

0x5000300E

0x50003010

0x50003012

0x50003014

0x50003020

0x50003022

0x50003024

0x50003026

0x50003028

0x5000302A

0x5000302C

0x5000302E

0x50003030

0x50003040

0x50003042

0x50003044

0x50003046

0x50003048

0x5000304A

0x5000304C

0x5000304E

0x50003050

0x50003052

0x50003054

0x50003056

0x50003058

GP_ADC_CTRL2_REG

GP_ADC_OFFP_REG

GP_ADC_OFFN_REG

GP_ADC_CLEAR_INT_REG

GP_ADC_RESULT_REG

GP_ADC_DELAY_REG

GP_ADC_DELAY2_REG

CLK_REF_SEL_REG

CLK_REF_CNT_REG

CLK_REF_VAL_L_REG

CLK_REF_VAL_H_REG

P0_DATA_REG

General Purpose ADC Second Control Register

General Purpose ADC Positive Offset Register

General Purpose ADC Negative Offset Register

General Purpose ADC Clear Interrupt Register

General Purpose ADC Result Register

General Purpose ADC Delay Register

General Purpose ADC Second Delay Register

Select clock for oscillator calibration

Count value for oscillator calibration

XTAL16M reference cycles, lower 16 bits

XTAL16M reference cycles, upper 16 bits

P0 Data input / output register

P0 Set port pins register

P0 Reset port pins register

P00 Mode Register

P0_SET_DATA_REG

P0_RESET_DATA_REG

P00_MODE_REG

P01_MODE_REG

P02_MODE_REG

P03_MODE_REG

P04_MODE_REG

P05_MODE_REG

P06_MODE_REG

P07_MODE_REG

P1_DATA_REG

P01 Mode Register

P02 Mode Register

P03 Mode Register

P04 Mode Register

P05 Mode Register

P06 Mode Register

P07 Mode Register

P1 Data input / output register

P1 Set port pins register

P1 Reset port pins register

P10 Mode Register

P1_SET_DATA_REG

P1_RESET_DATA_REG

P10_MODE_REG

P11_MODE_REG

P11 Mode Register

P12_MODE_REG

P13_MODE_REG

P14_MODE_REG

P15_MODE_REG

P2_DATA_REG

P12 Mode Register

P13 Mode Register

P14 Mode Register

P15 Mode Register

P2 Data input / output register

P2 Set port pins register

P2 Reset port pins register

P20 Mode Register

P2_SET_DATA_REG

P2_RESET_DATA_REG

P20_MODE_REG

P21_MODE_REG

P22_MODE_REG

P23_MODE_REG

P24_MODE_REG

P25_MODE_REG

P26_MODE_REG

P27_MODE_REG

P28_MODE_REG

P29_MODE_REG

P21 Mode Register

P22 Mode Register

P23 Mode Register

P24 Mode Register

P25 Mode Register

P26 Mode Register

P27 Mode Register

P28 Mode Register

P29 Mode Register

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

23 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 5: Register Map

Address

Port

Description

0x50003070

0x50003072

0x50003074

0x50003080

0x50003082

0x50003084

0x50003086

0x50003088

0x5000308A

0x5000308C

0x5000308E

0x50003090

0x50003092

0x50003094

0x50003100

0x50003102

0x50003200

0x50003201

0x50003202

0x50003203

0x50003204

0x50003300

0x50003302

0x50003304

0x50003306

0x50003308

0x50003400

0x50003402

0x50003404

0x50003406

0x50003408

0x5000340A

0x5000340C

0x5000340E

0x50003410

P01_PADPWR_CTRL_REG

P2_PADPWR_CTRL_REG

P3_PADPWR_CTRL_REG

P3_DATA_REG

Ports 0 and 1 Output Power Control Register

Port 2 Output Power Control Register

Port 3 Output Power Control Register

P3 Data input / output register

P3 Set port pins register

P3_SET_DATA_REG

P3_RESET_DATA_REG

P30_MODE_REG

P3 Reset port pins register

P30 Mode Register

P31_MODE_REG

P31 Mode Register

P32_MODE_REG

P32 Mode Register

P33_MODE_REG

P33 Mode Register

P34_MODE_REG

P34 Mode Register

P35_MODE_REG

P35 Mode Register

P36_MODE_REG

P36 Mode Register

P37_MODE_REG

P37 Mode Register

WATCHDOG_REG

WATCHDOG_CTRL_REG

CHIP_ID1_REG

Watchdog timer register.

Watchdog control register.

Chip identification register 1.

Chip identification register 2.

Chip identification register 3.

Software compatibility register.

Chip revision register.

CHIP_ID2_REG

CHIP_ID3_REG

CHIP_SWC_REG

CHIP_REVISION_REG

SET_FREEZE_REG

RESET_FREEZE_REG

DEBUG_REG

Controls freezing of various timers/counters.

Controls unfreezing of various timers/counters.

Various debug information register.

General purpose system status register.

General purpose system control register.

Timer0 control register

GP_STATUS_REG

GP_CONTROL_REG

TIMER0_CTRL_REG

TIMER0_ON_REG

TIMER0_RELOAD_M_REG

TIMER0_RELOAD_N_REG

PWM2_DUTY_CYCLE

PWM3_DUTY_CYCLE

PWM4_DUTY_CYCLE

TRIPLE_PWM_FREQUENCY

TRIPLE_PWM_CTRL_REG

Timer0 on control register

16 bits reload value for Timer0

Duty Cycle for PWM2

Duty Cycle for PWM3

Duty Cycle for PWM4

Frequency for PWM 2,3 and 4

PWM 2 3 4 Control

Table 6: OTPC_MODE_REG (0x40008000)

Bit

Mode Symbol

Description

Reset

31:30

-

Reserved

0x0

Datasheet

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Bluetooth Low Energy 4.2 SoC

Table 6: OTPC_MODE_REG (0x40008000)

Bit

Mode Symbol

Description

Reset

29:28

R/W

OTPC_MODE_PRG_ Selects the source that is connected to the prg_port port of

0x0

PORT_MUX

the controller.

00 - {16'd0, BANDGAP_REG[15:0]}

01 - {RF_RSSI_COMP_CTRL_REG[15:0], 8'd0,

RFIO_CTRL1_REG{7:0]}

10 - {3'd0, RF_LNA_CTRL3_REG[4:0],

RF_LNA_CTRL2_REG[11:0], RF_LNA_CTRL1_REG[11:0]}

11 - {28'd0, RF_VCO_CTRL_REG[3:0]}

See OTPC_MODE_PRG_PORT_SEL about the use of the

prg_port

27:9

8

-

Reserved

0x0

0

R/W

OPTC_MODE_PRG_ Defines the timing that will be used for all the programming

FAST

activities (APROG, MPROG and TWR)

0 - Selects the normal timing

1 - Selects the fast timing

7

R/W

OTPC_MODE_PRG_ Selects an alternative data source for the programming of

0x0

PORT_SEL

the OTP macrocells, when the controller is configured in

APROG mode.

0 - The fifo will be used as the data source. The fifo will be

filled with a way defined by the register

OTPC_MODE_USE_DMA. The number of words that will be

programmed is defined by OTPC_NWORDS.

1 - Only one word will programmed. The value of the word is

contained in the prg_port port of the controller. The values of

the registers OTPC_MODE_USE_DMA, OTPC_NWORDS

and the contents of the FIFO will not be used.

6

R/W

OTPC_MODE_TWO

_CC_ACC

Defines the duration of each read from the OTP macrocells.

0 - Reads 16 bits of data every one clock cycle.

1 - Reads 16 bits of data every two clock cycles.

0x0

5

4

R/W

OTPC_MODE_FIFO

_FLUSH

Writing 1, removes any content from the FIFO. This bit

returns automatically to 0.

0x0

OTPC_MODE_USE_

DMA

Selects the use of the dma, when the controller is configured

in one of the modes: AREAD or APROG.

0 - DMAis not used. The data should be transfered from/to

controller through OTPC_FFPRT_REG

1 - DMA is used. Data transfers from/to controller are per-

formed automatically. The AHB base address should be con-

figured in OTPC_AHBADR_REG before the selection of the

mode.

If programming of the OTPC_MODE_REG is performed

through the serial interface,the OTPC_MODE_USE_DMA

will be set to 0 automatically.

If the controller is in APROG mode and the

OTPC_MODE_PRG_PORT_SEL is enabled, the dma will

stay inactive.

3

-

Reserved

0x0

Datasheet

Revision 3.4

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DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 6: OTPC_MODE_REG (0x40008000)

Bit

Mode Symbol

R/W OTPC_MODE_MOD

Description

Reset

2:0

Defines the mode of operation of the OTPC controller. The

encoding of the modes is as follows:

000 - STBY mode

0x0

E

001 - MREAD mode

010 - MPROG mode

011 - AREAD mode

100 - APROG mode

101 - Test mode. Reserved

110 - Test mode. Reserved

111 - Test mode. Reserved

To manually move between modes, always return to STBY

mode first.

Table 7: OTPC_PCTRL_REG (0x40008004)

Bit

Mode Symbol

Description

Reset

0x0

31:28

27

-

Reserved

R/W

OTPC_PCTRL_ENU

Enables the programming in the upper bank of the OTP.

0 - Programming sequence is not applied in the upper bank.

1 - Programming sequence is applied in the upper bank.

0x0

26

25

R/W

OTPC_PCTRL_BITU

OTPC_PCTRL_ENL

Defines the value of the selected bit in the upper bank, after

the programming sequence.

0x0

Enables the programming in the lower bank.

0 - The programming sequence is not applied in the lower

bank.

1 -The programming sequence is applied in the lower bank.

24

23

R/W

OTPC_PCTRL_BITL

Defines the value of the selected bit in the lower bank, after

the programming sequence.

0x0

OTPC_PCTRL_BSE

LU

Selects between the U1 and U0 byte for the programming

sequence in the upper bank.

0 - Program the U0 byte

1 - Program the U1 byte

22:20

19

R/W

OTPC_PCTRL_BAD

RU

Selects the bit inside the Ux (x=0,1) byte, which will be pro-

grammed in the upper bank.

0x0

OTPC_PCTRL_BSE

LL

Selects between the L1 and L0 byte for the programming

sequence in the lower bank.

0 - Program the L0 byte

1 - Program the L1 byte

18:16

R/W

OTPC_PCTRL_BAD

RL

Selects the bit inside the Lx (x=0,1) byte, which will be pro-

grammed in the lower bank.

0x0

15:13

12:0

-

Reserved

0x0

R/W

OTPC_PCTRL_WAD

DR

Defines the address of a 32 bits word {U1,L1,U0,L0} in the

macrocells, where one or two bits will be programmed.

There are two macrocell banks, with 8 bits each. Each bank

contribute with two memory positions for each 32 bits word.

The Ux, Lx represent the bytes of the upper and lower bank

respectively.

Table 8: OTPC_STAT_REG (0x40008008)

Bit

Mode Symbol

Description

Reset

31:29

-

Reserved

0x0

Datasheet

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Bluetooth Low Energy 4.2 SoC

Table 8: OTPC_STAT_REG (0x40008008)

Bit

Mode Symbol

Description

Reset

28:16

R

OTPC_STAT_NWOR

DS

OTPC_STAT_TERR_ Indicates the upper bank as the source of a test error. This

Contains the current value of the words to be processed.

0

15

14

13

R

0x0

U

value is valid when OTPC_STAT_TERROR is valid.

0 - There is no test error in the upper bank

1 - A test error has occured in the upper bank

R

OTPC_STAT_TERR_ Indicates the lower bank as the source of a test error. The

0x0

L

value is valid when OTPC_STAT_TERROR is valid.

0 - There is no test error in the lower bank

1 - A test error has occured in the lower bank

OTPC_STAT_PERR_ Indicates the upper bank as the source of a programming

U

error. The value is valid when OTPC_STAT_PERROR is

valid.

0 - There is no programming error in the upper bank

1 - A programming error has occured in the upper bank

12

R

OTPC_STAT_PERR_ Indicates the lower bank as the source of a programming

0x0

L

error. The value is valid when OTPC_STAT_PERROR is

valid.

0 - There is no programming error in the lower bank

1 - A programming error has occured in the lower bank

11:8

OTPC_STAT_FWOR

DS

Indicates the number of words which contained in the fifo of

the controller.

7:5

4

-

Reserved

0x0

0x1

R

OTPC_STAT_ARDY

Monitors the progress of read or programming operations

while in the AREAD or APROG modes.

0 - The controller is busy while reading or programming

(AREAD or APROG modes).

1 - The controller is not busy in AREAD or APROG mode.

3

R

OTPC_STAT_TERR

OR

Indicates the result of a test sequence. Should be checked

after the end of a TBLANK, TDEC and TWR mode

(OTPC_STAT_TRDY= 1).

0x0

0 - The test sequence ends with no error.

1 - The test sequence has failed.

2

1

R

OTPC_STAT_TRDY

Indicates the state of a test mode. Should be used to monitor

the progress of the TBLANK, TDEC and TWR modes.

0 - The controller is busy. A test mode is in progress.

1 - There is no active test mode.

0x1

0x0

OTPC_STAT_PERR

OR

Indicates that an error has occurred during the bit-program-

ming process.

0 - No error during the bit-programming process.

1 - The process of bit-programming failed.

When the controller is in MPROG mode, this bit should be

checked after the end of the programming process

(OTPC_STAT_PRDY= 1).

During APROG mode, the value of this field is normal to

change periodically. Upon finishing the operation in the

APROG mode (OTPC_STAT_ARDY= 1), this field indicates

if the programming has failed or ended succesfully.

0

R

OTPC_STAT_PRDY

Indicates the state of a bit-programming process.

0 - The controller is busy. A bit-programming is in progress

1 - The logic which performs bit-programming is idle.

When the controller is in MPROG mode, this bit should be

used to monitor the progress of a programming request.

During APROG mode, the value of this field it is normal to

changing periodically.

0x1

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Table 9: OTPC_AHBADR_REG (0x4000800C)

Bit

Mode Symbol

Description

Reset

31:2

R/W

-

OTPC_AHBADR

Tthe AHB address used by the AHB master interface of the

controller (

bits [31:2]).

0x0

1:0

-

Reserved

0x0

Table 10: OTPC_CELADR_REG (0x40008010)

Bit

Mode Symbol

Description

Reset

0x0

31:13

12:0

-

Reserved

R/W

OTPC_CELADR

Defines a word address inside the macrocell. Used in modes

AREAD and APROG and is automatically updated.

0x0

Table 11: OTPC_NWORDS_REG (0x40008014)

Bit

Mode Symbol

Description

Reset

0x0

31:13

12:0

-

Reserved

R/W

OTPC_NWORDS

The number of words (minus one) for reading/programming

during the AREAD/APROG mode.

0x0

If in APROG mode, and the

OTPC_MODE_PRG_PORT_SEL is enabled (=1), this regis-

ter will not be used and will stay unchanged.

During mirroring, this register reflects the current amount of

data that will be copied. It keeps its value until be written by

the software with a new value. The number of the words that

remaining to be processed by the controller is contained in

the field OTPC_STAT_NWORDS.

Table 12: OTPC_FFPRT_REG (0x40008018)

Bit

Mode Symbol

R/W OTPC_FFPRT

Description

Reset

31:0

Provides access to the fifo through an access port. Write this

register with the corresponding data, when the APROG

mode is selected and the DMA is disabled. Read from this

register the corresponding data, when the AREAD mode is

selected and the DMA is disabled.

0x0

Check OTPC_STAT_FWORDS register for data/space avail-

ability, before accessing the fifo.

Table 13: OTPC_FFRD_REG (0x4000801C)

Bit

Mode Symbol

OTPC_FFRD

Description

Reset

31:0

R

Contains the value read from the fifo, after a read of the

OTPC_FFPRT_REG register.

0x0

Table 14: CLK_AMBA_REG (0x50000000)

Bit

15:8

7

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

-

OTP_ENABLE

-

Clock enable for OTP controller

Reserved

0x0

6

0x0

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Bluetooth Low Energy 4.2 SoC

Table 14: CLK_AMBA_REG (0x50000000)

Bit

Mode Symbol

Description

Reset

5:4

R/W

PCLK_DIV

APB interface clock (PCLK). Divider is cascaded with

HCLK_DIV. PCLK is HCLK divided by:

0x0: divide by 1

0x2

0x1: divide by 2

0x2: divide by 4

0x3: divide by 8

3:2

1:0

-

Reserved

0x0

0x2

R/W

HCLK_DIV

AHB interface and microprocessor clock (HCLK). HCLK is

source clock divided by:

0x0: divide by 1

0x1: divide by 2

0x2: divide by 4

0x3: divide by 8

Table 15: CLK_FREQ_TRIM_REG (0x50000002)

Bit

Mode Symbol

Description

Reset

0x0

15:11

10:8

-

Reserved

R/W

COARSE_ADJ

Xtal frequency course trimming register.

0x0: lowest frequency

0x0

0x7: highest frequencyIncrement or decrement the binary

value with 1. Wait approximately 200 us to allow the adjust-

ment to settle.

7:0

R/W

FINE_ADJ

Xtal frequency fine trimming register.

0x00: lowest frequency

0x0

0xFF: highest frequency

Table 16: CLK_PER_REG (0x50000004)

Bit

15

Mode Symbol

Description

Reset

0x0

R/W

-

QUAD_ENABLE

Enable the Quadrature clock

Reserved

14:12

11

-

0x0

R/W

-

SPI_ENABLE

Enable SPI clock

Reserved

0x0

10

-

0x0

9:8

R/W

SPI_DIV

Division factor for SPI

0x0: divide by 1

0x1: divide by 2

0x2: divide by 4

0x3: divide by 8

0x0

7

6

5

4

R/W

UART1_ENABLE

UART2_ENABLE

I2C_ENABLE

Enable UART1 clock

0x0

Enable UART2 clock

Enable I2C clock

WAKEUPCT_ENABL

E

Enable Wakeup CaptureTimer clock

3

R/W

-

TMR_ENABLE

Enable TIMER0 and TIMER2 clock

Reserved

0x0

2

-

1:0

R/W

TMR_DIV

Division factor for TIMER0

0x0: divide by 1

0x1: divide by 2

0x2: divide by 4

0x3: divide by 8

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Table 17: CLK_RADIO_REG (0x50000008)

Bit

15:8

7

Mode Symbol

Description

Reset

-

Reserved

0x0

0x1

0x0

R/W

BLE_ENABLE

BLE_LP_RESET

BLE_DIV

Enable the BLE core clocks

Reset for the BLE LP timer

6

5:4

Division factor for BLE core blocks

0x0: divide by 1

0x1: divide by 2

0x2: divide by 4

0x3: divide by 8

The programmed frequency should not be lower than 8 MHz

and not faster than the programmed CPU clock frequency.

Refer also to BLE_CNTL2_REG[BLE_CLK_SEL].

3

R/W

-

RFCU_ENABLE

Enable the RF control Unit clock

Reserved

0x0

2

-

1:0

R/W

RFCU_DIV

Division factor for RF Control Unit

0x0: divide by 1

0x1: divide by 2

0x2: divide by 4

0x3: divide by 8

The programmed frequency must be exactly 8 MHz.

Table 18: CLK_CTRL_REG (0x5000000A)

Bit

15:8

7

Mode Symbol

Description

Reset

0x0

-

Reserved

R

RUNNING_AT_XTAL

16M

Indicates that the XTAL16M clock is used as clock, and may

not be switched off

0x1

6

5

R

RUNNING_AT_RC16

M

Indicates that the RC16M clock is used as clock

0x0

RUNNING_AT_32K

Indicates that either the RC32k or XTAL32k is being used as

clock

4

3

-

Reserved

0x0

R/W

XTAL16M_SPIKE_FL Disable spikefilter in digital clock

T_DISABLE

2

R/W

XTAL16M_DISABLE

SYS_CLK_SEL

Setting this bit instantaneously disables the 16 MHz crystal

0x0

oscillator. Also, after sleep/wakeup cycle, the oscillator will

not be enabled. This bit may not be set to '1'when

"RUNNING_AT_XTAL16M is '1' to prevent deadlock. After

resetting this bit, wait for XTAL16_SETTLED or

XTAL16_TRIM_READY to become '1' before switching to

XTAL16 clock source.

1:0

R/W

Selects the clock source.

0x0: XTAL16M (check the XTAL16_SETTLED and

XTAL16_TRIM_READY bits!!)

0x1: RC16M

0x2/0x3: either RC32k or XTAL32k is used

Table 19: PMU_CTRL_REG (0x50000010)

Bit

Mode Symbol

Description

Reset

15:12

-

Reserved

0x0

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Table 19: PMU_CTRL_REG (0x50000010)

Bit

Mode Symbol

Description

Reset

11:8

R/W

RETENTION_MODE

Select the retainability of the 4 retention RAM macros.

'1' is retainable, '0' is power gated.

(3) is RETRAM4

0x0

(2) is RETRAM3

(1) is RETRAM2

(0) is RETRAM1

7

6

R/W

FORCE_BOOST

FORCE_BUCK

Force the DCDC into boost mode at next wakeup.

Setting this bit reduces the deepsleep current.

FORCE_BOOST has highest priority.

When either FORCE_BOOST or FORCE_BUCK have been

written, these bits cannot be changed.

0x0

Force the DCDC into buck mode at next wakeup.

Setting this bit reduces the deepsleep current.

FORCE_BOOST has highest priority.

When either FORCE_BOOST or FORCE_BUCK have been

written, these bits cannot be changed.

5:4

2

R/W

OTP_COPY_DIV

RADIO_SLEEP

PERIPH_SLEEP

Sets the HCLK division during OTP mirroring

Put the digital part of the radio in powerdown

Put all peripherals (I2C, UART, SPI, ADC) in powerdown

0x0

0x1

0x0

1

0

RESET_ON_WAKEU Perform a Hardware Reset after waking up. Booter will be

P

started.

Table 20: SYS_CTRL_REG (0x50000012)

Bit

Mode Symbol

Description

Reset

15

W

SW_RESET

Writing a '1' to this bit will reset the device, except for:

0x0

SYS_CTRL_REG

CLK_FREQ_TRIM_REG

...

9

R/W

TIMEOUT_DISABLE

Disables timeout in Power statemachine. By default, the

statemachine continues if after 2 ms the blocks are not

started up. This can be read back from

0x0

ANA_STATUS_REG.

8

7

-

Reserved

0x0

R/W

DEBUGGER_ENABL Enable the debugger. This bit is set by the booter according

E

to the OTP header. If not set, the SWDIO and SW_CLK can

be used as gpio ports.

6

5

R/W

OTPC_RESET_REQ

PAD_LATCH_EN

Reset request for the OTP controller.

0x0

0x1

Latches the control signals of the pads for state retention in

powerdown mode.

0: Control signals are retained

1: Latch is transparant, pad can be recontrolled

4

3

R/W

OTP_COPY

Enables OTP to SysRAM copy action after waking up

PD_SYS

0x0

CLK32_SOURCE

Sets the clock source of the 32 kHz clock

0 = RC-oscillator

1 = 32 kHz crystal oscillator

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Table 20: SYS_CTRL_REG (0x50000012)

Bit

Mode Symbol

Description

Reset

2

R/W

RET_SYSRAM

Sets the development phase mode.

0x0

The PD_SYS is not actually power gated (SysRAM is

retained).

No copy action to SysRAM is done when the system wakes

up.

For emulating startup time, the OTP_COPY bit still needs to

be set.

1:0

R/W

REMAP_ADR0

Controls which memory is located at address 0x0000 for

0x0

execution.

0x0: ROM

0x1: OTP

0x2: SysRAM

0x3: RetRAM

Table 21: SYS_STAT_REG (0x50000014)

Bit

15:8

7

Mode Symbol

Description

Reset

0x0

-

Reserved

R

XTAL16_SETTLED

Indicates that XTAL16 has had > 2 ms of settle time

0x0

6

XTAL16_TRIM_REA

DY

Indicates that XTAL trimming mechanism is ready, i.e. the

trimming equals CLK_FREQ_TRIM_REG.

0x1

5

4

3

2

1

0

R

DBG_IS_UP

Indicates that PD_DBG is functional

Indicates that PD_DBG is in power down

Indicates that PD_PER is functional

Indicates that PD_PER is in power down

Indicates that PD_RAD is functional

Indicates that PD_RAD is in power down

0x0

0x1

0x0

0x1

0x0

0x1

DBG_IS_DOWN

PER_IS_UP

PER_IS_DOWN

RAD_IS_UP

RAD_IS_DOWN

Table 22: TRIM_CTRL_REG (0x50000016)

Bit

Mode Symbol

Description

Reset

7:4

R/W

TRIM_TIME

Defines the delay between XTAL16M enable and applying

the CLK_FREQ_TRIM_REG in steps of 250 us.

0x0: apply directly

0xA

0x1: wait between 0 and 250 us

0x2: wait between 250 us and 500 us

etc.

(Note 1)

3:0

R/W

SETTLE_TIME

Defines the delay between applying

CLK_FREQ_TRIM_REG and XTAL16_SETTLED in steps of

250 us.

0x2

0x0: XTAL16_SETTLED is set direcly

0x1: wait between 0 and 250 us

0x2: wait between 250 us and 500 us

etc.

Note 1: The period duration of 250 us is derived by dividing the RC16M clock signal by 4000. Consequently, the period duration may vary over tem-

perature.

Table 23: CLK_32K_REG (0x50000020)

Bit

Mode Symbol

Description

Reset

15:13

-

Reserved

0x0

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Table 23: CLK_32K_REG (0x50000020)

Bit

Mode Symbol

Description

Reset

12

R/W

XTAL32K_DISABLE_

AMPREG

Setting this bit disables the amplitude regulation of the

XTAL32kHz oscillator.

0x0

Set this bit to '1' for an external clock applied at XTAL32Kp.

Keep this bit '0' with a crystal between XTAL32Kp and

XTAL32Km.

11:8

R/W

RC32K_TRIM

Controls the frequency of the RC32K oscillator.

0x0: lowest frequency

0x7

0x7: default

0xF: highest frequency

7

R/W

RC32K_ENABLE

XTAL32K_CUR

Enables the 32 kHz RC oscillator

0x1

0x3

6:3

Bias current for the 32kHz XTAL oscillator.

0x0: minimum

0x3: default

0xF: maximum

For each application there is an optimal setting for which the

startup behavior is optimal.

2:1

0

R/W

XTAL32K_RBIAS

Setting for the bias resistor of the 32 kHz XTAL oscillator.

0x0: maximum

0x3: minimum

0x2

0x0

Prefered setting will be provided by Dialog.

XTAL32K_ENABLE

Enables the 32 kHz XTAL oscillator

Table 24: CLK_16M_REG (0x50000022)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9

-

Reserved

R/W

XTAL16_NOISE_FIL

T_ENABLE

Enables noise flter in 16 MHz crystal oscillator

0x0

8

R/W

XTAL16_BIAS_SH_E Enables Ibias sample/hold function in 16 MHz crystal oscilla- 0x0

NABLE

tor. This bit should be set when the system wake up and

reset before entering deep or extended sleep mode.

7:5

4:1

0

XTAL16_CUR_SET

Bias current for the 16 MHz XTAL oscillator.

0x0: minimum

0x7: maximum

0x5

0x0

RC16M_TRIM

Controls the frequency of the RC16M oscillator.

0x0: lowest frequency

0xF: highest frequency

RC16M_ENABLE

Enables the 16 MHz RC oscillator

Table 25: CLK_RCX20K_REG (0x50000024)

Bit

Mode Symbol

Description

Reset

12

R/W

RCX20K_SELECT

Selects RCX oscillator.

0 : RC32K oscillator

1: RCX oscillator

0

11

R/W

RCX20K_ENABLE

RCX20K_LOWF

RCX20K_BIAS

RCX20K_NTC

Enable the RCX oscillator

Extra low frequency

Bias control

0

1

7

10

9:8

7:4

Temperature control

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Table 25: CLK_RCX20K_REG (0x50000024)

Bit

Mode Symbol

R/W RCX20K_TRIM

Description

Reset

3:0

Controls the frequency of the RCX oscillator.

0x0: lowest frequency

8

0x7: default

0xF: highest frequency

Table 26: BANDGAP_REG (0x50000028)

Bit

15

14

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

BGR_LOWPOWER

Test-mode, do not use.

0x0

It disables the bandgap core (voltages will continue for some

time, but will slowely drift away)

13:10

9:5

R/W

LDO_RET_TRIM

BGR_ITRIM

(Note 2)

0x0

Current trimming for bias

Trim register for bandgap

4:0

BGR_TRIM

Note 2: 0xF is the lowest voltage, but is too low for reliable startup at high temperature in combination with extended sleep. 0xA is 100 mV higher

and considered to be the lowest value which is safe to use. 0x0 or 0x1 is again 100 mV higher and 0x0 is the reset value. 0x4 is the maxi-

mum voltage.

Table 27: ANA_STATUS_REG (0x5000002A)

Bit

Mode Symbol

Description

Reset

0x0

15:10

-

Reserved

9

8

7

6

R

-

BOOST_SELECTED

-

Indicates that DCDC is in boost mode

Reserved

0x0

R

BANDGAP_OK

BOOST_VBAT_OK

Indicates that BANDGAP is OK

0x1

Indicates that VBAT is above threshold while in BOOST con- 0x0

verter mode.

5

R

LDO_ANA_OK

Indicates that LDO_ANA is in regulation. This LDO is used

for the general-purpose ADC only

0x0

4

3

2

1

0

R

LDO_VDD_OK

LDO_OTP_OK

VDCDC_OK

Indicates that LDO_VDD is in regulation

Indicates that LDO_OTP is in regulation

Indicates that VDCDC is above threshold.

Indicates that VBAT1V is above threshold.

0x1

0x0

VBAT1V_OK

VBAT1V_AVAILABLE Indicates that VBAT1V is available.

Table 28: WKUP_CTRL_REG (0x50000100)

Bit

Mode Symbol

Description

Reset

0x0

15:14

7

-

Reserved

R/W

WKUP_ENABLE_IR

Q

0: no interrupt will be enabled

1: if the event counter reaches the value set by

WKUP_COMPARE_REG an IRQ will be generated

0x0

6

R/W

WKUP_SFT_KEYHIT 0: no effect

1: emulate key hit. The event counter will increment by 1

0x0

(after debouncing if enabled). First make this bit 0 before any

new key hit can be sensed.

5:0

WKUP_DEB_VALUE

Keyboard debounce time (N*1 ms with N = 1 to 63).

0x0: no debouncing

0x0

0x1 to 0x3F: 1 ms to 63 ms debounce time

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Table 29: WKUP_COMPARE_REG (0x50000102)

Bit

Mode Symbol

Description

Reset

15:8

7:0

-

Reserved

0x0

R/W

COMPARE

The number of events that have to be counted before the

wakeup interrupt will be given

Table 30: WKUP_RESET_IRQ_REG (0x50000104)

Bit

Mode Symbol

WKUP_IRQ_RST

Description

Reset

15:0

W

writing any value to this register will reset the interrupt. read- 0x0

ing always returns 0.

Table 31: WKUP_COUNTER_REG (0x50000106)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R

EVENT_VALUE

This value represents the number of events that have been

counted so far. It will be reset by resetting the interrupt.

0x0

Table 32: WKUP_RESET_CNTR_REG (0x50000108)

Bit

Mode Symbol

WKUP_CNTR_RST

Description

Reset

15:0

W

writing any value to this register will reset the event counter

0x0

Table 33: WKUP_SELECT_P0_REG (0x5000010A)

Bit

Mode Symbol

R/W WKUP_SELECT_P0

Description

Reset

7:0

0: input P0x is not enabled for wakeup event counter

1: input P0x is enabled for wakeup event counter

0x0

Table 34: WKUP_SELECT_P1_REG (0x5000010C)

Bit

Mode Symbol

R/W WKUP_SELECT_P1

Description

Reset

5:0

0: input P1x is not enabled for wakeup event counter

1: input P1x is enabled for wakeup event counter

0x0

Table 35: WKUP_SELECT_P2_REG (0x5000010E)

Bit

Mode Symbol

R/W WKUP_SELECT_P2

Description

Reset

9:0

0: input P2x is not enabled for wakeup event counter

1: input P2x is enabled for wakeup event counter

0x0

Table 36: WKUP_SELECT_P3_REG (0x50000110)

Bit

Mode Symbol

R/W WKUP_SELECT_P3

Description

Reset

7:0

0: input P3x is not enabled for wakeup event counter

1: input P3x is enabled for wakeup event counter

0x0

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Table 37: WKUP_POL_P0_REG (0x50000112)

Bit

Mode Symbol

R/W WKUP_POL_P0

Description

Reset

7:0

0: enabled input P0x will increment the event counter if that

input goes high

0x0

1: enabled input P0x will increment the event counter if that

input goes low

Table 38: WKUP_POL_P1_REG (0x50000114)

Bit

Mode Symbol

R/W WKUP_POL_P1

Description

Reset

5:0

0: enabled input P1x will increment the event counter if that

input goes high

0x0

1: enabled input P1x will increment the event counter if that

input goes low

Table 39: WKUP_POL_P2_REG (0x50000116)

Bit

Mode Symbol

R/W WKUP_POL_P2

Description

Reset

9:0

0: enabled input P2x will increment the event counter if that

input goes high

0x0

1: enabled input P2x will increment the event counter if that

input goes low

Table 40: WKUP_POL_P3_REG (0x50000118)

Bit

Mode Symbol

R/W WKUP_POL_P3

Description

Reset

7:0

0: enabled input P3x will increment the event counter if that

input goes high

0x0

1: enabled input P3x will increment the event counter if that

input goes low

Table 41: QDEC_CTRL_REG (0x50000200)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:3

-

Reserved

R/W

QD_IRQ_THRES

The number of events on either counter (X or Y) that need to

be reached before an interrupt is generated. If 0 is written,

then threshold is considered to be 1.

0x2

2

1

R

QD_IRQ_STATUS

QD_IRQ_CLR

Interrupt Status. If 1 an interrupt has occured.

0x0

R/W

Writing 1 to this bit clears the interrupt. This bit is auto-

cleared

0

R/W

QD_IRQ_MASK

0: interrupt is masked

1: interrupt is enabled

0x0

Table 42: QDEC_XCNT_REG (0x50000202)

Bit

Mode Symbol

X_COUNTER

Description

Reset

15:0

R

Contains a signed value of the events. Zero when channel is

disabled

0x0

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Table 43: QDEC_YCNT_REG (0x50000204)

Bit

Mode Symbol

Y_COUNTER

Description

Reset

15:0

R

Contains a signed value of the events. Zero when channel is

disabled

0x0

Table 44: QDEC_CLOCKDIV_REG (0x50000206)

Bit

Mode Symbol

R/W CLOCK_DIVIDER

Description

Reset

9:0

Contains the number of the input clock cycles minus one,

that are required to generate one logic clock cycle.

0x0

Table 45: QDEC_CTRL2_REG (0x50000208)

Bit

Mode Symbol

Description

Reset

15:12

11:8

-

Reserved

0

R/W

CHZ_PORT_SEL

Defines which GPIOs are mapped on Channel Z

0: none

1: P0[0] -> CHZ_A, P0[1] -> CHZ_B

2: P0[2] -> CHZ_A, P0[3] -> CHZ_B

3: P0[4] -> CHZ_A, P0[5] -> CHZ_B

4: P0[6] -> CHZ_A, P0[7] -> CHZ_B

5: P1[0] -> CHZ_A, P1[1] -> CHZ_B

6: P1[2] -> CHZ_A, P1[3] -> CHZ_B

7: P2[3] -> CHZ_A, P2[4] -> CHZ_B

8: P2[5] -> CHZ_A, P2[6] -> CHZ_B

9: P2[7] -> CHZ_A, P2[8] -> CHZ_B

10: P2[9] -> CHZ_A, P2[0] -> CHZ_B

11..15: None

7:4

R/W

CHY_PORT_SEL

Defines which GPIOs are mapped on Channel Y

0: none

0

1: P0[0] -> CHY_A, P0[1] -> CHY_B

2: P0[2] -> CHY_A, P0[3] -> CHY_B

3: P0[4] -> CHY_A, P0[5] -> CHY_B

4: P0[6] -> CHY_A, P0[7] -> CHY_B

5: P1[0] -> CHY_A, P1[1] -> CHY_B

6: P1[2] -> CHY_A, P1[3] -> CHY_B

7: P2[3] -> CHY_A, P2[4] -> CHY_B

8: P2[5] -> CHY_A, P2[6] -> CHY_B

9: P2[7] -> CHY_A, P2[8] -> CHY_B

10: P2[9] -> CHY_A, P2[0] -> CHY_B

11..15: None

3:0

R/W

CHX_PORT_SEL

Defines which GPIOs are mapped on Channel X

0: none

0

1: P0[0] -> CHX_A, P0[1] -> CHX_B

2: P0[2] -> CHX_A, P0[3] -> CHX_B

3: P0[4] -> CHX_A, P0[5] -> CHX_B

4: P0[6] -> CHX_A, P0[7] -> CHX_B

5: P1[0] -> CHX_A, P1[1] -> CHX_B

6: P1[2] -> CHX_A, P1[3] -> CHX_B

7: P2[3] -> CHX_A, P2[4] -> CHX_B

8: P2[5] -> CHX_A, P2[6] -> CHX_B

9: P2[7] -> CHX_A, P2[8] -> CHX_B

10: P2[9] -> CHX_A, P2[0] -> CHX_B

11..15: None

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Table 46: QDEC_ZCNT_REG (0x5000020A)

Bit

Mode Symbol

Z_COUNTER

Description

Reset

15:0

R

Contains a signed value of the events. Zero when channel is

disabled

0

Table 47: UART_RBR_THR_DLL_REG (0x50001000)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

RBR_THR_DLL

Receive Buffer Register: This register contains the data byte

received on the serial input port (sin) in UART mode or the

serial infrared input (sir_in) in infrared mode. The data in this

register is valid only if the Data Ready (DR) bit in the Line

status Register (LSR) is set. If FIFOs are disabled (FCR[0]

set to zero), the data in the RBR must be read before the

next data arrives, otherwise it will be overwritten, resulting in

an overrun error. If FIFOs are enabled (FCR[0] set to one),

this register accesses the head of the receive FIFO. If the

receive FIFO is full and this register is not read before the

next data character arrives, then the data already in the

FIFO will be preserved but any incoming data will be lost. An

overrun error will also occur. Transmit Holding Register: This

register contains data to be transmitted on the serial output

port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost. Divisor Latch (Low): This register makes up the lower 8-

bits of a 16-bit, read/write, Divisor Latch register that con-

tains the baud rate divisor for the UART. This register may

only be accessed when the DLAB bit (LCR[7]) is set. The

output baud rate is equal to the serial clock (sclk) frequency

divided by sixteen times the value of the baud rate divisor, as

follows: baud rate = (serial clock freq) / (16 * divisor) Note

that with the Divisor Latch Registers (DLL and DLH) set to

zero, the baud clock is disabled and no serial communica-

tions will occur. Also, once the DLL is set, at least 8 clock

cycles of the slowest DW_apb_uart clock should be allowed

to pass before transmitting or receiving data.

0x0

Table 48: UART_IER_DLH_REG (0x50001004)

Bit

15:8

7

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

PTIME_DLH7

Interrupt Enable Register: PTIME, Programmable THRE

Interrupt Mode Enable. This is used to enable/disable the

generation of THRE Interrupt. 0 = disabled 1 = enabled Divi-

sor Latch (High): Bit[7] of the 8 bit DLH register.

0x0

6:4

-

Reserved

0x0

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Table 48: UART_IER_DLH_REG (0x50001004)

Bit

Mode Symbol

Description

Reset

3

R/W

EDSSI_DLH3

Interrupt Enable Register: EDSSI, Enable Modem Status

Interrupt. This is used to enable/disable the generation of

Modem Status Interrupt. This is the fourth highest priority

interrupt. 0 = disabled 1 = enabled Divisor Latch (High):

Bit[3] of the 8 bit DLH register

0x0

2

1

0

ELSI_DHL2

ETBEI_DLH1

ERBFI_DLH0

Interrupt Enable Register: ELSI, Enable Receiver Line Sta-

tus Interrupt. This is used to enable/disable the generation of

Receiver Line Status Interrupt. This is the highest priority

interrupt. 0 = disabled 1 = enabled Divisor Latch (High):

Bit[2] of the 8 bit DLH register.

Interrupt Enable Register: ETBEI, Enable Transmit Holding

Register Empty Interrupt. This is used to enable/disable the

generation of Transmitter Holding Register Empty Interrupt.

This is the third highest priority interrupt. 0 = disabled 1 =

enabled Divisor Latch (High): Bit[1] of the 8 bit DLH register.

Interrupt Enable Register: ERBFI, Enable Received Data

Available Interrupt. This is used to enable/disable the gener-

ation of Received Data Available Interrupt and the Character

Timeout Interrupt (if in FIFO mode and FIFO's enabled).

These are the second highest priority interrupts. 0 = disabled

1 = enabled Divisor Latch (High): Bit[0] of the 8 bit DLH reg-

ister.

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Table 49: UART_IIR_FCR_REG (0x50001008)

Bit

Mode Symbol

R/W IIR_FCR

Description

Reset

15:0

Interrupt Identification Register, reading this register; FIFO

Control Register, writing to this register. Interrupt Identifica-

tion Register: Bits[7:6], FIFO's Enabled (or FIFOSE): This is

used to indicate whether the FIFO's are enabled or disabled.

00 = disabled. 11 = enabled. Bits[3:0], Interrupt ID (or IID):

This indicates the highest priority pending interrupt which

can be one of the following types: 0000 = modem status.

0001 = no interrupt pending. 0010 = THR empty. 0100 =

received data available. 0110 = receiver line status. 0111 =

busy detect. 1100 = character timeout. Bits[7:6], RCVR Trig-

ger (or RT):. This is used to select the trigger level in the

receiver FIFO at which the Received Data Available Interrupt

will be generated. In auto flow control mode it is used to

determine when the rts_n signal will be de-asserted. It also

determines when the dma_rx_req_n signal will be asserted

when in certain modes of operation. The following trigger

levels are supported: 00 = 1 character in the FIFO 01 = FIFO

1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full Bits[5:4],

TX Empty Trigger (or TET): This is used to select the empty

threshold level at which the THRE Interrupts will be gener-

ated when the mode is active. It also determines when the

dma_tx_req_n signal will be asserted when in certain modes

of operation. The following trigger levels are supported: 00 =

FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full

11 = FIFO 1/2 full Bit[3], DMA Mode (or DMAM): This deter-

mines the DMA signalling mode used for the dma_tx_req_n

and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1

Bit[2], XMIT FIFO Reset (or XFIFOR): This resets the control

portion of the transmit FIFO and treats the FIFO as empty.

Note that this bit is 'self-clearing' and it is not necessary to

clear this bit. Bit[1], RCVR FIFO Reset (or RFIFOR): This

resets the control portion of the receive FIFO and treats the

FIFO as empty. Note that this bit is 'self-clearing' and it is not

necessary to clear this bit. Bit[0], FIFO Enable (or FIFOE):

This enables/disables the transmit (XMIT) and receive

(RCVR) FIFO's. Whenever the value of this bit is changed

both the XMIT and RCVR controller portion of FIFO's will be

reset.

0x0

Table 50: UART_LCR_REG (0x5000100C)

Bit

15:8

7

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

UART_DLAB

Divisor Latch Access Bit.

0x0

This bit is used to enable reading and writing of the Divisor

Latch register (DLL and DLH) to set the baud rate of the

UART.

This bit must be cleared after initial baud rate setup in order

to access other registers.

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Table 50: UART_LCR_REG (0x5000100C)

Bit

Mode Symbol

Description

Reset

6

R/W

UART_BC

Break Control Bit.

0x0

This is used to cause a break condition to be transmitted to

the receiving device. If set to one the serial output is forced

to the spacing (logic 0) state. When not in Loopback Mode,

as determined by MCR[4], the sout line is forced low until the

Break bit is cleared. If active (MCR[6] set to one) the

sir_out_n line is continuously pulsed. When in Loopback

Mode, the break condition is internally looped back to the

receiver and the sir_out_n line is forced low.

5

4

-

Reserved

0x0

R/W

UART_EPS

Even Parity Select.

This is used to select between even and odd parity, when

parity is enabled (PEN set to one). If set to one, an even

number of logic 1s is transmitted or checked. If set to zero,

an odd number of logic 1s is transmitted or checked.

3

2

R/W

UART_PEN

Parity Enable.

0x0

This bit is used to enable and disable parity generation and

detection in transmitted and received serial character

respectively.

0 = parity disabled

1 = parity enabled

UART_STOP

Number of stop bits.

This is used to select the number of stop bits per character

that the peripheral transmits and receives. If set to zero, one

stop bit is transmitted in the serial data.

If set to one and the data bits are set to 5 (LCR[1:0] set to

zero) one and a half stop bits is transmitted. Otherwise, two

stop bits are transmitted. Note that regardless of the number

of stop bits selected, the receiver checks only the first stop

bit.

0 = 1 stop bit

1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit

1:0

R/W

UART_DLS

Data Length Select.

0x0

This is used to select the number of data bits per character

that the peripheral transmits and receives. The number of bit

that may be selected areas follows:

00 = 5 bits

01 = 6 bits

10 = 7 bits

11 = 8 bits

Table 51: UART_MCR_REG (0x50001010)

Bit

15:7

6

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

UART_SIRE

SIR Mode Enable.

0x0

This is used to enable/disable the IrDA SIR Mode features

as described in "IrDA 1.0 SIR Protocol" on page 53.

0 = IrDA SIR Mode disabled

1 = IrDA SIR Mode enabled

5

R/W

UART_AFCE

Auto Flow Control Enable.

0x0

When FIFOs are enabled and the Auto Flow Control Enable

(AFCE) bit is set, hardware Auto Flow Control is enabled via

CTS and RTS.

0 = Auto Flow Control Mode disabled

1 = Auto Flow Control Mode enabled

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Table 51: UART_MCR_REG (0x50001010)

Bit

Mode Symbol

Description

Reset

4

R/W

UART_LB

LoopBack Bit.

0x0

This is used to put the UART into a diagnostic mode for test

purposes.

If operating in UART mode (SIR_MODE not active, MCR[6]

set to zero), data on the sout line is held high, while serial

data output is looped back to the sin line, internally. In this

mode all the interrupts are fully functional. Also, in loopback

mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n)

are disconnected and the modem control outputs (dtr_n,

rts_n, out1_n, out2_n) are looped back to the inputs, inter-

nally.

If operating in infrared mode (SIR_MODE active, MCR[6] set

to one), data on the sir_out_n line is held low, while serial

data output is inverted and looped back to the sir_in line.

3

2

1

R/W

UART_OUT2

UART_OUT1

UART_RTS

OUT2.

0x0

This is used to directly control the user-designated Output2

(out2_n) output. The value written to this location is inverted

and driven out on out2_n, that is:

0 = out2_n de-asserted (logic 1)

1 = out2_n asserted (logic 0)

Note that in Loopback mode (MCR[4] set to one), the out2_n

output is held inactive high while the value of this location is

internally looped back to an input.

OUT1.

This is used to directly control the user-designated Output1

(out1_n) output. The value written to this location is inverted

and driven out on out1_n, that is:

0 = out1_n de-asserted (logic 1)

1 = out1_n asserted (logic 0)

Note that in Loopback mode (MCR[4] set to one), the out1_n

output is held inactive high while the value of this location is

internally looped back to an input.

Request to Send.

This is used to directly control the Request to Send (rts_n)

output. The Request To Send (rts_n) output is used to inform

the modem or data set that the UART is ready to exchange

data.

When Auto Flow Control is disabled (MCR[5] set to zero),

the rts_n signal is set low by programming MCR[1] (RTS) to

a high. When Auto Flow Control is enabled (MCR[5] set to

one) and FIFOs are enabled (FCR[0] set to one), the rts_n

output is controlled in the same way, but is also gated with

the receiver FIFO threshold trigger (rts_n is inactive high

when above the threshold). The rts_n signal is de-asserted

when MCR[1] is set low.

Note that in Loopback mode (MCR[4] set to one), the rts_n

output is held inactive (high) while the value of this location is

internally looped back to an input.

0

-

Reserved

0x0

Table 52: UART_LSR_REG (0x50001014)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

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Table 52: UART_LSR_REG (0x50001014)

Bit

Mode Symbol

Description

Reset

7

R

UART_RFE

Receiver FIFO Error bit.

0x0

This bit is only relevant when FIFOs are enabled (FCR[0] set

to one). This is used to indicate if there is at least one parity

error, framing error, or break indication in the FIFO.

0 = no error in RX FIFO

1 = error in RX FIFO

This bit is cleared when the LSR is read and the character

with the error is at the top of the receiver FIFO and there are

no subsequent errors in the FIFO.

6

5

R

UART_TEMT

UART_THRE

Transmitter Empty bit.

0x1

If FIFOs enabled (FCR[0] set to one), this bit is set whenever

the Transmitter Shift Register and the FIFO are both empty.

If FIFOs are disabled, this bit is set whenever the Transmitter

Holding Register and the Transmitter Shift Register are both

empty.

Transmit Holding Register Empty bit.

If THRE mode is disabled (IER[7] set to zero) and regardless

of FIFO's being implemented/enabled or not, this bit indi-

cates that the THR or TX FIFO is empty.

This bit is set whenever data is transferred from the THR or

TX FIFO to the transmitter shift register and no new data has

been written to the THR or TX FIFO. This also causes a

THRE Interrupt to occur, if the THRE Interrupt is enabled. If

both modes are active (IER[7] set to one and FCR[0] set to

one respectively), the functionality is switched to indicate the

transmitter FIFO is full, and no longer controls THRE inter-

rupts, which are then controlled by the FCR[5:4] threshold

setting.

4

R

UART_B1

Break Interrupt bit.

0x0

This is used to indicate the detection of a break sequence on

the serial input data.

If in UART mode (SIR_MODE == Disabled), it is set when-

ever the serial input, sin, is held in a logic '0' state for longer

than the sum of start time + data bits + parity + stop bits.

If in infrared mode (SIR_MODE == Enabled), it is set when-

ever the serial input, sir_in, is continuously pulsed to logic '0'

for longer than the sum of start time + data bits + parity +

stop bits. A break condition on serial input causes one and

only one character, consisting of all zeros, to be received by

the UART.

In the FIFO mode, the character associated with the break

condition is carried through the FIFO and is revealed when

the character is at the top of the FIFO.

Reading the LSR clears the BI bit. In the non-FIFO mode,

the BI indication occurs immediately and persists until the

LSR is read.

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Table 52: UART_LSR_REG (0x50001014)

Bit

Mode Symbol

Description

Reset

3

R

UART_FE

Framing Error bit.

0x0

This is used to indicate the occurrence of a framing error in

the receiver. A framing error occurs when the receiver does

not detect a valid STOP bit in the received data.

In the FIFO mode, since the framing error is associated with

a character received, it is revealed when the character with

the framing error is at the top of the FIFO.

When a framing error occurs, the UART tries to resynchro-

nize. It does this by assuming that the error was due to the

start bit of the next character and then continues receiving

the other bit i.e. data, and/or parity and stop. It should be

noted that the Framing Error (FE) bit (LSR[3]) is set if a

break interrupt has occurred, as indicated by Break Interrupt

(BI) bit (LSR[4]).

0 = no framing error

1 = framing error

Reading the LSR clears the FE bit.

2

R

UART_PE

Parity Error bit.

0x0

This is used to indicate the occurrence of a parity error in the

receiver if the Parity Enable (PEN) bit (LCR[3]) is set.

In the FIFO mode, since the parity error is associated with a

character received, it is revealed when the character with the

parity error arrives at the top of the FIFO.

It should be noted that the Parity Error (PE) bit (LSR[2]) is

set if a break interrupt has occurred, as indicated by Break

Interrupt (BI) bit (LSR[4]).

0 = no parity error

1 = parity error

Reading the LSR clears the PE bit.

1

R

UART_OE

Overrun error bit.

0x0

This is used to indicate the occurrence of an overrun error.

This occurs if a new data character was received before the

previous data was read.

In the non-FIFO mode, the OE bit is set when a new charac-

ter arrives in the receiver before the previous character was

read from the RBR. When this happens, the data in the RBR

is overwritten. In the FIFO mode, an overrun error occurs

when the FIFO is full and a new character arrives at the

receiver. The data in the FIFO is retained and the data in the

receive shift register is lost.

0 = no overrun error

1 = overrun error

Reading the LSR clears the OE bit.

0

R

UART_DR

Data Ready bit.

0x0

This is used to indicate that the receiver contains at least

one character in the RBR or the receiver FIFO.

0 = no data ready

1 = data ready

This bit is cleared when the RBR is read in non-FIFO mode,

or when the receiver FIFO is empty, in FIFO mode.

Table 53: UART_MSR_REG (0x50001018)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

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Table 53: UART_MSR_REG (0x50001018)

Bit

Mode Symbol

R UART_DCD

Description

Reset

0x0

7

Data Carrier Detect.

This is used to indicate the current state of the modem con-

trol line dcd_n. This bit is the complement of dcd_n. When

the Data Carrier Detect input (dcd_n) is asserted it is an indi-

cation that the carrier has been detected by the modem or

data set.

0 = dcd_n input is de-asserted (logic 1)

1 = dcd_n input is asserted (logic 0)

In Loopback Mode (MCR[4] set to one), DCD is the same as

MCR[3] (Out2).

6

R

UART_R1

Ring Indicator.

0x0

This is used to indicate the current state of the modem con-

trol line ri_n. This bit is the complement of ri_n. When the

Ring Indicator input (ri_n) is asserted it is an indication that a

telephone ringing signal has been received by the modem or

data set.

0 = ri_n input is de-asserted (logic 1)

1 = ri_n input is asserted (logic 0)

In Loopback Mode (MCR[4] set to one), RI is the same as

MCR[2] (Out1).

5

4

-

Reserved

0x0

R

UART_CTS

Clear to Send.

This is used to indicate the current state of the modem con-

trol line cts_n. This bit is the complement of cts_n. When the

Clear to Send input (cts_n) is asserted it is an indication that

the modem or data set is ready to exchange data with the

UART Ctrl.

0 = cts_n input is de-asserted (logic 1)

1 = cts_n input is asserted (logic 0)

In Loopback Mode (MCR[4] = 1), CTS is the same as

MCR[1] (RTS).

3

R

UART_DDCD

Delta Data Carrier Detect.

0x0

This is used to indicate that the modem control line dcd_n

has changed since the last time the MSR was read.

0 = no change on dcd_n since last read of MSR

1 = change on dcd_n since last read of MSR

Reading the MSR clears the DDCD bit. In Loopback Mode

(MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2).

Note, if the DDCD bit is not set and the dcd_n signal is

asserted (low) and a reset occurs (software or otherwise),

then the DDCD bit is set when the reset is removed if the

dcd_n signal remains asserted.

2

R

UART_TERI

Trailing Edge of Ring Indicator.

0x0

This is used to indicate that a change on the input ri_n (from

an active-low to an inactive-high state) has occurred since

the last time the MSR was read.

0 = no change on ri_n since last read of MSR

1 = change on ri_n since last read of MSR

Reading the MSR clears the TERI bit. In Loopback Mode

(MCR[4] = 1), TERI reflects when MCR[2] (Out1) has

changed state from a high to a low.

1

-

Reserved

0x0

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Table 53: UART_MSR_REG (0x50001018)

Bit

Mode Symbol

UART_DCTS

Description

Reset

0

R

Delta Clear to Send.

0x0

This is used to indicate that the modem control line cts_n

has changed since the last time the MSR was read.

0 = no change on cts_n since last read of MSR

1 = change on cts_n since last read of MSR

Reading the MSR clears the DCTS bit. In Loopback Mode

(MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS).

Note, if the DCTS bit is not set and the cts_n signal is

asserted (low) and a reset occurs (software or otherwise),

then the DCTS bit is set when the reset is removed if the

cts_n signal remains asserted.

Table 54: UART_SCR_REG (0x5000101C)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

UART_SCRATCH_P

AD

This register is for programmers to use as a temporary stor-

age space. It has no defined purpose in the UART Ctrl.

0x0

Table 55: UART_LPDLL_REG (0x50001020)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

UART_LPDLL

This register makes up the lower 8-bits of a 16-bit, read/

write, Low Power Divisor Latch register that contains the

baud rate divisor for the UART, which must give a baud rate

of 115.2K. This is required for SIR Low Power (minimum

pulse width) detection at the receiver. This register may be

accessed only when the DLAB bit (LCR[7]) is set.

The output low-power baud rate is equal to the serial clock

(sclk) frequency divided by sixteen times the value of the

baud rate divisor, as follows:

0x0

Low power baud rate = (serial clock frequency)/(16* divisor)

Therefore, a divisor must be selected to give a baud rate of

115.2K.

NOTE: When the Low Power Divisor Latch registers (LPDLL

and LPDLH) are set to 0, the low-power baud clock is dis-

abled and no low-power pulse detection (or any pulse detec-

tion) occurs at the receiver. Also, once the LPDLL is set, at

least eight clock cycles of the slowest UART Ctrl clock

should be allowed to pass before transmitting or receiving

data.

Table 56: UART_LPDLH_REG (0x50001024)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

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Table 56: UART_LPDLH_REG (0x50001024)

Bit

Mode Symbol

R/W UART_LPDLH

Description

Reset

7:0

This register makes up the upper 8-bits of a 16-bit, read/

write, Low Power Divisor Latch register that contains the

baud rate divisor for the UART, which must give a baud rate

of 115.2K. This is required for SIR Low Power (minimum

pulse width) detection at the receiver. This register may be

accessed only when the DLAB bit (LCR[7]) is set.

The output low-power baud rate is equal to the serial clock

(sclk) frequency divided by sixteen times the value of the

baud rate divisor, as follows:

0x0

Low power baud rate = (serial clock frequency)/(16* divisor)

Therefore, a divisor must be selected to give a baud rate of

115.2K.

NOTE: When the Low Power Divisor Latch registers (LPDLL

and LPDLH) are set to 0, the low-power baud clock is dis-

abled and no low-power pulse detection (or any pulse detec-

tion) occurs at the receiver. Also, once the LPDLH is set, at

least eight clock cycles of the slowest UART Ctrl clock

should be allowed to pass before transmitting or receiving

data.

Table 57: UART_SRBR_STHR0_REG (0x50001030)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

SRBR_STHRX

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

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Table 58: UART_SRBR_STHR1_REG (0x50001034)

Bit

Mode Symbol

Description

Reset

15:8

7:0

-

Reserved

0x0

R/W

SRBR_STHRX

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

Table 59: UART_SRBR_STHR2_REG (0x50001038)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

48 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 59: UART_SRBR_STHR2_REG (0x50001038)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 60: UART_SRBR_STHR3_REG (0x5000103C)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

Revision 3.4

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CFR0011-120-01

49 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 60: UART_SRBR_STHR3_REG (0x5000103C)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 61: UART_SRBR_STHR4_REG (0x50001040)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

Revision 3.4

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CFR0011-120-01

50 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 61: UART_SRBR_STHR4_REG (0x50001040)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 62: UART_SRBR_STHR5_REG (0x50001044)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

51 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 62: UART_SRBR_STHR5_REG (0x50001044)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 63: UART_SRBR_STHR6_REG (0x50001048)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

52 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 63: UART_SRBR_STHR6_REG (0x50001048)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 64: UART_SRBR_STHR7_REG (0x5000104C)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

53 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 64: UART_SRBR_STHR7_REG (0x5000104C)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 65: UART_SRBR_STHR8_REG (0x50001050)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

54 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 65: UART_SRBR_STHR8_REG (0x50001050)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 66: UART_SRBR_STHR9_REG (0x50001054)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

55 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 66: UART_SRBR_STHR9_REG (0x50001054)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 67: UART_SRBR_STHR10_REG (0x50001058)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

56 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 67: UART_SRBR_STHR10_REG (0x50001058)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 68: UART_SRBR_STHR11_REG (0x5000105C)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

57 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 68: UART_SRBR_STHR11_REG (0x5000105C)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 69: UART_SRBR_STHR12_REG (0x50001060)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

58 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 69: UART_SRBR_STHR12_REG (0x50001060)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 70: UART_SRBR_STHR13_REG (0x50001064)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

Revision 3.4

09-Nov-2016

CFR0011-120-01

59 of 155

DA14580

FINAL

Bluetooth Low Energy 4.2 SoC

Table 70: UART_SRBR_STHR13_REG (0x50001064)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 71: UART_SRBR_STHR14_REG (0x50001068)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

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Table 71: UART_SRBR_STHR14_REG (0x50001068)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 72: UART_SRBR_STHR15_REG (0x5000106C)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

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Table 72: UART_SRBR_STHR15_REG (0x5000106C)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 73: UART_USR_REG (0x5000107C)

Bit

15:5

4

Mode Symbol

Description

Reset

0x0

-

Reserved

R

UART_RFF

Receive FIFO Full.

0x0

This is used to indicate that the receive FIFO is completely

full.

0 = Receive FIFO not full

1 = Receive FIFO Full

This bit is cleared when the RX FIFO is no longer full.

3

2

R

UART_RFNE

UART_TFE

Receive FIFO Not Empty.

This is used to indicate that the receive FIFO contains one or

more entries.

0 = Receive FIFO is empty

1 = Receive FIFO is not empty

0x0

0x1

This bit is cleared when the RX FIFO is empty.

Transmit FIFO Empty.

This is used to indicate that the transmit FIFO is completely

empty.

0 = Transmit FIFO is not empty

1 = Transmit FIFO is empty

This bit is cleared when the TX FIFO is no longer empty.

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Table 73: UART_USR_REG (0x5000107C)

Bit

Mode Symbol

Description

Reset

1

R

UART_TFNF

Transmit FIFO Not Full.

0x1

This is used to indicate that the transmit FIFO in not full.

0 = Transmit FIFO is full

1 = Transmit FIFO is not full

This bit is cleared when the TX FIFO is full.

0

-

Reserved

0x0

Table 74: UART_TFL_REG (0x50001080)

Bit

Mode Symbol

UART_TRANSMIT_F

IFO_LEVEL

Description

Reset

15:0

R

Transmit FIFO Level.

This is indicates the number of data entries in the transmit

FIFO.

0x0

Table 75: UART_RFL_REG (0x50001084)

Bit

Mode Symbol

UART_RECEIVE_FI

FO_LEVEL

Description

Reset

15:0

R

Receive FIFO Level.

This is indicates the number of data entries in the receive

FIFO.

0x0

Table 76: UART_SRR_REG (0x50001088)

Bit

15:3

2

Mode Symbol

Description

Reset

0x0

-

Reserved

W

UART_XFR

XMIT FIFO Reset.

0x0

This is a shadow register for the XMIT FIFO Reset bit

(FCR[2]). This can be used to remove the burden on soft-

ware having to store previously written FCR values (which

are pretty static) just to reset the transmit FIFO. This resets

the control portion of the transmit FIFO and treats the FIFO

as empty. Note that this bit is 'self-clearing'. It is not neces-

sary to clear this bit.

1

W

UART_RFR

RCVR FIFO Reset.

0x0

This is a shadow register for the RCVR FIFO Reset bit

(FCR[1]). This can be used to remove the burden on soft-

ware having to store previously written FCR values (which

are pretty static) just to reset the receive FIFO This resets

the control portion of the receive FIFO and treats the FIFO

as empty.

Note that this bit is 'self-clearing'. It is not necessary to clear

this bit.

0

W

UART_UR

UART Reset. This asynchronously resets the UART Ctrl and

synchronously removes the reset assertion. For a two clock

implementation both pclk and sclk domains are reset.

0x0

Table 77: UART_SRTS_REG (0x5000108C)

Bit

Mode Symbol

Description

Reset

15:1

-

Reserved

0x0

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Table 77: UART_SRTS_REG (0x5000108C)

Bit

Mode Symbol

R/W UART_SHADOW_R

EQUEST_TO_SEND

Description

Reset

0

Shadow Request to Send.

0x0

This is a shadow register for the RTS bit (MCR[1]), this can

be used to remove the burden of having to perform a read-

modify-write on the MCR. This is used to directly control the

Request to Send (rts_n) output. The Request To Send

(rts_n) output is used to inform the modem or data set that

the UART Ctrl is ready to exchange data.

When Auto Flow Control is disabled (MCR[5] = 0), the rts_n

signal is set low by programming MCR[1] (RTS) to a high.

When Auto Flow Control is enabled (MCR[5] = 1) and FIFOs

are enabled (FCR[0] = 1), the rts_n output is controlled in the

same way, but is also gated with the receiver FIFO threshold

trigger (rts_n is inactive high when above the threshold).

Note that in Loopback mode (MCR[4] = 1), the rts_n output is

held inactive-high while the value of this location is internally

looped back to an input.

Table 78: UART_SBCR_REG (0x50001090)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

UART_SHADOW_B

REAK_CONTROL

Shadow Break Control Bit.

0x0

This is a shadow register for the Break bit (LCR[6]), this can

be used to remove the burden of having to performing a read

modify write on the LCR. This is used to cause a break con-

dition to be transmitted to the receiving device.

If set to one the serial output is forced to the spacing (logic 0)

state. When not in Loopback Mode, as determined by

MCR[4], the sout line is forced low until the Break bit is

cleared.

If SIR_MODE active (MCR[6] = 1) the sir_out_n line is con-

tinuously pulsed. When in Loopback Mode, the break condi-

tion is internally looped back to the receiver.

Table 79: UART_SDMAM_REG (0x50001094)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

UART_SHADOW_D

MA_MODE

Shadow DMA Mode.

0x0

This is a shadow register for the DMA mode bit (FCR[3]).

This can be used to remove the burden of having to store the

previously written value to the FCR in memory and having to

mask this value so that only the DMA Mode bit gets updated.

This determines the DMA signalling mode used for the

dma_tx_req_n and dma_rx_req_n output signals.

0 = mode 0

1 = mode 1

Table 80: UART_SFE_REG (0x50001098)

Bit

Mode Symbol

Description

Reset

15:1

-

Reserved

0x0

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Table 80: UART_SFE_REG (0x50001098)

Bit

Mode Symbol

R/W UART_SHADOW_FI

FO_ENABLE

Description

Reset

0

Shadow FIFO Enable.

0x0

This is a shadow register for the FIFO enable bit (FCR[0]).

This can be used to remove the burden of having to store the

previously written value to the FCR in memory and having to

mask this value so that only the FIFO enable bit gets

updated.This enables/disables the transmit (XMIT) and

receive (RCVR) FIFOs. If this bit is set to zero (disabled)

after being enabled then both the XMIT and RCVR controller

portion of FIFOs are reset.

Table 81: UART_SRT_REG (0x5000109C)

Bit

Mode Symbol

Description

Reset

0x0

15:2

1:0

-

Reserved

R/W

UART_SHADOW_R

CVR_TRIGGER

Shadow RCVR Trigger.

0x0

This is a shadow register for the RCVR trigger bits

(FCR[7:6]). This can be used to remove the burden of having

to store the previously written value to the FCR in memory

and having to mask this value so that only the RCVR trigger

bit gets updated.

This is used to select the trigger level in the receiver FIFO at

which the Received Data Available Interrupt is generated. It

also determines when the dma_rx_req_n signal is asserted

when DMA Mode (FCR[3]) = 1. The following trigger levels

are supported:

00 = 1 character in the FIFO

01 = FIFO Â¼ full

10 = FIFO Â½ full

11 = FIFO 2 less than full

Table 82: UART_STET_REG (0x500010A0)

Bit

Mode Symbol

Description

Reset

0x0

15:2

1:0

-

Reserved

R/W

UART_SHADOW_TX Shadow TX Empty Trigger.

_EMPTY_TRIGGER This is a shadow register for the TX empty trigger bits

0x0

(FCR[5:4]). This can be used to remove the burden of having

to store the previously written value to the FCR in memory

and having to mask this value so that only the TX empty trig-

ger bit gets updated.

This is used to select the empty threshold level at which the

THRE Interrupts are generated when the mode is active.

The following trigger levels are supported:

00 = FIFO empty

01 = 2 characters in the FIFO

10 = FIFO Â¼ full

11 = FIFO Â½ full

Table 83: UART_HTX_REG (0x500010A4)

Bit

Mode Symbol

Description

Reset

15:1

-

Reserved

0x0

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Table 83: UART_HTX_REG (0x500010A4)

Bit

Mode Symbol

R/W UART_HALT_TX

Description

Reset

0

This register is use to halt transmissions for testing, so that

the transmit FIFO can be filled by the master when FIFOs

are implemented and enabled.

0x0

0 = Halt TX disabled

1 = Halt TX enabled

Note, if FIFOs are implemented and not enabled, the setting

of the halt TX register has no effect on operation.

Table 84: UART_CPR_REG (0x500010F4)

Bit

Mode Symbol

CPR

Description

Reset

15:0

R

Component Parameter Register

0x0

Table 85: UART_UCV_REG (0x500010F8)

Bit

Mode Symbol

UCV

Description

Reset

15:0

R

Component Version

0x33303

82A

Table 86: UART_CTR_REG (0x500010FC)

Bit

Mode Symbol

CTR

Description

Reset

15:0

R

Component Type Register

0x44570

110

Table 87: UART2_RBR_THR_DLL_REG (0x50001100)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

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Table 87: UART2_RBR_THR_DLL_REG (0x50001100)

Bit

Mode Symbol

R/W RBR_THR_DLL

Description

Reset

7:0

Receive Buffer Register: This register contains the data byte

received on the serial input port (sin) in UART mode or the

serial infrared input (sir_in) in infrared mode. The data in this

register is valid only if the Data Ready (DR) bit in the Line

status Register (LSR) is set. If FIFOs are disabled (FCR[0]

set to zero), the data in the RBR must be read before the

next data arrives, otherwise it will be overwritten, resulting in

an overrun error. If FIFOs are enabled (FCR[0] set to one),

this register accesses the head of the receive FIFO. If the

receive FIFO is full and this register is not read before the

next data character arrives, then the data already in the

FIFO will be preserved but any incoming data will be lost. An

overrun error will also occur. Transmit Holding Register: This

register contains data to be transmitted on the serial output

port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost. Divisor Latch (Low): This register makes up the lower 8-

bits of a 16-bit, read/write, Divisor Latch register that con-

tains the baud rate divisor for the UART. This register may

only be accessed when the DLAB bit (LCR[7]) is set. The

output baud rate is equal to the serial clock (sclk) frequency

divided by sixteen times the value of the baud rate divisor, as

follows: baud rate = (serial clock freq) / (16 * divisor) Note

that with the Divisor Latch Registers (DLL and DLH) set to

zero, the baud clock is disabled and no serial communica-

tions will occur. Also, once the DLL is set, at least 8 clock

cycles of the slowest DW_apb_uart clock should be allowed

to pass before transmitting or receiving data.

0x0

Table 88: UART2_IER_DLH_REG (0x50001104)

Bit

15:8

7

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

PTIME_DLH7

Interrupt Enable Register: PTIME, Programmable THRE

Interrupt Mode Enable. This is used to enable/disable the

generation of THRE Interrupt. 0 = disabled 1 = enabled Divi-

sor Latch (High): Bit[7] of the 8 bit DLH register.

0x0

6:4

3

-

Reserved

0x0

R/W

EDSSI_DLH3

Interrupt Enable Register: EDSSI, Enable Modem Status

Interrupt. This is used to enable/disable the generation of

Modem Status Interrupt. This is the fourth highest priority

interrupt. 0 = disabled 1 = enabled Divisor Latch (High):

Bit[3] of the 8 bit DLH register

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Table 88: UART2_IER_DLH_REG (0x50001104)

Bit

Mode Symbol

Description

Reset

2

R/W

ELSI_DHL2

Interrupt Enable Register: ELSI, Enable Receiver Line Sta-

tus Interrupt. This is used to enable/disable the generation of

Receiver Line Status Interrupt. This is the highest priority

interrupt. 0 = disabled 1 = enabled Divisor Latch (High):

Bit[2] of the 8 bit DLH register.

0x0

1

0

ETBEI_DLH1

ERBFI_DLH0

Interrupt Enable Register: ETBEI, Enable Transmit Holding

Register Empty Interrupt. This is used to enable/disable the

generation of Transmitter Holding Register Empty Interrupt.

This is the third highest priority interrupt. 0 = disabled 1 =

enabled Divisor Latch (High): Bit[1] of the 8 bit DLH register.

Interrupt Enable Register: ERBFI, Enable Received Data

Available Interrupt. This is used to enable/disable the gener-

ation of Received Data Available Interrupt and the Character

Timeout Interrupt (if in FIFO mode and FIFO's enabled).

These are the second highest priority interrupts. 0 = disabled

1 = enabled Divisor Latch (High): Bit[0] of the 8 bit DLH reg-

ister.

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Table 89: UART2_IIR_FCR_REG (0x50001108)

Bit

Mode Symbol

R/W IIR_FCR

Description

Reset

15:0

Interrupt Identification Register, reading this register; FIFO

Control Register, writing to this register. Interrupt Identifica-

tion Register: Bits[7:6], FIFO's Enabled (or FIFOSE): This is

used to indicate whether the FIFO's are enabled or disabled.

00 = disabled. 11 = enabled. Bits[3:0], Interrupt ID (or IID):

This indicates the highest priority pending interrupt which

can be one of the following types: 0000 = modem status.

0001 = no interrupt pending. 0010 = THR empty. 0100 =

received data available. 0110 = receiver line status. 0111 =

busy detect. 1100 = character timeout. Bits[7:6], RCVR Trig-

ger (or RT):. This is used to select the trigger level in the

receiver FIFO at which the Received Data Available Interrupt

will be generated. In auto flow control mode it is used to

determine when the rts_n signal will be de-asserted. It also

determines when the dma_rx_req_n signal will be asserted

when in certain modes of operation. The following trigger

levels are supported: 00 = 1 character in the FIFO 01 = FIFO

1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full Bits[5:4],

TX Empty Trigger (or TET): This is used to select the empty

threshold level at which the THRE Interrupts will be gener-

ated when the mode is active. It also determines when the

dma_tx_req_n signal will be asserted when in certain modes

of operation. The following trigger levels are supported: 00 =

FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full

11 = FIFO 1/2 full Bit[3], DMA Mode (or DMAM): This deter-

mines the DMA signalling mode used for the dma_tx_req_n

and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1

Bit[2], XMIT FIFO Reset (or XFIFOR): This resets the control

portion of the transmit FIFO and treats the FIFO as empty.

Note that this bit is 'self-clearing' and it is not necessary to

clear this bit. Bit[1], RCVR FIFO Reset (or RFIFOR): This

resets the control portion of the receive FIFO and treats the

FIFO as empty. Note that this bit is 'self-clearing' and it is not

necessary to clear this bit. Bit[0], FIFO Enable (or FIFOE):

This enables/disables the transmit (XMIT) and receive

(RCVR) FIFO's. Whenever the value of this bit is changed

both the XMIT and RCVR controller portion of FIFO's will be

reset.

0x0

Table 90: UART2_LCR_REG (0x5000110C)

Bit

15:8

7

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

UART_DLAB

Divisor Latch Access Bit.

0x0

This bit is used to enable reading and writing of the Divisor

Latch register (DLL and DLH) to set the baud rate of the

UART.

This bit must be cleared after initial baud rate setup in order

to access other registers.

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Table 90: UART2_LCR_REG (0x5000110C)

Bit

Mode Symbol

Description

Reset

6

R/W

UART_BC

Break Control Bit.

0x0

This is used to cause a break condition to be transmitted to

the receiving device. If set to one the serial output is forced

to the spacing (logic 0) state. When not in Loopback Mode,

as determined by MCR[4], the sout line is forced low until the

Break bit is cleared. If active (MCR[6] set to one) the

sir_out_n line is continuously pulsed. When in Loopback

Mode, the break condition is internally looped back to the

receiver and the sir_out_n line is forced low.

5

4

-

Reserved

0x0

R/W

UART_EPS

Even Parity Select.

This is used to select between even and odd parity, when

parity is enabled (PEN set to one). If set to one, an even

number of logic 1s is transmitted or checked. If set to zero,

an odd number of logic 1s is transmitted or checked.

3

2

R/W

UART_PEN

Parity Enable.

0x0

This bit is used to enable and disable parity generation and

detection in transmitted and received serial character

respectively.

0 = parity disabled

1 = parity enabled

UART_STOP

Number of stop bits.

This is used to select the number of stop bits per character

that the peripheral transmits and receives. If set to zero, one

stop bit is transmitted in the serial data.

If set to one and the data bits are set to 5 (LCR[1:0] set to

zero) one and a half stop bits is transmitted. Otherwise, two

stop bits are transmitted. Note that regardless of the number

of stop bits selected, the receiver checks only the first stop

bit.

0 = 1 stop bit

1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit

1:0

R/W

UART_DLS

Data Length Select.

0x0

This is used to select the number of data bits per character

that the peripheral transmits and receives. The number of bit

that may be selected areas follows:

00 = 5 bits

01 = 6 bits

10 = 7 bits

11 = 8 bits

Table 91: UART2_MCR_REG (0x50001110)

Bit

15:7

6

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

UART_SIRE

SIR Mode Enable.

0x0

This is used to enable/disable the IrDA SIR Mode features

as described in "IrDA 1.0 SIR Protocol" on page 53.

0 = IrDA SIR Mode disabled

1 = IrDA SIR Mode enabled

5

R/W

UART_AFCE

Auto Flow Control Enable.

0x0

When FIFOs are enabled and the Auto Flow Control Enable

(AFCE) bit is set, hardware Auto Flow Control is enabled via

CTS and RTS.

0 = Auto Flow Control Mode disabled

1 = Auto Flow Control Mode enabled

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Bluetooth Low Energy 4.2 SoC

Table 91: UART2_MCR_REG (0x50001110)

Bit

Mode Symbol

Description

Reset

4

R/W

UART_LB

LoopBack Bit.

0x0

This is used to put the UART into a diagnostic mode for test

purposes.

If operating in UART mode (SIR_MODE not active, MCR[6]

set to zero), data on the sout line is held high, while serial

data output is looped back to the sin line, internally. In this

mode all the interrupts are fully functional. Also, in loopback

mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n)

are disconnected and the modem control outputs (dtr_n,

rts_n, out1_n, out2_n) are looped back to the inputs, inter-

nally.

If operating in infrared mode (SIR_MODE active, MCR[6] set

to one), data on the sir_out_n line is held low, while serial

data output is inverted and looped back to the sir_in line.

3

2

1

R/W

UART_OUT2

UART_OUT1

UART_RTS

OUT2.

0x0

This is used to directly control the user-designated Output2

(out2_n) output. The value written to this location is inverted

and driven out on out2_n, that is:

0 = out2_n de-asserted (logic 1)

1 = out2_n asserted (logic 0)

Note that in Loopback mode (MCR[4] set to one), the out2_n

output is held inactive high while the value of this location is

internally looped back to an input.

OUT1.

This is used to directly control the user-designated Output1

(out1_n) output. The value written to this location is inverted

and driven out on out1_n, that is:

0 = out1_n de-asserted (logic 1)

1 = out1_n asserted (logic 0)

Note that in Loopback mode (MCR[4] set to one), the out1_n

output is held inactive high while the value of this location is

internally looped back to an input.

Request to Send.

This is used to directly control the Request to Send (rts_n)

output. The Request To Send (rts_n) output is used to inform

the modem or data set that the UART is ready to exchange

data.

When Auto Flow Control is disabled (MCR[5] set to zero),

the rts_n signal is set low by programming MCR[1] (RTS) to

a high. When Auto Flow Control is enabled (MCR[5] set to

one) and FIFOs are enabled (FCR[0] set to one), the rts_n

output is controlled in the same way, but is also gated with

the receiver FIFO threshold trigger (rts_n is inactive high

when above the threshold). The rts_n signal is de-asserted

when MCR[1] is set low.

Note that in Loopback mode (MCR[4] set to one), the rts_n

output is held inactive (high) while the value of this location is

internally looped back to an input.

0

-

Reserved

0x0

Table 92: UART2_LSR_REG (0x50001114)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

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Table 92: UART2_LSR_REG (0x50001114)

Bit

Mode Symbol

Description

Reset

7

R

UART_RFE

Receiver FIFO Error bit.

0x0

This bit is only relevant when FIFOs are enabled (FCR[0] set

to one). This is used to indicate if there is at least one parity

error, framing error, or break indication in the FIFO.

0 = no error in RX FIFO

1 = error in RX FIFO

This bit is cleared when the LSR is read and the character

with the error is at the top of the receiver FIFO and there are

no subsequent errors in the FIFO.

6

5

R

UART_TEMT

UART_THRE

Transmitter Empty bit.

0x1

If FIFOs enabled (FCR[0] set to one), this bit is set whenever

the Transmitter Shift Register and the FIFO are both empty.

If FIFOs are disabled, this bit is set whenever the Transmitter

Holding Register and the Transmitter Shift Register are both

empty.

Transmit Holding Register Empty bit.

If THRE mode is disabled (IER[7] set to zero) and regardless

of FIFO's being implemented/enabled or not, this bit indi-

cates that the THR or TX FIFO is empty.

This bit is set whenever data is transferred from the THR or

TX FIFO to the transmitter shift register and no new data has

been written to the THR or TX FIFO. This also causes a

THRE Interrupt to occur, if the THRE Interrupt is enabled. If

both modes are active (IER[7] set to one and FCR[0] set to

one respectively), the functionality is switched to indicate the

transmitter FIFO is full, and no longer controls THRE inter-

rupts, which are then controlled by the FCR[5:4] threshold

setting.

4

R

UART_B1

Break Interrupt bit.

0x0

This is used to indicate the detection of a break sequence on

the serial input data.

If in UART mode (SIR_MODE == Disabled), it is set when-

ever the serial input, sin, is held in a logic '0' state for longer

than the sum of start time + data bits + parity + stop bits.

If in infrared mode (SIR_MODE == Enabled), it is set when-

ever the serial input, sir_in, is continuously pulsed to logic '0'

for longer than the sum of start time + data bits + parity +

stop bits. A break condition on serial input causes one and

only one character, consisting of all zeros, to be received by

the UART.

In the FIFO mode, the character associated with the break

condition is carried through the FIFO and is revealed when

the character is at the top of the FIFO.

Reading the LSR clears the BI bit. In the non-FIFO mode,

the BI indication occurs immediately and persists until the

LSR is read.

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Table 92: UART2_LSR_REG (0x50001114)

Bit

Mode Symbol

Description

Reset

3

R

UART_FE

Framing Error bit.

0x0

This is used to indicate the occurrence of a framing error in

the receiver. A framing error occurs when the receiver does

not detect a valid STOP bit in the received data.

In the FIFO mode, since the framing error is associated with

a character received, it is revealed when the character with

the framing error is at the top of the FIFO.

When a framing error occurs, the UART tries to resynchro-

nize. It does this by assuming that the error was due to the

start bit of the next character and then continues receiving

the other bit i.e. data, and/or parity and stop. It should be

noted that the Framing Error (FE) bit (LSR[3]) is set if a

break interrupt has occurred, as indicated by Break Interrupt

(BI) bit (LSR[4]).

0 = no framing error

1 = framing error

Reading the LSR clears the FE bit.

2

R

UART_PE

Parity Error bit.

0x0

This is used to indicate the occurrence of a parity error in the

receiver if the Parity Enable (PEN) bit (LCR[3]) is set.

In the FIFO mode, since the parity error is associated with a

character received, it is revealed when the character with the

parity error arrives at the top of the FIFO.

It should be noted that the Parity Error (PE) bit (LSR[2]) is

set if a break interrupt has occurred, as indicated by Break

Interrupt (BI) bit (LSR[4]).

0 = no parity error

1 = parity error

Reading the LSR clears the PE bit.

1

R

UART_OE

Overrun error bit.

0x0

This is used to indicate the occurrence of an overrun error.

This occurs if a new data character was received before the

previous data was read.

In the non-FIFO mode, the OE bit is set when a new charac-

ter arrives in the receiver before the previous character was

read from the RBR. When this happens, the data in the RBR

is overwritten. In the FIFO mode, an overrun error occurs

when the FIFO is full and a new character arrives at the

receiver. The data in the FIFO is retained and the data in the

receive shift register is lost.

0 = no overrun error

1 = overrun error

Reading the LSR clears the OE bit.

0

R

UART_DR

Data Ready bit.

0x0

This is used to indicate that the receiver contains at least

one character in the RBR or the receiver FIFO.

0 = no data ready

1 = data ready

This bit is cleared when the RBR is read in non-FIFO mode,

or when the receiver FIFO is empty, in FIFO mode.

Table 93: UART2_MSR_REG (0x50001118)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

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Table 93: UART2_MSR_REG (0x50001118)

Bit

Mode Symbol

R UART_DCD

Description

Reset

0x0

7

Data Carrier Detect.

This is used to indicate the current state of the modem con-

trol line dcd_n. This bit is the complement of dcd_n. When

the Data Carrier Detect input (dcd_n) is asserted it is an indi-

cation that the carrier has been detected by the modem or

data set.

0 = dcd_n input is de-asserted (logic 1)

1 = dcd_n input is asserted (logic 0)

In Loopback Mode (MCR[4] set to one), DCD is the same as

MCR[3] (Out2).

6

R

UART_R1

Ring Indicator.

0x0

This is used to indicate the current state of the modem con-

trol line ri_n. This bit is the complement of ri_n. When the

Ring Indicator input (ri_n) is asserted it is an indication that a

telephone ringing signal has been received by the modem or

data set.

0 = ri_n input is de-asserted (logic 1)

1 = ri_n input is asserted (logic 0)

In Loopback Mode (MCR[4] set to one), RI is the same as

MCR[2] (Out1).

5

4

-

Reserved

0x0

R

UART_CTS

Clear to Send.

This is used to indicate the current state of the modem con-

trol line cts_n. This bit is the complement of cts_n. When the

Clear to Send input (cts_n) is asserted it is an indication that

the modem or data set is ready to exchange data with the

UART Ctrl.

0 = cts_n input is de-asserted (logic 1)

1 = cts_n input is asserted (logic 0)

In Loopback Mode (MCR[4] = 1), CTS is the same as

MCR[1] (RTS).

3

R

UART_DDCD

Delta Data Carrier Detect.

0x0

This is used to indicate that the modem control line dcd_n

has changed since the last time the MSR was read.

0 = no change on dcd_n since last read of MSR

1 = change on dcd_n since last read of MSR

Reading the MSR clears the DDCD bit. In Loopback Mode

(MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2).

Note, if the DDCD bit is not set and the dcd_n signal is

asserted (low) and a reset occurs (software or otherwise),

then the DDCD bit is set when the reset is removed if the

dcd_n signal remains asserted.

2

R

UART_TERI

Trailing Edge of Ring Indicator.

0x0

This is used to indicate that a change on the input ri_n (from

an active-low to an inactive-high state) has occurred since

the last time the MSR was read.

0 = no change on ri_n since last read of MSR

1 = change on ri_n since last read of MSR

Reading the MSR clears the TERI bit. In Loopback Mode

(MCR[4] = 1), TERI reflects when MCR[2] (Out1) has

changed state from a high to a low.

1

-

Reserved

0x0

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Table 93: UART2_MSR_REG (0x50001118)

Bit

Mode Symbol

UART_DCTS

Description

Reset

0

R

Delta Clear to Send.

0x0

This is used to indicate that the modem control line cts_n

has changed since the last time the MSR was read.

0 = no change on cts_n since last read of MSR

1 = change on cts_n since last read of MSR

Reading the MSR clears the DCTS bit. In Loopback Mode

(MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS).

Note, if the DCTS bit is not set and the cts_n signal is

asserted (low) and a reset occurs (software or otherwise),

then the DCTS bit is set when the reset is removed if the

cts_n signal remains asserted.

Table 94: UART2_SCR_REG (0x5000111C)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

UART_SCRATCH_P

AD

This register is for programmers to use as a temporary stor-

age space. It has no defined purpose in the UART Ctrl.

0x0

Table 95: UART2_LPDLL_REG (0x50001120)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

UART_LPDLL

This register makes up the lower 8-bits of a 16-bit, read/

write, Low Power Divisor Latch register that contains the

baud rate divisor for the UART, which must give a baud rate

of 115.2K. This is required for SIR Low Power (minimum

pulse width) detection at the receiver. This register may be

accessed only when the DLAB bit (LCR[7]) is set.

The output low-power baud rate is equal to the serial clock

(sclk) frequency divided by sixteen times the value of the

baud rate divisor, as follows:

0x0

Low power baud rate = (serial clock frequency)/(16* divisor)

Therefore, a divisor must be selected to give a baud rate of

115.2K.

NOTE: When the Low Power Divisor Latch registers (LPDLL

and LPDLH) are set to 0, the low-power baud clock is dis-

abled and no low-power pulse detection (or any pulse detec-

tion) occurs at the receiver. Also, once the LPDLL is set, at

least eight clock cycles of the slowest UART Ctrl clock

should be allowed to pass before transmitting or receiving

data.

Table 96: UART2_LPDLH_REG (0x50001124)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

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Table 96: UART2_LPDLH_REG (0x50001124)

Bit

Mode Symbol

R/W UART_LPDLH

Description

Reset

7:0

This register makes up the upper 8-bits of a 16-bit, read/

write, Low Power Divisor Latch register that contains the

baud rate divisor for the UART, which must give a baud rate

of 115.2K. This is required for SIR Low Power (minimum

pulse width) detection at the receiver. This register may be

accessed only when the DLAB bit (LCR[7]) is set.

The output low-power baud rate is equal to the serial clock

(sclk) frequency divided by sixteen times the value of the

baud rate divisor, as follows:

0x0

Low power baud rate = (serial clock frequency)/(16* divisor)

Therefore, a divisor must be selected to give a baud rate of

115.2K.

NOTE: When the Low Power Divisor Latch registers (LPDLL

and LPDLH) are set to 0, the low-power baud clock is dis-

abled and no low-power pulse detection (or any pulse detec-

tion) occurs at the receiver. Also, once the LPDLH is set, at

least eight clock cycles of the slowest UART Ctrl clock

should be allowed to pass before transmitting or receiving

data.

Table 97: UART2_SRBR_STHR0_REG (0x50001130)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

SRBR_STHRX

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

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Table 98: UART2_SRBR_STHR1_REG (0x50001134)

Bit

Mode Symbol

Description

Reset

15:8

7:0

-

Reserved

0x0

R/W

SRBR_STHRX

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

Table 99: UART2_SRBR_STHR2_REG (0x50001138)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

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Table 99: UART2_SRBR_STHR2_REG (0x50001138)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 100: UART2_SRBR_STHR3_REG (0x5000113C)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

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Table 100: UART2_SRBR_STHR3_REG (0x5000113C)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 101: UART2_SRBR_STHR4_REG (0x50001140)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

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Table 101: UART2_SRBR_STHR4_REG (0x50001140)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 102: UART2_SRBR_STHR5_REG (0x50001144)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

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FINAL

Bluetooth Low Energy 4.2 SoC

Table 102: UART2_SRBR_STHR5_REG (0x50001144)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 103: UART2_SRBR_STHR6_REG (0x50001148)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

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Bluetooth Low Energy 4.2 SoC

Table 103: UART2_SRBR_STHR6_REG (0x50001148)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 104: UART2_SRBR_STHR7_REG (0x5000114C)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

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Bluetooth Low Energy 4.2 SoC

Table 104: UART2_SRBR_STHR7_REG (0x5000114C)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 105: UART2_SRBR_STHR8_REG (0x50001150)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

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Bluetooth Low Energy 4.2 SoC

Table 105: UART2_SRBR_STHR8_REG (0x50001150)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 106: UART2_SRBR_STHR9_REG (0x50001154)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

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Bluetooth Low Energy 4.2 SoC

Table 106: UART2_SRBR_STHR9_REG (0x50001154)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 107: UART2_SRBR_STHR10_REG (0x50001158)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

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Bluetooth Low Energy 4.2 SoC

Table 107: UART2_SRBR_STHR10_REG (0x50001158)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 108: UART2_SRBR_STHR11_REG (0x5000115C)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

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FINAL

Bluetooth Low Energy 4.2 SoC

Table 108: UART2_SRBR_STHR11_REG (0x5000115C)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 109: UART2_SRBR_STHR12_REG (0x50001160)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

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FINAL

Bluetooth Low Energy 4.2 SoC

Table 109: UART2_SRBR_STHR12_REG (0x50001160)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 110: UART2_SRBR_STHR13_REG (0x50001164)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

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FINAL

Bluetooth Low Energy 4.2 SoC

Table 110: UART2_SRBR_STHR13_REG (0x50001164)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 111: UART2_SRBR_STHR14_REG (0x50001168)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

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Bluetooth Low Energy 4.2 SoC

Table 111: UART2_SRBR_STHR14_REG (0x50001168)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 112: UART2_SRBR_STHR15_REG (0x5000116C)

Bit

Mode Symbol

Description

Reset

15:8

-

Reserved

0x0

Datasheet

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FINAL

Bluetooth Low Energy 4.2 SoC

Table 112: UART2_SRBR_STHR15_REG (0x5000116C)

Bit

Mode Symbol

R/W SRBR_STHRX

Description

Reset

7:0

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

register contains the data byte received on the serial input

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the

Data Ready (DR) bit in the Line status Register (LSR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the

RBR must be read before the next data arrives, otherwise it

will be overwritten, resulting in an overrun error. If FIFOs are

enabled (FCR[0] set to one), this register accesses the head

of the receive FIFO. If the receive FIFO is full and this regis-

ter is not read before the next data character arrives, then

the data already in the FIFO will be preserved but any

incoming data will be lost. An overrun error will also occur.

Shadow Transmit Holding Register 0: This is a shadow reg-

ister for the THR and has been allocated sixteen 32-bit loca-

tions so as to accommodate burst accesses from the master.

This register contains data to be transmitted on the serial

output port (sout) in UART mode or the serial infrared output

(sir_out_n) in infrared mode. Data should only be written to

the THR when the THR Empty (THRE) bit (LSR[5]) is set. If

FIFO's are disabled (FCR[0] set to zero) and THRE is set,

writing a single character to the THR clears the THRE. Any

additional writes to the THR before the THRE is set again

causes the THR data to be overwritten. If FIFO's are enabled

(FCR[0] set to one) and THRE is set, x number of characters

of data may be written to the THR before the FIFO is full.

The number x (default=16) is determined by the value of

FIFO Depth that you set during configuration. Any attempt to

write data when the FIFO is full results in the write data being

lost.

0x0

Table 113: UART2_USR_REG (0x5000117C)

Bit

15:5

4

Mode Symbol

Description

Reset

0x0

-

Reserved

R

UART_RFF

Receive FIFO Full.

0x0

This is used to indicate that the receive FIFO is completely

full.

0 = Receive FIFO not full

1 = Receive FIFO Full

This bit is cleared when the RX FIFO is no longer full.

3

2

R

UART_RFNE

UART_TFE

Receive FIFO Not Empty.

This is used to indicate that the receive FIFO contains one or

more entries.

0 = Receive FIFO is empty

1 = Receive FIFO is not empty

0x0

0x1

This bit is cleared when the RX FIFO is empty.

Transmit FIFO Empty.

This is used to indicate that the transmit FIFO is completely

empty.

0 = Transmit FIFO is not empty

1 = Transmit FIFO is empty

This bit is cleared when the TX FIFO is no longer empty.

Datasheet

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Bluetooth Low Energy 4.2 SoC

Table 113: UART2_USR_REG (0x5000117C)

Bit

Mode Symbol

Description

Reset

1

R

UART_TFNF

Transmit FIFO Not Full.

0x1

This is used to indicate that the transmit FIFO in not full.

0 = Transmit FIFO is full

1 = Transmit FIFO is not full

This bit is cleared when the TX FIFO is full.

0

-

Reserved

0x0

Table 114: UART2_TFL_REG (0x50001180)

Bit

Mode Symbol

UART_TRANSMIT_F

IFO_LEVEL

Description

Reset

15:0

R

Transmit FIFO Level.

This is indicates the number of data entries in the transmit

FIFO.

0x0

Table 115: UART2_RFL_REG (0x50001184)

Bit

Mode Symbol

UART_RECEIVE_FI

FO_LEVEL

Description

Reset

15:0

R

Receive FIFO Level.

This is indicates the number of data entries in the receive

FIFO.

0x0

Table 116: UART2_SRR_REG (0x50001188)

Bit

15:3

2

Mode Symbol

Description

Reset

0x0

-

Reserved

W

UART_XFR

XMIT FIFO Reset.

0x0

This is a shadow register for the XMIT FIFO Reset bit

(FCR[2]). This can be used to remove the burden on soft-

ware having to store previously written FCR values (which

are pretty static) just to reset the transmit FIFO. This resets

the control portion of the transmit FIFO and treats the FIFO

as empty. Note that this bit is 'self-clearing'. It is not neces-

sary to clear this bit.

1

W

UART_RFR

RCVR FIFO Reset.

0x0

This is a shadow register for the RCVR FIFO Reset bit

(FCR[1]). This can be used to remove the burden on soft-

ware having to store previously written FCR values (which

are pretty static) just to reset the receive FIFO This resets

the control portion of the receive FIFO and treats the FIFO

as empty.

Note that this bit is 'self-clearing'. It is not necessary to clear

this bit.

0

W

UART_UR

UART Reset. This asynchronously resets the UART Ctrl and

synchronously removes the reset assertion. For a two clock

implementation both pclk and sclk domains are reset.

0x0

Table 117: UART2_SRTS_REG (0x5000118C)

Bit

Mode Symbol

Description

Reset

15:1

-

Reserved

0x0

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Table 117: UART2_SRTS_REG (0x5000118C)

Bit

Mode Symbol

R/W UART_SHADOW_R

EQUEST_TO_SEND

Description

Reset

0

Shadow Request to Send.

0x0

This is a shadow register for the RTS bit (MCR[1]), this can

be used to remove the burden of having to perform a read-

modify-write on the MCR. This is used to directly control the

Request to Send (rts_n) output. The Request To Send

(rts_n) output is used to inform the modem or data set that

the UART Ctrl is ready to exchange data.

When Auto Flow Control is disabled (MCR[5] = 0), the rts_n

signal is set low by programming MCR[1] (RTS) to a high.

When Auto Flow Control is enabled (MCR[5] = 1) and FIFOs

are enabled (FCR[0] = 1), the rts_n output is controlled in the

same way, but is also gated with the receiver FIFO threshold

trigger (rts_n is inactive high when above the threshold).

Note that in Loopback mode (MCR[4] = 1), the rts_n output is

held inactive-high while the value of this location is internally

looped back to an input.

Table 118: UART2_SBCR_REG (0x50001190)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

UART_SHADOW_B

REAK_CONTROL

Shadow Break Control Bit.

0x0

This is a shadow register for the Break bit (LCR[6]), this can

be used to remove the burden of having to performing a read

modify write on the LCR. This is used to cause a break con-

dition to be transmitted to the receiving device.

If set to one the serial output is forced to the spacing (logic 0)

state. When not in Loopback Mode, as determined by

MCR[4], the sout line is forced low until the Break bit is

cleared.

If SIR_MODE active (MCR[6] = 1) the sir_out_n line is con-

tinuously pulsed. When in Loopback Mode, the break condi-

tion is internally looped back to the receiver.

Table 119: UART2_SDMAM_REG (0x50001194)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

UART_SHADOW_D

MA_MODE

Shadow DMA Mode.

0x0

This is a shadow register for the DMA mode bit (FCR[3]).

This can be used to remove the burden of having to store the

previously written value to the FCR in memory and having to

mask this value so that only the DMA Mode bit gets updated.

This determines the DMA signalling mode used for the

dma_tx_req_n and dma_rx_req_n output signals.

0 = mode 0

1 = mode 1

Table 120: UART2_SFE_REG (0x50001198)

Bit

Mode Symbol

Description

Reset

15:1

-

Reserved

0x0

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Table 120: UART2_SFE_REG (0x50001198)

Bit

Mode Symbol

R/W UART_SHADOW_FI

FO_ENABLE

Description

Reset

0

Shadow FIFO Enable.

0x0

This is a shadow register for the FIFO enable bit (FCR[0]).

This can be used to remove the burden of having to store the

previously written value to the FCR in memory and having to

mask this value so that only the FIFO enable bit gets

updated.This enables/disables the transmit (XMIT) and

receive (RCVR) FIFOs. If this bit is set to zero (disabled)

after being enabled then both the XMIT and RCVR controller

portion of FIFOs are reset.

Table 121: UART2_SRT_REG (0x5000119C)

Bit

Mode Symbol

Description

Reset

0x0

15:2

1:0

-

Reserved

R/W

UART_SHADOW_R

CVR_TRIGGER

Shadow RCVR Trigger.

0x0

This is a shadow register for the RCVR trigger bits

(FCR[7:6]). This can be used to remove the burden of having

to store the previously written value to the FCR in memory

and having to mask this value so that only the RCVR trigger

bit gets updated.

This is used to select the trigger level in the receiver FIFO at

which the Received Data Available Interrupt is generated. It

also determines when the dma_rx_req_n signal is asserted

when DMA Mode (FCR[3]) = 1. The following trigger levels

are supported:

00 = 1 character in the FIFO

01 = FIFO Â¼ full

10 = FIFO Â½ full

11 = FIFO 2 less than full

Table 122: UART2_STET_REG (0x500011A0)

Bit

Mode Symbol

Description

Reset

0x0

15:2

1:0

-

Reserved

R/W

UART_SHADOW_TX Shadow TX Empty Trigger.

_EMPTY_TRIGGER This is a shadow register for the TX empty trigger bits

0x0

(FCR[5:4]). This can be used to remove the burden of having

to store the previously written value to the FCR in memory

and having to mask this value so that only the TX empty trig-

ger bit gets updated.

This is used to select the empty threshold level at which the

THRE Interrupts are generated when the mode is active.

The following trigger levels are supported:

00 = FIFO empty

01 = 2 characters in the FIFO

10 = FIFO Â¼ full

11 = FIFO Â½ full

Table 123: UART2_HTX_REG (0x500011A4)

Bit

Mode Symbol

Description

Reset

15:1

-

Reserved

0x0

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Table 123: UART2_HTX_REG (0x500011A4)

Bit

Mode Symbol

R/W UART_HALT_TX

Description

Reset

0

This register is use to halt transmissions for testing, so that

the transmit FIFO can be filled by the master when FIFOs

are implemented and enabled.

0x0

0 = Halt TX disabled

1 = Halt TX enabled

Note, if FIFOs are implemented and not enabled, the setting

of the halt TX register has no effect on operation.

Table 124: UART2_CPR_REG (0x500011F4)

Bit

Mode Symbol

CPR

Description

Reset

15:0

R

Component Parameter Register

0x0

Table 125: UART2_UCV_REG (0x500011F8)

Bit

Mode Symbol

UCV

Description

Reset

15:0

R

Component Version

0x33303

82A

Table 126: UART2_CTR_REG (0x500011FC)

Bit

Mode Symbol

CTR

Description

Reset

15:0

R

Component Type Register

0x44570

110

Table 127: SPI_CTRL_REG (0x50001200)

Bit

Mode Symbol

Description

Reset

15

R/W

SPI_EN_CTRL

0 = SPI_EN pin disabled in slave mode. Pin SPI_EN is don't

0x0

care.

1 = SPI_EN pin enabled in slave mode.

14

13

R/W

R

SPI_MINT

0 = Disable SPI_INT_BIT to the Interrupt Controller

1 = Enable SPI_INT_BIT to the Interrupt Controller

0x0

SPI_INT_BIT

0 = RX Register or FIFO is empty.

1 = SPI interrupt. Data has been transmitted and received-

Must be reset by SW by writing to SPI_CLEAR_INT_REG.

12

11

10

9

R

SPI_DI

Returns the actual value of pin SPI_DIN (delayed with two

internal SPI clock cycles)

0x0

R

SPI_TXH

0 = TX-FIFO is not full, data can be written.

1 = TX-FIFO is full, data can not be written.

R/W

SPI_FORCE_DO

SPI_RST

0 = normal operation

1 = Force SPIDO output level to value of SPI_DO.

0 = normal operation

1 = Reset SPI. Same function as SPI_ON except that inter-

nal clock remain active.

8:7

R/W

SPI_WORD

00 = 8 bits mode, only SPI_RX_TX_REG0 used

01 = 16 bit mode, only SPI_RX_TX_REG0 used

10 = 32 bits mode, SPI_RX_TX_REG0 &

SPI_RX_TX_REG1 used

0x0

11 = 9 bits mode. Only valid in master mode.

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Table 127: SPI_CTRL_REG (0x50001200)

Bit

Mode Symbol

Description

Reset

6

R/W

SPI_SMN

Master/slave mode

0 = Master,

0x0

1 = Slave(SPI1 only)

5

R/W

SPI_DO

Pin SPI_DO output level when SPI is idle or when

SPI_FORCE_DO=1

0x0

4:3

SPI_CLK

Select SPI_CLK clock frequency in master mode:00 =

(XTAL) / (CLK_PER_REG *8)

01 = (XTAL) / (CLK_PER_REG *4)

10 = (XTAL) / (CLK_PER_REG *2)

11 = (XTAL) / (CLK_PER_REG *14)

2

R/W

SPI_POL

Select SPI_CLK polarity.

0 = SPI_CLK is initially low.

1 = SPI_CLK is initially high.

0x0

1

0

R/W

SPI_PHA

SPI_ON

Select SPI_CLK phase. See functional timing diagrams in

SPI chapter

0x0

0 = SPI Module switched off (power saving). Everything is

reset except SPI_CTRL_REG0 and SPI_CTRL_REG1.

When this bit is cleared the SPI will remain active in master

mode until the shift register and holding register are both

empty.

1 = SPI Module switched on. Should only be set after all con-

trol bits have their desired values. So two writes are needed!

Table 128: SPI_RX_TX_REG0 (0x50001202)

Bit

Mode Symbol

R0/W SPI_DATA0

Description

Reset

15:0

Write: SPI_TX_REG0 output register 0 (TX-FIFO)

Read: SPI_RX_REG0 input register 0 (RX-FIFO)

In 8 or 9 bits mode bits 15 to 8 are not used, they contain old

data.

0x0

Table 129: SPI_RX_TX_REG1 (0x50001204)

Bit

Mode Symbol

R0/W SPI_DATA1

Description

Reset

15:0

Write: SPI_TX_REG1 output register 1 (MSB's of TX-FIFO)

Read: SPI_RX_REG1 input register 1 (MSB's of RX-FIFO)

In 8 or 9 or 16 bits mode bits this register is not used.

0x0

Table 130: SPI_CLEAR_INT_REG (0x50001206)

Bit

Mode Symbol

R0/W SPI_CLEAR_INT

Description

Reset

15:0

Writing any value to this register will clear the

SPI_CTRL_REG[SPI_INT_BIT]

Reading returns 0.

0x0

Table 131: SPI_CTRL_REG1 (0x50001208)

Bit

15:5

4

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

SPI_9BIT_VAL

Determines the value of the first bit in 9 bits SPI mode.

0x0

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Table 131: SPI_CTRL_REG1 (0x50001208)

Bit

Mode Symbol

Description

Reset

3

R

SPI_BUSY

0 = The SPI is not busy with a transfer. This means that

either no TX-data is available or that the transfers have been

suspended due to a full RX-FIFO. The

0x0

SPIx_CTRL_REG0[SPI_INT_BIT] can be used to distinguish

between these situations.

1 = The SPI is busy with a transfer.

2

R/W

SPI_PRIORITY

0 = The SPI has low priority, the DMA request signals are

reset after the corresponding acknowledge.

1 = The SPI has high priority, DMA request signals remain

active until the FIFOS are filled/emptied, so the DMA holds

the AHB bus.

0x0

0x3

1:0

SPI_FIFO_MODE

0: TX-FIFO and RX-FIFO used (Bidirectional mode).

1: RX-FIFO used (Read Only Mode) TX-FIFO single depth,

no flow control

2: TX-FIFO used (Write Only Mode), RX-FIFO single depth,

no flow control

3: No FIFOs used (backwards compatible mode)

Table 132: I2C_CON_REG (0x50001300)

Bit

15:7

6

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

I2C_SLAVE_DISABL

E

Slave enabled or disabled after reset is applied, which

means software does not have to configure the slave.

0=slave is enabled

0x1

1=slave is disabled

Software should ensure that if this bit is written with '0', then

bit 0 should also be written with a '0'.

5

4

3

R/W

I2C_RESTART_EN

Determines whether RESTART conditions may be sent

when acting as a master

0= disable

0x1

1=enable

I2C_10BITADDR_MA Controls whether the controller starts its transfers in 7- or 10- 0x1

STER

bit addressing mode when acting as a master.

0= 7-bit addressing

1= 10-bit addressing

I2C_10BITADDR_SL

AVE

When acting as a slave, this bit controls whether the control- 0x1

ler responds to 7- or 10-bit addresses.

0= 7-bit addressing

1= 10-bit addressing

2:1

0

R/W

I2C_SPEED

These bits control at which speed the controller operates.

1= standard mode (100 kbit/s)

2= fast mode (400 kbit/s)

0x2

0x1

I2C_MASTER_MOD

E

This bit controls whether the controller master is enabled.

0= master disabled

1= master enabled

Software should ensure that if this bit is written with '1' then

bit 6 should also be written with a '1'.

Table 133: I2C_TAR_REG (0x50001304)

Bit

Mode Symbol

Description

Reset

15:12

-

Reserved

0x0

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Table 133: I2C_TAR_REG (0x50001304)

Bit

Mode Symbol

Description

Reset

11

R/W

SPECIAL

This bit indicates whether software performs a General Call

0x0

or

START BYTE command.

0: ignore bit 10 GC_OR_START and use IC_TAR normally

1: perform special I2C command as specified in

GC_OR_START

bit

10

R/W

GC_OR_START

If bit 11 (SPECIAL) is set to 1, then this bit indicates whether

a General Call or START byte command is to be performed

by the controller.

0x0

0: General Call Address - after issuing a General Call, only

writes may be performed. Attempting to issue a read com-

mand results in setting bit 6 (TX_ABRT) of the

IC_RAW_INTR_STAT register. The controller remains in

General Call mode until the SPECIAL bit value (bit 11) is

cleared.

1: START BYTE

9:0

R/W

IC_TAR

This is the target address for any master transaction. When

transmitting a General Call, these bits are ignored. To gener-

ate a START BYTE, the CPU needs to write only once into

these bits.

0x55

Note: If the IC_TAR and IC_SAR are the same, loopback

exists but the FIFOs are shared between master and slave,

so full loopback is not feasible. Only one direction loopback

mode is supported (simplex), not duplex. A master cannot

transmit to itself; it can transmit to only a slave

Table 134: I2C_SAR_REG (0x50001308)

Bit

Mode Symbol

Description

Reset

15:10

9:0

-

Reserved

0x0

R/W

IC_SAR

The IC_SAR holds the slave address when the I2C is operat- 0x55

ing as a slave. For 7-bit addressing, only IC_SAR[6:0] is

used. This register can be written only when the I2C inter-

face is disabled, which corresponds to the IC_ENABLE reg-

ister being set to 0. Writes at other times have no effect.

Table 135: I2C_DATA_CMD_REG (0x50001310)

Bit

Mode Symbol

Description

Reset

15:9

-

Reserved

0x0

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Table 135: I2C_DATA_CMD_REG (0x50001310)

Bit

Mode Symbol

R/W CMD

Description

Reset

0x0

8

This bit controls whether a read or a write is performed. This

bit does not control the direction when the I2C Ctrl acts as a

slave. It controls only the direction when it acts as a master.

1 = Read

0 = Write

When a command is entered in the TX FIFO, this bit distin-

guishes the write and read commands. In slave-receiver

mode, this bit is a "don't care" because writes to this register

are not required. In slave-transmitter mode, a "0" indicates

that CPU data is to be transmitted and as DAT or

IC_DATA_CMD[7:0]. When programming this bit, you should

remember the following: attempting to perform a read opera-

tion after a General Call command has been sent results in a

TX_ABRT interrupt (bit 6 of the

I2C_RAW_INTR_STAT_REG), unless bit 11 (SPECIAL) in

the I2C_TAR register has been cleared.

If a "1" is written to this bit after receiving a RD_REQ inter-

rupt, then a TX_ABRT interrupt occurs.

NOTE: It is possible that while attempting a master I2C read

transfer on the controller, a RD_REQ interrupt may have

occurred simultaneously due to a remote I2C master

addressing the controller. In this type of scenario, it ignores

the I2C_DATA_CMD write, generates a TX_ABRT interrupt,

and waits to service the RD_REQ interrupt

7:0

R/W

DAT

This register contains the data to be transmitted or received

on the I2C bus. If you are writing to this register and want to

perform a read, bits 7:0 (DAT) are ignored by the controller.

However, when you read this register, these bits return the

value of data received on the controller's interface.

0x0

Table 136: I2C_SS_SCL_HCNT_REG (0x50001314)

Bit

Mode Symbol

R/W IC_SS_SCL_HCNT

Description

Reset

15:0

This register must be set before any I2C bus transaction can

take place to ensure proper I/O timing. This register sets the

SCL clock high-period count for standard speed. This regis-

ter can be written only when the I2C interface is disabled

which corresponds to the IC_ENABLE register being set to

0. Writes at other

0x48

times have no effect.

The minimum valid value is 6; hardware prevents values less

than this being written, and if attempted results in 6 being

set.

NOTE: This register must not be programmed to a value

higher than 65525, because the controller uses a 16-bit

counter to flag an I2C bus idle condition when this counter

reaches a value of IC_SS_SCL_HCNT + 10.

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Table 137: I2C_SS_SCL_LCNT_REG (0x50001318)

Bit

Mode Symbol

R/W IC_SS_SCL_LCNT

Description

Reset

15:0

This register must be set before any I2C bus transaction can

take place to ensure proper I/O timing. This register sets the

SCL clock low period count for standard speed.

This register can be written only when the I2C interface is

disabled which corresponds to the I2C_ENABLE register

being set to 0. Writes at other times have no effect.

The minimum valid value is 8; hardware prevents values less

than this being written, and if attempted, results in 8 being

set.

0x4F

Table 138: I2C_FS_SCL_HCNT_REG (0x5000131C)

Bit

Mode Symbol

R/W IC_FS_SCL_HCNT

Description

Reset

15:0

This register must be set before any I2C bus transaction can

take place to ensure proper I/O timing. This register sets the

SCL clock high-period count for fast speed. It is used in high-

speed mode to send the Master Code and START BYTE or

General CALL. This register can be written only when the

I2C interface is disabled, which corresponds to the

I2C_ENABLE register being set to 0. Writes at other times

have no effect.

0x8

The minimum valid value is 6; hardware prevents values less

than this being written, and if attempted results in 6 being

set.

Table 139: I2C_FS_SCL_LCNT_REG (0x50001320)

Bit

Mode Symbol

R/W IC_FS_SCL_LCNT

Description

Reset

15:0

This register must be set before any I2C bus transaction can

take place to ensure proper I/O timing. This register sets the

SCL clock low-period count for fast speed. It is used in high-

speed mode to send the Master Code and START BYTE or

General CALL. This register can be written only when the

I2C interface is disabled, which corresponds to the

I2C_ENABLE register being set to 0. Writes at other times

have no effect.

0x17

The minimum valid value is 8; hardware prevents values less

than this being written, and if attempted results in 8 being

set. For designs with APB_DATA_WIDTH = 8 the order of

programming is important to ensure the correct operation of

the controller. The lower byte must be programmed first.

Then the upper byte is programmed.

Table 140: I2C_INTR_STAT_REG (0x5000132C)

Bit

Mode Symbol

Description

Reset

0x0

15:12

11

-

Reserved

R

R_GEN_CALL

Set only when a General Call address is received and it is

acknowledged. It stays set until it is cleared either by dis-

abling controller or when the CPU reads bit 0 of the

I2C_CLR_GEN_CALL register. The controller stores the

received data in the Rx buffer.

0x0

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Table 140: I2C_INTR_STAT_REG (0x5000132C)

Bit

Mode Symbol

Description

Reset

10

R

R_START_DET

Indicates whether a START or RESTART condition has

occurred on the I2C interface regardless of whether control-

ler is operating in slave or master mode.

0x0

9

8

R_STOP_DET

R_ACTIVITY

Indicates whether a STOP condition has occurred on the I2C

interface regardless of whether controller is operating in

slave or master mode.

This bit captures I2C Ctrl activity and stays set until it is

cleared. There are four ways to clear it:

=> Disabling the I2C Ctrl

=> Reading the IC_CLR_ACTIVITY register

=> Reading the IC_CLR_INTR register

=> System reset

Once this bit is set, it stays set unless one of the four meth-

ods is used to clear it. Even if the controller module is idle,

this bit remains set until cleared, indicating that there was

activity on the bus.

7

6

R

R_RX_DONE

R_TX_ABRT

When the controller is acting as a slave-transmitter, this bit is

set to 1 if the master does not acknowledge a transmitted

byte. This occurs on the last byte of the transmission, indi-

cating that the transmission is done.

0x0

This bit indicates if the controller, as an I2C transmitter, is

unable to complete the intended actions on the contents of

the transmit FIFO. This situation can occur both as an I2C

master or an I2C slave, and is referred to as a "transmit

abort".

When this bit is set to 1, the I2C_TX_ABRT_SOURCE regis-

ter indicates the reason why the transmit abort takes places.

NOTE: The controller flushes/resets/empties the TX FIFO

whenever this bit is set. The TX FIFO remains in this flushed

state until the register I2C_CLR_TX_ABRT is read. Once

this read is performed, the TX FIFO is then ready to accept

more data bytes from the APB interface.

5

R

R_RD_REQ

This bit is set to 1 when the controller is acting as a slave

and another I2C master is attempting to read data from the

controller. The controller holds the I2C bus in a wait state

(SCL=0) until this interrupt is serviced, which means that the

slave has been addressed by a remote master that is asking

for data to be transferred. The processor must respond to

this interrupt and then write the requested data to the

I2C_DATA_CMD register. This bit is set to 0 just after the

processor reads the I2C_CLR_RD_REQ register

0x0

4

3

R

R_TX_EMPTY

This bit is set to 1 when the transmit buffer is at or below the

threshold value set in the I2C_TX_TL register. It is automati-

cally cleared by hardware when the buffer level goes above

the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO

is flushed and held in reset. There the TX FIFO looks like it

has no data within it, so this bit is set to 1, provided there is

activity in the master or slave state machines. When there is

no longer activity, then with ic_en=0, this bit is set to 0.

0x0

R_TX_OVER

Set during transmit if the transmit buffer is filled to 32 and the

processor attempts to issue another I2C command by writing

to the IC_DATA_CMD register. When the module is disabled,

this bit keeps its level until the master or slave state

machines go into idle, and when ic_en goes to 0, this inter-

rupt is cleared

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Table 140: I2C_INTR_STAT_REG (0x5000132C)

Bit

Mode Symbol

Description

Reset

0x0

2

R

R_RX_FULL

Set when the receive buffer reaches or goes above the

RX_TL threshold in the I2C_RX_TL register. It is automati-

cally cleared by hardware when buffer level goes below the

threshold. If the module is disabled (I2C_ENABLE[0]=0), the

RX FIFO is flushed and held in reset; therefore the RX FIFO

is not full. So this bit is cleared once the I2C_ENABLE bit 0 is

programmed with a 0, regardless of the activity that contin-

ues.

1

0

R

R_RX_OVER

Set if the receive buffer is completely filled to 32 and an addi- 0x0

tional byte is received from an external I2C device. The con-

troller acknowledges this, but any data bytes received after

the FIFO is full are lost. If the module is disabled

(I2C_ENABLE[0]=0), this bit keeps its level until the master

or slave state machines go into idle, and when ic_en goes to

0, this interrupt is cleared.

R_RX_UNDER

Set if the processor attempts to read the receive buffer when

it is empty by reading from the IC_DATA_CMD register. If the

module is disabled (I2C_ENABLE[0]=0), this bit keeps its

level until the master or slave state machines go into idle,

and when ic_en goes to 0, this interrupt is cleared.

0x0

Table 141: I2C_INTR_MASK_REG (0x50001330)

Bit

Mode Symbol

Description

Reset

0x0

15:12

11

-

Reserved

R/W

M_GEN_CALL

These bits mask their corresponding interrupt status bits in

the I2C_INTR_STAT register.

0x1

10

9

8

7

6

5

4

3

2

1

0

R/W

M_START_DET

M_STOP_DET

M_ACTIVITY

M_RX_DONE

M_TX_ABRT

M_RD_REQ

These bits mask their corresponding interrupt status bits in

the I2C_INTR_STAT register.

0x0

0x1

These bits mask their corresponding interrupt status bits in

the I2C_INTR_STAT register.

These bits mask their corresponding interrupt status bits in

the I2C_INTR_STAT register.

These bits mask their corresponding interrupt status bits in

the I2C_INTR_STAT register.

These bits mask their corresponding interrupt status bits in

the I2C_INTR_STAT register.

These bits mask their corresponding interrupt status bits in

the I2C_INTR_STAT register.

M_TX_EMPTY

M_TX_OVER

M_RX_FULL

M_RX_OVER

M_RX_UNDER

These bits mask their corresponding interrupt status bits in

the I2C_INTR_STAT register.

These bits mask their corresponding interrupt status bits in

the I2C_INTR_STAT register.

These bits mask their corresponding interrupt status bits in

the I2C_INTR_STAT register.

These bits mask their corresponding interrupt status bits in

the I2C_INTR_STAT register.

These bits mask their corresponding interrupt status bits in

the I2C_INTR_STAT register.

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Table 142: I2C_RAW_INTR_STAT_REG (0x50001334)

Bit

Mode Symbol

Description

Reset

15:12

11

-

Reserved

0x0

R

GEN_CALL

Set only when a General Call address is received and it is

acknowledged. It stays set until it is cleared either by dis-

abling controller or when the CPU reads bit 0 of the

I2C_CLR_GEN_CALL register. I2C Ctrl stores the received

data in the Rx buffer.

10

9

R

START_DET

STOP_DET

ACTIVITY

Indicates whether a START or RESTART condition has

occurred on the I2C interface regardless of whether control-

ler is operating in slave or master mode.

0x0

Indicates whether a STOP condition has occurred on the I2C

interface regardless of whether controller is operating in

slave or master mode.

8

This bit captures I2C Ctrl activity and stays set until it is

cleared. There are four ways to clear it:

=> Disabling the I2C Ctrl

=> Reading the IC_CLR_ACTIVITY register

=> Reading the IC_CLR_INTR register

=> System reset

Once this bit is set, it stays set unless one of the four meth-

ods is used to clear it. Even if the controller module is idle,

this bit remains set until cleared, indicating that there was

activity on the bus.

7

6

R

RX_DONE

TX_ABRT

When the controller is acting as a slave-transmitter, this bit is

set to 1 if the master does not acknowledge a transmitted

byte. This occurs on the last byte of the transmission, indi-

cating that the transmission is done.

0x0

This bit indicates if the controller, as an I2C transmitter, is

unable to complete the intended actions on the contents of

the transmit FIFO. This situation can occur both as an I2C

master or an I2C slave, and is referred to as a "transmit

abort".

When this bit is set to 1, the I2C_TX_ABRT_SOURCE regis-

ter indicates the reason why the transmit abort takes places.

NOTE: The controller flushes/resets/empties the TX FIFO

whenever this bit is set. The TX FIFO remains in this flushed

state until the register I2C_CLR_TX_ABRT is read. Once

this read is performed, the TX FIFO is then ready to accept

more data bytes from the APB interface.

5

R

RD_REQ

This bit is set to 1 when I2C Ctrl is acting as a slave and

another I2C master is attempting to read data from the con-

troller. The controller holds the I2C bus in a wait state

(SCL=0) until this interrupt is serviced, which means that the

slave has been addressed by a remote master that is asking

for data to be transferred. The processor must respond to

this interrupt and then write the requested data to the

I2C_DATA_CMD register. This bit is set to 0 just after the

processor reads the I2C_CLR_RD_REQ register

0x0

4

R

TX_EMPTY

This bit is set to 1 when the transmit buffer is at or below the

threshold value set in the I2C_TX_TL register. It is automati-

cally cleared by hardware when the buffer level goes above

the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO

is flushed and held in reset. There the TX FIFO looks like it

has no data within it, so this bit is set to 1, provided there is

activity in the master or slave state machines. When there is

no longer activity, then with ic_en=0, this bit is set to 0.

0x0

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Table 142: I2C_RAW_INTR_STAT_REG (0x50001334)

Bit

Mode Symbol

Description

Reset

3

R

TX_OVER

Set during transmit if the transmit buffer is filled to 32 and the

processor attempts to issue another I2C command by writing

to the IC_DATA_CMD register. When the module is disabled,

this bit keeps its level until the master or slave state

machines go into idle, and when ic_en goes to 0, this inter-

rupt is cleared

0x0

2

R

RX_FULL

Set when the receive buffer reaches or goes above the

RX_TL threshold in the I2C_RX_TL register. It is automati-

cally cleared by hardware when buffer level goes below the

threshold. If the module is disabled (I2C_ENABLE[0]=0), the

RX FIFO is flushed and held in reset; therefore the RX FIFO

is not full. So this bit is cleared once the I2C_ENABLE bit 0 is

programmed with a 0, regardless of the activity that contin-

ues.

0x0

1

0

R

RX_OVER

Set if the receive buffer is completely filled to 32 and an addi- 0x0

tional byte is received from an external I2C device. The con-

troller acknowledges this, but any data bytes received after

the FIFO is full are lost. If the module is disabled

(I2C_ENABLE[0]=0), this bit keeps its level until the master

or slave state machines go into idle, and when ic_en goes to

0, this interrupt is cleared.

RX_UNDER

Set if the processor attempts to read the receive buffer when

it is empty by reading from the IC_DATA_CMD register. If the

module is disabled (I2C_ENABLE[0]=0), this bit keeps its

level until the master or slave state machines go into idle,

and when ic_en goes to 0, this interrupt is cleared.

0x0

Table 143: I2C_RX_TL_REG (0x50001338)

Bit

Mode Symbol

Description

Reset

0x0

15:5

4:0

-

Reserved

R/W

RX_TL

Receive FIFO Threshold Level Controls the level of entries

(or above) that triggers the RX_FULL interrupt (bit 2 in

I2C_RAW_INTR_STAT register). The valid range is 0-31,

with the additional restriction that hardware does not allow

this value to be set to a value larger than the depth of the

buffer. If an attempt is made to do that, the actual value set

will be the maximum depth of the buffer. A value of 0 sets the

threshold for 1 entry, and a value of 31 sets the threshold for

32 entries.

0x0

Table 144: I2C_TX_TL_REG (0x5000133C)

Bit

Mode Symbol

Description

Reset

0x0

15:5

4:0

-

Reserved

R/W

RX_TL

Transmit FIFO Threshold Level Controls the level of entries

(or below) that trigger the TX_EMPTY interrupt (bit 4 in

I2C_RAW_INTR_STAT register). The valid range is 0-31,

with the additional restriction that it may not be set to value

larger than the depth of the buffer. If an attempt is made to

do that, the actual value set will be the maximum depth of

the buffer. A value of 0 sets the threshold for 0 entries, and a

value of 31 sets the threshold for 32 entries..

0x0

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Table 145: I2C_CLR_INTR_REG (0x50001340)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R

CLR_INTR

Read this register to clear the combined interrupt, all individ- 0x0

ual interrupts, and the I2C_TX_ABRT_SOURCE register.

This bit does not clear hardware clearable interrupts but soft-

ware clearable interrupts. Refer to Bit 9 of the

I2C_TX_ABRT_SOURCE register for an exception to clear-

ing I2C_TX_ABRT_SOURCE

Table 146: I2C_CLR_RX_UNDER_REG (0x50001344)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R

CLR_RX_UNDER

Read this register to clear the RX_UNDER interrupt (bit 0) of

0x0

the

I2C_RAW_INTR_STAT register.

Table 147: I2C_CLR_RX_OVER_REG (0x50001348)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R

CLR_RX_OVER

Read this register to clear the RX_OVER interrupt (bit 1) of

0x0

the

I2C_RAW_INTR_STAT register.

Table 148: I2C_CLR_TX_OVER_REG (0x5000134C)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R

CLR_TX_OVER

Read this register to clear the TX_OVER interrupt (bit 3) of

the I2C_RAW_INTR_STAT register.

0x0

Table 149: I2C_CLR_RD_REQ_REG (0x50001350)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R

CLR_RD_REQ

Read this register to clear the RD_REQ interrupt (bit 5) of

the I2C_RAW_INTR_STAT register.

0x0

Table 150: I2C_CLR_TX_ABRT_REG (0x50001354)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R

CLR_TX_ABRT

Read this register to clear the TX_ABRT interrupt (bit 6) of

the

0x0

IC_RAW_INTR_STAT register, and the

I2C_TX_ABRT_SOURCE register. This also releases the TX

FIFO from the flushed/reset state, allowing more writes to

the TX FIFO. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE

register for an exception to clearing

IC_TX_ABRT_SOURCE.

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Table 151: I2C_CLR_RX_DONE_REG (0x50001358)

Bit

15:1

0

Mode Symbol

Description

Reset

-

Reserved

0x0

R

CLR_RX_DONE

Read this register to clear the RX_DONE interrupt (bit 7) of

the

I2C_RAW_INTR_STAT register.

Table 152: I2C_CLR_ACTIVITY_REG (0x5000135C)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R

CLR_ACTIVITY

Reading this register clears the ACTIVITY interrupt if the I2C

is not active anymore. If the I2C module is still active on the

bus, the ACTIVITY interrupt bit continues to be set. It is auto-

matically cleared by hardware if the module is disabled and if

there is no further activity on the bus. The value read from

this register to get status of the ACTIVITY interrupt (bit 8) of

the IC_RAW_INTR_STAT register

0x0

Table 153: I2C_CLR_STOP_DET_REG (0x50001360)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R

CLR_ACTIVITY

Reading this register clears the ACTIVITY interrupt if the I2C

is not active anymore. If the I2C module is still active on the

bus, the ACTIVITY interrupt bit continues to be set. It is auto-

matically cleared by hardware if the module is disabled and if

there is no further activity on the bus. The value read from

this register to get status of the ACTIVITY interrupt (bit 8) of

the IC_RAW_INTR_STAT register.

0x0

Table 154: I2C_CLR_START_DET_REG (0x50001364)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R

CLR_START_DET

Read this register to clear the START_DET interrupt (bit 10)

of the IC_RAW_INTR_STAT register.

0x0

Table 155: I2C_CLR_GEN_CALL_REG (0x50001368)

Bit

15:1

0

Mode Symbol

Description

Reset

-

Reserved

0x0

R

CLR_GEN_CALL

Read this register to clear the GEN_CALL interrupt (bit 11) of 0x0

I2C_RAW_INTR_STAT register.

Table 156: I2C_ENABLE_REG (0x5000136C)

Bit

Mode Symbol

Description

Reset

15:1

-

Reserved

0x0

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Table 156: I2C_ENABLE_REG (0x5000136C)

Bit

Mode Symbol

R/W CTRL_ENABLE

Description

Reset

0

Controls whether the controller is enabled.

0: Disables the controller (TX and RX FIFOs are held in an

erased state)

0x0

1: Enables the controller

Software can disable the controller while it is active. How-

ever, it is important that care be taken to ensure that the con-

troller is disabled properly. When the controller is disabled,

the following occurs:

* The TX FIFO and RX FIFO get flushed.

* Status bits in the IC_INTR_STAT register are still active

until the controller goes into IDLE state.

If the module is transmitting, it stops as well as deletes the

contents of the transmit buffer after the current transfer is

complete. If the module is receiving, the controller stops the

current transfer at the end of the current byte and does not

acknowledge the transfer.

There is a two ic_clk delay when enabling or disabling the

controller

Table 157: I2C_STATUS_REG (0x50001370)

Bit

15:7

6

Mode Symbol

Description

Reset

0x0

-

Reserved

R

SLV_ACTIVITY

Slave FSM Activity Status. When the Slave Finite State

Machine (FSM) is not in the IDLE state, this bit is set.

0: Slave FSM is in IDLE state so the Slave part of the con-

troller is not Active

0x0

1: Slave FSM is not in IDLE state so the Slave part of the

controller is Active

5

R

MST_ACTIVITY

Master FSM Activity Status. When the Master Finite State

Machine (FSM) is not in the IDLE state, this bit is set.

0: Master FSM is in IDLE state so the Master part of the con-

troller is not Active

0x0

1: Master FSM is not in IDLE state so the Master part of the

controller is Active

4

3

2

R

RFF

Receive FIFO Completely Full. When the receive FIFO is

completely full, this bit is set. When the receive FIFO con-

tains one or more empty location, this bit is cleared.

0: Receive FIFO is not full

0x0

0x1

1: Receive FIFO is full

RFNE

TFE

Receive FIFO Not Empty. This bit is set when the receive

FIFO contains one or more entries; it is cleared when the

receive FIFO is empty.

0: Receive FIFO is empty

1: Receive FIFO is not empty

Transmit FIFO Completely Empty. When the transmit FIFO is

completely empty, this bit is set. When it contains one or

more valid entries, this bit is cleared. This bit field does not

request an interrupt.

0: Transmit FIFO is not empty

1: Transmit FIFO is empty

1

R

TFNF

Transmit FIFO Not Full. Set when the transmit FIFO contains

one or more empty locations, and is cleared when the FIFO

is full.

0x1

0: Transmit FIFO is full

1: Transmit FIFO is not full

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Table 157: I2C_STATUS_REG (0x50001370)

Bit

Mode Symbol

I2C_ACTIVITY

Description

Reset

0

R

I2C Activity Status.

0x0

Table 158: I2C_TXFLR_REG (0x50001374)

Bit

Mode Symbol

Description

Reset

0x0

15:6

5:0

-

Reserved

R

TXFLR

Transmit FIFO Level. Contains the number of valid data

entries in the transmit FIFO. Size is constrained by the

TXFLR value

0x0

Table 159: I2C_RXFLR_REG (0x50001378)

Bit

Mode Symbol

Description

Reset

0x0

15:6

5:0

-

Reserved

R

RXFLR

Receive FIFO Level. Contains the number of valid data

entries in the receive FIFO. Size is constrained by the

RXFLR value

0x0

Table 160: I2C_SDA_HOLD_REG (0x5000137C)

Bit

Mode Symbol

R/W IC_SDA_HOLD

Description

Reset

15:0

SDA Hold time

0x1

Table 161: I2C_TX_ABRT_SOURCE_REG (0x50001380)

Bit

Mode Symbol

Description

Reset

15

R

ABRT_SLVRD_INTX

1: When the processor side responds to a slave mode

request for data to be transmitted to a remote master and

user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register

0x0

14

ABRT_SLV_ARBLOS 1: Slave lost the bus while transmitting data to a remote

0x0

T

master.

I2C_TX_ABRT_SOURCE[12] is set at the same time. Note:

Even though the slave never "owns" the bus, something

could go wrong on the bus. This is a fail safe check. For

instance, during a data transmission at the low-to-high tran-

sition of SCL, if what is on the data bus is not what is sup-

posed to be transmitted, then the controller no longer own

the bus.

13

12

R

ABRT_SLVFLUSH_T

XFIFO

1: Slave has received a read command and some data

exists in the TX FIFO so the slave issues a TX_ABRT inter-

rupt to flush old data in TX FIFO.

0x0

ARB_LOST

1: Master has lost arbitration, or if

I2C_TX_ABRT_SOURCE[14] is also set, then the slave

transmitter has lost arbitration. Note: I2C can be both master

and slave at the same time.

11

10

R

ABRT_MASTER_DIS 1: User tries to initiate a Master operation with the Master

mode disabled.

0x0

ABRT_10B_RD_NO

RSTRT

1: The restart is disabled (IC_RESTART_EN bit

(I2C_CON[5]) = 0) and the master sends a read command in

10-bit addressing mode.

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Table 161: I2C_TX_ABRT_SOURCE_REG (0x50001380)

Bit

Mode Symbol

R ABRT_SBYTE_NOR

Description

Reset

0x0

9

To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT

must be fixed first; restart must be enabled (I2C_CON[5]=1),

the SPECIAL bit must be cleared (I2C_TAR[11]), or the

GC_OR_START bit must be cleared (I2C_TAR[10]). Once

the source of the ABRT_SBYTE_NORSTRT is fixed, then

this bit can be cleared in the same manner as other bits in

this register. If the source of the ABRT_SBYTE_NORSTRT

is not fixed before attempting to clear this bit, bit 9 clears for

one cycle and then gets re-asserted. 1: The restart is dis-

abled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user

is trying to send a START Byte.

STRT

8

R

ABRT_HS_NORSTR

T

1: The restart is disabled (IC_RESTART_EN bit

(I2C_CON[5]) = 0) and the user is trying to use the master to

transfer data in High Speed mode

0x0

7

6

5

R

ABRT_SBYTE_ACK

DET

1: Master has sent a START Byte and the START Byte was

acknowledged (wrong behavior).

0x0

ABRT_HS_ACKDET

1: Master is in High Speed mode and the High Speed Master

code was acknowledged (wrong behavior).

ABRT_GCALL_REA

D

1: the controller in master mode sent a General Call but the

user programmed the byte following the General Call to be a

read from the bus (IC_DATA_CMD[9] is set to 1).

4

3

R

ABRT_GCALL_NOA

CK

1: the controller in master mode sent a General Call and no

slave on the bus acknowledged the General Call.

0x0

ABRT_TXDATA_NO

ACK

1: This is a master-mode only bit. Master has received an

acknowledgement for the address, but when it sent data

byte(s) following the address, it did not receive an acknowl-

edge from the remote slave(s).

2

R

ABRT_10ADDR2_N

OACK

1: Master is in 10-bit address mode and the second address

byte of the 10-bit address was not acknowledged by any

slave.

0x0

1

0

R

ABRT_10ADDR1_N

OACK

1: Master is in 10-bit address mode and the first 10-bit

address byte was not acknowledged by any slave.

0x0

ABRT_7B_ADDR_N

OACK

1: Master is in 7-bit addressing mode and the address sent

was not acknowledged by any slave.

Table 162: I2C_SDA_SETUP_REG (0x50001394)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

SDA_SETUP

SDA Setup.

0x64

This register controls the amount of time delay (number of

I2C clock periods) between the rising edge of SCL and SDA

changing by holding SCL low when I2C block services a

read request while operating as a slave-transmitter. The rele-

vant I2C requirement is tSU:DAT (note 4) as detailed in the

I2C Bus Specification. This register must be programmed

with a value equal to or greater than 2.

It is recommended that if the required delay is 1000ns, then

for an I2C frequency of 10 MHz, IC_SDA_SETUP should be

programmed to a value of 11.Writes to this register succeed

only when IC_ENABLE[0] = 0.

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Table 163: I2C_ACK_GENERAL_CALL_REG (0x50001398)

Bit

15:1

0

Mode Symbol

Description

Reset

-

Reserved

0x0

R/W

ACK_GEN_CALL

ACK General Call. When set to 1, I2C Ctrl responds with a

ACK (by asserting ic_data_oe) when it receives a General

Call. When set to 0, the controller does not generate General

Call interrupts.

Table 164: I2C_ENABLE_STATUS_REG (0x5000139C)

Bit

15:3

2

Mode Symbol

Description

Reset

0x0

-

Reserved

R

SLV_RX_DATA_LOS

T

Slave Received Data Lost. This bit indicates if a Slave-

Receiver

0x0

operation has been aborted with at least one data byte

received from an I2C transfer due to the setting of

IC_ENABLE from 1 to 0. When read as 1, the controller is

deemed to have been actively engaged in an aborted I2C

transfer (with matching address) and the data phase of the

I2C transfer has been entered, even though a data byte has

been responded with a NACK. NOTE: If the remote I2C mas-

ter terminates the transfer with a STOP condition before the

controller has a chance to NACK a transfer, and IC_ENABLE

has been set to 0, then this bit is also set to 1.

When read as 0, the controller is deemed to have been dis-

abled without being actively involved in the data phase of a

Slave-Receiver transfer.

NOTE: The CPU can safely read this bit when IC_EN (bit 0)

is read as 0.

1

R

SLV_DISABLED_WH Slave Disabled While Busy (Transmit, Receive). This bit indi- 0x0

ILE_BUSY

cates if a potential or active Slave operation has been

aborted due to the setting of the IC_ENABLE register from 1

to 0. This bit is set when the CPU writes a 0 to the

IC_ENABLE register while:

(a) I2C Ctrl is receiving the address byte of the Slave-Trans-

mitter operation from a remote master; OR,

(b) address and data bytes of the Slave-Receiver operation

from a remote master. When read as 1, the controller is

deemed to have forced a NACK during any part of an I2C

transfer, irrespective of whether the I2C address matches

the slave address set in I2C Ctrl (IC_SAR register) OR if the

transfer is completed before IC_ENABLE is set to 0 but has

not taken effect.

NOTE: If the remote I2C master terminates the transfer with

a STOP condition before the the controller has a chance to

NACK a transfer, and IC_ENABLE has been set to 0, then

this bit will also be set to 1.

When read as 0, the controller is deemed to have been dis-

abled when there is master activity, or when the I2C bus is

idle.

NOTE: The CPU can safely read this bit when IC_EN (bit 0)

is read as 0.

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Table 164: I2C_ENABLE_STATUS_REG (0x5000139C)

Bit

Mode Symbol

IC_EN

Description

Reset

0

R

ic_en Status. This bit always reflects the value driven on the

output port ic_en. When read as 1, the controller is deemed

to be in an enabled state.

0x0

When read as 0, the controller is deemed completely inac-

tive.

NOTE: The CPU can safely read this bit anytime. When this

bit is read as 0, the CPU can safely read

SLV_RX_DATA_LOST (bit 2) and

SLV_DISABLED_WHILE_BUSY (bit 1).

Table 165: I2C_IC_FS_SPKLEN_REG (0x500013A0)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

IC_FS_SPKLEN

This register must be set before any I2C bus transaction can

take place to ensure stable operation. This register sets the

duration, measured in ic_clk cycles, of the longest spike in

the SCL or SDA lines that will be filtered out by the spike

suppression logic. This register can be written only when the

I2C interface is disabled which corresponds to the

IC_ENABLE register being set to 0. Writes at other times

have no effect. The minimum valid value is 2; hardware pre-

vents values less than this being written, and if attempted

results in 2 being set.

0x1

Table 166: GPIO_IRQ0_IN_SEL_REG (0x50001400)

Bit

Mode Symbol

Description

Reset

15:6

-

Reserved

0x0

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Table 166: GPIO_IRQ0_IN_SEL_REG (0x50001400)

Bit

Mode Symbol

R/W KBRD_IRQ0_SEL

Description

Reset

5:0

input selection that can generate a GPIO interrupt

0: no input selected

1: P0[0] is selected

0x0

2: P0[1] is selected

3: P0[2] is selected

4: P0[3] is selected

5: P0[4] is selected

6: P0[5] is selected

7: P0[6] is selected

8: P0[7] is selected

9: P1[0] is selected

10: P1[1] is selected

11: P1[2] is selected

12: P1[3] is selected

13: P1[4] is selected

14: P1[5] is selected

15: P2[0] is selected

16: P2[1] is selected

17: P2[2] is selected

18: P2[3] is selected

19: P2[4] is selected

20: P2[5] is selected

21: P2[6] is selected

22: P2[7] is selected

23: P2[8] is selected

24: P2[9] is selected

25: P3[0] is selected

26: P3[1] is selected

27: P3[2] is selected

28: P3[3] is selected

29: P3[4] is selected

30: P3[5] is selected

31: P3[6] is selected

32: P3[7] is selected

all others: no input selected

Table 167: GPIO_IRQ1_IN_SEL_REG (0x50001402)

Bit

Mode Symbol

Description

Reset

0x0

15:5

5:0

-

Reserved

R/W

KBRD_IRQ1_SEL

see KBRD_IRQ0_SEL

0x0

Table 168: GPIO_IRQ2_IN_SEL_REG (0x50001404)

Bit

Mode Symbol

Description

Reset

0x0

15:5

5:0

-

Reserved

R/W

KBRD_IRQ2_SEL

see KBRD_IRQ0_SEL

0x0

Table 169: GPIO_IRQ3_IN_SEL_REG (0x50001406)

Bit

Mode Symbol

Description

Reset

0x0

15:5

5:0

-

Reserved

R/W

KBRD_IRQ3_SEL

see KBRD_IRQ0_SEL

0x0

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Table 170: GPIO_IRQ4_IN_SEL_REG (0x50001408)

Bit

Mode Symbol

Description

Reset

15:5

5:0

-

Reserved

0x0

R/W

KBRD_IRQ4_SEL

see KBRD_IRQ0_SEL

Table 171: GPIO_DEBOUNCE_REG (0x5000140C)

Bit

Mode Symbol

Description

Reset

0x0

15:14

13

-

Reserved

R/W

DEB_ENABLE_KBR

D

enables the debounce counter for the KBRD interface

0x0

12

11

10

9

R/W

-

DEB_ENABLE4

DEB_ENABLE3

DEB_ENABLE2

DEB_ENABLE1

DEB_ENABLE0

-

enables the debounce counter for GPIO IRQ4

enables the debounce counter for GPIO IRQ3

enables the debounce counter for GPIO IRQ2

enables the debounce counter for GPIO IRQ1

enables the debounce counter for GPIO IRQ0

Reserved

0x0

8

7:6

5:0

R/W

DEB_VALUE

Keyboard debounce time if enabled. Generate KEYB_INT

after specified time.

Debounce time: N*1 ms. N =0..63

Table 172: GPIO_RESET_IRQ_REG (0x5000140E)

Bit

15:6

5

Mode Symbol

Description

Reset

0x0

-

Reserved

R0/W

RESET_KBRD_IRQ

writing a 1 to this bit will reset the KBRD IRQ.

Reading returns 0.

0x0

4

3

2

1

0

R0/W

RESET_GPIO4_IRQ

RESET_GPIO3_IRQ

RESET_GPIO2_IRQ

RESET_GPIO1_IRQ

RESET_GPIO0_IRQ

writing a 1 to this bit will reset the GPIO4 IRQ.

Reading returns 0.

0x0

writing a 1 to this bit will reset the GPIO3 IRQ.

Reading returns 0.

writing a 1 to this bit will reset the GPIO2 IRQ.

Reading returns 0.

writing a 1 to this bit will reset the GPIO1 IRQ.

Reading returns 0.

writing a 1 to this bit will reset the GPIO0 IRQ.

Reading returns 0.

Table 173: GPIO_INT_LEVEL_CTRL_REG (0x50001410)

Bit

15:14

12

11

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

EDGE_LEVELN4

EDGE_LEVELN3

EDGE_LEVELN2

EDGE_LEVELN1

EDGE_LEVELN0

see EDGE_LEVELn0, but for GPIO IRQ4

see EDGE_LEVELn0, but for GPIO IRQ3

see EDGE_LEVELn0, but for GPIO IRQ2

see EDGE_LEVELn0, but for GPIO IRQ1

10

9

8

0: do not wait for key release after interrupt was reset for

GPIO IRQ0, so a new interrupt can be initiated immediately

1: wait for key release after interrupt was reset for IRQ0

7:6

-

Reserved

0x0

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Table 173: GPIO_INT_LEVEL_CTRL_REG (0x50001410)

Bit

4

Mode Symbol

Description

Reset

R/W

INPUT_LEVEL4

see INPUT_LEVEL0, but for GPIO IRQ4

see INPUT_LEVEL0, but for GPIO IRQ3

see INPUT_LEVEL0, but for GPIO IRQ2

see INPUT_LEVEL0, but for GPIO IRQ1

0x0

3

INPUT_LEVEL3

INPUT_LEVEL2

INPUT_LEVEL1

INPUT_LEVEL0

2

1

0

0 = selected input will generate GPIO IRQ0 if that input is

high.

1 = selected input will generate GPIO IRQ0 if that input is

low.

Table 174: KBRD_IRQ_IN_SEL0_REG (0x50001412)

Bit

Mode Symbol

Description

Reset

15

R/W

KBRD_REL

0 = No interrupt on key release

1 = Interrupt also on key release (also debouncing if

enabled)

0x0

14

KBRD_LEVEL

KEY_REPEAT

0 = enabled input will generate KBRD IRQ if that input is

high.

1 = enabled input will generate KBRD IRQ if that input is low.

0x0

13:8

While key is pressed, automatically generate repeating

KEYB_INT after specified time unequal to 0.

Repeat time: N*1 ms. N =1..63, N=0 disables the timer.

7

6

5

4

3

2

1

0

R/W

KBRD_P07_EN

KBRD_P06_EN

KBRD_P05_EN

KBRD_P04_EN

KBRD_P03_EN

KBRD_P02_EN

KBRD_P01_EN

KBRD_P00_EN

enable P0[7] for the keyboard interrupt

enable P0[6] for the keyboard interrupt

enable P0[5] for the keyboard interrupt

enable P0[4] for the keyboard interrupt

enable P0[3] for the keyboard interrupt

enable P0[2] for the keyboard interrupt

enable P0[1] for the keyboard interrupt

enable P0[0] for the keyboard interrupt

0x0

Table 175: KBRD_IRQ_IN_SEL1_REG (0x50001414)

Bit

15

14

13

12

11

10

9

Mode Symbol

Description

Reset

0x0

R/W

KBRD_P15_EN

enable P1[5] for the keyboard interrupt

enable P1[4] for the keyboard interrupt

enable P1[3] for the keyboard interrupt

enable P1[2] for the keyboard interrupt

enable P1[1] for the keyboard interrupt

enable P1[0] for the keyboard interrupt

enable P2[9] for the keyboard interrupt

enable P2[8] for the keyboard interrupt

enable P2[7] for the keyboard interrupt

enable P2[6] for the keyboard interrupt

enable P2[5] for the keyboard interrupt

enable P2[4] for the keyboard interrupt

enable P2[3] for the keyboard interrupt

enable P2[2] for the keyboard interrupt

KBRD_P14_EN

KBRD_P13_EN

KBRD_P12_EN

KBRD_P11_EN

KBRD_P10_EN

KBRD_P29_EN

KBRD_P28_EN

KBRD_P27_EN

KBRD_P26_EN

KBRD_P25_EN

KBRD_P24_EN

KBRD_P23_EN

KBRD_P22_EN

8

7

6

5

4

3

2

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Table 175: KBRD_IRQ_IN_SEL1_REG (0x50001414)

Bit

1

Mode Symbol

Description

Reset

R/W

KBRD_P21_EN

KBRD_P20_EN

enable P2[1] for the keyboard interrupt

enable P2[0] for the keyboard interrupt

0x0

0

Table 176: KBRD_IRQ_IN_SEL2_REG (0x50001416)

Bit

7

Mode Symbol

Description

Reset

0x0

R/W

KBRD_P37_EN

enable P3[7] for the keyboard interrupt

enable P3[6] for the keyboard interrupt

enable P3[5] for the keyboard interrupt

enable P3[4] for the keyboard interrupt

enable P3[3] for the keyboard interrupt

enable P3[2] for the keyboard interrupt

enable P3[1] for the keyboard interrupt

enable P3[0] for the keyboard interrupt

6

KBRD_P36_EN

KBRD_P35_EN

KBRD_P34_EN

KBRD_P33_EN

KBRD_P32_EN

KBRD_P31_EN

KBRD_P30_EN

5

4

3

2

1

0

Table 177: GP_ADC_CTRL_REG (0x50001500)

Bit

Mode Symbol

Description

Reset

15

R/W

GP_ADC_LDO_ZER

Forces LDO-output to 0V.

0x0

O

14

13

R/W

GP_ADC_LDO_EN

GP_ADC_CHOP

Turns on LDO.

0x0

Takes two samples with opposite GP_ADC_SIGN to cancel

the internal offset voltage of the ADC; Highly recommended

for DC-measurements.

12

R/W

GP_ADC_MUTE

Takes sample at mid-scale (to dertermine the internal offset

and/or noise of the ADC with regards to VDD_REF which is

also sampled by the ADC).

0x0

11

10

R/W

GP_ADC_SE

0 = Differential mode

1 = Single ended mode

0x0

GP_ADC_SIGN

0 = Default

1 = Conversion with opposite sign at input and output to can-

cel out the internal offset of the ADC and low-frequency

9:6

R/W

GP_ADC_SEL

ADC input selection which must be set before the

GP_ADC_START bit is enabled.

If GP_ADC_SE = 1 (single ended mode):

0000 = P0[0]

0x0

0001 = P0[1]

0010 = P0[2]

0011 = P0[3]

0100 = AVS

0101 = VDD_REF

0110 = VDD_RTT

0111 = VBAT3V

1000 = VDCDC

1001 = VBAT1V

All other combinations are reserved.

If GP_ADC_SE = 0 (differential mode):

0000 = P0[0] vs P0[1]

All other combinations are P0[2] vs P0[3].

5

R/W

GP_ADC_MINT

0 = Disable (mask) GP_ADC_INT.

1 = Enable GP_ADC_INT to ICU.

0x0

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Table 177: GP_ADC_CTRL_REG (0x50001500)

Bit

Mode Symbol

Description

Reset

4

R

GP_ADC_INT

1 = AD conversion ready and has generated an interrupt.

Must be cleared by writing any value to

GP_ADC_CLEAR_INT_REG.

0x0

3

R/W

GP_ADC_CLK_SEL

0 = Internal high-speed ADC clock used.

1 = Digital clock used.

0x0

2

1

-

GP_ADC_TEST

GP_ADC_START

Reserved, keep 0.

0x0

R/W

0 = ADC conversion ready.

1 = If a 1 is written, the ADC starts a conversion. After the

conversion this bit will be set to 0 and the GP_ADC_INT bit

will be set.

0

R/W

GP_ADC_EN

0 = ADC is disabled and in reset.

0x0

1 = ADC is enabled and sampling of input is started.

Table 178: GP_ADC_CTRL2_REG (0x50001502)

Bit

15:4

3

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

GP_ADC_I20U

Adds 20uA constant load current at the ADC LDO to mini-

mize ripple on the reference voltage of the ADC.

0x0

2

1

R/W

GP_ADC_IDYN

Enables dynamic load current at the ADC LDO to minimize

ripple on the reference voltage of the ADC.

0x0

GP_ADC_ATTN3X

0 = Input voltages up to 1.2V allowed.

1 = Input voltages up to 3.6V allowed by enabling 3x attenu-

ator.

0

R/W

GP_ADC_DELAY_E

N

Enables delay function for several signals. This is not auto-

cleared. Toggle this bit before every sampling to enable suc-

cesive conversions.

0x0

Table 179: GP_ADC_OFFP_REG (0x50001504)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:0

-

Reserved

R/W

GP_ADC_OFFP

Offset adjust of 'positive' array of ADC-network (effective if

"GP_ADC_SE=0", or "GP_ADC_SE=1 AND

GP_ADC_SIGN=0")

0x200

Table 180: GP_ADC_OFFN_REG (0x50001506)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:0

-

Reserved

R/W

GP_ADC_OFFN

Offset adjust of 'negative' array of ADC-network (effective if

"GP_ADC_SE=0", or "GP_ADC_SE=1 AND

GP_ADC_SIGN=1")

0x200

Table 181: GP_ADC_CLEAR_INT_REG (0x50001508)

Bit

Mode Symbol

R0/W GP_ADC_CLR_INT

Description

Reset

15:0

Writing any value to this register will clear the ADC_INT

interrupt. Reading returns 0.

0x0

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Table 182: GP_ADC_RESULT_REG (0x5000150A)

Bit

Mode Symbol

Description

Reset

15:10

9:0

-

Reserved

0x0

R

GP_ADC_VAL

Returns the 10 bits linear value of the last AD conversion.

Table 183: GP_ADC_DELAY_REG (0x5000150C)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

DEL_LDO_EN

Defines the delay before the LDO enable

0x0

(GP_ADC_LDO_EN). Reset value is 0 µs since the LDO

enable should be the first thing to be programmed in the

sequence of bringing the GP ADC up.

Table 184: GP_ADC_DELAY2_REG (0x5000150E)

Bit

Mode Symbol

Description

Reset

15:8

R/W

DEL_ADC_START

Defines the delay for the GP_ADC_START bit. Reset value

is 17 µs which is the recommended value to wait before

starting the GP ADC. This is the third and last step of bring-

ing up the GP ADC

0x88

7:0

R/W

DEL_ADC_EN

Defines the delay for the GP_ADC_EN bit. Reset value is 16

µs which is the recommended value to wait after enabling

the LDO. This is the second step in bringing up the GP ADC.

0x80

Table 185: CLK_REF_SEL_REG (0x50001600)

Bit

15:3

2

Mode Symbol

Description

Reset

-

Reserved

0x0

R/W

REF_CAL_START

Writing a '1' starts a calibration. This bit is cleared when cali- 0x0

bration is finished, and CLK_REF_VAL is ready.

1:0

R/W

REF_CLK_SEL

Select clock input for calibration:

0x0 : RC32KHz oscillator

0x0

0x1 : RC16MHz oscillator

0x2 : XTAL32KHz oscillator

0x3 : RCX32KHz oscillator

Table 186: CLK_REF_CNT_REG (0x50001602)

Bit

Mode Symbol

R/W REF_CNT_VAL

Description

Reset

15:0

Indicates the calibration time, with a decrement counter to 1.

0x0

Table 187: CLK_REF_VAL_L_REG (0x50001604)

Bit

Mode Symbol

XTAL_CNT_VAL

Description

Reset

15:0

R

Returns the lower 16 bits of XTAL16 clock cycles during the

calibration time, defined with REF_CNT_VAL

0x0

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Table 188: CLK_REF_VAL_H_REG (0x50001606)

Bit

Mode Symbol

XTAL_CNT_VAL

Description

Reset

15:0

R

Returns the upper 16 bits of XTAL16 clock cycles during the

calibration time, defined with REF_CNT_VAL

0x0

Table 189: P0_DATA_REG (0x50003000)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

P0_DATA

Set P0 output register when written; Returns the value of P0

port when read

0x0

Table 190: P0_SET_DATA_REG (0x50003002)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

P0_SET

Writing a 1 to P0[y] sets P0[y] to 1. Writing 0 is discarded;

Reading returns 0

0x0

Table 191: P0_RESET_DATA_REG (0x50003004)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

P0_RESET

Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded;

Reading returns 0

0x0

Table 192: P00_MODE_REG (0x50003006)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

-

Reserved

0x0

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Table 192: P00_MODE_REG (0x50003006)

Bit

Mode Symbol

R/W PID

Description

Reset

4:0

Function of port

0x0

0 = Port function, PUPD as set above

1 = UART1_RX

2 = UART1_TX

3 = UART2_RX

4 = UART2_TX

5 = SPI_DI

6 = SPI_DO

7 = SPI_CLK

8 = SPI_EN

9 = I2C_SCL

10 = I2C_SDA

11 = UART1_IRDA_RX

12 = UART1_IRDA_TX

13 = UART2_IRDA_RX

14 = UART2_IRDA_TX

15 = ADC (only for P0[3:0])

16 = PWM0

17 = PWM1

18 = BLE_DIAG (only for P0[7:0])

19 = UART1_CTSN

20 = UART1_RTSN

21 = UART2_CTSN

22 = UART2_RTSN

23 = PWM2

24 = PWM3

25 = PWM4

Note: when a certain input function (like SPI_DI) is selected

on more than 1 port pin, the port with the lowest index has

the highest priority and P0 has higher priority than P1.

Table 193: P01_MODE_REG (0x50003008)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

-

Reserved

0x0

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Table 193: P01_MODE_REG (0x50003008)

Bit

Mode Symbol

R/W PID

Description

Reset

4:0

Function of port

0x0

0 = Port function, PUPD as set above

1 = UART1_RX

2 = UART1_TX

3 = UART2_RX

4 = UART2_TX

5 = SPI_DI

6 = SPI_DO

7 = SPI_CLK

8 = SPI_EN

9 = I2C_SCL

10 = I2C_SDA

11 = UART1_IRDA_RX

12 = UART1_IRDA_TX

13 = UART2_IRDA_RX

14 = UART2_IRDA_TX

15 = ADC (only for P0[3:0])

16 = PWM0

17 = PWM1

18 = BLE_DIAG (only for P0[7:0])

19 = UART1_CTSN

20 = UART1_RTSN

21 = UART2_CTSN

22 = UART2_RTSN

23 = PWM2

24 = PWM3

25 = PWM4

Note: when a certain input function (like SPI_DI) is selected

on more than 1 port pin, the port with the lowest index has

the highest priority and P0 has higher priority than P1.

Table 194: P02_MODE_REG (0x5000300A)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

-

Reserved

0x0

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Table 194: P02_MODE_REG (0x5000300A)

Bit

Mode Symbol

R/W PID

Description

Reset

4:0

Function of port

0x0

0 = Port function, PUPD as set above

1 = UART1_RX

2 = UART1_TX

3 = UART2_RX

4 = UART2_TX

5 = SPI_DI

6 = SPI_DO

7 = SPI_CLK

8 = SPI_EN

9 = I2C_SCL

10 = I2C_SDA

11 = UART1_IRDA_RX

12 = UART1_IRDA_TX

13 = UART2_IRDA_RX

14 = UART2_IRDA_TX

15 = ADC (only for P0[3:0])

16 = PWM0

17 = PWM1

18 = BLE_DIAG (only for P0[7:0])

19 = UART1_CTSN

20 = UART1_RTSN

21 = UART2_CTSN

22 = UART2_RTSN

23 = PWM2

24 = PWM3

25 = PWM4

Note: when a certain input function (like SPI_DI) is selected

on more than 1 port pin, the port with the lowest index has

the highest priority and P0 has higher priority than P1.

Table 195: P03_MODE_REG (0x5000300C)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

-

Reserved

0x0

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Table 195: P03_MODE_REG (0x5000300C)

Bit

Mode Symbol

R/W PID

Description

Reset

4:0

Function of port

0x0

0 = Port function, PUPD as set above

1 = UART1_RX

2 = UART1_TX

3 = UART2_RX

4 = UART2_TX

5 = SPI_DI

6 = SPI_DO

7 = SPI_CLK

8 = SPI_EN

9 = I2C_SCL

10 = I2C_SDA

11 = UART1_IRDA_RX

12 = UART1_IRDA_TX

13 = UART2_IRDA_RX

14 = UART2_IRDA_TX

15 = ADC (only for P0[3:0])

16 = PWM0

17 = PWM1

18 = BLE_DIAG (only for P0[7:0])

19 = UART1_CTSN

20 = UART1_RTSN

21 = UART2_CTSN

22 = UART2_RTSN

23 = PWM2

24 = PWM3

25 = PWM4

Note: when a certain input function (like SPI_DI) is selected

on more than 1 port pin, the port with the lowest index has

the highest priority and P0 has higher priority than P1.

Table 196: P04_MODE_REG (0x5000300E)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

-

Reserved

0x0

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Table 196: P04_MODE_REG (0x5000300E)

Bit

Mode Symbol

R/W PID

Description

Reset

4:0

Function of port

0x0

0 = Port function, PUPD as set above

1 = UART1_RX

2 = UART1_TX

3 = UART2_RX

4 = UART2_TX

5 = SPI_DI

6 = SPI_DO

7 = SPI_CLK

8 = SPI_EN

9 = I2C_SCL

10 = I2C_SDA

11 = UART1_IRDA_RX

12 = UART1_IRDA_TX

13 = UART2_IRDA_RX

14 = UART2_IRDA_TX

15 = ADC (only for P0[3:0])

16 = PWM0

17 = PWM1

18 = BLE_DIAG (only for P0[7:0])

19 = UART1_CTSN

20 = UART1_RTSN

21 = UART2_CTSN

22 = UART2_RTSN

23 = PWM2

24 = PWM3

25 = PWM4

Note: when a certain input function (like SPI_DI) is selected

on more than 1 port pin, the port with the lowest index has

the highest priority and P0 has higher priority than P1.

Table 197: P05_MODE_REG (0x50003010)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

-

Reserved

0x0

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Table 197: P05_MODE_REG (0x50003010)

Bit

Mode Symbol

R/W PID

Description

Reset

4:0

Function of port

0x0

0 = Port function, PUPD as set above

1 = UART1_RX

2 = UART1_TX

3 = UART2_RX

4 = UART2_TX

5 = SPI_DI

6 = SPI_DO

7 = SPI_CLK

8 = SPI_EN

9 = I2C_SCL

10 = I2C_SDA

11 = UART1_IRDA_RX

12 = UART1_IRDA_TX

13 = UART2_IRDA_RX

14 = UART2_IRDA_TX

15 = ADC (only for P0[3:0])

16 = PWM0

17 = PWM1

18 = BLE_DIAG (only for P0[7:0])

19 = UART1_CTSN

20 = UART1_RTSN

21 = UART2_CTSN

22 = UART2_RTSN

23 = PWM2

24 = PWM3

25 = PWM4

Note: when a certain input function (like SPI_DI) is selected

on more than 1 port pin, the port with the lowest index has

the highest priority and P0 has higher priority than P1.

Table 198: P06_MODE_REG (0x50003012)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

-

Reserved

0x0

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Table 198: P06_MODE_REG (0x50003012)

Bit

Mode Symbol

R/W PID

Description

Reset

4:0

Function of port

0x0

0 = Port function, PUPD as set above

1 = UART1_RX

2 = UART1_TX

3 = UART2_RX

4 = UART2_TX

5 = SPI_DI

6 = SPI_DO

7 = SPI_CLK

8 = SPI_EN

9 = I2C_SCL

10 = I2C_SDA

11 = UART1_IRDA_RX

12 = UART1_IRDA_TX

13 = UART2_IRDA_RX

14 = UART2_IRDA_TX

15 = ADC (only for P0[3:0])

16 = PWM0

17 = PWM1

18 = BLE_DIAG (only for P0[7:0])

19 = UART1_CTSN

20 = UART1_RTSN

21 = UART2_CTSN

22 = UART2_RTSN

23 = PWM2

24 = PWM3

25 = PWM4

Note: when a certain input function (like SPI_DI) is selected

on more than 1 port pin, the port with the lowest index has

the highest priority and P0 has higher priority than P1.

Table 199: P07_MODE_REG (0x50003014)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

-

Reserved

0x0

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Table 199: P07_MODE_REG (0x50003014)

Bit

Mode Symbol

R/W PID

Description

Reset

4:0

Function of port

0x0

0 = Port function, PUPD as set above

1 = UART1_RX

2 = UART1_TX

3 = UART2_RX

4 = UART2_TX

5 = SPI_DI

6 = SPI_DO

7 = SPI_CLK

8 = SPI_EN

9 = I2C_SCL

10 = I2C_SDA

11 = UART1_IRDA_RX

12 = UART1_IRDA_TX

13 = UART2_IRDA_RX

14 = UART2_IRDA_TX

15 = ADC (only for P0[3:0])

16 = PWM0

17 = PWM1

18 = BLE_DIAG (only for P0[7:0])

19 = UART1_CTSN

20 = UART1_RTSN

21 = UART2_CTSN

22 = UART2_RTSN

23 = PWM2

24 = PWM3

25 = PWM4

Note: when a certain input function (like SPI_DI) is selected

on more than 1 port pin, the port with the lowest index has

the highest priority and P0 has higher priority than P1.

Table 200: P1_DATA_REG (0x50003020)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

P1_DATA

Set P1 output register when written; Returns the value of P1

port when read

0x0

Table 201: P1_SET_DATA_REG (0x50003022)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

P1_SET

Writing a 1 to P1[y] sets P1[y] to 1. Writing 0 is discarded;

Reading returns 0

0x0

Table 202: P1_RESET_DATA_REG (0x50003024)

Bit

Mode Symbol

Description

Reset

0x0

15:8

7:0

-

Reserved

R/W

P1_RESET

Writing a 1 to P1[y] sets P1[y] to 0. Writing 0 is discarded;

Reading returns 0

0x0

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Table 203: P10_MODE_REG (0x50003026)

Bit

Mode Symbol

Description

Reset

15:10

9:8

-

Reserved

0x0

0x2

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

P14_MODE_REG and P15_MODE_REG reset value is 1

(i.e. pulled up)

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 204: P11_MODE_REG (0x50003028)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

P14_MODE_REG and P15_MODE_REG reset value is 1

(i.e. pulled up)

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 205: P12_MODE_REG (0x5000302A)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

P14_MODE_REG and P15_MODE_REG reset value is 1

(i.e. pulled up)

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 206: P13_MODE_REG (0x5000302C)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

P14_MODE_REG and P15_MODE_REG reset value is 1

(i.e. pulled up)

7:5

-

Reserved

0x0

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Table 206: P13_MODE_REG (0x5000302C)

Bit

Mode Symbol

R/W PID

Description

Reset

4:0

See P0x_MODE_REG[PID]

0x0

Table 207: P14_MODE_REG (0x5000302E)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

P14_MODE_REG and P15_MODE_REG reset value is 1

(i.e. pulled up)

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 208: P15_MODE_REG (0x50003030)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x1

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

P14_MODE_REG and P15_MODE_REG reset value is 1

(i.e. pulled up)

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 209: P2_DATA_REG (0x50003040)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:0

-

Reserved

R/W

P2_DATA

Set P2 output register when written; Returns the value of P2

port when read

0x0

Table 210: P2_SET_DATA_REG (0x50003042)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:0

-

Reserved

R/W

P2_SET

Writing a 1 to P2[y] sets P2[y] to 1. Writing 0 is discarded;

Reading returns 0

0x0

Table 211: P2_RESET_DATA_REG (0x50003044)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:0

-

Reserved

R/W

P2_RESET

Writing a 1 to P2[y] sets P2[y] to 0. Writing 0 is discarded;

Reading returns 0

0x0

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Table 212: P20_MODE_REG (0x50003046)

Bit

Mode Symbol

Description

Reset

15:10

9:8

-

Reserved

0x0

0x2

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 213: P21_MODE_REG (0x50003048)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 214: P22_MODE_REG (0x5000304A)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 215: P23_MODE_REG (0x5000304C)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 216: P24_MODE_REG (0x5000304E)

Bit

Mode Symbol

Description

Reset

15:10

-

Reserved

0x0

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Table 216: P24_MODE_REG (0x5000304E)

Bit

Mode Symbol

Description

Reset

9:8

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 217: P25_MODE_REG (0x50003050)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 218: P26_MODE_REG (0x50003052)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 219: P27_MODE_REG (0x50003054)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 220: P28_MODE_REG (0x50003056)

Bit

Mode Symbol

Description

Reset

15:10

-

Reserved

0x0

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Table 220: P28_MODE_REG (0x50003056)

Bit

Mode Symbol

Description

Reset

9:8

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 221: P29_MODE_REG (0x50003058)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:8

-

Reserved

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

0x2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In analog mode, these bits are don't care

7:5

4:0

-

Reserved

0x0

R/W

PID

See P0x_MODE_REG[PID]

Table 222: P01_PADPWR_CTRL_REG (0x50003070)

Bit

Mode Symbol

Description

Reset

0x0

15:12

13:8

-

Reserved

R/W

P1_OUT_CTRL

1 = P1_x port output is powered by the 1 V rail

0 = P1_x port output is powered by the 3 V rail

bit 8 controls the power of P1[0],

bit 13 controls the power of P1[5]

(Note 3)

0x0

7:0

R/W

P0_OUT_CTRL

1 = P0_x port output is powered by the 1 V rail

0 = P0_x port output is powered by the 3 V rail

bit 0 controls the power of P0[0],

bit 7 controls the power of P0[7]

(Note 4)

0x0

Note 3: In Buck mode the output must be powered by the 3 V rail. In Boost mode the outputs can be powered by the 1 V rail or by the 3 V rail. In

Boost mode the 3 V rail can only supply a limited current, e.g. for switching a high-impedance input of an external device. See table 'Digital

input/output characteristics'.

Note 4: In Buck mode the output must be powered by the 3 V rail. In Boost mode the outputs can be powered by the 1 V rail or by the 3 V rail. In

Boost mode the 3 V rail can only supply a limited current, e.g. for switching a high-impedance input of an external device. See table 'Digital

input/output characteristics'.

Table 223: P2_PADPWR_CTRL_REG (0x50003072)

Bit

Mode Symbol

Description

Reset

0x0

15:10

9:0

-

Reserved

R/W

P2_OUT_CTRL

1 = P2_x port output is powered by the 1 V rail

0 = P2_x port output is powered by the 3 V rail

bit 0 controls the power of P2[0],

bit 9 controls the power of P2[9],

(Note 5)

0x0

Note 5: In Buck mode the output must be powered by the 3 V rail. In Boost mode the outputs can be powered by the 1 V rail or by the 3 V rail. In

Boost mode the 3 V rail can only supply a limited current, e.g. for switching a high-impedance input of an external device. See table 'Digital

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input/output characteristics'.

Table 224: P3_PADPWR_CTRL_REG (0x50003074)

Bit

Mode Symbol

Description

Reset

15:8

7:0

-

Reserved

0

R/W

P3_OUT_CTRL

1 = P3_x port output is powered by the 1 V rail

0 = P3_x port output is powered by the 3 V rail

bit 0 controls the power of P3[0],

bit 7 controls the power of P3[7],

(Note 6)

Note 6: In Buck mode the output must be powered by the 3 V rail. In Boost mode the outputs can be powered by the 1 V rail or by the 3 V rail. In

Boost mode the 3 V rail can only supply a limited current, e.g. for switching a high-impedance input of an external device. See table 'Digital

input/output characteristics'.

Table 225: P3_DATA_REG (0x50003080)

Bit

Mode Symbol

Description

Reset

15:8

7:0

-

Reserved

0

R/W

P3_DATA

Set P3 output register when written; Returns the value of P3

port when read

Table 226: P3_SET_DATA_REG (0x50003082)

Bit

Mode Symbol

Description

Reset

15:8

7:0

-

Reserved

0

R0/W

P3_SET

Writing a 1 to P3[y] sets P3[y] to 1. Writing 0 is discarded;

Reading returns 0

Table 227: P3_RESET_DATA_REG (0x50003084)

Bit

Mode Symbol

Description

Reset

15:8

7:0

-

Reserved

0

R0/W

P3_RESET

Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded;

Reading returns 0

Table 228: P30_MODE_REG (0x50003086)

Bit

Mode Symbol

Description

Reset

15:10

9:8

-

Reserved

0

2

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

4:0

-

Reserved

0

R/W

PID

See P0x_MODE_REG[PID]

Table 229: P31_MODE_REG (0x50003088)

Bit

Mode Symbol

Description

Reset

15:10

-

Reserved

0

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Table 229: P31_MODE_REG (0x50003088)

Bit

Mode Symbol

Description

Reset

9:8

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

4:0

-

Reserved

0

R/W

PID

See P0x_MODE_REG[PID]

Table 230: P32_MODE_REG (0x5000308A)

Bit

Mode Symbol

Description

Reset

15:10

9:8

-

Reserved

0

2

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

4:0

-

Reserved

0

R/W

PID

See P0x_MODE_REG[PID]

Table 231: P33_MODE_REG (0x5000308C)

Bit

Mode Symbol

Description

Reset

15:10

9:8

-

Reserved

0

2

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

4:0

-

Reserved

0

R/W

PID

See P0x_MODE_REG[PID]

Table 232: P34_MODE_REG (0x5000308E)

Bit

Mode Symbol

Description

Reset

15:10

9:8

-

Reserved

0

2

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

4:0

-

Reserved

0

R/W

PID

See P0x_MODE_REG[PID]

Table 233: P35_MODE_REG (0x50003090)

Bit

Mode Symbol

Description

Reset

15:10

-

Reserved

0

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Bluetooth Low Energy 4.2 SoC

Table 233: P35_MODE_REG (0x50003090)

Bit

Mode Symbol

Description

Reset

9:8

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

2

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

4:0

-

Reserved

0

R/W

PID

See P0x_MODE_REG[PID]

Table 234: P36_MODE_REG (0x50003092)

Bit

Mode Symbol

Description

Reset

15:10

9:8

-

Reserved

0

2

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

4:0

-

Reserved

0

R/W

PID

See P0x_MODE_REG[PID]

Table 235: P37_MODE_REG (0x50003094)

Bit

Mode Symbol

Description

Reset

15:10

9:8

-

Reserved

0

2

R/W

PUPD

00 = Input, no resistors selected

01 = Input, pull-up selected

10 = Input, Pull-down selected

11 = Output, no resistors selected

In ADC mode, these bits are don't care

7:5

4:0

-

Reserved

0

R/W

PID

See P0x_MODE_REG[PID]

Table 236: WATCHDOG_REG (0x50003100)

Bit

Mode Symbol

Description

Reset

15:9

R0/W

WDOG_WEN

0000.000 = Write enable for Watchdog timer

else Write disable. This filter prevents unintentional preset-

ting the watchdog with a SW run-away.

0x0

8

R/W

WDOG_VAL_NEG

WDOG_VAL

0 = Watchdog timer value is positive.

1 = Watchdog timer value is negative.

0x0

7:0

Write: Watchdog timer reload value. Note that all bits 15-9

must be 0 to reload this register.

0xFF

Read: Actual Watchdog timer value. Decremented by 1

every 10.24 msec. Bit 8 indicates a negative counter value.

2, 1, 0, 1FF , 1FE etc. An NMI or WDOG (SYS) reset is

16

generated under the following conditions:

If WATCHDOG_CTRL_REG[NMI_RST] = 0 then

If WDOG_VAL = 0 -> NMI (Non Maskable Interrupt)

if WDOG_VAL = 1F0 -> WDOG reset -> reload FF

16

If WATCHDOG_CTRL_REG[NMI_RST] = 1 then

if WDOG_VAL <= 0 -> WDOG reset -> reload FF

16

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Table 237: WATCHDOG_CTRL_REG (0x50003102)

Bit

15:2

1

Mode Symbol

Description

Reserved

Reset

-

0x0

-

0

R/W

NMI_RST

0 = Watchdog timer generates NMI at value 0, and WDOG

(SYS) reset at <=-16. Timer can be frozen /resumed using

SET_FREEZE_REG[FRZ_WDOG]/

RESET_FREEZE_REG[FRZ_WDOG].

1 = Watchdog timer generates a WDOG (SYS) reset at value

0 and can not be frozen by Software.

Note that this bit can only be set to 1 by SW and only be

reset with a WDOG (SYS) reset or SW reset.

The watchdog is always frozen when the Cortex-M0 is halted

in DEBUG State.

Table 238: CHIP_ID1_REG (0x50003200)

Bit

Mode Symbol

CHIP_ID1

Description

Reset

7:0

R

First character of device type "580" in ASCII.

0x35

Table 239: CHIP_ID2_REG (0x50003201)

Bit

Mode Symbol

CHIP_ID2

Description

Reset

7:0

R

Second character of device type "580" in ASCII.

0x38

Table 240: CHIP_ID3_REG (0x50003202)

Bit

Mode Symbol

CHIP_ID3

Description

Reset

7:0

R

Third character of device type "580" in ASCII.

0x30

Table 241: CHIP_SWC_REG (0x50003203)

Bit

7:4

3:0

Mode Symbol

Description

Reset

0x0

-

Reserved

R

CHIP_SWC

SoftWare Compatibility code.

0x0

Integer (default = 0) which is incremented if a silicon change

has impact on the CPU Firmware.

Can be used by software developers to write silicon revision

dependent code.

Table 242: CHIP_REVISION_REG (0x50003204)

Bit

Mode Symbol

REVISION_ID

Description

Reset

7:0

R

Chip version, corresponds with type number in ASCII.

0x41 = 'A', 0x42 = 'B'

0x41

Table 243: SET_FREEZE_REG (0x50003300)

Bit

Mode Symbol

Description

Reset

15:4

-

Reserved

0x0

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Table 243: SET_FREEZE_REG (0x50003300)

Bit

Mode Symbol

Description

Reset

3

R/W

FRZ_WDOG

If '1', the watchdog timer is frozen, '0' is discarded.

WATCHDOG_CTRL_REG[NMI_RST] must be '0' to allow

the freeze function.

0x0

2

1

0

R/W

FRZ_BLETIM

FRZ_SWTIM

FRZ_WKUPTIM

If '1', the BLE master clock is frozen, '0' is discarded.

If '1', the SW Timer (TIMER0) is frozen, '0' is discarded.

If '1', the Wake Up Timer is frozen, '0' is discarded.

0x0

Table 244: RESET_FREEZE_REG (0x50003302)

Bit

15:4

3

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

FRZ_WDOG

FRZ_BLETIM

FRZ_SWTIM

FRZ_WKUPTIM

If '1', the watchdog timer continues, '0' is discarded.

If '1', the the BLE master clock continues, '0' is discarded.

If '1', the SW Timer (TIMER0) continues, '0' is discarded.

If '1', the Wake Up Timer continues, '0' is discarded.

0x0

2

0x0

1

0x0

0

0x0

Table 245: DEBUG_REG (0x50003304)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

DEBUGS_FREEZE_

EN

Default '1', freezing of the on-chip timers is enabled when the

Cortex-M0 is halted in DEBUG State.

0x1

If '0', freezing of the on-chip timers is depending on

FREEZE_REG when the Cortex-M0 is halted in DEBUG

State except the watchdog timer. The watchdog timer is

always frozen when the Cortex-M0 is halted in DEBUG

State.

Table 246: GP_STATUS_REG (0x50003306)

Bit

15:1

0

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

CAL_PHASE

If '1', it designates that the chip is in Calibration Phase i.e.

the OTP has been initially programmed but no Calibration

has occured.

0x0

Table 247: GP_CONTROL_REG (0x50003308)

Bit

Mode Symbol

Description

Reset

15:6

-

Reserved

0

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Table 247: GP_CONTROL_REG (0x50003308)

Bit

Mode Symbol

Description

Reset

0x1

5:1

R/W

EM_MAP

Select the mapping of the Exchange memory pages.

0: EM size 0 kB, SysRAM size 42 kB

1: EM size 2 kB, SysRAM size 48 kB

2: EM size 3 kB, SysRAM size 47 kB

3: EM size 4 kB, SysRAM size 46 kB

4: EM size 5 kB, SysRAM size 45 kB

5: EM size 6 kB, SysRAM size 44 kB

6: EM size 7 kB, SysRAM size 43 kB

7: EM size 8 kB, SysRAM size 42 kB

8: Reserved

9: EM size 4 kB, SysRAM size 40 kB

10: EM size 5 kB, SysRAM size 40 kB

11: EM size 6 kB, SysRAM size 40 kB

12: EM size 7 kB, SysRAM size 40 kB

13: EM size 8 kB, SysRAM size 40 kB

14: EM size 9 kB, SysRAM size 40 kB

15: EM size 10 kB, SysRAM size 40 kB

16: Reserved

17: EM size 6 kB, SysRAM size 38 kB

18: EM size 7 kB, SysRAM size 38 kB

19: EM size 8 kB, SysRAM size 38 kB

20: EM size 9 kB, SysRAM size 38 kB

21: EM size 10 kB, SysRAM size 38 kB

22: EM size 11 kB, SysRAM size 38 kB

23: EM size 12 kB, SysRAM size 38 kB

other: Reserved.

0

R/W

BLE_WAKEUP_REQ

If '1', the BLE wakes up. Must be kept high at least for 1 low

power clock period.

0x0

If the BLE is in deep sleep state, then by setting this bit it will

cause the wakeup LP IRQ to be asserted with a delay of 3 to

4 low power cycles.

Table 248: TIMER0_CTRL_REG (0x50003400)

Bit

15:4

3

Mode Symbol

Description

Reset

0x0

-

Reserved

R/W

PWM_MODE

0 = PWM signals are '1' during high time.

0x0

1 = PWM signals send out the (fast) clock divided by 2 dur-

ing high time. So it will be in the range of 1 to 8 MHz.

2

R/W

TIM0_CLK_DIV

1 = Timer0 uses selected clock frequency as is.

0 = Timer0 uses selected clock frequency divided by 10.

Note that this applies only to the ON-counter.

0x0

1

0

R/W

TIM0_CLK_SEL

TIM0_CTRL

1 = Timer0 uses 16, 8, 4 or 2 MHz (fast) clock frequency.

0 = Timer0 uses 32 kHz (slow) clock frequency.

0x0

0 = Timer0 is off and in reset state.

1 = Timer0 is running.

Table 249: TIMER0_ON_REG (0x50003402)

Bit

Mode Symbol

R0/W TIM0_ON

Description

Reset

15:0

Timer0 On reload value:

0x0

If read the actual counter value ON_CNTer is returned

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Table 250: TIMER0_RELOAD_M_REG (0x50003404)

Bit

Mode Symbol

R0/W TIM0_M

Description

Reset

15:0

Timer0 'high' reload valueIf read the actual counter value

T0_CNTer is returned

0x0

Table 251: TIMER0_RELOAD_N_REG (0x50003406)

Bit

Mode Symbol

R0/W TIM0_N

Description

Reset

15:0

Timer0 'low' reload value:

0x0

If read the actual counter value T0_CNTer is returned

Table 252: PWM2_DUTY_CYCLE (0x50003408)

Bit

Mode Symbol

R/W DUTY_CYCLE

Description

Reset

13:0

duty cycle for PWM

0x0

Table 253: PWM3_DUTY_CYCLE (0x5000340A)

Bit

Mode Symbol

R/W DUTY_CYCLE

Description

Reset

13:0

duty cycle for PWM

0x0

Table 254: PWM4_DUTY_CYCLE (0x5000340C)

Bit

Mode Symbol

R/W DUTY_CYCLE

Description

Reset

13:0

duty cycle for PWM

0x0

Table 255: TRIPLE_PWM_FREQUENCY (0x5000340E)

Bit

Mode Symbol

R/W FREQ

Description

Reset

13:0

Freq for PWM 2 3 4

0x0

Table 256: TRIPLE_PWM_CTRL_REG (0x50003410)

Bit

2

Mode Symbol

Description

Reset

0x1

R/W

HW_PAUSE_EN

'1' = HW can pause PWM 2,3,4

'1' = PWM 2 3 4 is paused

'1' = PWM 2 3 4 is enabled

1

SW_PAUSE_EN

0x0

0

TRIPLE_PWM_ENA

BLE

0x0

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6

Specifications

All MIN/MAX specification limits are guaranteed by design, production testing and/or statistical characterization. Typ-

ical values are based on characterization results at default measurement conditions and are informative only.

Default measurement conditions (unless otherwise specified): V

(VBAT3V) = 3.0 V (buck mode), V

(VBAT1V)

BAT

= 1.2 V (boost mode), T = 25 C. All radio measurements are performed with standard RF measurement equipment

A

providing a source/load impedance of 50 .

The specifications in the following tables are valid for the reference circuits shown in Figure 11 (Boost mode) and

Figure 12 (Buck mode).

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Figure 11: Alkaline Battery Cell Powered System Diagram (Boost Mode)

Datasheet

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Figure 12: Lithium Coin Cell Powered System Diagram (Buck Mode)

Datasheet

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Table 257: Absolute Maximum Ratings

Parameter

Description

Conditions

Min

Typ

Max

Unit

V

t)

(defaul limiting voltage on a pin

Voltage between pin and

GND

(Note 7)

-0.1

min{3.6,

VBAT_RF

+0.2}

V

PIN(LIM)

T

storage temperature

supply rise time

-50

150

100

3.6

°C

ms

V

STG

t

Power supply rise time

R(SUP)

V

1V)

(VBAT limiting battery supply

voltage

Supply voltage on

VBAT1V in a boost con-

verter application

(VBAT3V is second out-

put of boost-converter in

this case)

-0.1

BAT(LIM)

(Note 7)

V

3V)

(VBAT limiting battery supply

voltage

Supply voltage on

VBAT3V and VBAT_RF

in a buck-converter

application, pin VBAT1V

is connected to ground

(Note 7)

-0.1

3.6

V

BAT(LIM)

V

(1V2)

(VDC

limiting voltage on a pin

XTAL32Km, XTAL16Mp,

XTAL16Mm

(Note 7)

-0.2

min(1.2,V

BAT_RF+

0.2)

V

PIN(LIM)

limiting voltage on the

VDCDC_RF pin

Supply voltage on

VDCDC_RF

(Note 7)

min(3.3,V

BAT_RF+

0.2)

PIN(LIM)

DC_RF)

V

(XTAL limiting voltage on a pin

XTAL32Kp

min(1.5,V

BAT_RF+

0.2)

PIN(LIM)

32Kp)

V

(WL electrostatic discharge

voltage (Human Body

Model)

2000

4000

ESD(HBM)

CSP34)

V

(QF

electrostatic discharge

voltage (Human Body

Model)

ESD(HBM)

N40)

V

(QF

electrostatic discharge

voltage (Human Body

Model)

ESD(HBM)

N48)

V

(WLC electrostatic discharge

voltage (Machine Model)

200

500

V

ESD(MM)

SP34)

V

(QFN electrostatic discharge

voltage (Machine Model)

ESD(MM)

40)

V

(QFN electrostatic discharge

voltage (Machine Model)

ESD(MM)

48)

V

(WL electrostatic discharge

voltage (Charged Device

Model)

ESD(CDM)

CSP34)

V

N40)

(QF

electrostatic discharge

voltage (Charged Device

Model)

1000

V

ESD(CDM)

V

(QF

electrostatic discharge

voltage (Charged Device

Model)

ESD(CDM)

N48)

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Note 7: The device should not be exposed for prolonged periods of time to voltages between the Recommended Operating Conditions and the

Absolute Maximum Ratings range.

Table 258: Recommended Operating Conditions

Parameter

Description

Conditions

Min

Typ

Max

Unit

V

programming voltage

Supply voltage on pin

VPP during OTP pro-

6.6

6.7

6.8

V

PP

gramming; T  50 C

J

V

(VBAT1V) battery supply voltage

Supply voltage on

VBAT1V in a boost con-

verter application

(VBAT3V is second out-

put of boost-converter in

this case)

0.9

3.3

V

BAT

V

(VBAT3V) battery supply voltage

Supply voltage on

VBAT3V and VBAT_RF

in a buck-converter

application, pin VBAT1V

is connected to ground

2.35

(Note 8)

V

BAT

(default)

voltage on a pin

Voltage between pin and

GND

0

min(3.3,V

BAT_RF+

0.2)

V

(1V2)

XTAL32Km, XTAL16Mp,

XTAL16Mm

0

1.2

V

(VDCDC_ voltage on a pin

ambient temperature

Supply voltage on

VDCDC_RF

3.3

RF)

T

-40

85

°C

A

Note 8: Cold boot should not be performed if voltage is less than 2.5 V because of possible corruption during OTP data mirroring. Trim values pro-

grammed in the OTP as well as the application image, should be copied into RAM while VBAT3V >= 2.5 V.

Table 259: DC Characteristics

Parameter

Description

Conditions

Min

Typ

Max

Unit

I

(DP_SLP)_ battery supply current

Boost configuration in

deep-sleep with 1 kB

retention RAM active,

running from RC32K

oscillator at lowest fre-

quency

0.48

A

BAT

BOOST_1kB

I

(DP_SLP)_ battery supply current

Boost configuration in

deep-sleep with 2 kB

retention RAM active,

running from XTAL32K

oscillator

0.55

0.7

A

BAT

BOOST_2kB

I

(DP_SLP)_ battery supply current

Typical boost-applica-

tion in deep-sleep with 8

kB retention RAM active,

running from XTAL32K

oscillator

2

BAT

BOOST_8kB

I

(EXT_SLP) battery supply current

Typical boost-applica-

tion in extended-sleep

mode with 42 kB (Sys-

RAM) and 1 kB

1.37

BAT

_BOOST_43K

B

(RetRAM) retained

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Table 259: DC Characteristics

Parameter

Description

Conditions

Min

Typ

Max

Unit

I

(EXT_SLP) battery supply current

Typical boost-applica-

tion in extended-sleep

mode with 42 kB (Sys-

RAM) and 8 kB

1.5

3

A

BAT

_BOOST_50kB

(RetRAM) retained

I

(DP_SLP)_ battery supply current

Buck configuration in

deep-sleep with 1 kB

retention RAM active,

running from RC32K

oscillator at lowest fre-

quency

0.4

A

BAT

BUCK_1kB

I

(DP_SLP)_ battery supply current

Buck configuration in

deep-sleep with 2 kB

retention RAM active,

running from XTAL32K

oscillator

0.45

0.6

A

BAT

BUCK_2kB

I

(DP_SLP)_ battery supply current

Typical buck-application

in deep-sleep with 8 kB

retention RAM active,

running from XTAL32K

oscillator

2

BAT

BUCK_8kB

I

(EXT_SLP) battery supply current

Typical buck-application

in extended-sleep mode

with 42 kB (SysRAM)

and 1 kB (RetRAM)

retained

1.2

BAT

_BUCK_43KB

I

(EXT_SLP) battery supply current

Typical buck-application

in extended-sleep mode

with 42 kB (SysRAM)

and 8 kB (RetRAM)

retained

1.4

3

BAT

_BUCK_50kB

I

(ACT_RX)_ battery supply current

Typical application with

boost converter and

receiver active

13.4

12.4

5.1

16

15

6

mA

BAT

BOOST

I

(ACT_TX)_ battery supply current

Typical application with

boost converter and

transmitter active

BAT

BOOST

I

(ACT_RX)_ battery supply current

Typical application with

buck converter and

receiver active

BAT

BUCK

I

(ACT_TX)_ battery supply current

Typical application with

buck converter and

transmitter active

4.8

6

BAT

BUCK

Table 260: Timing Characteristics

Parameter

(BOOST)

Description

Conditions

Min

Typ

Max

Unit

t

startup time

Boost-mode; time from

deep-sleep to software

start.

1.2

(Note 9)

ms

STA

Typical application, run-

ning from retention RAM

on 16 MHz RC oscillator

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Table 260: Timing Characteristics

Parameter

(BUCK)

Description

Conditions

Min

Typ

Max

Unit

t

startup time

Buck-mode; time from

deep-sleep to software

start.

1

ms

STA

(Note 9)

Typical application, run-

ning from retention RAM

on 16 MHz RC oscillator

Note 9: Worst-case value under Normal Operating Conditions.

Table 261: 16 MHz Crystal Oscillator: Recommended Operating Conditions

Parameter

(16M)

Description

Conditions

Min

Typ

Max

Unit

f

crystal oscillator fre-

quency

16

MHz

XTAL

ESR(16M)

C (16M)

equivalent series resis-

tance

100

12



load capacitance

No external capacitors

are required

10

pF

L

C (16M)

shunt capacitance

5

pF

0

f

(16M)

crystal frequency toler-

ance

After optional trimming;

including aging and tem-

perature drift

-20

20

ppm

XTAL

(Note 10)

crystal frequency toler-

ance

Untrimmed; including

aging and temperature

drift

-40

40

ppm

X-

(16M)UNT

TAL

(Note 11)

P

)

(16M maximum drive power

(16M) external clock voltage

(Note 12)

100

1

W

DRV(MAX)

V

Only in case of an exter-

nal reference clock on

XTAL16Mp (XTAL16Mm

floating or connected to

mid-level 0.6 V)

1.2

V

CLK(EXT)

 (EXTER-

NAL)16M

phase noise

f = 50 kHz

in case of an external

reference clock

-130

dBc/

Hz

N

C

Note 10: Using the internal varicaps a wide range of crystals can be trimmed to the required tolerance.

Note 11: Maximum allowed frequency tolerance for compensation by the internal varicap trimming mechanism.

Note 12: Select a crystal which can handle a drive-level equal or more than this specification

Table 262: 16 MHz Crystal Oscillator: Timing Characteristics

Parameter

Description

Conditions

Min

Typ

Max

Unit

t

(16M) crystal oscillator startup

time

0.5

2

3

ms

STA(XTAL)

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Table 263: 32 kHz Crystal Oscillator: Recommended Operating Conditions

Parameter

Description

Conditions

Min

Typ

Max

Unit

V

(32K) external clock voltage

peak-peak voltage of

external clock at

0.1

0.2

1.5

V

CLK(EXT)

XTAL32Kp, pin

XTAL32Km floating.

note: XTAL32Kp is inter-

nally AC coupled

f

(32k)

crystal oscillator fre-

quency

frequency range for an

external clock

10

32.768

100

kHz

XTAL

(for a crystal, use either

32.000 kHz or 32.768

kHz)

ESR(32k)

C (32k)

equivalent series resis-

tance

100

9

k

load capacitance

no external capacitors

are required for a 6 pF or

7 pF crystal

6

7

1

pF

L

C (32k)

shunt capacitance

2

pF

0

f

(32k)

crystal frequency toler-

ance (including aging)

Timing accuracy is domi-

nated by crystal accu-

racy. A much smaller

value is preferred

-250

0.1

250

ppm

XTAL

P

(32k) maximum drive power

(Note 13)

W

DRV(MAX)

Note 13: Select a crystal that can handle a drive-level of at least this specification.

Table 264: 32 kHz Crystal Oscillator: Timing Characteristics

Parameter

Description

Conditions

Min

Typ

Max

Unit

t

(32k) crystal oscillator startup

time

Typical application, time

until 1000 clocks are

detected

0.4

s

STA(XTAL)

(Note 14)

Note 14: This parameter is very much dependent on crystal parameters

Table 265: DC-DC Converter: Recommended Operating Conditions

Parameter

Description

Conditions

Min

1.5

0.5

Typ

2.2

1

Max

3

Unit

H

L

effective inductance

C

(VDCDC) effective load capaci-

tance

VDCDC and VDDCRF

combined

10

F

OUT

(Note 15)

C

(VBAT3V) effective load capaci-

tance

VBATRF and VBAT3V

combined are the sec-

ond output of the boost-

converter

0.5

1

10

F

OUT

(Note 15)

Note 15: A low value will result in lowest power consumption, keep this value at 1 uF or 2 uF.

Table 266: DC-DC Converter: DC Characteristics

Parameter

Description

Conditions

Min

Typ

Max

Unit

V (BUCK)

output voltage

default settings

1.41

V

O

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Table 266: DC-DC Converter: DC Characteristics

Parameter

V (BOOST)

Description

Conditions

Min

Typ

1.41

86

Max

Unit

V

output voltage

default settings, VDCDC

O



(BU maximum conversion

efficiency

%

CONV_MAX

CK)



OST)

(BO maximum conversion

efficiency

80

%

CONV_MAX

V /

line regulation

2.35 V  VBAT3V  3.3 V

-2

0.7

2

4

%/V

O

V (BUCK)

I

V /

line regulation

0.9 V  VBAT1V  1.2 V

(Note 16)

1

%/V

O

V (BOOST)

I

V /I (BUCK) load regulation

VBAT3V = 2.5 V

VBAT1V = 1.2 V

-0.2

-0.02

-0.07

0.2

%/mA

O

L

V /

load regulation

O

I (BOOST)

L

V

(BUCK)

ripple voltage

buck mode; RMS ripple

voltage

5

8

mV

RPL

V

(BOOST) ripple voltage

VBAT1V  1.2 V, boost

mode; RMS ripple volt-

age

RPL

(Note 16)

Note 16: When VBAT1V > VDCDC_nominal, VDCDC will follow VBAT1V.

Table 267: Digital Input/Output: DC Characteristics

Parameter

Description

Conditions

Min

Typ

Max

0.36

Unit

V

HIGH level input voltage

LOW level input voltage

0.84

IH

IL

V

V (RST)

HIGH level input voltage RST pin

LOW level input voltage RST pin

0.84

0.72

V

IH

V (RST)

V

IL

V

(VBAT1V)

HIGH level output volt-

age

Iout = -250 A, VBAT3V

= 2.35 V, VBAT1V = 0.9

V

OH

(VBAT3V)

HIGH level output volt-

age

Iout = -4.8 mA, VBAT3V

= 2.35 V, VBAT1V = 0 V

(Note 17)

1.88

V

OH

V

(VBAT1V)

(VBAT3V)

LOW level output voltage Iout = 250 A, VBAT3V =

0.18

0.47

V

OL

2.35 V, VBAT1V = 0.9 V

LOW level output voltage Iout = 4.8 mA, VBAT3V =

2.35 V, VBAT1V = 0 V

OL

(Note 18)

I

HIGH level input current Vin = VBAT3V = 2.5 V

-1

1

A

IH

I

LOW level input current

HIGH level input current Vin = VBAT3V = 2.5 V

LOW level input current Vin = VSS = 0 V

HIGH level input current RST pin, V(RST) = 1.2 V

Vin = VSS = 0 V

IL

I (PD)

50

150

-50

75

IH

I (PU)

-150

25

IL

I (RST)

IH

Note 17: In Boost mode the output source current is limited to Iout = -250 uA.

Note 18: In Boost mode the output sink current is limited to Iout = 250 uA.

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Table 268: General Purpose ADC: Recommended Operating Conditions

Parameter

(ADC)

Description

Conditions

Min

Typ

Max

Unit

N

number of bits (resolu-

tion)

10

bit

BIT

Table 269: General Purpose ADC: DC Characteristics

Parameter Description Conditions

Min

Typ

Max

Unit

V

zero-scale input voltage single-ended, calibrated

at zero input

-2.5

0

2.5

mV

I(ZS)

full-scale input voltage

single-ended, calibrated

at zero input

1150

1180

-1180

1180

1250

mV

I(FS)

negative full-scale input

voltage

differential, calibrated at

zero input

I(FSN)

I(FSP)

positive full-scale input

voltage

differential, calibrated at

zero input

INL

integral non-linearity

-2

2

LSB

DNL

differential non-linearity

Table 270: General Purpose ADC: Timing Characteristics

Parameter

(ADC)

Description

Conditions

Min

Typ

Max

Unit

t

conversion time

Excluding initial settling

time of the LDO and the

3x-attenuation (if used):

0.25

0.4

s

CONV

LDO settling time is 20

s (max), 3x-attenuation

settling time = 1 s (max)

Using internal ADC-clock

(~200 MHz)

Table 271: Radio: DC Characteristics

Parameter

Description

Conditions

Min

Typ

Max

Unit

I

(RF)RX

battery supply current

receive mode; radio

3.7

4.3

mA

BAT

receiver and synthesizer

active; DCDC converter

assumed ideal; T = 25

A

°C

(Note 19)

I

(RF)TX

battery supply current

transmit mode; radio

transmitter and synthe-

sizer active; DCDC con-

3.4

4

mA

BAT

verter assumed ideal; T

A

= 25 °C

(Note 19)

Note 19: The DCDC-converter efficiency is assumed to be 100 % to enable benchmarking of the radio currents at battery supply domain (VBAT3V =

3 V).

Datasheet

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Table 272: Radio: AC Characteristics

Parameter

Description

Conditions

Min

Typ

Max

Unit

P

(CLEAN) sensitivity level

DC-DC converter

-93

dBm

SENS

enabled; Dirty Transmit-

ter disabled; T = 25 °C;

A

PER = 30.8 %

(Note 20)

P

sensitivity level

Normal Operating Condi-

tions; DC-DC converter

-92.5

dBm

SENS

enabled; T = 25 °C;

A

PER = 30.8 %

(Note 20)

P (max)

input power level

DC-DC converter dis-

10

dBm

I

abled; T = 25 C; PER 

A

30.8 %

(Note 20)

P

intermodulation distor-

tion interferer power

level

worst case interferer

-35

-31

INT(IMD)

level @ f , f with 2f -f =

1

2

1 2

f , |f -f | = n MHz and n =

0

1 2

3,4,5; P

= -64

WANTED

dBm @ f ; PER = 30.8

0

%; T = 25 °C

A

(Note 22)

CIR(0)

CIR(1)

CIR(P2)

carrier to interferer ratio

n = 0; interferer @ f = f

7

21

15

-9

dB

1

0

+ n*1 MHz; T = 25 °C

A

(Note 23)

n = ±1; interferer @ f =

-3

1

f + n*1 MHz; T = 25 °C

0

A

(Note 23)

n = +2 (image fre-

-20

quency); interferer @ f1

= f0 + n*1 MHz; T = 25

A

C

(Note 23)

CIR(M2)

CIR(P3)

carrier to interferer ratio

n = -2; interferer @ f1 =

-30

-17

-15

dB

f0 + n*1 MHz; T = 25 C

A

(Note 23)

n = +3 (image frequency

+ 1 MHz); interferer @ f1

= f0 + n*1 MHz; T = 25

A

C

(Note 23)

CIR(M3)

CIR(4)

carrier to interferer ratio

n = -3; interferer @ f1 =

-35

-37

-27

dB

f0 + n*1 MHz; T = 25 C

A

(Note 23)

|n| >= 4 (any other BLE

channel); interferer @ f

1

= f + n*1 MHz; T = 25

0

A

°C

(Note 23)

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Table 272: Radio: AC Characteristics

Parameter

Description

Conditions

Min

Typ

Max

Unit

P

(I)

blocker power level

30 MHz  f  2000

-5

dBm

BL

MHz; P

= -67

WANTED

dBm; T = 25 °C

A

(Note 24)

(II)

(III)

(IV)

blocker power level

2003 MHz  f  2399

-15

-5

dBm

BL

MHz; P

= -67

WANTED

dBm; T = 25 °C

A

(Note 24)

2484 MHz  f  2997

BL

MHz; P

= -67

WANTED

dBm; T = 25 C

A

(Note 24)

3000 MHz  f  12.75

BL

GHz; P

= -67

WANTED

dBm; T = 25 C

A

(Note 24)

P

(min)

RSSI power level

absolute power level for

-115

-26

-112

-109

RSSI

RXRSSI[7:0] = 0; T =

A

25 °C

(Note 25)

(max)

upper limit of monoto-

-19

0

dBm

dB

RSSI

nous range; T = 25 °C

A

L

(RSSI)BO level accuracy

tolerance of 5 % to 95 %

confidence interval of

3

ACC

OST

P

: when RXRSSI[7:0]

RF

= X, 50 < X < 175; burst

mode 1500 packets; T

A

= 25 °C; DC-DC con-

verter in BOOST mode

L

CK

(RSSI)BU level accuracy

tolerance of 5 % to 95 %

confidence interval of

0

2

dB

ACC

P

: when RXRSSI[7:0]

RF

= X, 50 < X < 175; burst

mode 1500 packets; T

A

= 25 °C; DC-DC con-

verter in BUCK mode

L

(RSSI)

level resolution

gradient of monotonous

range for RXRSSI[7:0] =

X, 50 < X < 175; burst

0.46

0.474

0.485

dB/

LSB

RES

mode 1500 packets; T

A

= 25C

ACP(2M)

adjacent channel power

level

f

= 2 MHz; T =

-53

-50

-47

dBm

OFFSET

A

25C

(Note 26)

ACP(2M)(EOC) adjacent channel power

level

f

= 2 MHz; -40C

OFFSET

 T  +85C

A

(Note 26)

ACP(3M)

adjacent channel power

level

f

 3 MHz; T =

-57

-55

dBm

OFFSET

A

25C

(Note 26)

Datasheet

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Table 272: Radio: AC Characteristics

Parameter

Description

Conditions

 3 MHz; -40C

Min

Typ

Max

Unit

ACP(3M)(EOC) adjacent channel power

level

f

-57

-47

dBm

OFFSET

 T  +85C

A

(Note 26)

P

output power level

V

= 3 V; maximum

-2

-1

0

dBm

O

DD

gain; T = 25 °C

A

P (HD2)

output power level (sec- VDD = 3 V; maximum

ond harmonic) gain; T = 25 C

-54

-56

-70

-20

-40

-15

dBm

O

A

P (HD3)

output power level (third VDD = 3 V; maximum

O

harmonic)

gain; T = 25 C

A

P (HD4)

output power level

(fourth harmonic)

VDD = 3 V; maximum

O

gain; T = 25 C

A

P (HD5)

output power level (fifth

harmonic)

VDD = 3 V; maximum

O

gain; T = 25 C

A

P (NFM)

output power level in

'Near Field Mode'

V

= 3 V; maximum

-25

O

DD

gain; T = 25 °C

A

(Note 27)

Note 20: Measured according to Bluetooth® Low Energy Test Specification RF-PHY.TS/4.0.1, section 6.4.1.

Note 21: Measured according to Bluetooth® Low Energy Test Specification RF-PHY.TS/4.0.1, section 6.4.2.

Note 22: Measured according to Bluetooth® Core Technical Specification document, version 4.2, volume 6, section 4.4. Published value is for n =

IXIT = 4 . IXIT = 5 gives the same results, IXIT = 3 gives results that are 5 dB lower.

Note 23: Measured according to Bluetooth® Core Technical Specification document, version 4.2, volume 6, section 4.2.

Note 24: Measured according to Bluetooth® Core Technical Specification document, version 4.2, volume 6, section 4.3. Due to limitations of the

measurement equipment, levels of -5 dBm should be interpreted as > -5 dBm.

Note 25: PRF = PRSSI(min) + LRES(RSSI) x RXRSSI[7:0] ± LACC(RSSI). Thanks to constant gain biasing of RF part in the receiver, the RSSI can

be used to estimate absolute power levels, rather than mere level changes. Even across the full temperature range the variation is limited.

Note 26: Measured according to Bluetooth® Low Energy Test Specification RF-PHY.TS/4.0.1, section 6.2.3.

Note 27: To activate the "Near Field Mode", program address 0x50002418 with the value 0x0030.

Table 273: Stable Low Frequency RCX Oscillator: Timing Characteristics

Parameter

(RCX)

Description

Conditions

Min

Typ

Max

Unit

f

RCX oscillator frequency default setting, buck

mode only

5

10

40

kHz

RC

f (RCX)

RCX oscillator fre-

quency drift

buck mode only

(Note 28)

-500

500

ppm

°C/s

RC

T /

ambient temperature

gradient

buck mode only; connec-

tion interval 100 ms

0.66

A

t(RCX)100ms

T /t(RCX)4s ambient temperature

buck mode only; connec-

tion interval 4 s

0.33

°C/s

A

gradient

Note 28: Maximum recommended connection interval (including slave latency) for the RCX usage is 2 s.

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7

Package Information

7.1 MOISTURE SENSITIVITY LEVEL (MSL)

The MSL is an indicator for the maximum allowable

time period (floor life time) in which a moisture sensi-

tive plastic device, once removed from the dry bag, can

be exposed to an environment with a maximum tem-

perature of 30 °C and a maximum relative humidity of

60 % RH. before the solder reflow process.

WLCSP packages are qualified for MSL 1.

QFN packages are qualified for MSL 3.

MSL Level

MSL 4

Floor Life Time

72 hours

MSL 3

168 hours

MSL 2A

MSL 2

4 weeks

1 year

MSL 1

Unlimited at 30 °C / 85 % RH

7.2 WLCSP HANDLING

Manual handling of WLCSP packages should be

reduced to the absolute minimum. In cases where it is

still necessary, a vacuum pick-up tool should be used.

In extreme cases plastic tweezers could be used, but

metal tweezers are not acceptable, since contact may

easily damage the silicon chip.

Removal will cause damage to the solder balls and

therefore a removed sample cannot be reused.

WLCSP is sensitive to visible and infrared light. Pre-

cautions should be taken to properly shield the chip in

the final product.

7.3 SOLDERING INFORMATION

Refer to the JEDEC standard J-STD-020 for relevant

soldering information.

This document can be downloaded from http://

www.jedec.org

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7.4 PACKAGE OUTLINES

Figure 13: QFN48 Package Outline Drawing

Datasheet

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Figure 14: QFN40 Package Outline Drawing

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Figure 15: WLCSP34 Package Outline Drawing

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Status Definitions

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Datasheet Status

Product Status

Definition

1.<n>

Target

Development

This datasheet contains the design specifications for product

development. Specifications may change in any manner without

notice.

2.<n>

3.<n>

Preliminary

Final

Qualification

Production

This datasheet contains the specifications and preliminary char-

acterization data for products in pre-production. Specifications

may be changed at any time without notice in order to improve

the design.

This datasheet contains the final specifications for products in

volume production. The specifications may be changed at any

time in order to improve the design, manufacturing and supply.

Major specification changes are communicated via Customer

Product Notifications. Datasheet changes are communicated

via www.dialog-semiconductor.com.

4.<n>

Obsolete

Archived

This datasheet contains the specifications for discontinued

products. The information is provided for reference only.

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型号：	DA14580-01UNA
厂家：	Dialog Semiconductor
描述：	Bluetooth Low Energy 4.2 SoC 电信电信集成电路
文件：	总155页 (文件大小：1209K)
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