DA7219-02VBA [DIALOG]
Audio codec with Advanced Accessory Detect;型号: | DA7219-02VBA |
厂家: | Dialog Semiconductor |
描述: | Audio codec with Advanced Accessory Detect 商用集成电路 |
文件: | 总123页 (文件大小:2700K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DA7219
Audio codec with Advanced Accessory Detect
Company confidential
General description
The DA7219 is an audio codec with Advanced Accessory Detection (AAD).
DA7219 contains a mono microphone to ADC path, and a stereo DAC to HP path.
The AAD block supports three-pole (headphone) and four-pole (headset) jacks, and allows the
automatic pin order switching of MIC/GND on CTIA or OMTP headsets. It also supports automatic
button detection.
Key features
■
High performance mono microphone to ADC
record path with 90 dB SNR
■
A microphone input with ALC (automatic
level control)
□
ADC digital filters with audio and voice
mode high-pass characteristics
■
■
■
Digital Sidetone path with gain
Digital tone generator
□
A low-noise microphone bias regulator
with programmable output
System controller for simplified pop-free
start-up and shutdown
■
■
High performance stereo DAC to headphone
playback path with 100 dB SNR
■
■
■
■
■
■
Single interface 24 kHz ADC/48 kHz DAC
mixed sample rates supported
□
DAC digital filters with audio and voice
mode high-pass cut-off and 5-band
equaliser
Shutdown mode for very low current
consumption during standby
Phase locked loop with sample rate
tracking to generate system clock
Advanced Accessory Detection supports
□
□
□
□
Three/four pole jack detection
MIC/GND polarity switching
Multiple button detection
4-wire digital audio interface with support
for I2S, TDM and other audio formats
2-wire I2C compatible with support for
High Speed mode up to 3.4 MHz
Headphone impedance testing
WL-CSP RouteEasy™ package for low
cost PCB manufacture
Applications
■
■
■
Chromebooks
■
Headphone accessories
Remote controllers
Gaming controllers
Portable audio applications
Tablets and eBooks
■
■
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DA7219
Audio codec with Advanced Accessory Detect
Company confidential
System diagram
DA7219
Audio
switch
Analog
Audio
Jack
Codec
Analog
HP Amp
Headset
Digital
SoC
DMIC
Digital
Digital
Digital
Class D
Class D
Stereo
Speaker
Figure 1: DA7219 in a digital distributed system
Datasheet
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DA7219
Audio codec with Advanced Accessory Detect
Company confidential
Contents
General description............................................................................................................................. 1
Key features ......................................................................................................................................... 1
Applications ......................................................................................................................................... 1
System diagram................................................................................................................................... 2
Contents ............................................................................................................................................... 3
1
2
3
4
Terms and definitions................................................................................................................... 6
References ..................................................................................................................................... 6
Block diagram................................................................................................................................ 7
Pinout ............................................................................................................................................. 8
4.1 Microphone pins.................................................................................................................. 10
4.2 Accessory detect pins ......................................................................................................... 10
4.3 Interface input pins.............................................................................................................. 10
4.4 Interface output pins............................................................................................................ 11
4.5 Interface bidirectional pins .................................................................................................. 11
4.6 Headphone output pins....................................................................................................... 11
4.7 Charge pump pins............................................................................................................... 11
4.8 References.......................................................................................................................... 12
4.9 Supply pins.......................................................................................................................... 12
4.10 Ground pins......................................................................................................................... 12
5
6
7
8
9
Absolute maximum ratings ........................................................................................................ 13
Recommended operating conditions........................................................................................ 13
Electrical characteristics............................................................................................................ 14
Timing characteristics ................................................................................................................ 18
Functional description................................................................................................................ 21
9.1 Device operating modes ..................................................................................................... 21
9.2 Input paths .......................................................................................................................... 23
9.2.1
Microphone input ................................................................................................. 23
9.2.1.1
9.2.1.2
9.2.1.3
Microphone bias .............................................................................. 23
Microphone amplifier ....................................................................... 24
Input amplifiers ................................................................................ 24
9.2.2
Analogue to Digital Converter (ADC)................................................................... 25
9.3 Digital engine ...................................................................................................................... 26
9.3.1
Input processing .................................................................................................. 27
9.3.1.1
9.3.1.2
9.3.1.3
ADC digital gain............................................................................... 27
High-pass filter................................................................................. 27
Automatic Level Control (ALC)........................................................ 28
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
Sidetone processing ............................................................................................ 29
Tone generator .................................................................................................... 30
Digital router ........................................................................................................ 31
System controller................................................................................................. 31
Output processing................................................................................................ 32
9.3.6.1
9.3.6.2
DAC digital gain............................................................................... 32
High-pass filter................................................................................. 32
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Audio codec with Advanced Accessory Detect
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9.3.6.3
9.3.6.4
5-band equaliser.............................................................................. 33
DAC soft mute ................................................................................. 35
9.4 Output paths........................................................................................................................ 36
9.4.1
9.4.2
Digital to Analogue Converter (DAC)................................................................... 36
Headphone outputs ............................................................................................. 36
9.4.2.1
9.4.2.2
Buffer amplifier................................................................................. 36
Headphone amplifiers...................................................................... 37
9.4.3
9.4.4
Charge pump control ........................................................................................... 37
Tracking the demands on the charge pump output............................................. 39
9.4.4.1
9.4.4.2
9.4.4.3
cp_mchange = 01 (tracking the PGA gain setting).......................... 39
cp_mchange = 10 (tracking the DAC signal setting) ....................... 39
cp_mchange = 11 (tracking the output signal magnitude) .............. 39
9.5 Advanced Accessory Detection (AAD) ............................................................................... 40
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
Configuring Advanced Accessory Detection (AAD) ............................................ 41
Detection of jack insertion or removal ................................................................. 44
Three-pole or four-pole jack insertion.................................................................. 45
Jack pin order detection with four-pole jacks....................................................... 45
Headphone output and line output ...................................................................... 46
Detection of buttons............................................................................................. 46
9.6 Clocking .............................................................................................................................. 49
9.6.1
MCLK input .......................................................................................................... 49
9.6.1.1 MCLK detection ............................................................................... 49
9.6.2
9.6.3
9.6.4
9.6.5
9.6.6
Audio reference oscillator .................................................................................... 49
PLL bypass mode................................................................................................ 49
Normal PLL mode (DAI master) .......................................................................... 50
Example calculation of the feedback divider setting:........................................... 51
SRM PLL mode (DAI slave) ................................................................................ 52
9.7 Reference generation.......................................................................................................... 52
9.7.1
9.7.2
9.7.3
9.7.4
Voltage references............................................................................................... 52
Bias currents........................................................................................................ 52
Voltage levels ...................................................................................................... 52
IO voltage level.................................................................................................... 52
9.8 I2C control interface............................................................................................................ 53
9.9 Digital Audio Interface (DAI) ............................................................................................... 56
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
DAI channels ....................................................................................................... 57
I2S mode ............................................................................................................. 57
Left justified mode................................................................................................ 57
Right justified mode ............................................................................................. 57
DSP mode ........................................................................................................... 58
10 Register maps and definitions................................................................................................... 59
11 Package information................................................................................................................. 113
12 Ordering information ................................................................................................................ 114
Appendix A Applications information........................................................................................... 115
A.1 Codec initialisation ............................................................................................................ 115
A.2 Automatic ALC calibration................................................................................................. 115
Appendix B Components................................................................................................................ 116
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DA7219
Audio codec with Advanced Accessory Detect
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B.1 Audio inputs ...................................................................................................................... 116
B.2 Microphone bias................................................................................................................ 117
B.3 Audio outputs .................................................................................................................... 117
B.4 Headphone charge pump ................................................................................................. 118
B.5 Digital interfaces................................................................................................................ 119
B.6 References........................................................................................................................ 119
B.7 Supplies ............................................................................................................................ 120
B.8 Ground .............................................................................................................................. 120
Appendix C PCB layout guidelines ............................................................................................... 121
C.1 Layout and schematic support.......................................................................................... 121
C.2 General recommendations................................................................................................ 121
C.3 Capacitor selection............................................................................................................ 122
Datasheet
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DA7219
Audio codec with Advanced Accessory Detect
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1
Terms and definitions
ADC
ALC
CTIA
Analogue to Digital Converter
Automatic Level Control
Cellular Telecommunications Industry Association,
(now known as ‘The Wireless Association’)
DAC
DAI
Digital to Analogue Converter
Digital Audio Interface
Digital Microphone
DMIC
DTMF
FS
Dual Tone Multi-Frequency
Sample Rate
I2C
Inter-Integrated Circuit interface
Inter-IC Sound
I2S
LDO
MCLK
OMTP
PC
Low Dropout Regulator
Master Clock
Open Mobile Terminals Platform
Program Counter
PGA
PLL
Programmable Gain Amplifier
Phase Locked Loop
PSRR
RC
Power Supply Rejection Ratio
Resistance-Capacitance
System Controller
SC
SDM
SNR
SRM
SWG
TDM
THD+N
VCO
Sigma Delta Modulator
Signal to Noise Ratio
Sample Rate Matching
Sine Wave Generator
Time Division Multiplexing
Total Harmonic Distortion plus Noise
Voltage-Controlled Oscillator
2
References
[1] Android wired audio headset specification (v1.1)
(https://source.android.com/accessories/headset/specification.html )
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DA7219
Audio codec with Advanced Accessory Detect
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3
Block diagram
DIGITAL ENGINE
Impedance
Detection
Sidetone
Path
DA7219
System
Controller
HP_L
DACL
DACR
Tone
Generator
HP_R
MIC_P
MIC_N
ADC
MICBIAS
MIC
RING2
SLEEVE
AAD
MCLK
PLL
JACKDET
SLEEVE_SENSE
RING2_SENSE
DIGITAL
AUDIO
INTERFACE
I2C CONTROL
INTERFACE
CHARGE
PUMP
VOLTAGE
REFS
Figure 2: DA7219 block diagram
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DA7219
Audio codec with Advanced Accessory Detect
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4
Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HPCSP
HP_L
HP_R
VREF
VMID
SLEEVE
VDD_MIC
MIC_N
A
B
C
D
RING2_
SENSE
SLEEVE_
SENSE
GND_CP
DACREF
GND
GND_HP
MICBIAS
MIC_P
HPCSN
HPCFN
VDD
DATIN
DATOUT
RING2
MIC
MCLK
HPCFP
VDD_IO
BCLK
WCLK
nIRQ
SCL
SDA
JACKDET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
View from above
“Live Bug”
Analogue
Digital
Power
Ground
Figure 3: DA7219 ballout diagram
Table 1: DA7219 pin description
Pin no.
Pin name
Type
(Table 2)
Description
Microphone Inputs
B16
A15
B14
MIC_P
AI
Differential analogue microphone 1 input (Pos)
Differential analogue microphone 1 input (Neg)
Microphone bias output
MIC_N
AI
MICBIAS
AO
Accessory Detect
D16
A11
C13
B6
JACKDET
SLEEVE
RING2
DI
Jack Detect Input from socket
AIO
AIO
AIO
Socket Sleeve (configured as MIC or GND)
Socket Ring 2 (configured as GND or MIC)
SLEEVE_
SENSE
Socket Sleeve (Sense)
B4
RING2_
SENSE
AIO
AIO
Socket Ring 2 (Sense)
Microphone DC input
C15
MIC
Headphone Outputs
A3
A5
HP_L
HP_R
AO
AO
Single-ended headphone output (Left)
Single-ended headphone output (Right)
Charge Pump
A1
C1
D2
C3
HPCSP
HPCSN
HPCFP
HPCFN
AIO
AIO
AIO
AIO
Charge pump reservoir capacitor (Positive)
Charge pump reservoir capacitor (Negative)
Charge pump flying capacitor (Positive)
Charge pump flying capacitor (Negative)
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DA7219
Audio codec with Advanced Accessory Detect
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Pin no.
Pin name
Type
Description
(Table 2)
Digital Interface
I2C bidirectional data
I2C clock
D14
D12
D10
C7
SDA
DIOD
DI
SCL
nIRQ
DIOD
DIO
DIO
DIO
DIO
DI
Interrupt output (open drain active low)
DAI data input to DA7219
DAI data output from DA7219
DAI bit clock
DATIN
DATOUT
BCLK
WCLK
MCLK
C9
D6
D8
DAI word clock
C11
Master clock input
References
B8
A9
A7
DACREF
VMID
AIO
AIO
AIO
DAC reference decoupling capacitor
Mid-rail reference decoupling capacitor
Bandgap reference decoupling capacitor
Supplies
VREF
C5
VDD
AI
AI
AI
Main analogue and digital supply
Supply for MICBIAS LDO
Supply for digital interfaces
Grounds
A13
D4
VDD_MIC
VDD_IO
B2
GND_CP
GND
AI
AI
AI
Ground
B10
B12
Ground
GND_HP
Ground
Table 2: Pin type definition
Pin type Description
Pin type
AI
Description
DI
Digital Input
Analogue Input
Analogue Output
Analogue Input/Output
DIO
DIOD
Digital Input/Output
AO
Digital Input/Output open Drain AIO
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DA7219
Audio codec with Advanced Accessory Detect
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4.1 Microphone pins
Pin MIC_P
MIC_P is the positive differential input for the analogue microphone channel. It can be used as a
single-ended input if MIC_N is grounded (see Figure 7).
Pin MIC_N
MIC_N is the negative differential input for the analogue microphone channel. It should be grounded
when using a single-ended analogue microphone configuration.
Pin MICBIAS
MICBIAS is the internally generated microphone supply. This must be decoupled with a 1 µF
capacitor.
4.2 Accessory detect pins
Pin JACKDET
JACKDET is used to signal to the device when the Jack is fully inserted into the 3.5 mm jack (or
alternative) socket
If not required it should be left unconnected.
Pin SLEEVE
Sleeve is tested during the sense stage and then configured as either the headset microphone input
or the headset ground connection
Pin RING2
RING2 is tested during the sense stage and then configured as either the headset microphone input
or the headset ground connection.
Pin SLEEVE_SENSE
SLEEVE sense line to guarantee accuracy over distance, cables and connectors.
Pin RING2_SENSE
RING2 sense line to guarantee accuracy over distance, cables and connectors.
Pin MIC
MIC is the DC input for the analogue accessory detect.
4.3 Interface input pins
Pin MCLK
MCLK is the master clock input pin. It is used as the main system clock either directly or via the PLL.
Pin SCL
SCL is the Control Interface (I2C) clock input and is used in conjunction with SDA to control the
device.
Pin DATIN
DATIN is the data input pin which forms part of the Digital Audio Interface. It is used to present audio
playback data to the device.
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Audio codec with Advanced Accessory Detect
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4.4 Interface output pins
Pin nIRQ
nIRQ is the open drain active-low interrupt output to alert the host to either an accessory or a
level-detect event.
Pin DATOUT
DATOUT is the data output pin which forms part of the Digital Audio Interface. It is used to present
audio record data to the host.
4.5 Interface bidirectional pins
Pin SDA
SDA is the Control Interface (I2C) data input/output and is used in conjunction with SCL to control the
device.
Pin BCLK
BCLK is the bit clock input/output pin which forms part of the Digital Audio Interface (DAI). It is used
to clock audio data bits into or out from the device or both.
Pin WCLK
WCLK is the word clock input/output pin which forms part of the DAI. It is used to indicate whether
the data bits belong to the left or right audio channel.
4.6 Headphone output pins
Pin HP_L
3.6.2 HP_L is the left-channel headphone output. It is ground-centred so the headphone speaker
can be connected directly between HP_L and ground.
Pin HP_R
HP_R is the right-channel single ended headphone output. It is ground-centred so the headphone
speaker can be connected directly between HP_R and ground.
4.7 Charge pump pins
Pin HPCSP
HPCSP is the positive output from the headphone charge pump. It should be connected to GND_CP
via a reservoir capacitor.
Pin HPCSN
HPCSN is the negative output from the headphone charge pump. It must be connected to GND_CP
via a reservoir capacitor.
Pin HPCFP
HPCFP is one of the flying capacitor connections required by the headphone charge pump. It must
be connected to HPCFN via a capacitor.
Pin HPCFN
HPCFN is one of the flying capacitor connections required by the headphone charge pump. It must
be connected to HPCFP via a capacitor.
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Audio codec with Advanced Accessory Detect
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4.8 References
Pin VMID
VMID is mid-rail reference decoupling capacitor connection.
Pin DACREF
DACREF is the DAC reference decoupling capacitor connection.
Pin VREF
VREF is the bandgap reference decoupling capacitor connection.
4.9 Supply pins
Pin VDD
VDD is main analogue supply pin. It supplies all the analogue circuits except the MICBIAS output
and the HPAMP outputs.
Pin VDD_IO
VDD_IO is the supply pin for the digital input/output signals.
Pin VDD_MIC
VDD_MIC is the supply pin for the MICBIAS.
4.10 Ground pins
Pin GND
GND is the main analogue Ground pin. It is the Ground connection for all analogue circuits with the
exception of the charge pump.
Pin GND_CP
GND_CP is the Ground pin for the charge pump and the digital engine.
Pin GND_HP
GND_HP is the ground point for the headset. When a headset is connected this pin is automatically
connected internally to either RING2 or SLEEVE.
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Audio codec with Advanced Accessory Detect
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5
Absolute maximum ratings
Table 3: Absolute maximum ratings
Parameter Description
Storage Temperature
Conditions (Note 1)
Min
–65
–40
–0.3
–0.3
–0.3
Max
+165
+85
Unit
°C
°C
V
Operating Temperature
VDD
Main supply voltage
+2.75
+5.5
+5.5
VDD_IO
VDD_MIC
Digital IO supply voltage
V
Microphone bias supply
voltage
V
Digital IO pins
SDA, SCL, BCLK,
WCLK, DATIN,
–0.3
VDD_IO + 0.3
V
DATOUT, MCLK
Accessory detect pins
JACKDET
–0.3
–0.3
VDD + 0.3
V
V
RING2, SLEEVE, MIC,
RING2_SENSE,
VDD_MIC + 0.3
SLEEVE_SENSE
Analogue input pins
MIC_P, MIC_N
–0.3
VDD + 0.3
V
Package thermal resistance
°C/W
kV
Human body model
(HBM)
2
ESD susceptibility
Charged device model
(CDM)
500
V
Note 1 Stresses beyond those listed under ‘Absolute maximum ratings’ may cause permanent damage to the
device. These are stress ratings only, so functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specification are not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2 All figures are to JEDEC specifications
6
Recommended operating conditions
Table 4: Recommended operating conditions
Parameter Description Conditions
Operating temperature
Min
–25
1.7
1.5
1.8
Typ
Max
+85
Unit
°C
V
VDD
Main supply voltage
+2.5
+3.6
+3.6
VDD_IO
VDD_MIC
Digital IO supply voltage
Microphone bias supply voltage
V
V
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Audio codec with Advanced Accessory Detect
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7
Electrical characteristics
Unless otherwise stated, test conditions are as follows:
VDD = VDD_IO = 1.8 V, VDD_MIC = 3.3 V, MCLK = 12.288 MHz, SR = 48 kHz, PLL = Bypass
Mode.
Table 5: Power consumption
Description
Conditions
Min
Typ
Max
Unit
Powerdown mode
10
µA
Digital playback to Headphone,
no load
DAC to HP_L/R, quiescent
3.4
mW
Digital playback to Headphone,
with load
DAC to HP_L/R, 16Ω load,
0.1 mW at 0 dBFS
7.5
mW
mW
Microphone stereo record
MIC P/N to ADCL/R
2.75
Microphone stereo record and
digital playback to Headphone,
no load
MIC P/N to ADCL/R and
DACL/R to HP_L/R, quiescent
4.8
8.9
mW
mW
Microphone stereo record and
digital playback to Headphone,
with load
MIC P/N to ADCL/R and
DACL/R to HP_L/R, 16 Ω load,
0.1 mW at 0 dBFS
Table 6: Electrical characteristics: Microphone bias
Parameter Description
Conditions
Min
Typ
Max
Unit
VMICBIAS
Bias voltage
No load, VDD_MIC > VMICBIAS
200 mV
+
1.8
2.9
V
Output voltage step
Output current
1.8 / 2.0 / 2.2 / 2.4 / 2.6 / 2.8 / 2.9
Output voltage drop < 50 mV
200
2
mV
mA
dB
IBIAS
PSRR
Power supply
rejection ratio
20 Hz to 2 kHz
2 kHz to 20 kHz
70
50
VN
Output voltage
noise
VMICBIAS ≤ 2.2 V
5
µVRMS
Table 7: Electrical characteristics: micamp
Parameter Description Conditions
Full-scale input signal
Min
Typ
Max
Unit
0 dB, singled-ended
0 dB gain, differential
0.8×VDD
1.6×VDD
VPP
Input resistance
Programmable gain
Gain step size
Single-ended
12
15
18
36
kΩ
dB
−6
6
dB
Absolute gain accuracy
Gain step error
0 dB @ 1 kHz
-1.0
-0.1
1.0
0.1
dB
20 Hz to 20 kHz
dB
Input noise level
Inputs connected to GND,
24 dB gain, input-referred,
A-weighted
5
µVRMS
Amplitude ripple
20 Hz to 20 kHz
-0.5
0.5
dB
dB
PSRR
Power supply rejection
ratio
20 Hz to 2 kHz
2 kHz to 20 kHz
90
70
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Audio codec with Advanced Accessory Detect
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Table 8: Electrical characteristics: mixinamp
Parameter Description
Conditions
Min
Typ
Max
Unit
VPP
dB
VMAX
Full-scale input signal
0 dB gain
1.6×VDD
Programmable gain
Gain step size
−4.5
18
1.5
dB
Absolute gain accuracy
Gain step error
0 dB @ 1 kHz
-1.0
-0.1
-0.5
1.0
0.1
0.5
dB
20 Hz to 20 kHz
20 Hz to 20 kHz
dB
Amplitude ripple
dB
PSRR
Power supply rejection
ratio
20 Hz to 2 kHz
2 kHz to 20 kHz
90
70
dB
Table 9: Electrical characteristics: adc_mono
Parameter Description
Conditions
Min
Typ
1.6×VDD
90
Max
Unit
VPP
dB
VMAX
Full-scale input signal
0 dBFS digital output level
A-weighted
SNR
Signal to Noise Ratio
THD+N
Total harmonic distortion
plus noise
-1 dBFS analogue input level
-85
dB
In-band spurious
0 dBFS analogue input level
-85
dB
dB
PSRR
Power supply rejection
ratio
20 Hz to 2 kHz
2 kHz to 20 kHz
Relative to VDD
70
50
Table 10: Electrical characteristics: dac_stereo
Parameter Description
Conditions
Min
Typ
1.6×VDD
100
Max
Unit
VPP
dB
VMAX
Full-scale output signal
0 dBFS digital input level
A-weighted
SNR
Signal to Noise Ratio
THD+N
Total harmonic distortion
plus noise
-1 dBFS digital input level
-90
dB
PSRR
Power supply rejection
ratio
20 Hz to 2 kHz
2 kHz to 20 kHz
Relative to VDD
70
50
dB
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Audio codec with Advanced Accessory Detect
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Table 11: Electrical characteristics: audio_hpamp_stereo
Parameter Description
Conditions
No load
Min
Typ
1.6×VDD
250
Max
Unit
VPP
VMAX
Full-scale output signal
DC output offset
−30 dB gain
µV
Maximum output power
per channel
VDD = 1.8 V, THD < 0.1%,
RLOAD = 16 Ω, 1 kHz
27
mWRMS
Maximum output power
per channel
VDD = 2.5 V, THD < 0.1%,
RLOAD = 16 Ω, 1 kHz
45
16
mWRMS
Load resistance
Load capacitance
Load inductance
Single-ended mode
13
Ω
pF
500
400
µH
VDD = 1.8 V, 0 dB gain
VDD = 2.5 V, 0 dB gain
98
dB
SNR
Signal to Noise Ratio
Output noise level
100
dB
VNOISE
20 Hz to 20 kHz,
<20 dB gain
2.5
µVRMS
THD+N
Total harmonic distortion
plus noise
VDD = 1.8 V,
−75
dB
RLOAD = 16 Ω, -5 dBFS,
1 kHz
Programmable gain
Gain step size
−57
6
dB
dB
dB
dB
dB
dB
dB
1.0
Absolute gain accuracy
Left/right gain mismatch
Gain step error
0 dB @ 1 kHz
−0.8
−0.1
−0.1
−0.5
0.8
0.1
0.1
0.5
20 Hz to 20 kHz
20 Hz to 20 kHz
20 Hz to 20 kHz
Amplitude ripple
Mute attenuation
−70
PSRR
Power supply rejection
ratio
20 Hz to 2 kHz
2 kHz to 20 kHz
70
50
dB
Table 12: Electrical characteristics: Input filters
Parameter Description
Conditions
Min
Typ
Max
Unit
Hz
BPASS
Pass band
0.45×FS
Pass band ripple
Voice mode
Music mode
±0.3
±0.1
dB
BSTOP
Stop band
FS ≤ 48 kHz
0.56×FS
7×FS
Hz
dB
s
FS = 88.2 or 96 kHz
3.5×FS
Stop band attenuation
Group delay
Voice mode
Music mode
70
55
Voice mode
4.3/FS
18/FS
9/FS
Music mode
FS = 88.2 or 96 kHz
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Table 13: DAC filter specifications
Symbol
Parameter
Pass band
Conditions
Min
Typ
Max
Unit
BPASS
0.45×FS
Hz
Voice mode
±0.3
±0.1
Pass band ripple
Stop band
dB
Hz
dB
Music mode
FS ≤ 48 kHz
7×FS
BSTOP
0.56×FS
FS = 88.2 or 96 kHz
3.5×FS
Voice mode
Music mode
70
55
Stop band attenuation
Voice mode
4.3/FS
18/FS
9/FS
Group delay
Music mode
s
FS = 88.2 or 96 kHz
Group delay variation
20 Hz to 20 kHz
1
2
µs
µs
Left/right channel group
delay mismatch
Table 14: Electrical characteristics: ALC
Parameter Description
Attack rate
Conditions
Min
1.6
1.6
1.3
Typ
Max
6500
1675
42300
0
Unit
dB/s
dB/s
ms
FS = 48 kHz
FS = 48 kHz
FS = 48 kHz
Release rate
Hold time
Maximum threshold
−94.5
−94.5
−94.5
dBFS
dBFS
dBFS
dB
Minimum threshold
Noise threshold
0
0
Threshold step size
Maximum overall gain
1.5
0
0
90
90
dB
Maximum overall
attenuation
dB
Maximum analogue gain
Minimum analogue gain
Gain step size
0
0
36
36
dB
dB
dB
1.5
Table 15: Electrical characteristics: Accessory detect
Parameter Description
Ring2 ground switch resistance
Sleeve ground switch resistance
Conditions
Min
Typ
Max
50
Unit
mΩ
mΩ
50
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8
Timing characteristics
Table 16: Timing I/O voltage characteristics
Parameter
Description
Conditions
Min
Typ
Max
Unit
SCL, SDA,
Input High Voltage
VIH
0.7*VDD_IO
V
SCL, SDA,
Input Low Voltage
VIL
VIH
0.3*VDD_IO
V
V
MCLK, BCLK, WCLK, DATIN,
DATOUT
0.7*VDD_IO
Input High Voltage
MCLK, BCLK, WCLK, DATIN,
DATOUT
Input Low Voltage
VIL
0.3*VDD_IO
0.24
V
V
VOL
@3 mA
SDA Output Low Voltage
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CLKL
CLKH
SCL
SDA
STH
DST
TSS
DHT
Figure 4: I2C bus timing
Table 17: I2C control bus (VDD_IO = 1.8 V)
Parameter
Description
Conditions
Min
Typ
Max
Unit
Bus free time STOP to START
Bus line capacitive load
500
ns
150
pF
Standard/Fast Mode
SCL clock frequency
0
1000
kHz
ns
Start condition setup time
260
STH
CLKL
CLKH
Start condition hold time
SCL low time
260
500
260
ns
ns
ns
ns
ns
ns
ns
ns
SCL high time
SCL rise/fall time
SDA rise/fall time
SDA setup time
Input requirement
Input requirement
1000
300
DST
DHT
TSS
50
0
SDA hold time
Stop condition setup time
260
High-Speed Mode
SCL clock frequency
Start condition setup time
Start condition hold time
SCL low time
0
3400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
160
160
160
60
STH
CLKL
CLKH
SCL high time
SCL rise/fall time
SDA rise/fall time
SDA setup time
Input requirement
Input requirement
160
160
DST
DHT
TSS
10
0
SDA hold time
Stop condition setup time
160
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T
WCLK
tdCW
tf
tsW
thW
thC
tlC
tr
BCLK
DATOUT
DATIN
tdWD
tdCD
tsD
thD
Figure 5: Digital audio interface timing diagram
Note 3 Diagram shown is valid for all modes except DSP. For DSP mode the BCLK signal is inverted
Table 18: Digital audio interface timing (I2S/DSP in master/slave mode)
Conditions
Parameter
Description
Min
Typ
Max
Unit
(VDD_IO = 1.8 V)
300
1.0
Ω
DC impedance >
Input impedance
10 MΩ
2.5
pF
T
tr
BCLK period
75
ns
ns
ns
T
BCLK rise time
BLCK fall time
BCLK high period
BCLK low period
8
tf
8
thC
tlC
40 %
40 %
60 %
60 %
T
BCLK to WCLK
delay
tdCW
-30 %
+30 %
+30 %
T
BCLK to DATOUT
delay
tdCD
thW
-30 %
100 %
T
T
DSP mode
Non-DSP mode
DSP mode
Word
length
(Note 4)
WCLK high time
WCLK low time
T
T
T
tlW
100 %
Word
length
Non-DSP mode
(Note 5)
tsW
thW
tsD
thD
WCLK setup time
WCLK hold time
DATIN setup time
DATIN hold time
Slave mode
Slave mode
7
2
7
2
ns
ns
ns
ns
DATOUT to WCLK
delay
tdWD
DATOUT is synchronised to BCLK
Note 4 WCLK must be high for at least the word length number of BCLK periods
Note 5 WCLK must be low for at least the word length number of BCLK periods
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9
Functional description
DA7219 is a high-performance, low-power audio codec with in-built Advanced Accessory Detection
(AAD). The AAD supports the detection of three-pole (headphone or lineout) or four-pole (headset)
jacks, with automatic pin order switching of MIC/GND on CTIA and OMTP headsets.
The DA7219 contains a mono analogue microphone-to-ADC path and a digital audio interface (DAI)
for input and output. The DAC to headphone path has a ground centred, single ended stereo
headphone output.
The digital core has an input filter with a high pass filter, and automatic level control (ALC), while the
output filter has a high pass filter, and a 5-band EQ.
There is also a sidetone path with gain and a tone generator that supports Dual Tone Multi-
Frequency (DTMF).
9.1 Device operating modes
The DA7219 codec has three operating modes:
●
●
DEEP SLEEP – There is no clocking in DEEP SLEEP mode and consequently no functionality
available and no accessory detection is performed. The system will awake when
system_active = 1.
SLEEP – In SLEEP mode and with micbias OFF, AAD performs jack detection and jack
configuration detection. Any button press is detected, but identification of the button cannot be
performed until micbias is ON. No clocking is performed in SLEEP mode, and playback and
record are not supported.
●
ON – AAD performs full-function accessory detection. Playback and record are supported.
All modes, their maximum current consumption, and functionality are listed in Table 19.
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Table 19: System states, configuration, and current consumption
Typical current
consumption
Comments
Configuration
CODEC
Mode
VDD +
VDD_IO
system_
active
AAD
config
Internal Internal
VDD +
VDD_MIC
MCLK
PLL mode
Audio path
AAD
VDD_MIC
VDD_IO
ref osc
PLL
OFF
OFF
OFF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
None
None
N/A
Wake on
system_active
= 1.
DEEP
SLEEP
ON
ON
0
N/A
N/A
N/A
OFF
OFF
OFF
OFF
< 10 µA
0
Jack
Buttons
OFF
insertion,
jack type and
pin order
<200 µA
<500 µA
0
0
As above
plus Button
detection
(without
identification)
OFF
All ON
(playback/
record not
supported)
SLEEP
ON
ON
1
OFF
OFF
ON
OFF
FULL
DETECTION
(as above
but with
All ON +
micbias_en
<300 µA <2 mA
button
Identification)
SRM - locks
to WCLK if
DAI is in
OFF
ON
ON
ON
slave mode
ALL ON +
micbias_en
Dependent on use
case (playback level
into load etc)
AAD uses
clock on
demand to
save power
ON (Playback/
record etc) DETECTION
FULL
ON
ON
ON
1
(11.8 MHz or BYPASS
12.288 MHz)
OFF
OFF
OFF
ON
ON
Normal - lock
(Valid Freq
to MCLK
2-80 MHz)
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9.2 Input paths
9.2.1
Microphone input
The DA7219 analogue input consists of one set of amplifiers and an ADC as shown in Figure 6.
-6:+6:+36 dB
MIC_1_AMP
-4.5:+1.5:+18 dB
MIXIN_L_AMP
MIC_P
MIC_N
ADC
to ADC filter
Figure 6: Analogue inputs block diagram
Microphone bias
9.2.1.1
The device has a microphone bias output, which is a programmable voltage source that can be used
to supply analogue microphones.
The bias output can be independently programmed from 1.8 V to 2.9 V in 0.2 V steps using
micbias1_level.
The microphone bias level can only be changed while the associated micbias circuit is disabled
(micbias1_en = 0).
Table 20: Microphone bias settings
micbias1_level
Output voltage (V) in low noise mode
000
001
010
011
100
101
110
111
reserved
1.8
2.0
2.2
2.4
2.6
2.8
2.9
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9.2.1.2
Microphone amplifier
MICBIAS
MICBIAS
MIC_P
MICBIAS
MICBIAS
MIC_P
MIC
MIC_P
MIC_N
SLEEVE_SENSE
MIC_P
MIC_N
MIC_N
MIC_N
RING2_SENSE
(b) Differential
(c) Pseudo-differential
(d) Single-ended
(a) Headset
Figure 7: ECM microphone configurations
The microphone amplifier can be configured in
a) Headset mode, microphone amplifier is fully differential
b) fully differential mode for improved common-mode noise rejection
c) pseudo-differential mode
d) single-ended mode (MIC_P or MIC_N)
All configurations are illustrated in Figure 7.
The configuration of the first microphone amplifier is specified using the MIC_1_CTRL register. It is
enabled by setting the mic_1_amp_en bit, and is muted by setting the mic_1_amp_mute_en bit.
The gain of the amplifier can be set in the range of –6 dB to +36 dB in 6 dB steps using
mic_1_amp_gain (see Table 21:).
Table 21: MIC_1_GAIN gain settings
mic_1_amp_gain
Amplifier gain (dB)
000
001
010
011
100
101
110
111
-6
0
6
12
18
24
30
36
9.2.1.3
Input amplifiers
The input amplifier provides an additional gain stage between the microphone amplifier (see section
0 and Figure 6) and the ADC input. The input amplifier is enabled by setting
mixin_l_amp_ramp_en = 1.
The gain can be set in the range of –4.5 dB to +18 dB in 1.5 dB steps using mixin_l_amp_gain.
Gain updates can be synchronised with signal zero-crossings by setting mixin_l_amp_zc_en = 1. If
no zero-crossing is detected within the timeout period of approximately 100 ms, the update is applied
unconditionally.
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As an alternative to zero-cross synchronisation, gain updates can be ramped through all intermediate
values by setting mixin_l_amp_ramp_en = 1. This ramp setting overrides the settings of
mixin_l_amp_zc_en.
The amplifier can be muted using mixin_l_amp_mute_en.
Table 22: MIXIN_L_GAIN settings
mixin_l_amp_gain Amplifier gain (dB)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
-4.5
-3.0
-1.5
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
16.5
18.0
9.2.2
Analogue to Digital Converter (ADC)
The DA7219 codec contains a high quality audio ADC. The ADC is clocked at a fixed rate of either
3.072 MHz or 2.8224 MHz, depending on the required input sample rate (SR).
The DA7219 includes a low power 24-bit high quality audio ADC that supports sampling rates from
8 kHz to 96 kHz. The sample rate is specified using the SR register.
The ADC can be enabled and disabled using adc_l_en.
The ADC channels offer a configurable digital gain from -83.25 dB to +12 dB in 0.75 dB steps after
the digital conversion. Individual gain settings can be programmed via the adc_l_digital_gain_status
control. The currently active gain settings are stored in the ADC_L_GAIN_STATUS register.
Muting, and the ramping of digital gain changes, can be controlled using the dedicated
ADC_L_CTRL register. If the ramping is enabled using the control bit adc_l_ramp_en, the rate of the
ramping is controlled using gain_ramp_rate in the GAIN_RAMP_CTRL register.
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9.3 Digital engine
The DA7219 chip contains a digital engine that performs the signal processing and also provides
overall system control.
The input signals from the ADCs are passed to the input filter block. The filter block includes a
high-pass filter for DC offset removal and wind noise suppression, and an automatic level control.
The signals from the input filters are sent to the digital mixer where they can be combined with
signals from the tone generator and the digital audio interface (DAI), and routed to the output filters
and the DAI. The output filters contain a high-pass filter for DC offset removal, and a fixed 5-band
equaliser to adjust the sound of the output signals.
There is also a low latency sidetone path that can take one signal from the ADC and apply gain
before passing the signal straight to the output filters.
The filter paths are shown in more detail in Figure 9.
Finally a system controller module is included to ensure correct sequencing of the events required to
bring up and shut down signal paths without creating pops and clicks.
DIGITAL ENGINE
I2C Pads
DAI Pads
I2C
Accessory
Detect Logic
Accessory
Detect
DAI
System
Control
Output Filters
High Pass
5-Band EQ
Analogue
Outputs
Analogue
Audio Input
Input Filters
High Pass
MUX
Tone
Generator
and S-Ramp
ALC
Sidetone Path
with Gain
Charge
Pumps
Clock
Generation
Charge Pump
Control
PLL
Figure 8: Digital engine block diagram
IN_1_FILTER
GAIN
STAGE
TONE GEN +
SRAMP
OUT_1_FILTER
5BEQ
5BEQ
DAC_1L_DATA
DAC_1R_DATA
DWA
DWA
SDM
SDM
ADC_Audio_DATA
CIC
X
MUX
to Mic Gain
ALC
ZeroCross from Mic
DAI
ADC_AccDet_DATA
JACKDET
Accessory
Detect
DAI
Figure 9: Digital filters block diagram
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9.3.1
Input processing
ADC digital gain
9.3.1.1
The ADC channels offer a configurable digital gain from -83.25 dB to +12 dB in 0.75 dB steps after
the digital conversion. Individual gain settings can be programmed via the adc_l_digital_gain control.
The currently active gain settings are stored in the ADC_L_GAIN_STATUS register.
9.3.1.2
High-pass filter
Any DC offset from the input path is removed via IIR filters (typically <2 Hz roll-off, configurable).
After reset the filters for both channels are enabled by default, but can be disabled by clearing
adc_hpf_en. The cut-off frequency of the filters can be programmed using adc_audio_hpf_corner.
To improve the quality of microphone recordings, the DA7219 provides a programmable high pass
filter engine, enabled via adc_voice_en in the ADC_FILTERS1 register. For the first filter, in music
mode adc_voice_en must be set to 0 and the HPF corner frequency is set using
adc_audio_hpf_corner.
In ADC voice mode, adc_voice_en must = 1 and adc_hpf_en must = 1 in which case the HPF corner
frequency is set using adc_voice_hpf_corner.
The low frequency roll off is configured over a wide range using the adc_voice_hpf_corner control.
This allows for flexible removal of wind and pop noise.
The input high-pass filter is controlled using ADC_FILTERS1. For the first filter, in music mode
adc_voice_en must be set to 0 and the HPF corner frequency is set using adc_audio_hpf_corner.
In voice mode, adc_voice_en must = 1 in which case the HPF corner frequency is set using
adc_audio_hpf_corner.
The value of the HPF corner frequency also depends on the input sample rate (SR) as shown in
Table 23.
The sample rates available in the different ADC power modes are summarised in Table 23.
Table 23: Input high-pass filter settings
SR Sample Rate (kHz)
8
11.025
0.46
12
0.5
1
16
22.05
0.92
1.84
3.68
7.35
24
1
32
44.1
48
2
88.2
3.68
7.35
14.7
29.4
96
4
00
01
10
11
0.33
0.67
1.33
2.67
0.67
1.33
2.67
5.33
1.33 1.84
2.67 3.68
5.33 7.35
0.92
2
4
8
0
1.84
2
4
8
16
32
3.68
4
8
10.6 14.7
7
16
000
001
010
011
100
101
110
111
2.5
25
3.45
34.5
3.75
37.5
75
5
50
50
68.9
100
200
300
400
600
800
100
150
200
300
400
137.8
206.7
275.6
413.4
551.3
150
225
300
450
600
Voice HPF not available for sample rates above
16 kHz.
1
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9.3.1.3
Automatic Level Control (ALC)
For improved sound recordings of signals with a large volume range, the DA7219 offers a fully-
configurable automatic recording level control (ALC) for microphone inputs. This is enabled via the
alc_en control. The ALC monitors the digital signal after the ADC and adjusts the microphones’
analogue and digital gain to maintain a constant recording level, whatever the analogue input signal
level.
Operation of ALC is illustrated in Figure 10. When the input signal volume is high, the ALC system
will reduce the overall gain until the output volume is below the specified maximum value. When the
input signal volume is low, the ALC will increase the gain until the output volume increases above the
specified minimum value. If the output signal is within the desired signal level (between the specified
minimum and maximum levels), the ALC does nothing.
The maximum and the minimum thresholds that trigger a gain change of the ALC are programmed
by the alc_threshold_min and alc_threshold_max controls.
ALC Input
ALC Gain
ALC Output
Release time
Attack time
Figure 10: Principle of operation of the ALC
In hybrid mode, the total gain is made up of an analogue gain, which is applied to the microphone
amplifier, and a digital gain, which is implemented in the filtering stage. The ALC block monitors and
controls the gain of the microphone and the ADC.
Although the ALC is controlling the gain, it does not modify any of the registers MIXIN_L_GAIN or
ADC_L_GAIN, nor does it modify the digital gain register ADC_L_GAIN. These registers are ignored
while the ALC is in operation.
In digital-only mode only the digital gain in the ADC is altered. Although the ALC is controlling the
gain, it does not modify adc_l_digital_gain in the ADC_L_GAIN register. This register is ignored while
the ALC is in operation.
Hybrid mode should be used whenever analogue microphones are being used. The hybrid
analogue/digital gain mode (hybrid mode) can be enabled using. alc_sync_mode.
The minimum and maximum levels of digital gain that can be applied by the ALC are controlled using
alc_atten_max and alc_gain_max.
Similarly the minimum and maximum levels of analogue gain are controlled by alc_ana_gain_min
and alc_ana_gain_max. The rates at which the gain is changed are defined by the attack and decay
rates in register ALC_CTRL2. When attacking, the gain decreases with alc_attack rate. When
decaying, the gain increases with alc_release rate.
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The hold-time is defined by alc_hold in the ALC_CTRL3 register. This controls the length of time that
the system maintains the current gain level before starting to decay. This prevents unwanted
changes in the recording level when there is a short-lived ‘spike’ in input volume, for example when
recording speech.
Typically the attack rate should be much faster than the decay rate, as it is necessary to reduce
rapidly increasing waveforms as quickly as possible, whereas fast release times will result in the
signal appearing to ‘pump’. The ALC also has an anti clipping function that applies a very fast attack
rate when the input signal is close to full-range. This prevents clipping of the signal by reducing the
signal gain at a faster rate than would normally be applied. The anti clip function is enabled using
alc_anticlip_en, and the threshold above which it is activated is set in the range 0.034 dB/fs to
0.272 dB/fs using alc_anticlip_step.
A recording Noise-Gate feature is provided to avoid increasing the gain of the channel when there is
no signal, or when only a noise signal is present. Boosting a signal on which only noise is present is
known as ‘noise pumping’. The Noise-Gate prevents this. Whenever the level of the input signal
drops below the noise threshold configured in alc_noise, the channel gain remains constant.
max
input signal
min
time
gain level
atk rate
dcy rate
time
atk
hld
dcy
Figure 11: Attack, delay and hold parameters
9.3.2
Sidetone processing
There is a low latency filter channel between inputs and outputs for implementing a sidetone path.
The gain is controlled using sidetone_gain and provides gain in the range -42 dB to +0 dB in +3 dB
steps.
The sidetone path is enabled using sidetone_en. It is muted using sidetone_mute_en.
The output from the sidetone channel can be added to left or right (or both) output filters using
outfilt_st_1l_src and outfilt_st_1r_src.
The sidetone path is enabled using sidetone_en. It is muted using sidetone_mute_en.
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9.3.3
Tone generator
Parameter
Conditions
Min
Typ
Max
Unit
Single-tone frequency
FS = 8,12,16,24,32,48,96kHz
1
1
12000
11025
Hz
FS = 11.025, 22.05, 44.1, 88.2kHz
Single-tone frequency step
0.2
Hz
Hz
Dual-tone modulation
frequency A
697
770
852
941
Dual-tone modulation
frequency B
1209
1336
1477
1633
Hz
Output signal level
On/off pulse duration
On/off pulse step size
0
dBFS
ms
10
2000
10 to 200ms duration
10
50
ms
200 to 2000ms duration
On/off pulse repeat
Programmable
Continuous
1,2,3,4,
5,6∞
Cycles
The tone generator contains two independent Sine Wave Generators, SWG1 and SWG2. Each SWG
can generate a sine wave at a frequency (FREQ) from approximately 10 Hz to 12 kHz according to
the programmed 16-bit value:
FREQ[15:0] = 2^16 × fSWG/12000 – 1, for SR2 = 8, 12, 16, 24, 32, 48,96 kHz
FREQ[15:0] = 2^16 × fSWG/11025 – 1, for SR2 = 11.025, 22.05, 44.1, 88.2 kHz
For SWG1, the FREQ value is stored in two 8-bit registers as freq1_u = FREQ[15:8] and
freq1_l = FREQ[7:0]. The SWG2 frequency is programmed in the same way using freq2_u and
freq2_l. The output of the tone generator can come from either of the SWGs, or from a combination
of both of them as specified by swg_sel. In addition the tone generator can produce standard Dual
Tone Multi-Frequency (DTMF) tones using the two SWGs if dtmf_reg = 1 and the required key pad
value is programmed in dtmf_reg as shown in Table 24.
Table 24: DTMF tones corresponding to the dtmf_reg value
SWG2 Freq
(Hz)
SWG1 Frequency (Hz)
1209 1336 1477 1633
697
770
852
941
0x1
0x4
0x7
0xE
0x2
0x5
0x8
0x0
0x3
0x6
0x9
0xF
0xA
0xB
0xC
0xD
The tone generator can produce 1, 2, 3, 4, 8, 16, or 32 beeps, or a continuous beep, as determined
by beep_cycles. Each beep has an ‘On’ period from 10 ms to 2 s as programmed in beep_on_per.
and an ‘Off’ period from 10 ms to 2 s as programmed in beep_off_per. The tone generator is started
by setting the start_stopn bit, and is halted by clearing this bit. If start_stopn is cleared, the tone
generator stops at the completion of the current beep cycle or at the next zero-cross if the number of
beeps is set to continuous (beep_cycles = 110 or = 111). The start_stopn bit is automatically cleared
once the programmed number of beep cycles has been completed.
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9.3.4
Digital router
There is a digital router block which is configured by registers DIG_ROUTING_DAI and
DIG_ROUTING_DAC.
The router options are illustrated in Figure 12.
DA7219 Digital Router
2E[1:0]
ADC_L
[00]
DAC_L
dac_l_src
DIG_ROUTING_DAC
2E[5:4]
TONEGEN
DAC_R
[01]
dac_r_src
2A[1:0]
DAI_OUT_L
DAI_IN_L
[10]
dai_l_src
DIG_ROUTING_DAI
2A[5:4]
DAI_OUT_R
DAI_IN_R
[11]
dai_r_src
Figure 12: DA7219 digital router
DIG_ROUTING_DAC is used to select the inputs to go into the DAC filter chain from the router.
DIG_ROUTING_DAI is used to select the inputs to go into the DAI from the router.
For example, for dac_l_src, data selection to the DAC_L path is
00 = ADC left output
01 = Tone generator
10 = DAI input left / dai mono mix
11 = DAI input right / dai mono mix
The same 2-bit code (00, 01, 10, 11) is used for dac_r_src, dai_l_src and dai_r_src.
9.3.5
System controller
The System Controller (SC) automates the sequencing of the multiple blocks required to set up one
or more particular audio paths. It is an optional feature, and operates by performing register writes
with optimal sequencing and timing, thus eliminating pops and clicks.
System control for the inputs is controlled using SYSTEM_MODES_INPUT, and for the outputs by
using SYSTEM_MODES_OUTPUT.
Writing to the mode_submit field either of these registers will cause the system controller to process
both input and output paths.
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9.3.6
Output processing
DAC digital gain
9.3.6.1
Each channel includes individual gain settings that are controllable in 0.75 dB steps ranging from
-78 dB (= mute) to 12 dB using dac_l_digital_gain and dac_r_digital_gain. The currently active gain
settings are stored in DAC_L_GAIN_STATUS and DAC_R_GAIN_STATUS registers.
9.3.6.2
High-pass filter
Any DC offset from the input path is removed via IIR filters (typically <2 Hz roll-off, configurable).
After reset the filters for both channels are enabled by default, but can be disabled by clearing
dac_hpf_en. The cut-off frequency of the filters can be programmed using dac_audio_hpf_corner.
During playback, dedicated voiceband filtering can be enabled using dac_voice_en in the
DAC_FILTERS1 register. In DAC voice mode, dac_voice_en must = 1 and dac_hpf_en must = 1 in
which case the HPF corner frequency is set using dac_voice_hpf_corner.
The low frequency roll off is configured over a wide range using the dac_voice_hpf_corner control.
In voice mode, the wind noise high-pass filter cut-off frequency is determined by the settings of the
adc_voice_hpf_corner and the dac_voice_hpf_corner register bits, These cut-off frequencies are not
fixed and vary with the sample rate being used. Table 25 shows the cut-off frequencies for all valid
settings of adc_voice_hpf_corner and dac_voice_hpf_corner, at all sample rates of 16 kHz and
below.
Table 25: Output high-pass filter settings
SR Sample Rate (kHz)
8
11.025
0.46
12
0.5
1
16
22.05
0.92
1.84
3.68
7.35
24
1
32
44.1
48
2
88.2
3.68
7.35
14.7
29.4
96
4
00
01
10
11
0.33
0.67
1.33
2.67
0.67
1.33
2.67
5.33
1.33 1.84
2.67 3.68
5.33 7.35
0.92
2
4
8
0
1.84
2
4
8
16
32
3.68
4
8
10.6 14.7
7
16
000
001
010
011
100
101
110
111
2.5
25
3.45
34.5
3.75
37.5
75
5
50
50
68.9
100
200
300
400
600
800
100
150
200
300
400
137.8
206.7
275.6
413.4
551.3
150
225
300
450
600
Voice HPF not available for sample rates above
16 kHz.
1
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9.3.6.3
5-band equaliser
The gains of each band can be individually configured, from -10.5 to 12.0 dB in 1.5 dB steps, using
the dac_eq_band1, dac_eq_band2, dac_eq_band3, dac_eq_band4, dac_eq_band5 controls.
The output filters can provide gain or attenuation in each of five separate (fixed) frequency bands
using the 5-band equaliser. The equaliser, for both left and right channels, is enabled using
dac_eq_en.
The centre or cut-off frequency of each of the five bands depends on the output sample rate as
shown in Table 26.
Table 26: Output 5-band equaliser centre/cut-off frequencies
FS (kHz)
Centre frequency (Hz) at programmed setting
Band 1
Band 2
99
Band 3
493
680
740
440
607
660
418
576
627
N/A
N/A
Band 4
1528
2106
2293
2128
2933
3191
1797
2386
2596
N/A
Band 5
4000
8
11.025
12
0
0
136
148
96
5512
0
6000
16
0
8000
22.05
24
0
133
145
95
11025
12000
16000
22050
24000
N/A
0
32
0
44.1
48
0
131
143
N/A
N/A
0
88.2
96
N/A
N/A
N/A
N/A
Figure 13: Equaliser filter band 1 frequency response at FS = 48 kHz
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Figure 14: Equaliser filter band 2 frequency response at FS = 48 kHz
Figure 15: Equaliser filter band 3 frequency response at FS = 48 kHz
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Figure 16: Equaliser filter band 4 frequency response at FS = 48 kHz
Figure 17: Equaliser filter band 5 frequency response at FS = 48 kHz
DAC soft mute
9.3.6.4
To improve the user’s perception of audio reconfigurations, the DAC channel signals may be soft
muted by asserting the control dac_softmute_en (in register. DAC_FILTERS5).The soft mute function
attenuates the digital input to the DAC, ramping the gain down in steps of 0.1875 dB from its current
level to -77.25 dB, then completely muting the channel. When dac_softmute_en is released, the
attenuation is set to -77.25 dB, and then ramped up to the previous gain level. Both left and right
channels of soft mute enabled output amplifiers are muted simultaneously. The ramping up and
down rate is dependent on the audio sample rate and can be individually configured using control
dac_softmute_en.
Setting dac_softmute_en = 1 enables a soft mute on both channels.
During active soft muting, the digital gain of the DAC will be different to the value programmed inside
controls dac_l_digital_gain_status and dac_r_digital_gain_status.
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9.4 Output paths
9.4.1
Digital to Analogue Converter (DAC)
The DA7219 codec includes a stereo audio DAC. Left and right channels of the DAC are
independently and automatically enabled whenever the corresponding output filter channel is
enabled.
The DAC is clocked at 3.072 MHz or 2.8224 MHz depending on the output sample rate (SR). Left
and right channels of the DAC are independently and automatically enabled whenever the
corresponding output filter channel is enabled.
The integrated stereo DAC is suitable for high quality audio playback by MP3 players and by portable
multimedia players of all kinds.
The left and right channels of the DAC can be individually enabled using controls dac_l_en and
dac_r_en.
Each channel includes individual gain settings that are controllable in 0.75 dB steps from -78 dB to
12 dB using dac_l_digital_gain_status and dac_r_digital_gain_status. The currently active gain
settings are stored in DAC_L_GAIN_STATUS and DAC_R_GAIN_STATUS registers.
On the dedicated DAC_L_CTRL and DAC_R_CTRL registers, settings such as mute and ramping of
gain changes can be configured. If ramping is enabled using the control bits dac_l_ramp_en or
dac_r_ramp_en, the rate of the ramping can be controlled using gain_ramp_rate in the
GAIN_RAMP_CTRL register.
A digital high-pass filter for each DAC channel is implemented with a 3 dB cut-off frequency
controlled in the DAC_FILTERS1 register by dac_audio_hpf_corner. The high-pass filter is enabled
by control dac_hpf_en. After Reset, the high pass filters for both channels are enabled by default.
9.4.2
Headphone outputs
DIGITAL ENGINE
DA7219
DACL
HP_L
HP_L_AMP
-57: 1.0: +6 dB
MIXOUT_L
DACR
HP_R
HP_R_AMP
-57: 1.0: +6 dB
MIXOUT_R
Figure 18: Headphone output paths showing the two amplifiers
Buffer amplifier
9.4.2.1
The left-channel buffer amplifier MIXOUT_L, is enabled by setting mixout_l_amp_en = 1.
The right channel output buffer MIXOUT_R is controlled in the same manner.
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9.4.2.2
Headphone amplifiers
Each headphone path has one headphone amplifier stage providing a gain of –57 dB to +6 dB in
1.0 dB steps.
The amplifiers are configured to operate in single ended mode. The headphone loads are connected
between HP_L and HP_R and the internal ground set by the MIC/GND switches set during the detect
sequence.
The headphone amplifiers are configured to operate in true-ground (charge pump) mode. In true-
ground supply mode, the charge pump must be enabled to generate the ground-centred supply rails
for the amplifiers.
The left-channel headphone amplifier (HP_L_CTRL) is enabled by setting hp_l_amp_en = 1. The
output stage is enabled independently by setting hp_l_amp_oe = 1.
The amplifier gain can be set in the range of –57 dB to +6 dB in 1.0 dB steps using hp_l_amp_gain.
Gain updates can be ramped through all intermediate values by setting hp_l_amp_zc_en = 1. This
ramp setting overrides the settings of hp_l_amp_zc_en. To prevent zipper noise when gain ramping
is selected, the gain is ramped through additional sub-range gain steps.
As an alternative to gain ramping, gain updates can be synchronised with signal zero-crossings by
setting hp_l_amp_zc_en = 1. If no zero-crossing is detected within the timeout period, then the gain
update is applied unconditionally. The timeout period is approximately 0.1 second, and is hard-coded
into the device. It is not user-configurable.
The amplifier can be muted by setting hp_l_amp_mute_en = 1.
The amplifier can be put in its minimum gain configuration by setting hp_l_amp_min_gain_en = 1. If
either zero-crossing or ramping are enabled when minimum gain is set, the ramping or the zero
crossing or both will be performed while activating the minimum gain.
The right-channel headphone amplifier (HP_R_CTRL) is controlled in the same manner.
9.4.3
Charge pump control
The charge pump is enabled by asserting cp_en in the CP_CTRL register. Once enabled, the charge
pump can be controlled manually or automatically. When under manual control (cp_mchange = 00),
the output voltage level is directly determined by cp_mod.
The amount of charge stored, and therefore the voltage generated, by the charge pump is controlled
by the charge pump controller. As the power consumed by devices such as amplifiers is proportional
to Voltage2, significant power savings are available by matching the charge pump’s output with the
system’s power requirement.
There are three modes of operation that are determined by the cp_mchange setting. All three modes
are described in Table 27.
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Table 27: Charge pump output voltage control
Charge pump
tracking mode
Charge pump output voltage
Details
cp_mchange
00
01
Reserved
Reserved
The charge pump controller monitors the PGA
volume settings, and generates the minimum
voltage that is high enough to drive a full-scale
signal at the current gain level.
Voltage level depends on the
programmed gain setting
The charge pump controller monitors the DAC
signal, and generates a voltage that is high enough
to drive a full-scale output at the current DAC signal
volume level
Voltage level depends on the DAC
signal envelope
10
11
The charge pump monitors both the programmed
volume settings and the actual signal size, and
generates the appropriate output voltage.
Voltage level depends on the signal
magnitude and the programmed
gain setting
This is the most power-efficient mode of operation.
When cp_mchange is set to 10 (tracking DAC signal size, described in Table 27) or cp_mchange is
set to 11 (tracking the output signal size), the charge pump switches its supply between the VDD_A
rail and the VDD_A/2 rail depending on its power requirements.
When low output voltages are needed, the charge pump saves power by using the lower-voltage
VDD_A /2 rail.
The switching point between using the VDD_A rail and the VDD_A/2 rail is determined by the
cp_thresh_vdd2 register setting. The switching points determined by cp_thresh_vdd2 vary between
the two cp_mchange modes, and are summarised in Table 28 and Table 29.
When the charge pump output voltage is controlled manually (cp_mchange = 00) or when it is
tracking the PGA gain settings (cp_mchange = 01), the charge pump always takes its supply from
VDD_CP.
Table 28: cp_thresh_vdd2 settings in DAC_VOL mode (cp_mchange = 10)
Approximate switching
cp_thresh_vdd2 setting
Notes
point (Note 6)
Do not use. Very power-inefficient as nearly
always VDD/1
0x01
0x03
-30 dBFS
Not recommended. Very power-inefficient as
nearly always VDD/1
-24 dBFS
0x07
0x0E
-18 dBFS
-12 dBFS
-10 dBFS
Good to use but not power efficient
Good to use
0x10
Recommended setting
Not recommended
0x3F – 0x13
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Table 29: cp_thresh_vdd2 settings in signal size mode (cp_mchange = 11)
Approximate switching
cp_thresh_vdd2 setting
Notes
point (Note 6)
0x00
0x01
Never
Not recommended. Always VDD/1 mode
Not recommended. Always VDD/1 mode
Never
Not recommended. Very power-inefficient as
nearly always VDD/1
0x02
-32 dBFS
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
-24 dBFS
-20 dBFS
-17 dBFS
-15 dBFS
-13 dBFS
-12 dBFS
-11 dBFS
-10 dBFS
-9 dBFS
Never
Good to use
Good to use
Good to use
Recommended setting
Good to use
Good to use
Good to use
Good to use
Not recommended. VDD/2 begins to clip
Not recommended. Always VDD/2 mode
Not recommended. Always VDD/2 mode
Not recommended. Always VDD/2 mode
Not recommended. Always VDD/2 mode
Never
Never
Never
Note 6 Full Scale (FS) = 1.6 * VDD_A
9.4.4
Tracking the demands on the charge pump output
There are three points at which the demands on the charge pump can be tracked. These tracking
points are determined by cp_mchange.
9.4.4.1
cp_mchange = 01 (tracking the PGA gain setting)
If cp_mchange = 01, it is the PGA gain setting that is tracked, and which provides the feedback to
boost the clock frequency when necessary.
9.4.4.2
cp_mchange = 10 (tracking the DAC signal setting)
If cp_mchange = 10, it is the size of the DAC signal that is tracked, and which provides the feedback
to boost the clock frequency when necessary.
9.4.4.3
cp_mchange = 11 (tracking the output signal magnitude)
If cp_mchange = 11, it is the magnitude of the output signal that is tracked, and which provides the
feedback to boost the clock frequency when necessary.
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9.5 Advanced Accessory Detection (AAD)
If the DA7219 is configured for Advanced Accessory Detection (AAD), the insertion of a jack wakes
the system up. No external clocking is required to detect a jack insertion, and the clock is only
requested if the input is changing and if debouncing is required. This ensures the lowest possible
power consumption with no digital leakage.
Once a jack has been inserted, the AAD differentiates between a three-pole jack (used on
headphones and lineouts) and a four-pole jack (used on headsets). Two-pole jacks are detected as a
three-pole jack, and will work as designed as a mono output.
There are two combinations of four-pole jack available in the market, both of which are supported by
the AAD. The jack configurations are shown in Figure 19.
Jack Type
Position
SLEEVE
RING2
CTIA
MIC
OMTP
GND
MIC
SLEEVE
RING2
RING1
GND
HP_R
RING1
HP_R
TIP
TIP
HP_L
HP_L
Figure 19: Jack socket variants
On detecting the insertion of a jack, the DA7219 moves to the microphone-detect state where it
drives current down the SLEEVE pin and measures the impedance to the RING2 pin, which will be
connected to GND_HP by the internal GND switch.
If the impedance measured between the SLEEVE and RING2 pins is below 500 Ω (configurable), the
DA7219 detects the connected accessory as a three-pole jack. The DA7219 then returns to the jack
detection state to poll for removal, but continues to periodically pulse current down the SLEEVE pin
to verify that the connected accessory is three-pole. This continued polling avoids an incorrect
detection, for example, if a four-pole accessory is inserted with a button depressed.
Note that a two-pole jack is detected as three-pole jack, and will work as designed as a mono output.
If the impedance measured between the SLEEVE and RING2 pins is above 500 Ω (configurable), the
DA7219 detects the connected accessory as a four-pole jack. The DA7219 then moves to the pin
order-detect state, where it first drives current down the SLEEVE and then the RING2 pins, and
compares the voltages measured in each case. The pin that develops the largest voltage will be
deemed to be the accessory’s microphone, and the other pin as the ground.
The headphone impedance can also be to determine whether the output is to a headphone or to a
line output. Impedance measurements below a pre-set threshold are deemed to be headphones, and
impedances above the threshold are line outputs.
The DA7219 will then move to the button detect state, where polling is carried out to detect button
presses. If a button is pressed while MICBIAS is off, the DA7219 can only detect that a button has
been pressed, but cannot distinguish between the buttons.
To distinguish which one of up to four buttons was pressed, the MICBIAS rail must be enabled so
that the impedance can be measured between the MIC and GND pins. See section 9.5.6 for further
details.
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While any of the four possible buttons is being pressed, any further button presses are ignored. Only
once the first button has been released can a second or subsequent button press be detected.
Detection of the jack type and its configuration, detection of the number of buttons, detection of a mic
input, and detection of headphone or line outputs are all performed automatically when the AAD
block is enabled.
On detecting a button press, the DA7219 can identify all buttons as defined in the Android wired
headset specification (v1.1) when MICBIAS is present.
The DA7219 also offers the possibility of overriding the automatically detected accessories, and of
setting them manually.
A full cross-reference of the DA7219’s functionality and power consumption in different modes is
listed in Table 19.
9.5.1
Configuring Advanced Accessory Detection (AAD)
AAD is enabled by setting accdet_en = 1.
Within the AAD block, all individual accessory detection measurements can be enabled or disabled,
and all accessory detect interrupt signals can be masked.
All accessory detection measurements can be manually overridden, and the current statuses of all
measurements can be interrogated from the status register fields.
Jack type detection, jack configuration detection, and button detection are all based on
measurements of resistance between different pins. The resistance thresholds for every
measurement type are all configurable by using the relevant register fields.
A signal timing diagram is illustrated in Figure 20. These features are all summarised in Table 30,
and are described in greater detail in the following sections.
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Table 30: DA7219 Advanced Accessory Detection (AAD) feature summary
Feature
DA7219 support
Configuration
Host reporting
Enabled when
system_active and
accdet_en are both 1.
Host notifiaction via
e_jack_inserted and
e_jack_removed IRQ
events.
Jack
insertion/removal
detection
Yes
Jack insertion latency set by
jackdet_debounce
(1 ms <--> 1 s).
Jack Type detection runs on
insertion, Duration set by
jack_detect_rate . Host
configurable microphone
detection impendance
threshold mic_det_thresh
(100/200/500/750 Ω).
Host notification via
e_jack_detect_complete
IRQ event. jack_type_sts
register available for host
readback ( 3-Pole or 4-
Pole reported), data is
qualified by
Jack type detection
Yes - 3-Pole / 4-Pole
Optional Host manual type
override provided.
e_jack_detect_complete.
Host notification via
e_jack_detect_complete
IRQ event.
Detection with GND
switching runs on insertion if jack_pin_order_sts
Pin order detection
Yes - CTIA/OMTP
a 4-pole jack is detected.
Optional Host manual pin
Order override provided.
register available for host
readback (LRGM or
LRMG reported ), data is
qualified by
e_jack_detect_complete.
Button detection enable and
frequency (2 ms<--> 500 ms)
set by button_config. Host
controlled a_d_button_thresh,
d_b_button_thresh,
b_c_button_thresh, and
c_mic_button_thresh set the
ADC voltage thresholds for
button press impedance
measurements
Yes - Press / Release
detection for A,B,C and D
button impedances with +/-
1% accuracy, as per
Google Chromebook
Headset Accessory
Host notification via
e_button_*_pressed and
e_button_*_released IRQ
events, (where * = a/b/c/d).
button_type_sts 8 bit adc
measurement result also
available for host readback.
Button press detection
Electrical Specification.
= (RLOAD / (RLOAD + RMICBIAS))
Interrupt line asserted to
host when any unmasked
Yes - Single dedicated h/w All events are maskable and events are captured.
Interrupt reporting
interrupt line.
are 'Write 1 to clear'.
Interrupt line is de asserted
when all unmasked events
have been cleared by host.
Host control when the
MICBIAS rail can be enabled
(requires VDD_MIC) with
micbias1_en. Accdet will
automatically enable the
MICBIAS LDO following
e_jack_detect_complete if
micbias_up_sts available
for host readback to report
Yes- Both on insertion and
removal.
MICBIAS isolation
jack_type_sts reports '4 pole'. MICBIAS rail is up.
MICBIAS is auto disabled,
discharged and isolated on
e_jack_removed to prevent
audible artefacts on HPs
during a fast jack removal.
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Feature
DA7219 support
Configuration
Host reporting
Yes -supported by DA7219
using s/w controlled
sequence following
insertion.
HP_L impedance
measurement
N/A: This feature does not live N/A: This feature does not
in the accdet block.
live in the accdet block.
HP_L / HP_R to GND
when device
Yes-supported by DA7219 N/A: This feature does not live
N/A
using pulldown on HPs.
in the accdet block.
unpowered
DET
(5ms – 1s)
(64 – 512ms)
(2 – 500ms)
(1ms)
NO_JACK
INS_DEB
JACK_DETECT
JACK_IN
BTN_CHECK
JACK_IN
BTN_CHECK
JACK_IN
REM_DEB NO_JACK
Accdet State
e_jack_insertion
Host IRQ
clear
Host IRQ
clear
e_jack_removal
Host IRQ
clear
e_jack_detect_complete
Host type
check
DEFAULT
DEFAULT
3-Pole / 4-Pole
DEFAULT
DEFAULT
JACK_TYPE_STS
JACK_PIN_ORDER_STS
LRGM – CTIA / LRMG - OMTP
MICBIAS_UP_STS
MICBIAS OFF
MICBIAS ON
MICBIAS OFF
MICBIAS
MIC
D Button Press
Host IRQ
clear
e_d_button_pressed
Host IRQ
clear
e_d_button_released
nIRQ
Jack
insertion
Detection
Complete
Button Pressed
Button Released
Jack removal
RED: Device PIN
BLUE: Device Internal Signal
Figure 20: Signal timing diagram for the AAD function
Note 7 VDD_MIC must always be greater than VDD
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9.5.2
Detection of jack insertion or removal
Whenever a jack is inserted, a jack insertion event is flagged by e_jack_inserted getting set to1.
Similarly, a jack removal event is flagged by e_jack_removed getting set to1.
The presence or absence of a jack is recorded in jack_insertion_sts.
Any jack insertion will be detected, and is recorded by the setting of jack_insertion_sts. The register
field jack_insertion_sts = 1 if a jack has been inserted, and jack_insertion_sts = 0 if no jack has been
inserted.
Jack detection latency, that is, the time from an e_jack_insertion event to the point where
e_jack_detect_complete is asserted, is configurable using jack_detect_rate. The jack detection
latency times are different for three-pole and four-pole jacks, and are listed in
Table 22: Jack detection latency timings controlled by jack_detect_rate
Three-pole jacks
(ms)
Four-pole jacks
(ms)
jack_detect_rate
value
00
01
10
11
32
64
64
128
256
512
128
256
Debouncing is avaliable on jack insertion and removal events. Debounce on jack insertion is
specified using jackdet_debounce, and on jack removal using jackdet_rem_deb. The debounce times
are listed in Table 31 and Table 32.
Table 31: Debounce settings for jack insertion events
jackdet_debounce
Debounce time (ms)
000
001
010
011
100
101
110
111
5
10
20 (default)
50
100
200
500
1
Table 32: Debounce settings for jack removal events
jackdet_rem_deb
Debounce time (ms)
00
01
10
11
1 (default)
5
10
20
The jack insertion, jack removal, and jack complete interrupts can be masked using the register fields
in the ACCDET_IRQ_MASK_A register. The jack insertion interrupt is masked by setting
m_jack_inserted = 1, the jack removal interrupt is masked by setting m_jack_removed = 1, and the
jack detection complete interrupt is masked by setting m_jack_detect_complete = 1. These masking
fields mask the interrupt signals, but do not prevent updating of the event fields or the status fields
previously described.
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9.5.3
Three-pole or four-pole jack insertion
The type of jack inserted can be determined automatically by setting jack_type_det_en = 1.
Once the jack insertion measurement has been completed as indicated by
e_jack_detect_complete = 1, the AAD determines whether a three-pole or a four-pole jack has been
inserted. This is done by measuring the resistance between the SLEEVE and the RING2 pins. If the
measured impedance is below the threshold setting, a three-pole jack is deemed to have been
inserted. If the resistance is above this threshold setting, a four-pole jack is deemed to have been
inserted.
Note that if a mono two-pole jack is inserted, the AAD will detect this as a three-pole jack, but the
two-pole jack will work as designed, that is, as a mono output.
The threshold setting used to determine whether a three-pole or a four-pole jack has been inserted is
set using mic_det_thresh. The settings are listed in Table 33.
Table 33: Resistance threshold settings for three-pole and four-pole jack determination
Resistance
mic_det_thresh
threshold (Ω)
00
01
10
11
200
500 (default)
750
1000
Once the jack type has been successfully determined, the type of jack is recorded in jack_type_sts. A
three-pole jack is indicated by jack_type_sts = 0, and a four-pole jack by jack_type_sts = 1.
The jack type status recorded in the register field jack_type_sts is not valid until the measurement
has been completed. Measurement completion is indicated when e_jack_detect_complete = 1. Note
that e_jack_detect_complete = 1 indicates the completion of both the jack_type_sts measurement
and the jack_pin_order_sts measurement.
The measurement of the type of jack, which is performed automatically when jack_type_det_en = 1,
can be overridden if required. To do this, set jack_type_det_en = 0 to prevent the measurement
taking place, and then use the jack_type_force register field to force the jack type. A three-pole jack
is specified by setting jack_type_force = 0, and a four-pole jack by setting jack_type_force = 1.
9.5.4
Jack pin order detection with four-pole jacks
Two different polarities are widely used with four-pole jacks. These are the CTIA tip-ring-ring-sleeve
configuration of GND-MIC-RIGHT-LEFT, and the OMTP configuration of MIC-GND-RIGHT-LEFT.
If pin_order_det_en = 1, the detection of jack configuration is performed automatically. The
measurement of jack configuration can be overridden by setting pin_order_det_en = 0, and using
pin_order_force = 0 to specify the CTIA configurations. Setting pin_order_force = 1 specifies the
OMTP configuration.
The jack configuration status recorded in the register field jack_pin_order_sts is not valid until the
measurement has been completed. Measurement completion is indicated when
e_jack_detect_complete = 1. Note that e_jack_detect_complete = 1 indicates the completion of both
jack_type_sts measurement and jack_pin_order_sts measurement.
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9.5.5
Headphone output and line output
The DA7219 can detect whether the output is a headphone or a line output. Headphone or lineout
detection is enabled by setting hptest_en = 1.
The impedance is measured between HP_L (or HP_R) and the local GND connection on either
SLEEVE or RING2 (depending on the jack configuration) to determine whether the output is to a
headphone or to a lineout. Impedance measurements below a pre-set threshold are deemed to be
headphones, and impedances above the threshold are line outputs.
The threshold value is set between 1 and 10 kΩ by setting hptest_res_sel appropriately. The
threshold settings available are listed in Table 34.
The Tone Generator is used to develop a slow S-ramp of the signal amplitude at a frequency below
the audible range on the HP outputs. The S-ramp profile is configurable for maximum flexibility.
The device monitors the current drawn by the HP amps during this process, and reports back the
load as either above or below the threshold level. The accuracy of the measurement is ±40%.
The host AP must control the test:
●
●
●
●
Program the S-ramp profile
Initialise the DA7219 signal path and outputs
Initiate the S-ramp function
Read back the impedance detection status register for the load condition.
Table 34: Resistance threshold settings for headphone and lineout determination
hptest_res_sel
setting
Test threshold
impedance (kΩ)
00
01
10
11
1.0
2.5
5.0
10.0
The result of the headphone threshold test is stored in hptest_comp.
9.5.6
Detection of buttons
After successful detection of the insertion of a four-pole jack (e_jack_detect_compete = 1 and
jack_type_sts = 1), the DA7219 will move to the button detect state, where polling is carried out for
button presses. If a button is pressed while MICBIAS is off, the DA7219 can only detect that a button
has been pressed, but cannot distinguish between the buttons. On detecting a button press, the
DA7219 can identify all buttons as defined in the Android wired headset specification (v1.1) when
MICBIAS is present.
The Android wired audio headset specification (v1.1) specifies the impedance associated with any
button press. The impedance is measured between the MIC and GND. Note that when measuring
the impedance of a button press, the measured impedance includes both the impedance of the
resistor associated with a button and the impedance of the microphone. This is illustrated in
Figure 21.
While any of the four possible buttons is being pressed, any further button presses are ignored. Only
after the first button has been released can a second or subsequent button press be detected.
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Measured
impedance
NOTE:
The impedance for any button press is measured
between MIC and GND. Note that the circuit
includes both the resistor associated with the
button AND the MIC’s impedance in parallel.
GND
or
MIC
MIC
or
LEFT
RIGHT
GND
R1
R2
R3
R4
Microphone
Button
A
Button
B
Button
C
Button
D
Figure 21: Measuring the impedance of a button press
The Android wired audio headset specification (v1.1) stipulates the functions and names of the four
possible buttons on a headset. These are listed in Table 35.
Table 35: Button names and functions in Android devices
Button
Function
Play, pause, or hook (short press)
Trigger assist (long press)
Next (double-press)
Function A
Function B
Function C
Function D
Volume +
Volume -
Google voice search feature
Headsets with only one button must implement Function A.
Headsets with multiple buttons must implement functions according to the following patterns:
●
●
●
Two functions: Functions A and D
Three functions: Functions A, B, and C
Four functions: Functions A, B, C, and D
Whenever a button is pressed, a button press event is flagged by e_button_<a|b|c|d>_pressed
getting set = 1.
Similarly, a button release event is flagged by e_button_<a|b|c|d>_released getting set = 1.
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The measured impedance of the last button press is recorded in button_type_sts. The impedance
measurements can be averaged using button_average. Averaging in this manner provides greater
immunity to spurious measurements caused my noise, but at a cost of consuming more power and of
increasing the measurement latency (every extra measurement used in the averaging takes
approximately 1 ms to perform). The number of measurements that are used in the averaging are
listed in Table 36.
Table 36: Setting the number of measurements used in averaging
Number of
button_average
measurements
used in averaging
setting
00
01
10
11
1
2
4
8
The button press interrupts can be masked by asserting the register fields
m_button_<a|b|c|d>_pressed. The button released interrupts can be masked by setting
m_button_<a|b|c|d>_released = 1. These masking fields mask the interrupt signals, but do not
prevent updating of the event fields or the status fields previously described.
The impedance threshold between Button A and Button D is specified using a_d_button_thresh, and
is specified as (RLOAD / RLOAD + RMICBIAS).
Similarly, the impedance threshold between Button D and Button B is specified using
d_b_button_thresh, and is specified in the same manner (RLOAD / RLOAD + RMICBIAS). The impedance
threshold between Button B and Button C is specified using b_c_button_thresh, and is specified in
the same manner (RLOAD / RLOAD + RMICBIAS).
The impedance threshold between Button C and MIC is specified using c_mic_button_thresh and is
again specified in the same manner (RLOAD / RLOAD + RMICBIAS).
The time between the periodic button press measurements is specified using button_config. The
inter-measurement period can be between 2 ms and 500 ms.
The button_config register is only active after a four-pole jack has been detected. Setting
button_config = 0 also disables the button measurements.
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9.6 Clocking
The internal system clock (SYSCLK) from which all other clocks are derived is always at one of two
possible frequencies:
●
●
12.288 MHz for SR from the 48 kHz family (8, 12, 16, 24, 32, 48, 96 kHz)
11.2896 MHz for SR from the 44.1 kHz family (11.025, 22.05, 44.1, 88.2 kHz).
The DA7219 can run with or without an applied MCLK. If no MCLK is applied, the internal reference
oscillator will clock the device. However when using the DAI an MCLK must be provided and
correctly configured.
The DA7219 contains a phase-locked loop (PLL), which supports a range of clocking modes and
input clock (MCLK) frequencies.
9.6.1
MCLK input
MCLK is the master clock input which must be in the range of 2 to 54 MHz.
MCLK can be applied as a full-amplitude square wave, or as a low-amplitude sine wave if the MCLK
squarer circuit has been enabled. The clock squarer circuit is enabled by writing pll_mclk_sqr_en = 1.
This clock squarer allows a sine wave or other low amplitude clock (down to 300 mVpp) to be applied
to the chip. The MCLK input is AC coupled on chip when using the clock squarer mode.
9.6.1.1
MCLK detection
A clock detection circuit will set bit [0] of pll_srm_status = 1 whenever the applied MCLK frequency is
above the minimum detection frequency of approximately 1 MHz. Whenever this bit is high, the
MCLK signal is selected as the clock input to the PLL.
9.6.2
Audio reference oscillator
For best audio performance, a system clock within the specified range is required. The DA7219
codec has an internal reference oscillator that provides the system clock when there is no valid
MCLK signal.
The reference oscillator is automatically enabled whenever the codec is in ACTIVE mode and the
MCLK frequency is below the minimum frequency of 1 MHz. When the codec enters STANDBY
mode, the oscillator is automatically disabled to save power.
9.6.3
PLL bypass mode
If an MCLK signal at 11.2896/12.288 MHz or 22.5792/24.576 MHz or 45.1584/49.152 MHz is
available, the PLL is not required and should be disabled to save power. PLL bypass mode is
activated by setting pll_mode = 00.
In this mode the PLL is bypassed and an audio frequency clock is applied to the MCLK pin of the
codec. The required clock frequency depends on the sample rate at which the audio DACs and
ADCs are operating. These clock frequencies are summarized in Table 37 for the range of DAC and
ADC sample rates that can be configured using the SR register.
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Table 37: Sample rate control register and corresponding system clock frequency
System clock frequency
Sample rate, FS (kHz)
SR register
(MHz)
12.288
11.2896
12.288
12.288
11.2896
12.288
12.288
11.2896
12.288
11.2896
12.288
8
11.025
12
0001
0010
0011
0101
0110
0111
1001
1010
1011
1110
1111
16
22.05
24
32
44.1
48
88.2
96
If digital playback or record is required in bypass mode then the MCLK frequency should be set to
11.2896/12.288 MHz, or to 22.5792/24.576 MHz, or to 45.1584/49.152 MHz and pll_indiv should be
programmed accordingly.
If no valid MCLK is detected, the output of the internal reference oscillator is used instead. However
in this case only analogue bypass paths may be used.
9.6.4
Normal PLL mode (DAI master)
The DA7212 contains a Phase Locked Loop (PLL) that can be used to generate the required
11.2896 MHz or 12.288 MHz internal system clock when a frequency of between 2 and 54 MHz is
applied to MCLK. This allows sharing of clocks between devices in an application, reducing total
system cost. For example, the codec may operate from common 13 MHz or 19.2 MHz system clock
frequency.
The PLL is enabled by asserting pll_mode = 01. Once the PLL is enabled and has achieved phase
lock, PLL bypass mode is disabled, and the output of the PLL is used as the system clock.
The PLL input divider register (pll_indiv) is used to reduce the PLL reference frequency to the usable
range of 2 to 54 MHz as shown in Table 38, this reduces the PLL reference frequency according to
the following equation:
FREF = FMCLK ÷ N
Table 38: PLL input divider
MCLK input frequency (MHz)
Input divider, (÷N)
pll_indiv register (0x27 [3:2])
2 – 5
÷1
÷2
000
001
010
011
100
5 – 10
10 – 20
20 – 40
40 – 54
÷4
÷8
÷16
The value of the PLL feedback divider is used to set the voltage controlled oscillator (VCO) frequency
to 8 times the required system clock frequency (see Table 37).
FVCO = FREF × PLL feedback divider
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The value of the PLL feedback divider is an unsigned number in the range of 0 to 128. It consists of
seven integer bits and 13 fractional bits split across three registers:
●
●
●
PLL_INTEGER holds the seven integer bits
PLL_FRAC_BOT holds the top bits (MSB) of the fractional part of the divisor
PLL_FRAC_BOT holds the bottom bits (LSB) of the fractional part of the divisor
9.6.5
Example calculation of the feedback divider setting:
We will use as an example a codec operating with Fs (sample rate) = 48 kHz and a reference input
clock frequency of 12.288 MHz. The required output frequency is 98.304 MHz.
The reference clock input = 12.288 MHz, which falls in the range 10-20 MHz so pll_indiv be set to
0b010 (dividing the reference input frequency by 4 – see Table 38.
The formula for calculating the feedback divider is:
Feedback divider (F) = VCO output frequency * input divider (pll_indiv) / reference input clock
Feedback divider = (98.304 * 4) / 12.288 = 32
So
●
●
●
pll_fbdiv_integer (holding the seven integer bits) = 0x20
pll_fbdiv_frac_top (holding the top bits (MSB) of the fractional part of the divisor) = 0x00
pll_fbdiv_frac_bot (holding the bottom bits (LSB) of the fractional part of the divisor) = 0x00
Table 39 shows example register settings that will configure the PLL when using a 13 MHz, 15 MHz
or 19.2 MHz clock. Note that any MCLK input frequency between 2 and 54 MHz is supported.
pll_indiv must be used to reduce the PLL reference frequency to the usable range of
2 to 5 MHz as shown in Table 39.
Table 39: Example PLL configurations
System
MCLK input
frequency
(MHz)
clock
frequency
(MHz)
pll_mode
register
PLL_FRAC_TOP
register
PLL_FRAC_BOT
register
PLL_INTEGER
register
13
13
11.2896
12.288
11.2896
12.288
11.2896
12.288
0x01
0x01
0x01
0x01
0x01
0x01
0x19
0x07
0x02
0x06
0x1A
0x0F
0x45
0xEA
0xB4
0xDC
0x1C
0x5C
0x1B
0x1E
0x18
0x1A
0x12
0x14
15
15
19.2
19.2
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9.6.6
SRM PLL mode (DAI slave)
SRM mode enables the PLL output clock to be synchronized to the incoming WCLK signal on the
DAI. The SRM PLL mode is enabled by setting pll_mode = 10.
When using the digital audio interface in slave mode with the SRM enabled, removing and re-
applying the DAI interface word clock WCLK may cause the PLL lock to be lost. To re-lock the PLL it
is recommended that you disable the SRM (pll_mode = 00), reset the PLL by re-writing to register
PLL_INTEGER, and then re-enable the SRM (pll_mode = 10) after the DAI WCLK has been
reapplied.
When switching sample rates between 44.1 kHz and 48 kHz (or between the multiples of these
sample rates), SRM must be disabled and then re enabled using register bit pll_mode.
9.7 Reference generation
9.7.1
Voltage references
The audio circuits use supply-derived references of 0.45×VDD (VMID) and 0.9×VDD (DACREF).
There is also bandgap-derived fixed voltage reference of 1.2 V (VREF). All three voltage references
require off-chip decoupling capacitors (see Appendix B.6).
Both VREF and VMID are automatically enabled whenever the device enters ACTIVE mode. They
are automatically disabled when entering STANDBY mode.
The VMID reference comes from a high-resistance voltage divider, which combines with the
decoupling capacitor to create a large RC (resistance-capacitance) time constant. This ensures a
noise-free VMID reference.
To minimise startup time, set vmid_fast_charge = 1. This enables a low resistance path to charge the
decoupling capacitor faster.
Fast charge (vmid_fast_charge) must be disabled after start-up as it will increase the noise on the
VMID reference.
The bandgap reference VREF also takes time to charge its decoupling capacitor, but an internal
timer ensures that no circuit that requires VREF is enabled until VREF has reached 1.2 V.
The DACREF voltage reference is produced from VMID by a times-two buffer so is capable of
charging its decoupling capacitor quickly.
9.7.2
Bias currents
DA7219 has a master bias current generation block that is enabled by default using the bias_en bit.
Master bias current generation is set to ‘On’ by default. Each sub system has its own local current
generation block, which is automatically enabled whenever any of its sub-blocks are enabled.
9.7.3
9.7.4
Voltage levels
IO voltage level
The digital input/output pins can be set to operate in either a high voltage (2.5 to 3.6 V) or low voltage
(1.5 to 2.5 V) range using the io_voltage_level bit. See Table 40.
Table 40: IO voltage level setting
io_voltage_level setting
Digital I/O voltage range (V)
2.5 to 3.6
0
1
1.2 to 2.5
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9.8 I2C control interface
The DA7219 is completely software-controlled from the host by registers. The DA7219 provides an
I2C compliant serial control interface to access these registers. Data is shifted into or out of the
DA7219 under the control of the host processor, which also provides the serial clock.
The I2C clock is supplied by the SCL line and the bi-directional I2C data is carried by the SDA line.
The I2C interface is open-drain supporting multiple devices on a single line. The bus lines have to be
pulled HIGH by external pull-up resistors (1 kΩ to 20 kΩ range). The attached devices only drive the
bus lines LOW by connecting them to ground. This means that two devices cannot conflict if they
drive the bus simultaneously.
Table 41: Device I2C slave addresses
Register
Device I2C address
cif_i2c_addr_cfg
00
01
10
11
0x18
0x19
0x1A (default)
0x1B
In standard/fast mode the highest frequency of the bus is 1 MHz. The exact frequency can be
determined by the application and does not have any relation to the DA7219 internal clock signals.
DA7219 will follow the host clock speed within the described limitations and does not initiate any
clock arbitration or slow down.
In high-speed mode the maximum frequency of the bus can be increased up to 3.4 MHz. This mode
is supported if the SCL line is driven with a push-pull stage from the host and if the host enables an
external 3 mA pull-up at the SDA pin to decrease the rise time of the data. In this mode the SDA line
on DA7219 is able to sink up to 12 mA. In all other respects the high speed mode behaves as the
standard/fast mode. Communication on the I2C bus always takes place between two devices, one
acting as the master and the other as the slave. The DA7219 will only operate as a slave. The I2C
interface has direct access to the whole register map of the DA7219.
VDD_IO
Host
VDD_IO
SCL
Processor
SCL
SDA
SDA Codec
SCL
SDA
Peripheral
Device
Figure 22: Schematic of the I2C control interface bus
All data is transmitted across the I2C bus in groups of eight bits. To send a bit the SDA line is driven
to the intended state while the SDA is LOW (a LOW on SDA indicates a zero bit). Once the SDA has
settled, the SCL line is brought HIGH and then LOW. This pulse on SCL clocks the SDA bit into the
receiver’s shift register.
A two byte serial protocol is used containing one byte for address and one byte for data. Data and
address transfer is transmitted MSB first for both read and write operations. All transmission begins
with the START condition from the master while the bus is in the IDLE state (the bus is free). It is
initiated by a high to low transition on the SDA line while the SCL is in the high state (a STOP
condition is indicated by a low to high transition on the SDA line while the SCL line is in the high
state).
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SCL
SDA
Figure 23: I2C START and STOP conditions
The I2C bus is monitored by DA7219 for a valid SLAVE address whenever the interface is enabled. It
responds with an Acknowledge immediately when it receives its own slave address. The
Acknowledge is done by pulling the SDA line low during the following clock cycle (white blocks
marked with ‘A’ in Figure 24 to Figure 28).
The protocol for a register write from master to slave consists of a start condition, a slave address
with read/write bit and the 8-bit register address followed by 8 bits of data terminated by a STOP
condition (the DA7219 responds to all bytes with Acknowledge). This is illustrated in Figure 24.
P
S
SLAVE addr
7-bits
W
A
REG addr
8-bits
A
DATA
8-bits
A
1-bit
Master to Slave
Slave to Master
S = START condition
P = STOP condition
A = Acknowledge (low)
W = Write (low)
Figure 24: I2C byte write (SDA line)
When the host reads data from a register it first has to write-access DA7219 with the target register
address and then read access DA7219 with a repeated START, or alternatively a second START
condition. After receiving the data the host sends a Not Acknowledge (NAK) and terminates the
transmission with a STOP condition:
A*
P
S SLAVEaddr W A REG addr A Sr SLAVEaddr R
1-bit
A
DATA
8-bits
7-bits 1-bit
8-bits
7-bits
A*
P
S SLAVEaddr W A REG addr
A
P
S SLAVEaddr R
7-bits 1-bit
A
DATA
8-bits
7-bits 1-bit
8-bits
Master to Slave
Slave to Master
S = START condition
Sr = Repeated START condition
P = STOP condition
A = Acknowledge (low)
A* = Not Acknowledge (NAK)
W = Write (low) R = Read (high)
Figure 25: Examples of the I2C byte read (SDA line)
Consecutive (Page Mode) read-out mode (cif_i2c_write_mode = 0) is initiated from the master by
sending an Acknowledge instead of Not Acknowledge (NAK) after receipt of the data word. The I2C
control block then increments the address pointer to the next I2C address and sends the data to the
master. This enables an unlimited read of data bytes until the master sends a NAK directly after the
receipt of data, followed by a subsequent STOP condition. If a non-existent I2C address is read out,
the DA7219 will return code zero.
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A*
P
S SLAVEaddr W
7-bits 1 bit
A
REG addr A Sr SLAVEaddr R
A
DATA
8-bits
A
DATA
8-bits
A
DATA
8-bits
8-bits
7-bits 1-bit
S
SLAVEaddr W
7-bits
A
REG addr
8-bits
A
P
S SLAVEaddr R
7-bits 1-bit
A
DATA
8-bits
A
DATA
8-bits
A*
P
1-bit
Master to Slave
Slave to Master
A
S = START condition
= Acknowledge (low)
Sr = Repeat START condition
P = STOP condition
A* = Not Acknowledge (NAK)
W = Write (low)
R = Read (high)
Figure 26: Examples of I2C page read (SDA line)
The slave address after the Repeated START condition must be the same as the previous slave
address.
Consecutive write-mode (cif_i2c_write_mode = 0) is supported if the Master sends several data bytes
following a slave register address. The I2C control block then increments the address pointer to the
next I2C address, stores the received data and sends an Acknowledge until the master sends the
STOP condition.
S SLAVEaddr W
7-bits 1 bit
A
REGadr
8-bits
A
DATA
A
DATA
8-bits
A
DATA
8-bits
A
……….
Repeated writes
A
P
8-bits 1-bit
Master to Slave
Slave to Master
A
S = START condition
= Acknowledge (low)
Sr = Repeat START condition
P = STOP condition
A* = Not Acknowledge (NAK)
W = Write (low)
R = Read (high)
Figure 27: I2C page write (SDA line)
An alternative repeated-write mode that uses non-consecutive slave register addresses is available
using the cif_i2c_write_mode register. In this Repeat Mode (cif_i2c_write_mode = 1), the slave can
be configured to support a host’s repeated write operations into several non-consecutive registers.
Data is stored at the previously received register address. If a new START or STOP condition occurs
within a message, the bus returns to IDLE mode. This is illustrated in Figure 28.
S SLAVEaddr W
7-bits 1 bit
A
REG addr
8-bits
A
DATA
A
REG addr
8-bits
A
DATA
8-bits
A
……….
Repeated writes
A
P
8-bits 1-bit
Master to Slave
Slave to Master
A
S = START condition
= Acknowledge (low)
Sr = Repeat START condition
P = STOP condition
A* = Not Acknowledge (NAK)
W = Write (low)
R = Read (high)
Figure 28: I2C repeated write (SDA line)
In Page Mode (cif_i2c_write_mode = 0), both Page Mode reads and writes using auto incremented
addresses, and Repeat Mode reads and writes using non-auto-incremented addresses, are
supported. In Repeat Mode (cif_i2c_write_mode = 1) however, only Repeat Mode reads and writes
are supported.
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9.9 Digital Audio Interface (DAI)
DA7219 provides one Digital Audio Interface (DAI) to input DAC data or to output ADC data. It is
enabled by asserting dai_en. The DSP provides flexible routing options allowing each interface to be
connected to different signal paths as desired in each application.
The DAI consists of a four-wire serial interface, with bit clock (BCLK), word clock (WCLK), data-in
(DATIN) and data-out (DATOUT) pins. Both master and slave clock modes are supported by the
DA7219. Master mode is enabled by setting register dai_clk_en = 1. In master mode, the bit clock
and word clock signals are outputs from the codec. In slave mode these are inputs to the codec.
BCLK
WCLK
DA7219
Processor
Codec
DATIN
DATOUT
Figure 29: Master mode (dai_clk_en = 1)
BCLK
WCLK
DA7219
Processor
Codec
DATIN
DATOUT
Figure 30: Slave mode (dai_clk_en = 0)
The internal serialised DAI data is 24 bits wide. Serial data that is not 24 bits wide is either shortened
or zero-filled at input to, or at output from, the DAI’s internal 24-bit data width. The serial data word
length can be configured to be 16, 20, 24 or 32 bits wide using the dai_word_length register bits.
Four different data formats are supported by the digital audio interface. The data format is
determined by the setting of the dai_format register bits.
●
●
●
●
I2S mode
Left Justified mode
Right Justified mode
DSP mode
Time division multiplexing (TDM) is available in any of these modes to support the case where
multiple devices are communicating simultaneously on the same bus. TDM is enabled by asserting
the dai_tdm_mode_en bit.
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9.9.1
DAI channels
The DAI supports one to two channels, even in non-TDM modes. The number of channels required is
specified by setting dai_ch_num which controls the position of the channels.
In TDM mode, each of the two channels can be individually enabled using the dai_tdm_ch_en
register.
9.9.2
I2S mode
In I2S mode (dai_format = 0), the MSB of the left channel is valid on the second rising edge of the bit
clock after the falling edge of the word clock. The MSB of the right channel is valid on the second
rising edge of the bit clock after the rising edge of the word clock.
WCLK 1 = RIGHT CHANNEL DATA
WCLK 0 = LEFT CHANNEL DATA
WCLK
BCLK
msb
Right Channel
lsb
msb
Left Channel
lsb
msb
DATIN/DATOUT
Figure 31: I2S mode
9.9.3
Left justified mode
In left-justified mode (dai_format = 1), the MSB of the right channel is valid on the rising edge of the
bit clock following the falling edge of the word clock. The MSB of the left channel is valid on the rising
edge of the bit clock following the rising edge of the word clock.
WCLK 1 = LEFT CHANNEL DATA
WCLK 0 = RIGHT CHANNEL DATA
WCLK
BCLK
msb
Left Channel
lsb
msb
Right Channel
lsb
msb
DATIN/DATOUT
Figure 32: Left justified mode
9.9.4
Right justified mode
In right-justified mode (dai_format = 2), the LSB of the left channel is valid on the rising edge of the
bit clock preceding the falling edge of word clock. The LSB of the right channel is valid on the rising
edge of the bit clock preceding the rising edge of the word clock.
WCLK 1 = LEFT CHANNEL DATA
WCLK 0 = RIGHT CHANNEL DATA
WCLK
BCLK
lsb
msb
Left Channel
lsb
msb
Right Channel
lsb
DATIN/DATOUT
Figure 33: Right justified mode
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9.9.5
DSP mode
In DSP mode (dai_format = 3), the rising edge of the word clock starts the data transfer with the left
channel data first and immediately followed by the right channel data. Each data bit is valid on the
falling edge of the bit clock.
The falling edge of WCLK can occur anywhere in this area
WCLK
BCLK
msb
Left Channel
lsb msb
Right Channel
lsb
msb
DATIN/DATOUT
The falling edge of WCLK can occur anywhere in this area
WCLK
BCLK
msb
Left Channel
lsb msb
Right Channel
lsb
msb
DATIN/DATOUT
Offset
Figure 34: DSP mode
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10 Register maps and definitions
Table 42: Register map accdet_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x000000C0
ACCDET_STA
TUS_A
micbias_up_ jack_pin_ord
sts er_sts
jack_insertio
n_sts
Reserved
jack_type_sts
0x000000C1
ACCDET_STA
TUS_B
button_type_sts
0x000000C2
ACCDET_IRQ
_EVENT_A
e_jack_detec e_jack_remo e_jack_insert
t_complete ved ed
Reserved
0x000000C3
ACCDET_IRQ
_EVENT_B
e_button_a_r e_button_b_r e_button_c_r e_button_d_r e_button_d_ e_button_c_p e_button_b_ e_button_a_
eleased
eleased
eleased
eleased
pressed
ressed
pressed
pressed
0x000000C4
ACCDET_IRQ
_MASK_A
m_jack_dete m_jack_remo m_jack_inser
ct_complete ved ted
Reserved
0x000000C5
ACCDET_IRQ
_MASK_B
m_button_a_ m_button_b_ m_button_c_ m_button_d_ m_button_d_ m_button_c_ m_button_b_ m_button_a_
released
released
released
released
pressed
pressed
pressed
pressed
0x000000C6
ACCDET_CO
NFIG_1
pin_order_de jack_type_de
t_en t_en
mic_det_thresh
button_config
accdet_en
0x000000C7
ACCDET_CO
NFIG_2
accdet_paus
e
jackdet_rem_deb
jack_detect_rate
jackdet_debounce
0x000000C8
ACCDET_CO
NFIG_3
A_D_BUTTON_THRESH
D_B_BUTTON_THRESH
B_C_BUTTON_THRESH
C_MIC_BUTTON_THRESH
0x000000C9
ACCDET_CO
NFIG_4
0x000000CA
ACCDET_CO
NFIG_5
0x000000CB
ACCDET_CO
NFIG_6
0x000000CC
ACCDET_CO
NFIG_7
jack_type_for pin_order_for
Reserved
adc_1_bit_repeat
button_average
ce
ce
0x000000CD
ACCDET_CO
NFIG_8
Reserved
hptest_comp
Reserved
hptest_res_sel
hptest_en
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Table 43: ACCDET_STATUS_A (Page 0: 0x000000C0)
Bit
Mode
Symbol
Description
Reset
3
R
micbias_up_sts
Status of the microphone supply rail MICBIAS
0x0
0 = MICBIAS off
1 = MICBIAS On
MICBIAS is enabled automatically when a four-pole
jack is inserted
2
R
jack_pin_order_sts
Status of the jack pin-order detection. Pins are
measured in Tip-Ring1-Ring2-Sleeve order.
0x0
0 = LRGM (CTIA format)
1 = LRMG (OMTP format)
The data in this bit field is only valid after the
e_jack_detect_complete event has fired, that is,
once e_jack_detect_complete = 1
1
0
R
R
jack_type_sts
Status of the jack-type detection.
0x0
0x0
0 = 3-pole jack detected
1 = 4-pole jack detected
The data in this bit field is only valid after the
e_jack_detect_complete event has fired, that is,
once e_jack_detect_complete = 1
jack_insertion_sts
Jack insertion status
0 = No jack is present
1 = Jack is present
Table 44: ACCDET_STATUS_B (Page 0: 0x000000C1)
Bit
Mode
Symbol
Description
Reset
7:0
R
button_type_sts
The last measured 8-bit button impendance value
from the ADC.
0x0
Table 45: ACCDET_IRQ_EVENT_A (Page 0: 0x000000C2)
Bit
Mode
Symbol
Description
Reset
2
R
e_jack_detect_compl Jack detection IRQ event field. This is asserted
0x0
ete
once the jack detection has completed. This is a
'write 1 to clear' field.
jack_type_sts and jack_pin_order_sts status bits
are only valid after this event has been asserted.
1
0
R
R
e_jack_removed
e_jack_inserted
Jack removal IRQ event field. This is asserted when 0x0
a jack is removed. This is a 'write 1 to clear' field.
Jack insertion IRQ event field. This is asserted
when a jack is inserted. This is a 'write 1 to clear'
field.
0x0
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Table 46: ACCDET_IRQ_EVENT_B (Page 0: 0x000000C3)
Bit
Mode
Symbol
Description
Reset
7
R
e_button_a_released Button A release IRQ event field. This is asserted
when Button A is released. This is a 'write 1 to
clear' field.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
6
5
4
3
2
1
0
R
R
R
R
R
R
R
e_button_b_released Button B release IRQ event field. This is asserted
when Button B is released. This is a 'write 1 to
clear' field.
e_button_c_released Button C release IRQ event field. This is asserted
when Button C is released. This is a 'write 1 to
clear' field.
e_button_d_released Button D release IRQ event field. This is asserted
when Button D is released. This is a 'write 1 to
clear' field.
e_button_d_pressed
e_button_c_pressed
e_button_b_pressed
e_button_a_pressed
Button A press IRQ event field. This is asserted
when Button A is pressed. This is a 'write 1 to clear'
field.
Button B press IRQ event field. This is asserted
when Button B is pressed. This is a 'write 1 to clear'
field.
Button C press IRQ event field. This is asserted
when Button C is pressed. This is a 'write 1 to clear'
field.
Button D press IRQ event field. This is asserted
when Button D is pressed. This is a 'write 1 to clear'
field.
Table 47: ACCDET_IRQ_MASK_A (Page 0: 0x000000C4)
Bit
Mode
Symbol
Description
Reset
2
R/W
m_jack_detect_comp Interrupt mask for e_jack_detect_complete
lete
0x0
0 = Jack detection IRQ is not masked
1 = Jack detection IRQ is masked
1
0
R/W
R/W
m_jack_removed
m_jack_inserted
Interrupt mask for e_jack_removed
0x0
0x0
0 = Jack removal IRQ is not masked
1 = Jack removal IRQ is masked
Interrupt mask for e_jack_inserted
0 = Jack insertion IRQ is not masked
1 = Jack insertion IRQ is masked
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Table 48: ACCDET_IRQ_MASK_B (Page 0: 0x000000C5)
Bit
Mode
Symbol
Description
Reset
7
R/W
m_button_a_release
d
Interrupt mask for e_button_a_released
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0 = Button A release IRQ is not masked
1 = Button A release IRQ is masked
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
m_button_b_release
d
Interrupt mask for e_button_b_released
0 = Button B release IRQ is not masked
1 = Button B release IRQ is masked
m_button_c_release
d
Interrupt mask for e_button_c_released
0 = Button C release IRQ is not masked
1 = Button C release IRQ is masked
m_button_d_release
d
Interrupt mask for e_button_d_released
0 = Button D release IRQ is not masked
1 = Button D release IRQ is masked
m_button_d_pressed Interrupt mask for e_button_a_pressed
0 = Button A press IRQ is not masked
1 = Button A press IRQ is masked
m_button_c_pressed Interrupt mask for e_button_b_pressed
0 = Button B press IRQ is not masked
1 = Button B press IRQ is masked
m_button_b_pressed Interrupt mask for e_button_c_pressed
0 = Button C press IRQ is not masked
1 = Button C press IRQ is masked
m_button_a_pressed Interrupt mask for e_button_d_pressed
0 = Button D press IRQ is not masked
1 = Button D press IRQ is masked
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Table 49: ACCDET_CONFIG_1 (Page 0: 0x000000C6)
Bit
Mode
Symbol
Description
Reset
7
R/W
pin_order_det_en
Controls detection of the pin order on insertion of a
4-pole jack
0x1
0 = Pin order is determined by the setting of the
pin_order_force register field when jack_type_sts =
4-pole
1 = Pin order detection ( LRGM / LRMG ) runs on
insertion of a 4-pole Jack
6
R/W
R/W
jack_type_det_en
Controls detection of the type of jack (3-pole without 0x1
a mic or 4-pole with a mic) when a jack is inserted
0 = The type of jack (3-pole or 4-pole) is determined
by the setting of the jack_type_force register field
1 = Jack type detection runs on jack insertion to
determine Jack Type (3-pole with no mic, or 4-pole
with a mic)
5:4
mic_det_thresh
Impedance threshold for MIC detection
measurement.
0x1
0x3
0x0
If SLEEVE to RING2 impedance is below the
threshold specified here, jack_type_sts is set to 0
(3-pole). If SLEEVE to RING2 impedance is above
the threshold specified here, jack_type_sts is set to
1 (4-pole).
00 = 200 Ω
01 = 500 Ω (default)
10 = 750 Ω
11 = 1000 Ω
3:1
R/W
button_config
Specifies the time between the periodic button-
press measurements when jack_type_sts = 1 (4-
Pole).
000 = Disabled
001 = 2 ms
010 = 5 ms
011 = 10 ms (default)
100 = 50 ms
101 = 100 ms
110 = 200 ms
111 = 500 ms
0
R/W
accdet_en
Controls Accessory Detection
0 = Accessory Detection is disabled
1 = Accessory Detection is enabled
The ACCDET analogue components require master
bias to be enabled before enabling the digital block
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Table 50: ACCDET_CONFIG_2 (Page 0: 0x000000C7)
Bit
Mode
Symbol
Description
Reset
7:6
R/W
jackdet_rem_deb
Control of the JACKDET deassertion debounce
0x0
00 = 1 ms (default)
01 = 5 ms
10 = 10 ms
11 = 20 ms
5:4
R/W
jack_detect_rate
Controls the jack-detection latency time, that is, the
time from assertion of e_jack_insertion to assertion
of e_jack_detect_complete
0x3
3-pole jack:
00 = 32 ms
01 = 64 ms
10 = 128 ms
11 = 256 ms (default)
4-pole jack:
00 = 64 ms
01 = 128 ms
10 = 256 ms
11 = 512 ms (default)
Latency time is altered by changing the ramp rate of
the MICDET current during jack type and pin order
detection.
3:1
R/W
jackdet_debounce
Control of the JACKDET assertion debounce
0x2
0 = 5 ms
1 = 10 ms
2 = 20 ms (default)
3 = 50 ms
4 = 100 ms
5 = 200 ms
6 = 500 ms
7 = 1 s
0
R/W
accdet_pause
Pauses the periodic button checking within the
accessory detection function. This allows you to
reconfigure the button measurements or to change
MICBIAS or both.
0x0
0 = No effect
1 = Pauses the periodic button checking within the
accessory detection block
The difference between pausing by asserting this
register field and disabling the accessory detection
function entirely (accdet_en = 0) is that pausing
allows for dynamic reconfiguration of the button
measurements. When paused, the DA7219 chip will
still respond to new removal or insertion events
whereas when disabled, no insertion or removal
events are detected.
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Table 51: ACCDET_CONFIG_3 (Page 0: 0x000000C8)
Bit
Mode
Symbol
Description
Reset
7:0
R/W
A_D_BUTTON_THR Sets the impedance threshold between Button A
0xA
ESH
and Button D. If the measured impedance of a
button-press is lower than the threshold value
specified here, the button that was pressed is
Button A.
The value of this register field is a calculated value.
It is calculated as:
256 * Required threshold in Ω/(Required
threshold in Ω + MICBIAS resistance in Ω)
Example calculation:
Assuming that MICBIAS resistance = 2200 Ω and
the required threshold = 89 Ω, the bit value of this
register field = 256 * 89/(89 + 2200) = 10 [or 0x0A].
So, in this example, setting this register field = 0x0A
will give you a threshold value of 89 Ω.
Table 52: ACCDET_CONFIG_4 (Page 0: 0x000000C9)
Bit
Mode
Symbol
Description
Reset
7:0
R/W
D_B_BUTTON_THR Sets the impedance threshold between Button D
0x16
ESH
and Button B. If the measured impedance of a
button-press is lower than the threshold value
specified here, the button that was pressed is
Button D.
The value of this register field is a calculated value.
It is calculated as:
256 * Required threshold in Ω/(Required
threshold in Ω + MICBIAS resistance in Ω)
Example calculation:
Assuming that MICBIAS resistance = 2200 Ω and
the required threshold = 195 Ω, the bit value of this
register field = 256 * 195/(195 + 2200) = 21 [or
0x15].
So, in this example, setting this register field = 0x15
will give you a threshold value of 195 Ω.
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Table 53: ACCDET_CONFIG_5 (Page 0: 0x000000CA)
Bit
Mode
Symbol
Description
Reset
7:0
R/W
B_C_BUTTON_THR Sets the impedance threshold between Button B
0x21
ESH
and Button C. If the measured impedance of a
button-press is lower than the threshold value
specified here, the button that was pressed is
Button B.
The value of this register field is a calculated value.
It is calculated as:
256 * Required threshold in Ω/(Required
threshold in Ω + MICBIAS resistance in Ω)
Example calculation:
Assuming that MICBIAS resistance = 2200 Ω and
the required threshold = 325 Ω, the bit value of this
register field = 256 * 325/(325 + 2200) = 33 [or
0x21].
So, in this example, setting this register field = 0x21
will give you a threshold value of 325 Ω.
Table 54: ACCDET_CONFIG_6 (Page 0: 0x000000CB)
Bit
Mode
Symbol
Description
Reset
7:0
R/W
C_MIC_BUTTON_T
HRESH
Sets the impedance threshold between Button C
and the microphone. If the measured impedance of
a button-press is lower than the threshold value
specified here, the button that was pressed is
Button C.
0x3E
The value of this register field is a calculated value.
It is calculated as:
256 * Required threshold in Ω/(Required
threshold in Ω + MICBIAS resistance in Ω)
Example calculation:
Assuming that MICBIAS resistance = 2200 Ω and
the required threshold = 688 Ω, the bit value of this
register field = 256 * 688/(688 + 2200) = 61 [or
0x3D].
So, in this example, setting this register field = 0x3D
will give you a threshold value of 688 Ω.
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Table 55: ACCDET_CONFIG_7 (Page 0: 0x000000CC)
Bit
Mode
Symbol
Description
Reset
5
R/W
jack_type_force
Specifies the Jack type when jack type detection is
disabled (jack_type_det_en is 0)
0x0
0 = 3-pole jack is specified
1 = 4-pole jack is specified
4
R/W
R/W
pin_order_force
Specifies the jack pin order for 4-Pole Jacks when
pin order detection is disabled (pin_order_det_en =
0)
0x0
0 = LRGM (CTIA format)
1 = LRMG (OMTP format)
3:2
adc_1_bit_repeat
Sets the number of repeated 1-bit measurements.
0x0
Repeating the 1-bit measurements multiple times
gives greater noise immunity but adds latency, and
possible distortion, during periodic button checking
00 = One 1-bit measurement (default)
01 = Two 1-bit measurements
10 = Four 1-bit measurements
11 = Eight 1-bit measurements
1:0
R/W
button_average
Sets the number of repeated 8-bit ADC
0x1
measurements used to generate an averaged result
Using more measurements for averaging will
increase button-checking noise immunity but also
increases the detection latency by about 1 ms per
measurement
00 = One 8-bit measurement (no averaging)
01 = Two 8-bit measurements used for averaging
(default)
10 = Four 8-bit measurements used for averaging
11 = Eight 8-bit measurements used for averaging
Table 56: ACCDET_CONFIG_8 (Page 0: 0x000000CD)
Bit
Mode
Symbol
Description
Reset
4
R
hptest_comp
HP TEST comparator result
0x0
1 = HP Impedance is < Threshold
0 = HP Impedance is > Threshold
2:1
R/W
R/W
hptest_res_sel
hptest_en
HP Impedance Test threshold control
0x1
0x0
00 - 1000 Ω
01 = 2500 Ω
10 = 5000 Ω
11 = 10000 Ω
0
Headphone Impedance test block control
0 = HP Impedance test block disabled
1 = HP Impedance test block enabled
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Table 57: Register map adc_filters_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x00000038
ADC_FILTER
S1
adc_voice_e
n
adc_hpf_en
Reserved
adc_audio_hpf_corner
adc_voice_hpf_corner
Table 58: ADC_FILTERS1 (Page 0: 0x00000038)
Bit
Mode
Symbol
Description
Reset
7
R/W
adc_hpf_en
ADC high pass filter control
0x1
0 = ADC high pass filter disabled
1 = ADC high pass filter enabled
5:4
R/W
adc_audio_hpf_corn
er
ADC high pass filter 3 dB cut-off point.
At 48 kHz, the cutoff point is at:
0x0
00 = 2 Hz
01 = 4 Hz
10 = 8 Hz
11 = 16 Hz
For other sample rates the 3 dB cuttoff point scales
proportionately
3
R/W
R/W
adc_voice_en
ADC voice filter control
0x0
0x0
0 = Voice filter disabled
1 = Voice filter enabled
2:0
adc_voice_hpf_corn
er
Voice (8 kHz) High pass 3 dB cutoff point
000 = 2.5 Hz
001 = 25 Hz
010 = 50 Hz
011 = 100 Hz
100 = 150 Hz
101 = 200 Hz
110 = 300 Hz
111 = 400 Hz
For other sample rates the 3 dB cuttoff point scales
proportionately
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Table 59: Register map alc_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x0000002F
ALC_CTRL1
alc_calib_ove alc_auto_cali
rflow b_en
alc_sync_mo
de
Reserved
alc_en
Reserved
alc_offset_en
0x0000009A
ALC_CTRL2
alc_release
alc_attack
0x0000009B
ALC_CTRL3
alc_integ_release
Reserved
alc_integ_attack
alc_hold
0x0000009C
ALC_NOISE
alc_noise
0x0000009D
ALC_TARGET
_MIN
Reserved
Reserved
alc_threshold_min
alc_threshold_max
0x0000009E
ALC_TARGET
_MAX
0x0000009F
ALC_GAIN_LI
MITS
alc_gain_max
alc_atten_max
0x000000A0
ALC_ANA_GA
IN_LIMITS
Reserved
alc_ana_gain_max
Reserved
alc_ana_gain_min
0x000000A1
ALC_ANTICLI
P_CTRL
alc_antipclip_
en
Reserved
alc_anticlip_step
0x000000A2
ALC_ANTICLI
P_LEVEL
Reserved
alc_anticlip_level
0x000000A3
ALC_OFFSET
_AUTO_M_L
alc_offset_auto_m_l
0x000000A4
ALC_OFFSET
_AUTO_U_L
Reserved
alc_offset_auto_u_l
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Table 60: ALC_CTRL1 (Page 0: 0x0000002F)
Bit
Mode
Symbol
Description
Reset
5
R
alc_calib_overflow
Indicates that an offset overflow occurred during
calibration
0x0
0 = No offset overflow
1 = Offset overflow occurred
4
R/W
alc_auto_calib_en
Automatic calibration control
0x0
0 = Automatic calibration not enabled
1 = Automatic calibration enabled
This is a self-clearing bit
3
1
R/W
R/W
alc_en
Controls the ALC operation on the left ADC channel 0x0
0 = ALC is disabled
1 = ALC is enabled
alc_sync_mode
ALC hybrid mode control. Hybrid mode uses both
analogue and digital gains.
0x0
0x0
0 = Hybrid mode is Off (digital gain only)
1 = Hybrid mode is On (digital and analogue gain)
0
R/W
alc_offset_en
DC Offset cancellation control
0 = DC Offset cancellation is disabled
1 = DC Offset cancellation is enabled
Table 61: ALC_CTRL2 (Page 0: 0x0000009A)
Bit
Mode
Symbol
Description
Reset
7:4
R/W
alc_release
Sets the ALC release rate. This is the speed at
which the ALC increases the gain.
0x0
0000 = 28.66/Fs (0.6 ms/dB @48 kHz)
0001 = 57.33/Fs (1.2 ms/dB @48 kHz)
0010 = 114.66/Fs (2.4 ms/dB @48 kHz)
then doubling at every step to...
1001 = 14674/Fs (306 ms/dB @48 kHz)
1010 to 1111 = 29348/Fs (611 ms/dB @48 kHz)
3:0
R/W
alc_attack
ALC attack rate control. This is the speed at which
the ALC reduces the gain.
0x0
0000 = 7.33/Fs (0.153 ms/dB @48 kHz)
0001 = 14.66/Fs (0.305 ms/dB @48 kHz)
0010 = 29.32/Fs (0.612 ms/dB @48 kHz)
then doubling at every step to...
1011 = 15012/Fs (312 ms/dB @48 kHz)
1100 to 1111 = 30024/Fs (625 ms/dB @48 kHz)
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Table 62: ALC_CTRL3 (Page 0: 0x0000009B)
Bit
Mode
Symbol
Description
Reset
7:6
R/W
alc_integ_release
Controls the rate at which the input signal envelope
is tracked as the signal gets smaller
0x0
00 = 1/4
01 = 1/16
10 = 1/256
11 = 1/65537
5:4
3:0
R/W
R/W
alc_integ_attack
Comtrols the rate at which the input signal envelope 0x0
is tracked as the signal gets larger
00 = 1/4
01 = 1/16
10 = 1/256
11 = 1/65537
alc_hold
ALC hold time control. This is the period the ALC
waits before releasing.
0x0
0000 = 62/Fs (1.3 ms @48 kHz)
0001 = 124/Fs (2.6 ms @48 kHz)
0010 = 248/Fs (5.2 ms @48 kHz)
then doubling at every step to…
1110 = 1015808/Fs (21 s @48 kHz)
1111 = 2031616/Fs (42 s @48 kHz)
Table 63: ALC_NOISE (Page 0: 0x0000009C)
Bit
Mode
Symbol
Description
Reset
5:0
R/W
alc_noise
Sets the threshold below which input signals will not 0x3F
cause the ALC to change gain
000000 = 0 dBFS
000001 = -1.5 dBFS
000010 = -3.0 dBFS
then continuing in -1.5 dBFS steps to…
111110 = -93.0 dBFS
111111 = -94.5 dBFS (default)
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Table 64: ALC_TARGET_MIN (Page 0: 0x0000009D)
Bit
Mode
Symbol
Description
Reset
5:0
R/W
alc_threshold_min
Sets the minimum amplitude of the ALC output
signal at which the ALC increases the gain. If the
minimum attenution level is reached, the ALC will
not increase the gain even if this threshold is
breached.
0x3F
000000 = 0 dBFS
000001 = -1.5 dBFS
000010 = -3.0 dBFS
then continuing in -1.5 dBFS steps to...
111110 = -93.0 dBFS
111111 = -94.5 dBFS (default)
Table 65: ALC_TARGET_MAX (Page 0: 0x0000009E)
Bit
Mode
Symbol
Description
Reset
5:0
R/W
alc_threshold_max
Sets the maximum amplitude of the ALC output
signal at which the ALC reduces the gain. If the
maximum attenution level is reached, the ALC will
not reduce the gain even if this threshold is
exceeded.
0x0
000000 = 0 dBFS
000001 = -1.5 dBFS
000010 = -3.0 dBFS
then continuing in -1.5 dBFS steps to...
111110 = -93.0 dBFS
111111 = -94.5 dBFS
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Table 66: ALC_GAIN_LIMITS (Page 0: 0x0000009F)
Bit
Mode
Symbol
Description
Reset
7:4
R/W
alc_gain_max
Sets the maximum amount of gain that can be
applied to the input signal by the ALC when the
input signal is large relative to the maximum
threshold
0xF
0000 = 0 dB
0001 = 6 dB
0010 = 12 dB
then continuing in 6 dB steps to…
1110 = 84 dB
1111 = 90 dB
3:0
R/W
alc_atten_max
Sets the maximum amount of attenuation that can
be applied to the input signal by the ALC when the
input signal is large relative to the maximum
threshold
0xF
0000 = 0 dB
0001 = 6 dB
0010 = 12 dB
then continuing in 6 dB steps to…
1110 = 84 dB
1111 = 90 dB
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Table 67: ALC_ANA_GAIN_LIMITS (Page 0: 0x000000A0)
Bit
Mode
Symbol
Description
Reset
6:4
R/W
alc_ana_gain_max
Sets the maximum amount of analogue gain that
can be applied to the input signal by the ALC when
the input signal is large relative to the maximum
threshold. This setting applies only to mixed
analogue and digital gain mode (alc_sync_mode =
1).
0x7
000 = reserved
001 = 0 dB
010 = 6 dB
011 = 12 dB
100 = 18 dB
101 = 24 dB
110 = 30 dB
111 = 36 dB
2:0
R/W
alc_ana_gain_min
Sets the minimum amount of analogue gain that
can be applied to the input signal by the ALC when
the input signal is large relative to the maximum
threshold. This setting applies only to mixed
analogue and digital gain mode (alc_sync_mode =
1).
0x1
000 = reserved
001 = 0 dB
010 = 6 dB
011 = 12 dB
100 = 18 dB
101 = 24 dB
110 = 30 dB
111 = 36 dB
Table 68: ALC_ANTICLIP_CTRL (Page 0: 0x000000A1)
Bit
Mode
Symbol
Description
Reset
7
R/W
alc_antipclip_en
Controls the ALC signal clip prevention mechanism
0x0
0 = Clip prevention is disabled
1 = Clip prevention is enabled
1:0
R/W
alc_anticlip_step
Sets the attack rate for the ALC when the output
signal exceeds the anticlip threshold level
0x0
00 = 0.034 dB/Fs
01 = 0.068 dB/Fs
10 = 0.136 dB/Fs
11 = 0.272 dB/Fs
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Table 69: ALC_ANTICLIP_LEVEL (Page 0: 0x000000A2)
Bit
Mode
Symbol
Description
Reset
6:0
R/W
alc_anticlip_level
ALC anticlip threshold control. The ALC anticlip
operates when signals are above this threshold.
0x0
The formula used to calculate the threshold value,
using 'x' to denote the decimal value of this bit field,
is:
x = ((x+1)/128) Fs
0x00 = 0.0078 Fs
0x01 = 0.0156 Fs
0x02 = 0.0234 Fs
then contnuing in aproximately 0.0078 steps to...
0x7E = 0.9922 Fs
0x7F = 1.0 Fs
Table 70: ALC_OFFSET_AUTO_M_L (Page 0: 0x000000A3)
Bit
Mode
Symbol
Description
Reset
7:0
R
alc_offset_auto_m_l
This read-only bit field contains the middle eight bits 0x0
(bits [15:8]) of the value used for automatic offset
correction
Table 71: ALC_OFFSET_AUTO_U_L (Page 0: 0x000000A4)
Bit
Mode
Symbol
Description
Reset
3:0
R
alc_offset_auto_u_l
This read-only bit field contains the upper four bits
(bits [19:16]) of the value used for automatic offset
correction
0x0
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Table 72: Register map analogue_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x00000006
MIC_1_GAIN_
STATUS
Reserved
mic_1_amp_gain_status
0x00000008
MIXIN_L_GAI
N_STATUS
Reserved
mixin_l_amp_gain_status
0x0000000A
ADC_L_GAIN
_STATUS
Reserved
Reserved
Reserved
adc_l_digital_gain_status
dac_l_digital_gain_status
dac_r_digital_gain_status
0x0000000C
DAC_L_GAIN
_STATUS
0x0000000D
DAC_R_GAIN
_STATUS
0x0000000E
HP_L_GAIN_
STATUS
Reserved
hp_l_amp_gain_status
0x0000000F
HP_R_GAIN_
STATUS
Reserved
hp_r_amp_gain_status
0x00000010
MIC_1_SELE
CT
Reserved
mic_1_amp_in_sel
0x00000032
REFERENCE
S
vmid_fast_ch
arge
Reserved
bias_en
Reserved
0x00000033
MIXIN_L_SEL
ECT
mixin_l_mix_
Reserved
select
0x00000034
MIXIN_L_GAI
N
Reserved
mixin_l_amp_gain
0x00000036
Reserved
adc_l_digital_gain
ADC_L_GAIN
0x00000039
MIC_1_GAIN
Reserved
mic_1_amp_gain
0x00000045
Reserved
Reserved
dac_l_digital_gain
dac_r_digital_gain
DAC_L_GAIN
0x00000046
DAC_R_GAIN
0x00000048
HP_L_GAIN
Reserved
hp_l_amp_gain
0x00000049
HP_R_GAIN
Reserved
hp_r_amp_gain
0x0000004B
MIXOUT_L_S
ELECT
mixout_l_mix
_select
Reserved
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Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x0000004C
MIXOUT_R_S
ELECT
mixout_r_mix
_select
Reserved
0x00000062
MICBIAS_CT
RL
Reserved
micbias1_en
micbias1_level
0x00000063
mic_1_amp_ mic_1_amp_ mic_1_amp_r
en mute_en amp_en
Reserved
MIC_1_CTRL
0x00000065
MIXIN_L_CTR
L
mixin_l_amp mixin_l_amp mixin_l_amp mixin_l_amp mixin_l_mix_
Reserved
_en
_mute_en
_ramp_en
_zc_en
en
0x00000067
adc_l_mute_ adc_l_ramp_
en en
adc_l_en
dac_l_en
dac_r_en
hp_l_amp_en
Reserved
Reserved
Reserved
ADC_L_CTRL
0x00000069
dac_l_mute_ dac_l_ramp_
en en
DAC_L_CTRL
0x0000006A
dac_r_mute_ dac_r_ramp_
en en
DAC_R_CTRL
0x0000006B
HP_L_CTRL
hp_l_amp_m hp_l_amp_ra hp_l_amp_zc
hp_l_amp_mi
n_gain_en
hp_l_amp_oe
Reserved
ute_en
mp_en
_en
0x0000006C
HP_R_CTRL
hp_r_amp_e hp_r_amp_m hp_r_amp_ra hp_r_amp_zc hp_r_amp_o hp_r_amp_m
Reserved
n
ute_en
mp_en
_en
e
in_gain_en
0x0000006E
MIXOUT_L_C
TRL
mixout_l_am
p_en
Reserved
0x0000006F
MIXOUT_R_C
TRL
mixout_r_am
p_en
Reserved
0x00000091
IO_CTRL
io_voltage_le
Reserved
vel
Table 73: MIC_1_GAIN_STATUS (Page 0: 0x00000006)
Bit
Mode
Symbol
Description
Reset
2:0
R
mic_1_amp_gain_st
atus
Contains the currently active mic_1_amp gain
setting
0x1
000 = -6 dB
001 = 0 dB
010 = 6 dB
011 = 12 dB
100 = 18 dB
101 = 24 dB
110 = 30 dB
111 = 36 dB
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Table 74: MIXIN_L_GAIN_STATUS (Page 0: 0x00000008)
Bit
Mode
Symbol
Description
Reset
3:0
R
mixin_l_amp_gain_st Contains the currently active mixin_l_amp gain
0x0
atus
setting
0000 = -4.5 dB
0001 = -3.0 dB
0010 = -1.5 dB
0011 = 0.0 dB
then continuing in 1.5 dB steps to…
1110 = 16.5 dB
1111 = 18.0 dB
Table 75: ADC_L_GAIN_STATUS (Page 0: 0x0000000A)
Bit
Mode
Symbol
Description
Reset
6:0
R
adc_l_digital_gain_st Contains the currently active ADC_L digital gain
0x0
atus
setting
0x00 = -83.25 dB
0x01 = -82.5 dB
then continuing in 0.75 dB steps through
0x6F = 0 dB
to...
0x7E = 11.25 dB
0x7F = 12 dB
Table 76: DAC_L_GAIN_STATUS (Page 0: 0x0000000C)
Bit
Mode
Symbol
Description
Reset
6:0
R
dac_l_digital_gain_st Contains the currently active DAC_L digital gain
0x0
atus
setting
0x00 to 0x07 = mute
0x08 = -77.25 dB
0x09 = -76.5 dB
then continuing in 0.75 dB steps through
0x6F = 0 dB
to...
0x7E = 11.25 dB
0x7F = 12 dB
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Table 77: DAC_R_GAIN_STATUS (Page 0: 0x0000000D)
Bit
Mode
Symbol
Description
Reset
6:0
R
dac_r_digital_gain_st Contains the currently active DAC_R digital gain
0x0
atus
setting
0x00 to 0x07 = mute
0x08 = -77.25 dB
0x09 = -76.5 dB
then continuing in 0.75 dB steps through
0x6F = 0 dB
to...
0x7E = 11.25 dB
0x7F = 12 dB
Table 78: HP_L_GAIN_STATUS (Page 0: 0x0000000E)
Bit
Mode
Symbol
Description
Reset
5:0
R
hp_l_amp_gain_stat
us
Contains the currently active HP_L_AMP gain
setting
0x0
000000 = -57.0 dB
000001 = -56.0 dB
000010 = -55.0 dB
then continuing in 1 dB steps to…
111001 = 0.0 dB
111111 = 6.0 dB
Table 79: HP_R_GAIN_STATUS (Page 0: 0x0000000F)
Bit
Mode
Symbol
Description
Reset
5:0
R
hp_r_amp_gain_stat
us
Contains the currently active HP_R_AMP gain
setting
0x0
000000 = -57.0 dB
000001 = -56.0 dB
000010 = -55.0 dB
then continuing in 1 dB steps to…
111001 = 0.0 dB
111111 = 6.0 dB
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Table 80: MIC_1_SELECT (Page 0: 0x00000010)
Bit
Mode
Symbol
Description
Reset
1:0
R/W
mic_1_amp_in_sel
MIC_1 input source control
0x0
00 = Differential
01 = MIC_1_P single-ended
10 = MIC_1_N single-ended
11 = Reserved
Table 81: REFERENCES (Page 0: 0x00000032)
Bit
Mode
Symbol
Description
Reset
4
R/W
vmid_fast_charge
VMID reference fast charge control
0x0
0 = low noise, slow charge mode
1 = high noise, fast charge mode
3
R/W
bias_en
Master Bias control.
0x1
Master Bias is required for analogue circuitry.
0 = Master Bias disabled
1 = Master Bias enabled
Table 82: MIXIN_L_SELECT (Page 0: 0x00000033)
Bit
Mode
Symbol
Description
Reset
0
R/W
mixin_l_mix_select
MIXIN_L mixer input control
0x0
0 = No input selected
1 = MIC_1 selected as input
Table 83: MIXIN_L_GAIN (Page 0: 0x00000034)
Bit
Mode
Symbol
Description
Reset
3:0
R/W
mixin_l_amp_gain
mixin_l_amp gain control
0x3
0000 = -4.5 dB
0001 = -3.0 dB
0010 = -1.5 dB
0011 = 0.0 dB
then continuing in 1.5 dB steps to…
1110 = 16.5 dB
1111 = 18.0 dB
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Table 84: ADC_L_GAIN (Page 0: 0x00000036)
Bit
Mode
Symbol
Description
Reset
6:0
R/W
adc_l_digital_gain
ADC_L digital gain control
0x6F
00x0 = -83.25 dB
0x01 = -82.5 dB
then continuing in 0.75 dB steps through
0x6F = 0 dB
to...
0x7E = 11.25 dB
0x7F = 12 dB
Table 85: MIC_1_GAIN (Page 0: 0x00000039)
Bit
Mode
Symbol
Description
Reset
2:0
R/W
mic_1_amp_gain
mic_1_amp gain control
0x1
000 = -6 dB
001 = 0 dB
010 = 6 dB
011 = 12 dB
100 = 18 dB
101 = 24 dB
110 = 30 dB
111 = 36 dB
Table 86: DAC_L_GAIN (Page 0: 0x00000045)
Bit
Mode
Symbol
Description
Reset
6:0
R/W
dac_l_digital_gain
DAC_L digital gain control
0x6F
0x00 to 0x07 = mute
0x08 = -77.25 dB
0x09 = -76.5 dB
then continuing in 0.75 dB steps through
0x6F = 0 dB
to...
0x7E = 11.25 dB
0x7F = 12 dB
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Table 87: DAC_R_GAIN (Page 0: 0x00000046)
Bit
Mode
Symbol
Description
Reset
6:0
R/W
dac_r_digital_gain
DAC_R digital gain control
0x6F
0x00 to 0x07 = mute
0x08 = -77.25 dB
0x09 = -76.5 dB
then continuing in 0.75 dB steps through
0x6F = 0 dB
to...
0x7E = 11.25 dB
0x7F = 12 dB
Table 88: HP_L_GAIN (Page 0: 0x00000048)
Bit
Mode
Symbol
Description
Reset
5:0
R/W
hp_l_amp_gain
HP_L_AMP gain control
0x39
000000 = -57.0 dB
000001 = -56.0 dB
000010 = -55.0 dB
then continuing in 1 dB steps through…
111001 = 0.0 dB
to…
111111 = 6.0 dB
Table 89: HP_R_GAIN (Page 0: 0x00000049)
Bit
Mode
Symbol
Description
Reset
5:0
R/W
hp_r_amp_gain
HP_R_AMP gain control
0x39
000000 = -57.0 dB
000001 = -56.0 dB
000010 = -55.0 dB
then continuing in 1 dB steps through…
111001 = 0.0 dB
to…
111111 = 6.0 dB
Table 90: MIXOUT_L_SELECT (Page 0: 0x0000004B)
Bit
Mode
Symbol
Description
Reset
0
R/W
mixout_l_mix_select
Output left mixer channel selection
0x0
0 = No channel selected
1 = DAC_L selected as output
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Table 91: MIXOUT_R_SELECT (Page 0: 0x0000004C)
Bit
Mode
Symbol
Description
Reset
0
R/W
mixout_r_mix_select
Ouput right mixer channel selection
0x0
0 = No channel selected
1 = DAC_R selected as output
Table 92: MICBIAS_CTRL (Page 0: 0x00000062)
Bit
Mode
Symbol
Description
Reset
3
R/W
micbias1_en
Microphone Bias 1 control
0x0
0 = Micbias1 disabled
1 = Micbias1 enabled
2:0
R/W
micbias1_level
Microphone Bias 1 level control
0x3
000 = 1.6 V
001 = 1.8 V
010 = 2.0 V
011 = 2.2 V
100 = 2.4 V
101 = 2.6 V
110 = 2.8 V
111 = 2.9 V
This must only be modified while micbias_1 is
disabled (micbias1_en = 0)
Table 93: MIC_1_CTRL (Page 0: 0x00000063)
Bit
Mode
Symbol
Description
Reset
7
R/W
mic_1_amp_en
MIC_1 amplifier control
0x0
0 = MIC_1 disabled
1 = MIC_1 enabled
6
5
R/W
-
mic_1_amp_mute_e
n
MIC_1 amplifier mute control
0x1
0x0
0 = MIC_1 unmuted
1 = MIC_1 muted
mic_1_amp_ramp_e
n
MIC_1 amplifier gain ramping control
0 = Gain changes are instant
1 = Gain changes are ramped to the new level
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Table 94: MIXIN_L_CTRL (Page 0: 0x00000065)
Bit
Mode
Symbol
Description
Reset
7
R/W
mixin_l_amp_en
MIXIN_L amplifier control
0x0
0 = MIXIN_L disabled
1 = MIXIN_L enabled
6
5
R/W
R/W
mixin_l_amp_mute_
en
MIXIN_L amplifier mute control
0x1
0 = MIXIN_L unmuted
1 = MIXIN_L muted
mixin_l_amp_ramp_
en
MIXIN_L amplifier gain ramping control
0x0
0x0
0 = Gain changes are instant
1 = Gain changes are ramped to the new level
This setting overrides zero crossing
MIXIN_L amplifier zero cross control
4
R/W
mixin_l_amp_zc_en
0 = Gain changes are instant
1 = Gain changes are performed when the signal
crosses zero
If no zero-crossing is detected within the timeout
period of approximately 100 ms, the update is
applied unconditionally
3
R/W
mixin_l_mix_en
MIXIN_L mixer control. When this mixer is disabled, 0x0
all inputs are deselected.
0 = Mixer disabled
1 = Mixer enabled
Table 95: ADC_L_CTRL (Page 0: 0x00000067)
Bit
Mode
Symbol
Description
Reset
7
R/W
adc_l_en
ADC_L control
0x0
0 = ADC_L disabled
1 = ADC_L enabled
6
5
R/W
R/W
adc_l_mute_en
adc_l_ramp_en
ADC_L mute control
0x1
0x0
0 = ADC_L unmuted
1 = ADC_L muted
ADC_L digital gain ramping control
0 = Gain changes are instant
1 = Gain changes are ramped to the new level
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Table 96: DAC_L_CTRL (Page 0: 0x00000069)
Bit
Mode
Symbol
Description
Reset
7
R/W
dac_l_en
DAC_L control
0x0
0 = DAC_L disabled
1 = DAC_L enabled
6
5
R/W
R/W
dac_l_mute_en
dac_l_ramp_en
DAC_L mute control
0x1
0 = DAC_L unmuted
1 = DAC_L muted
DAC_L digital gain ramping control
0x0
0 = Gain changes are instant
1 = Gain changes are ramped to the new level
Table 97: DAC_R_CTRL (Page 0: 0x0000006A)
Bit
Mode
Symbol
Description
Reset
7
R/W
dac_r_en
DAC_R control
0x0
0 = DAC_R disabled
1 = DAC_R enabled
6
5
R/W
R/W
dac_r_mute_en
dac_r_ramp_en
DAC_R mute control
0x1
0x0
0 = DAC_R unmuted
1 = DAC_R muted
DAC_R digital gain ramping control
0 = Gain changes are instant
1 = Gain changes are ramped to the new level
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Table 98: HP_L_CTRL (Page 0: 0x0000006B)
Bit
Mode
Symbol
Description
Reset
7
R/W
hp_l_amp_en
HP_L_AMP amplifier control
0x0
0 = HP_L_AMP disabled
1 = HP_L_AMP enabled
6
5
R/W
R/W
hp_l_amp_mute_en
hp_l_amp_ramp_en
HP_L_AMP amplifier mute control
0x1
0x0
0 = HP_L_AMP unmuted
1 = HP_L_AMP muted
HP_L_AMP amplifier gain ramping control
0 = Gain changes are instant
1 = Gain changes are ramped to the new level
This setting overrides zero crossing
4
R/W
hp_l_amp_zc_en
HP_L_AMP amplifier zero cross control
0x0
0 = Gain changes are instant
1 = Gain changes are performed when the signal
crosses zero
If no zero-crossing is detected within the timeout
period of approximately 100 ms, the update is
applied unconditionally
3
2
R/W
R/W
hp_l_amp_oe
HP_L_AMP amplifier output control
0x0
0x0
0 = Output is high-impedance
1 = Output is driven
hp_l_amp_min_gain
_en
HP_L_AMP amplifier minimum gain control.
0 = Normal gain operation
1 = Minimum gain only. HP_L amplifier is held at
minimum gain regardless of other gain settings
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Table 99: HP_R_CTRL (Page 0: 0x0000006C)
Bit
Mode
Symbol
Description
Reset
7
R/W
hp_r_amp_en
HP_R_AMP amplifier control
0x0
0 = HP_R_AMP disabled
1 = HP_R_AMP enabled
6
5
R/W
R/W
hp_r_amp_mute_en
hp_r_amp_ramp_en
HP_R_AMP amplifier mute control
0x1
0x0
0 = HP_R_AMP unmuted
1 = HP_R_AMP muted
HP_R_AMP amplifier gain ramping control
0 = Gain changes are instant
1 = Gain changes are ramped to the new level
This setting overrides zero crossing
4
R/W
hp_r_amp_zc_en
HP_R_AMP amplifier zero cross control
0x0
0 = Gain changes are instant
1 = Gain changes are performed when the signal
crosses zero
If no zero-crossing is detected within the timeout
period of approximately 100 ms, the update is
applied unconditionally
3
2
R/W
R/W
hp_r_amp_oe
HP_R_AMP amplifier output control
0x0
0x0
0 = Output is high-impedance
1 = Output is driven
hp_r_amp_min_gain
_en
HP_R_AMP amplifier minimum gain control.
0 = Normal gain operation
1 = Minimum gain only. HP_R_AMP is held at
minimum gain regardless of other gain settings
Table 100: MIXOUT_L_CTRL (Page 0: 0x0000006E)
Bit
Mode
Symbol
Description
Reset
7
R/W
mixout_l_amp_en
MIXIN_L amplifier control
0x0
0 = Mixer disabled
1 = Mixer enabled
Table 101: MIXOUT_R_CTRL (Page 0: 0x0000006F)
Bit
Mode
Symbol
Description
Reset
7
R/W
mixout_r_amp_en
MIXIN_R amplifier control
0x0
0 = Mixer disabled
1 = Mixer enabled
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Table 102: IO_CTRL (Page 0: 0x00000091)
Bit
Mode
Symbol
Description
Reset
0
R/W
io_voltage_level
Digital I/O voltage range control
0x0
0 = 2.5 to 3.6 V
1 = 1.2 to 2.8 V
Table 103: Register map charge_pump_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x00000047
CP_CTRL
cp_en
Reserved
cp_mchange
Reserved
0x00000095
CP_VOL_THR
ESHOLD1
Reserved
cp_thresh_vdd2
Table 104: CP_CTRL (Page 0: 0x00000047)
Bit
Mode
Symbol
Description
Reset
7
R/W
cp_en
Chargepump control
0x0
0 = Chargepump disabled
1 = Chargepump enabled
5:4
R/W
cp_mchange
Charge pump tracking mode control
00 = Reserved
0x2
01 = Voltage level is controlled by the largest output
volume level
10 = Voltage level is controlled by the DAC volume
level
11 = Voltage level is controlled by the signal
magnitude
Table 105: CP_VOL_THRESHOLD1 (Page 0: 0x00000095)
Bit
Mode
Symbol
Description
Reset
5:0
R/W
cp_thresh_vdd2
Threshold at and below which the charge pump can 0xE
use the CPVDD/2 rail.
This setting is only effective when cp_mchange =
10 or cp_mchange = 11. It is ignored for
cp_mchange settings of 00 and 01
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Table 106: Register map cif_i2c_addr_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x0000001B
CIF_I2C_ADD
R_CFG
Reserved
cif_i2c_addr_cfg
Table 107: CIF_I2C_ADDR_CFG (Page 0: 0x0000001B)
Bit
Mode
Symbol
Description
I2C address [1:0] configuration
Reset
0x2
1:0
R/W
cif_i2c_addr_cfg
This allows multiple DA7219 devices to reside on
the same bus by allowing the least significant two
bits to be written to a specific value. The I2C clock
must be externally controlled while writing this
register to ensure that only the target DA7219
device's I2C address is modified.
Table 108: Register map common1_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x00000012
CIF_TIMEOUT
_CTRL
i2c_timeout_
en
Reserved
0x00000013
CIF_CTRL
cif_reg_soft_r
eset
cif_i2c_write_
mode
Reserved
0x00000016
SR_24_48
Reserved
sr_24_48
0x00000017
SR
Reserved
sr
0x00000092
GAIN_RAMP_
CTRL
Reserved
gain_ramp_rate
0x00000094
PC_COUNT
pc_resync_a
uto
Reserved
pc_freerun
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Table 109: CIF_TIMEOUT_CTRL (Page 0: 0x00000012)
Bit
Mode
Symbol
Description
Reset
0
R/W
i2c_timeout_en
I2C (2-wire) timeout control.
0x0
The timeout period is approximately 43.9 ms.
0 = Timeout disabled
1 = Timeout enabled
Table 110: CIF_CTRL (Page 0: 0x00000013)
Bit
Mode
Symbol
Description
Reset
7
R/W
cif_reg_soft_reset
Software reset which returns all the registers back
to their default values. Writing to this bit causes all
the registers to reset.
0x0
0 = No reset
1 = Reset all registers to their default values
0
R/W
cif_i2c_write_mode
I2C (2-wire) interface write mode control
0x0
0 = Page mode. The register address is
autoincremented after the first write.
1 = Repeat mode. The register address and data
are sent for each write.
Table 111: SR_24_48 (Page 0: 0x00000016)
Bit
Mode
Symbol
Description
Reset
0
R/W
sr_24_48
24_48_mode control.
0x0
Setting this bit runs the ADC and the DAC paths at
different speeds.
0 = The ADC path and the DAC path both run at the
same speed. This speed is determined by the
setting of the sr bit in this register
1 = The ADC path runs at 24 kHz, and the DAC
path and the rest of the system run at 48 KHz
To use this mode, the system sample rate sr must
be set to 48 kHz. Therefore the I2S will also run at
48 kHz and the 24 kHz ADC output will be double
sampled.
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Table 112: SR (Page 0: 0x00000017)
Bit
Mode
Symbol
Description
Reset
3:0
R/W
sr
Sample rate control:
0001 = 8.000 kHz
0010 = 11.025 kHz
0011 = 12.000 kHz
0101 = 16.000 kHz
0110 = 22.050 kHz
0111 = 24.000 kHz
1001 = 32.000 kHz
1010 = 44.100 kHz
1011 = 48.000 kHz
1110 = 88.200 kHz
1111 = 96.000 kHz
0xA
Table 113: GAIN_RAMP_CTRL (Page 0: 0x00000092)
Bit
Mode
Symbol
Description
Reset
1:0
R/W
gain_ramp_rate
Controls the speed of the gain ramping when
ramping is activated
0x0
0 = nominal rate * 8
1 = nominal rate
2 = nominal rate / 8
3 = nominal rate / 16 (slowest)
The nominal rate (excluding headphone circuits) =
0.88 ms/dB. The nominal rate for the headphone
circuits is = 1.3 ms/dB.
Table 114: PC_COUNT (Page 0: 0x00000094)
Bit
Mode
Symbol
Description
Reset
1
R/W
pc_resync_auto
Program Counter resynchronisation control
0x1
0 = No resynchronisation. If the DAI drifts with
respect to the system clocks, either a sample is
skipped or it is double-sampled
1 = Automatic resynchronisation if the DAI drifts
with respect to the system clock
0
R/W
pc_freerun
Controls the filter operation when the DAI is not
enabled or when no DAI clocks are available on the
ADC to DAC processing path
0x0
0 = Filters are synchronised to the DAI
1 = Filters are free running
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Table 115: Register map common2_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x00000081
CHIP_ID1
chip_id1
chip_id2
0x00000082
CHIP_ID2
0x00000083
CHIP_REVISI
ON
chip_major
chip_minor
Table 116: CHIP_ID1 (Page 0: 0x00000081)
Bit
Mode
Symbol
Description
Reset
7:0
R
chip_id1
First two digits of the four-digit Chip ID
0x23
The last two numbers of the Chip ID are held in
chip_id2
Table 117: CHIP_ID2 (Page 0: 0x00000082)
Bit
Mode
Symbol
Description
Reset
7:0
R
chip_id2
Last two digits of the four-digit Chip ID
The first two numbers of the Chip ID are held in
chip_id1
0x93
Table 118: CHIP_REVISION (Page 0: 0x00000083)
Bit
7:4
3:0
Mode
Symbol
Description
Reset
0x0
R
R
chip_major
chip_minor
Chip major revision
Chip minor revision
0x1
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Table 119: Register map dac_filters_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x00000040
DAC_FILTER
S5
dac_softmute
_en
dac_softmute_rate
Reserved
0x00000041
DAC_FILTER
S2
dac_eq_band2
dac_eq_band1
dac_eq_band3
dac_eq_band5
0x00000042
DAC_FILTER
S3
dac_eq_band4
0x00000043
DAC_FILTER
S4
dac_eq_en
dac_hpf_en
Reserved
0x00000044
DAC_FILTER
S1
dac_voice_e
n
Reserved
dac_audio_hpf_corner
dac_voice_hpf_corner
Table 120: DAC_FILTERS5 (Page 0: 0x00000040)
Bit
Mode
Symbol
Description
Reset
7
R/W
dac_softmute_en
DAC softmute control. When this bit is set, both
channels are soft-muted.
0x0
0 = Soft-mute disabled
1 = Soft-mute enabled
6:4
R/W
dac_softmute_rate
Softmute gain update control
0x0
000 = 1 sample per 0.1875 dB
001 = 2 samples per 0.1875 dB
010 = 4 samples per 0.1875 dB
011 = 8 samples per 0.1875 dB
100 = 16 samples per 0.1875 dB
101 = 32 samples per 0.1875 dB
110 = 64 samples per 0.1875 dB
111 = Reserved
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Table 121: DAC_FILTERS2 (Page 0: 0x00000041)
Bit
Mode
Symbol
Description
Reset
7:4
R/W
dac_eq_band2
Gain control of Band 2 in the 5-band EQ
0x8
0000 = -10.5 dB
0001 = -9.0 dB
0010 = -7.5 dB
Continuing in 1.5 dB steps through
0111 = 0 dB
to…
1110 = 10.5 dB
1111 = 12 dB
3:0
R/W
dac_eq_band1
Gain control of Band 1 in the 5-band EQ
0x8
0000 = -10.5 dB
0001 = -9.0 dB
0010 = -7.5 dB
Continuing in 1.5 dB steps through
0111 = 0 dB
to…
1110 = 10.5 dB
1111 = 12 dB
Table 122: DAC_FILTERS3 (Page 0: 0x00000042)
Bit
Mode
Symbol
Description
Reset
7:4
R/W
dac_eq_band4
Gain control of Band 4 in the 5-band EQ
0x8
0000 = -10.5 dB in 1.5 dB steps
0001 = -9.0 dB
0010 = -7.5 dB
Continuing in 1.5 dB steps through
0111 = 0 dB
to…
1110 = 10.5 dB
1111 = 12 dB
3:0
R/W
dac_eq_band3
Gain control of Band 3 in the 5-band EQ
0x8
0000 = -10.5 dB
0001 = -9.0 dB
0010 = -7.5 dB
Continuing in 1.5 dB steps through
0111 = 0 dB
to…
1110 = 10.5 dB
1111 = 12 dB
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Table 123: DAC_FILTERS4 (Page 0: 0x00000043)
Bit
Mode
Symbol
Description
Reset
7
R/W
dac_eq_en
DAC 5-band EQ control
0x0
0 = Equaliser disabled
1 = Equaliser enabled
3:0
R/W
dac_eq_band5
Gain control of Band 5 in the 5-band EQ
0x8
0000 = -10.5 dB
0001 = -9.0 dB
0010 = -7.5 dB
Continuing in 1.5 dB steps through
0111 = 0 dB
to…
1110 = 10.5 dB
1111 = 12 dB
Table 124: DAC_FILTERS1 (Page 0: 0x00000044)
Bit
Mode
Symbol
Description
Reset
7
R/W
dac_hpf_en
DAC High Pass Filter control
0x1
0 = High Pass Filter disabled
1 = High Pass Filter enabled
5:4
R/W
R/W
R/W
dac_audio_hpf_corn
er
High Pass Filter 3 dB cutoff control.
At 48 kHz, the 3 dB cutoff point is at:
0x0
0x0
0x0
00 = 2 Hz
01 = 4 Hz
10 = 8 Hz
11 = 16 Hz
For other sample rates, the corner cutoff point
scales proportionately.
3
dac_voice_en
DAC Voice Filter control : For 8/11.025/12/16 kHz
sample rates and for best performance should
always be enabled when running at one these
rates.
0 = DAC Voice Filter disabled
1 = DAC Voice Filter enabled
This DAC Voice Filter control overrides the 5-band
EQ setting in dac_eq_en
2:0
dac_voice_hpf_corn
er
Voice Filter 3 dB cutoff control.
At 8 kHz, the 3 dB cutoff point is at:
000 = 2.5 Hz
001 = 25 Hz,
010 = 50 Hz
011 = 100 Hz
100 = 150 Hz
101 = 200 Hz
110 = 275 Hz
111 = 363 Hz
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Table 125: Register map dac_ng_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x000000AF
DAC_NG_SET
UP_TIME
dac_ng_ram dac_ng_ram
pdn_rate pup_rate
Reserved
dac_ng_setup_time
0x000000B0
DAC_NG_OF
F_THRESH
Reserved
Reserved
dac_ng_off_threshold
0x000000B1
DAC_NG_ON
_THRESH
dac_ng_on_threshold
0x000000B2
DAC_NG_CT
RL
dac_ng_en
Reserved
Table 126: DAC_NG_SETUP_TIME (Page 0: 0x000000AF)
Bit
Mode
Symbol
Description
Reset
3
R/W
dac_ng_rampdn_rat
e
DAC Noise Gate ramp down control
0x0
0 = 0.88 ms/dB
1 = 14.08 ms/dB
2
R/W
R/W
dac_ng_rampup_rat
e
DAC Noise Gate ramp up control
0x0
0x0
0 = 0.22 ms/dB
1 = 0.0138 ms/dB
1:0
dac_ng_setup_time
Noise Gate timing control
This specifies the number of samples for which the
largest signal through the DACs must be above (or
below) dac_ng_off _threshold (or
dac_ng_on_threshold) for the Noise Gate to
unmute (or mute) the data
00 = 256 samples
01 = 512 samples
10 = 1024 samples
11 = 2048 samples
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Table 127: DAC_NG_OFF_THRESH (Page 0: 0x000000B0)
Bit
Mode
Symbol
Description
Reset
2:0
R/W
dac_ng_off_threshol
d
Threshold above which the Noise Gate is
deactivated. If the signal rises above this level, the
Noise Gate is deactivated.
0x0
000 = -102 dB
001 = -96 dB
010 = -90 dB
011 = -84 dB
100 = -78 dB
101 = -72 dB
110 = -66 dB
111 = -60 dB
Table 128: DAC_NG_ON_THRESH (Page 0: 0x000000B1)
Bit
Mode
Symbol
Description
Reset
2:0
R/W
dac_ng_on_threshol
d
Threshold below which the Noise Gate is
dactivated. If the signal drops below this level for
dac_ng_setup_time samples, the Noise Gate is
activated.
0x0
000 = -102 dB
001 = -96 dB
010 = -90 dB
011 = -84 dB
100 = -78 dB
101 = -72 dB
110 = -66 dB
111 = -60 dB
Table 129: DAC_NG_CTRL (Page 0: 0x000000B2)
Bit
Mode
Symbol
Description
Reset
7
R/W
dac_ng_en
DAC Noise Gate control
0x0
0 = Noise Gate is disabled
1 = Noise Gate is enabled
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Table 130: Register map dai_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x0000002B
DAI_CLK_MO
DE
dai_wclk_tri_
state
dai_clk_en
dai_en
Reserved
dai_wclk_pol
dai_clk_pol
dai_bclks_per_wclk
dai_format
0x0000002C
DAI_CTRL
Reserved
dai_oe
dai_ch_num
dai_word_length
0x0000002D
DAI_TDM_CT
RL
dai_tdm_mod
e_en
Reserved
dai_tdm_ch_en
0x00000030
DAI_OFFSET
_LOWER
dai_offset_lower
0x00000031
DAI_OFFSET
_UPPER
Reserved
dai_offset_upper
Table 131: DAI_CLK_MODE (Page 0: 0x0000002B)
Bit
Mode
Symbol
Description
Reset
7
R/W
dai_clk_en
DAI Master mode control
0x0
0 = Slave mode (BCLK/WCLK inputs)
1 = Master mode (BCLK/WCLK outputs)
4
R/W
dai_wclk_tri_state
WLCK tri-state control
0x0
0 = WCLK state is set by dai_clk_en. WCLK is set
as output in master mode, and as input in slave
mode
1 = WCLK forced as an input
3
R/W
R/W
R/W
dai_wclk_pol
DAI word clock polarity control
0x0
0x0
0x1
0 = Normal polarity
1 = Inverted polarity
2
dai_clk_pol
DAI bit clock polarity control
0 = Normal polarity
1 = Inverted polarity
1:0
dai_bclks_per_wclk
Number of BCLKs per WCLK period when in DAI
Master mode
00 = 32 BCLKS per WCLK
01 = 64 BCLKS per WCLK
10 = 128 BCLKS per WCLK
11 = 256 BCLKS per WCLK
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Table 132: DAI_CTRL (Page 0: 0x0000002C)
Bit
Mode
Symbol
Description
Reset
7
R/W
dai_en
DAI control
0x0
0 = DAI disabled. No data is transferred.
1 = DAI enabled. Input and output data streams are
transferred
5:4
3:2
1:0
R/W
R/W
R/W
dai_ch_num
dai_word_length
dai_format
Channel control
0x2
0x2
0x0
00 = No channels are enabled
01 = Left channel is enabled
10 = Left and right channels are enabled
11 = Reserved
DAI data word length control
0 = 16 bits per channel
1 = 20 bits per channel
2 = 24 bits per channel
3 = 32 bits per channel
DAI data format
00 = I2S mode
01 = Left justified mode
10 = Right justified mode
11 = DSP mode
Table 133: DAI_TDM_CTRL (Page 0: 0x0000002D)
Bit
Mode
Symbol
Description
Reset
7
R/W
dai_tdm_mode_en
DAI TDM mode control.
0x0
In TDM mode, the output is high impedence when
not actively driving data as this allows other devices
to share the DATOUT line.
0 = DAI normal mode
1 = DAI TDM mode
6
R/W
R/W
dai_oe
DAI output control
0x1
0x0
0 = DAI DATOUT pin is high impedence
1 = DAI DATOUT pin is driven when required
1:0
dai_tdm_ch_en
DAI TDM channel control.
Bit 0 = Left channel; Bit 1: Riight channel.
For each bit, 0 = Disabled; 1 = Enabled.
00 = Left channel and right channel both disabled
01 = Left channel enabled, right channel disabled
10 = Left channel disabled, right channel enabled
11 = Left channel and right channel both enabled
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Table 134: DAI_OFFSET_LOWER (Page 0: 0x00000030)
Bit
Mode
Symbol
Description
Reset
7:0
R/W
dai_offset_lower
DAI data offset with respect to WCLK measured in
BCLK periods.
0x0
The total offset is determined by an 11-bit binary
number formed by a combination of this register
(dai_offset_lower) and dai_offset_upper.
With the maximum BCLK frequency of 6 MHz, the
maximum number of BCLK periods is 768. The
maximum DAI offset value is therefore 767 (0x2FF),
represented by dai_offset_lower = 1111 1111, and
dai_offset_upper = 010.
0x000 = No offset relative to the normal formatting
0x001 = One BCLK period offset relative to the
normal formatting
0x002 = Two BCLK periods offset relative to the
normal formatting
0xn = n BCLK periods offset relative to the normal
formatting (max = 0x2FF)
Table 135: DAI_OFFSET_UPPER (Page 0: 0x00000031)
Bit
Mode
Symbol
Description
Reset
2:0
R/W
dai_offset_upper
DAI data offset with respect to WCLK measured in
BCLK periods.
0x0
The total offset is determined by an 11-bit binary
number formed by a combination of
dai_offset_lower and this register
(dai_offset_upper).
With the maximum BCLK frequency of 6 MHz, the
maximum number of BCLK periods is 768. The
maximum DAI offset value is therefore 767 (0x2FF),
represented by dai_offset_lower = 1111 1111, and
dai_offset_upper = 010.
0x000 = No offset relative to the normal formatting
0x001 = One BCLK period offset relative to the
normal formatting
0x002 = Two BCLK periods offset relative to the
normal formatting
0xn = n BCLK periods offset relative to the normal
formatting (max = 0x2FF)
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Table 136: Register map pll_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x00000020
PLL_CTRL
pll_mclk_sqr
_en
pll_mode
pll_indiv
Reserved
0x00000022
PLL_FRAC_T
OP
Reserved
pll_fbdiv_frac_top
0x00000023
PLL_FRAC_B
OT
pll_fbdiv_frac_bot
0x00000024
PLL_INTEGE
R
Reserved
pll_fbdiv_integer
0x00000025
PLL_SRM_ST
S
pll_srm_status
Reserved
Table 137: PLL_CTRL (Page 0: 0x00000020)
Bit
Mode
Symbol
Description
PLL mode control
Reset
7:6
R/W
pll_mode
0x0
00 = Bypass mode. The PLL is disabled, and the
system clock is MCLK (after input divider)
01 = Normal mode.The PLL is enabled, and the
system clock is a fixed multiple of MCLK
10 = SRM. The PLL is enabled, and the system
clock tracks WCLK
11 = Reserved
5
R/W
R/W
pll_mclk_sqr_en
pll_indiv
PLL clock squarer control.
0x0
0x4
0 = Clock squarer is disabled
1 = Clock squarer is enabled
4:2
PLL reference input clock (MCLK) control
0 = 2 to 4.5 MHz
1 = 4.5 to 9 MHz
2 = 9 to 18 MHz
3 = 18 to 36 MHz
4 = 36+ MHz
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Table 138: PLL_FRAC_TOP (Page 0: 0x00000022)
Bit
Mode
Symbol
Description
Reset
4:0
R/W
pll_fbdiv_frac_top
PLL fractional division value (top bits).
The full PLL fractional division value is a
concatenation of these bits (MSB) and
PLL_FBDIV_FRAC_BOT (LSB).
0x0
The value in this register does not take effect until
pll_fbdiv_integer is written.
Table 139: PLL_FRAC_BOT (Page 0: 0x00000023)
Bit
Mode
Symbol
Description
Reset
7:0
R/W
pll_fbdiv_frac_bot
PLL fractional division value (bottom bits).
The full PLL fractional division value is a
concatenation of PLL_FBDIV_FRAC_TOP (MSB)
and these bits (LSB).
0x0
The value in this register does not take effect until
pll_fbdiv_integer is written.
Table 140: PLL_INTEGER (Page 0: 0x00000024)
Bit
Mode
Symbol
Description
Reset
6:0
R/W
pll_fbdiv_integer
PLL integer division value.
0x20
Writing this register causes the entire pll_fbdiv
value (PLL_INTEGER, PLL_FRAC_TOP,
PLL_FRAC_BOT) to be updated.
Table 141: PLL_SRM_STS (Page 0: 0x00000025)
Bit
Mode
Symbol
Description
Reset
7:4
R
pll_srm_status
PLL/SRM status (user mode).
0x1
Within this four-bit register field,
Bit position [3] = SRM lock
Bit position [2] = PLL/SRM active
Bit position [1] = PLL lock
Bit position [0] = MCLK status (1=valid MCLK
detected, subject to minimum detection frequency
of approximately 1 MHz)
For each bit position,
0 = Inactive or invalid
1 = Active or valid
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Table 142: Register map router_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x0000002A
DIG_ROUTIN
G_DAI
Reserved
dai_r_src
dac_r_src
Reserved
dai_l_src
dac_l_src
0x0000002E
DIG_ROUTIN
G_DAC
dac_r_mono
dac_r_inv
Reserved
dac_l_mono
dac_l_inv
Reserved
0x00000099
DIG_CTRL
Reserved
Reserved
Table 143: DIG_ROUTING_DAI (Page 0: 0x0000002A)
Bit
Mode
Symbol
Description
Reset
5:4
R/W
dai_r_src
Data selection for the DAI right output stream
0x1
00 = ADC left
01 = Tone generator
10 = DAI input left data / DAI mono mix
11 = DAI input right data / DAI mono mix
1:0
R/W
dai_l_src
Data selection for the DAI left output stream
0x0
00 = ADC left
01 = Tone generator
10 = DAI input left data / DAI mono mix
11 = DAI input right data / DAI mono mix
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Table 144: DIG_ROUTING_DAC (Page 0: 0x0000002E)
Bit
Mode
Symbol
Description
Reset
7
R/W
dac_r_mono
Mono-mix control for the DAI right input stream
0x0
0 = No mono-mix
1 = The DAI right input stream is replaced with a
mono mix of left and right
5:4
R/W
dac_r_src
Data selection to the DAC_R path
0x3
00 = ADC left output
01 = Tone generator
10 = DAI input left / dai mono mix
11 = DAI input right / dai mono mix
3
R/W
R/W
dac_l_mono
dac_l_src
Mono-mix control for the DAI left input stream
0x0
0x2
0 = No mono-mix
1 = The DAI left input stream is replaced with a
mono mix of left and right
1:0
Data selection to the DAC_L path
00 = ADC left output
01 = Tone generator
10 = DAI input left / dai mono mix
11 = DAI input right / dai mono mix
Table 145: DIG_CTRL (Page 0: 0x00000099)
Bit
Mode
Symbol
Description
Reset
7
R/W
dac_r_inv
DAC right input stream invertion control
0x0
0 = No inversion of the right input strem
1 = The right input stream is inverted
3
R/W
dac_l_inv
DAC left input stream invertion control
0x0
0 = No inversion of the left input stream
1 = The left input stream is inverted
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Table 146: Register map sidetone_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x0000003A
SIDETONE_C
TRL
sidetone_mut
e_en
sidetone_en
Reserved
0x0000003B
SIDETONE_G
AIN
Reserved
sidetone_gain
0x0000003C
DROUTING_S
T_OUTFILT_1
L
Reserved
Reserved
outfilt_st_1l_src
outfilt_st_1r_src
0x0000003D
DROUTING_S
T_OUTFILT_1
R
Table 147: SIDETONE_CTRL (Page 0: 0x0000003A)
Bit
Mode
Symbol
Description
Reset
7
R/W
sidetone_en
Sidetone path control
0x0
0 = Sidetone path disabled
1 = Sidetone path enabled
6
R/W
sidetone_mute_en
SideTone mute control
0x1
0 = Sidetone mute disabled
1 = Sidetone mute enabled
Table 148: SIDETONE_GAIN (Page 0: 0x0000003B)
Bit
Mode
Symbol
Description
Reset
3:0
R/W
sidetone_gain
Sidetone gain control
0xE
0000 = -42 dB
0001 = -39 dB
0010 = -36 dB
Continuing in 3 dB steps to…
1101 = -3dB
1110 = 0dB
1111 = Reserved
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Table 149: DROUTING_ST_OUTFILT_1L (Page 0: 0x0000003C)
Bit
Mode
Symbol
Description
Reset
2:0
R/W
outfilt_st_1l_src
Data selection for the output filter 1 left output
stream
0x1
bit 0 = Output filter 1L
bit 1 = Output filter 1R
bit 2 = Sidetone
For each bit position/output stream, 0 = disabled
and 1 = enabled
Table 150: DROUTING_ST_OUTFILT_1R (Page 0: 0x0000003D)
Bit
Mode
Symbol
Description
Reset
2:0
R/W
outfilt_st_1r_src
Data selection for the output filter 1 right output
stream
0x2
bit 0 = Output filter 1L
bit 1 = Output filter 1R
bit 2 = Sidetone
For each bit position/output stream, 0 = disabled
and 1 = enabled
Table 151: Register map system_active_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x000000FD
SYSTEM_ACT
IVE
system_activ
e
Reserved
Table 152: SYSTEM_ACTIVE (Page 0: 0x000000FD)
Bit
Mode
Symbol
Description
Reset
0
R/W
system_active
System Standby mode
0x0
0 = Standby mode
1 = Active mode
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Table 153: Register map system_controller_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x00000050
SYSTEM_MO
DES_INPUT
adc_mode
dac_mode
mode_submit
mode_submit
sc1_busy
0x00000051
SYSTEM_MO
DES_OUTPU
T
0x000000E0
SYSTEM_STA
TUS
Reserved
sc2_busy
Table 154: SYSTEM_MODES_INPUT (Page 0: 0x00000050)
Bit
Mode
Symbol
Description
Reset
7:1
R/W
adc_mode
preconfigured system modes (input side):
[1] = reserved
0x0
[2] = MIC
[3] = reserved
[4] = MIXIN
[5] = reserved
[6] = ADC
[7] = reserved
0
R/W
mode_submit
Causes both the adc_mode and dac_mode to
become active
0x0
Table 155: SYSTEM_MODES_OUTPUT (Page 0: 0x00000051)
Bit
Mode
Symbol
Description
Reset
7:1
R/W
dac_mode
preconfigured system modes (output side):
[1] = reserved
0x0
[2] = reserved
[3] = reserved
[4] = HP_L
[5] = HP_R
[6] = DAC_L
[7] = DAC_R
0
-
mode_submit
Causes both the adc_mode and dac_mode to
become active
0x0
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Table 156: SYSTEM_STATUS (Page 0: 0x000000E0)
Bit
Mode
Symbol
Description
Reset
1
R
sc2_busy
Indicates the current status of the system mode
0x0
controller
0 = complete
1 = busy
0
R
sc1_busy
Indicates the current status of the system controller
0x0
0 = complete
1 = busy
Table 157: Register map tone_gen_cad_00 page 0
Address
Name
#
7
6
5
4
3
2
1
0
Register Page 0
0x000000B4
TONE_GEN_
CFG1
start_stopn
Reserved
dtmf_en
dtmf_reg
0x000000B5
TONE_GEN_
CFG2
tone_gen_gain
Reserved
swg_sel
0x000000B6
TONE_GEN_
CYCLES
Reserved
beep_cycles
0x000000B7
TONE_GEN_F
REQ1_L
freq1_l
freq1_u
freq2_l
freq2_u
0x000000B8
TONE_GEN_F
REQ1_U
0x000000B9
TONE_GEN_F
REQ2_L
0x000000BA
TONE_GEN_F
REQ2_U
0x000000BB
TONE_GEN_
ON_PER
Reserved
beep_on_per
beep_off_per
0x000000BC
TONE_GEN_
OFF_PER
Reserved
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Table 158: TONE_GEN_CFG1 (Page 0: 0x000000B4)
Bit
Mode
Symbol
Description
Reset
7
R/W
start_stopn
Tone Generator stop-start control.
0x0
Setting this bit = 1 starts the Tone Generator for the
number of beeps defined by beep_cycles. Once
complete, the bit is automatically cleared.
If beep_cycles = 111 (continuous), then this bit
must be cleared manually
0 = Tone Generator disabled
1 = Tone Generator enabled
4
R/W
R/W
dtmf_en
DTMF control
0x0
0x0
0 = DTMF is disabled. The Tone Generator uses
values in the registers freq1 and freq2 to generate
sine wave(s)
1 = DTMF is enabled. The Tone Generator uses
values from the register dtmf_reg to generate sine-
waves
3:0
dtmf_reg
The DTMF key pad values 0 to 15
0000 = 0
0001 = 1
0010 = 2
0011 = 3
0100 = 4
0101 = 5
0110 = 6
0111 = 7
1000 = 8
1001 = 9
1010 = A
1011 = B
1100 = C
1101 = D
1110 = *
1111 = #
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Table 159: TONE_GEN_CFG2 (Page 0: 0x000000B5)
Bit
Mode
Symbol
Description
Reset
7:4
R/W
tone_gen_gain
Tone Generator gain control
0x0
0000 = 0 dB
0001 = -2.5 dB
0010 = -6 dB
Continuing in 2.5/3.5 dB steps to…
1110 = -42 dB
1111 = -44.5 dB
1:0
R/W
swg_sel
Sine wave selection control
0x0
00 = Sum of both Sine Wave Generator (SWG)
values is mixed into the audio stream
01 = Only the first SWG value is output
10 = Only the second SWG value is output
11 = 1-Cos(SWG1) or S_ramp function for
headphone detection. The high period is
determined by the beep_on_per setting
Table 160: TONE_GEN_CYCLES (Page 0: 0x000000B6)
Bit
Mode
Symbol
Description
Reset
2:0
R/W
beep_cycles
Beep control.
0x0
This specified the number of beep cycles required.
000 = 1 cycle
001 = 2 cycles
010 = 3 cycles
011 = 4 cycles
100 = 8 cycles
101 = 16 cycles
110 = 32 cycles
111 = continuous (until start_stopn is set to 0)
Table 161: TONE_GEN_FREQ1_L (Page 0: 0x000000B7)
Bit
Mode
Symbol
Description
Reset
7:0
R/W
freq1_l
Lower byte of the output frequency for the first Sine
Wave Generator (SWG)
0x55
If sample rate (SR) = 8/12/16/24/32/48/96 kHz
freq1=(2^16*(f/12000))-1
If sample rate (SR) =11.025/22.05/44.4/88.2 kHz,
freq1=(2^16*(f/11025))-1
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Table 162: TONE_GEN_FREQ1_U (Page 0: 0x000000B8)
Bit
Mode
Symbol
Description
Reset
7:0
R/W
freq1_u
Upper byte of the output frequency for the first Sine
Wave Generator (SWG)
0x15
If sample rate (SR) = 8/12/16/24/32/48/96 kHz
freq1=(2^16*(f/12000))-1
If sample rate (SR) =11.025/22.05/44.4/88.2 kHz,
freq1=(2^16*(f/11025))-1
Table 163: TONE_GEN_FREQ2_L (Page 0: 0x000000B9)
Bit
Mode
Symbol
Description
Reset
7:0
R/W
freq2_l
Lower byte of the output frequency for the second
Sine Wave Generator (SWG)
0x0
If sample rate (SR) = 8/12/16/24/32/48/96 kHz
freq1=(2^16*(f/12000))-1
If sample rate (SR) =11.025/22.05/44.4/88.2 kHz,
freq1=(2^16*(f/11025))-1
Table 164: TONE_GEN_FREQ2_U (Page 0: 0x000000BA)
Bit
Mode
Symbol
Description
Reset
7:0
R/W
freq2_u
Upper byte of the output frequency for the second
Sine Wave Generator (SWG)
0x40
If sample rate (SR) = 8/12/16/24/32/48/96 kHz
freq1=(2^16*(f/12000))-1
If sample rate (SR) =11.025/22.05/44.4/88.2 kHz,
freq1=(2^16*(f/11025))-1
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Table 165: TONE_GEN_ON_PER (Page 0: 0x000000BB)
Bit
Mode
Symbol
Description
Reset
5:0
R/W
beep_on_per
Beep ON period control
0x2
0x0 = 10 ms
0x1 = 20 ms
0x2 = 30 ms
Continuing in 10 ms steps to…
0x14 = 200 ms
then…
0x15 = Reserved
0x16 = Reserved
0x17 = Reserved
0x18 = Reserved
then...
0x19 = 250 ms
0x1A = 300 ms
0x1B = 350 ms
Continuing in 50 ms steps to
0x3B = 1950 ms
0x3C = 2000 ms
0x3D = Reserved
0x3E = Reserved
0x3F = Continuous
Table 166: TONE_GEN_OFF_PER (Page 0: 0x000000BC)
Bit
Mode
Symbol
Description
Reset
5:0
R/W
beep_off_per
Beep OFF period control
0x1
0x0 = 10 ms
0x1 = 20 ms
0x2 = 30 ms
Continuing in 10 ms steps to…
0x14 = 200 ms
then…
0x15 = Reserved
0x16 = Reserved
0x17 = Reserved
0x18 = Reserved
then...
0x19 = 250 ms
0x1A = 300 ms
0x1B = 350 ms
Continuing in 50 ms steps to…
0x3B = 1950 ms
0x3C = 2000 ms
0x3D = Reserved
0x3E = Reserved
0x3F = Reserved
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11 Package information
Figure 35: DA7219 package outline drawing
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12 Ordering information
The ordering number consists of the part number followed by a suffix indicating the packing method.
For details and availability, please contact Dialog Semiconductor’s local sales representative.
Table 167: Ordering information
Part number
DA7219-02VBA
DA7219-02VB6
Package
32 WL-CSP
32 WL-CSP
Size (mm)
4.5 x 1.64 mm
4.5 x 1.64 mm
Shipment form
Pack quantity
Tape & reel
4,500
98
Tray/Waffle Pack
(engineering samples only -
not for mass production
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Appendix A Applications information
A.1 Codec initialisation
Depending on the specific application, some general settings need to be set. Examples of these
settings include the sample rate, the PLL, and the Digital Audio Interface. Then the amplifiers, the
mixers and channels of the ADC/DAC have to be configured and enabled using their respective
control registers.
An example sequence is shown below:
1. Configure clock mode as required for operation, (for example PLL bypass, PLL or SRM mode)
2. Configure the digital audio interface
3. Configure the charge pump if the headphone path is in use
4. Set input and output mixer paths and gains
5. Enable input and output paths using the System Controller
A.2 Automatic ALC calibration
When using the automatic level control (ALC) in sync-mode the DC offset between the digital and
analogue PGAs must be cancelled. This is performed automatically if the following procedure is
performed:
6. Enable microphone amplifiers unmuted
7. Mute microphones
8. Enable input mixer and ADC unmuted
9. Enable AIF interface
10. Set alc_auto_calib_en in ALC_CTRL1 to ‘1’ (ALC_CTRL1 = 0x2F). This bit will auto clear when
calibration is complete.
11. When calibration is complete, enable the ALC with alc_sync_mode and alc_offset_en
(ALC_CTRL1 = 0x2F)
12. Unmute microphones
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Appendix B Components
The following recommended components are examples selected from requirements of a typical
application. The electrical characteristics (that is, the supported voltage/current ranges) have to be
cross-checked and component types may need to be adapted from the individual needs of the target
circuitry.
B.1 Audio inputs
Table 168: Audio inputs
Pin name
Bump/
pin
Power domain
Description
Type
Differential mic. input (negative)
/ Single-ended mic. Input
MIC_N
MIC_P
MIC
A15
B16
C15
VDD
VDD
N/A
Analogue input
Analogue input
Analogue input
Differential mic. input (positive) /
Single-ended mic. Input
Supply input for headset
microphone power
The DA7219 microphone inputs can be configured to accommodate single-ended or differential
analogue microphones, line inputs or digital microphones.
When using the inputs in an analogue configuration, a DC blocking capacitor is required for each
used input bump used in the target application. The choice of capacitor is determined by the filter that
is formed between that capacitor and the input impedance of the input pin, which can be found in the
‘Input Mixing Units’ section of the datasheet.
1
퐶 =
2휋. 푅. 퐹
푐
Where Fc is the 3 dB cut off frequency of the low pass filter (typically 20 Hz for audio applications). A
1 µF capacitor is suitable for most applications.
Due to their high stability, tantalum capacitors are particularly suitable for this application. Ceramic
equivalents with an X5R dielectric are recommended as a cost-effective alternative. Care should be
taken to ensure that the desired capacitance is maintained over operating temperature and voltage.
Z5U dielectric ceramics should be avoided due to their susceptibility to microphonic effects.
Unused input bumps can be left floating or connected via a capacitor to ground.
The MIC pin would normally be connected to MICBIAS using a 2k2 resistor. This pin is an input to
supply the microphone power when a headset is connected to the headset socket. The polarity of the
microphone pin is determined by the accessory detect circuitry and the power is switched internally in
the device to allow the microphone bias to be provided from this pin.
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B.2 Microphone bias
Table 169: Microphone bias
Pin Name
Bump/Pin
Power Domain
Description
Type
MICBIAS
B14
VDD_MIC
Microphone bias output
Analogue output
MIC
C15
VDD_MIC
Microphone bias input to AccDet
Analogue Input
A 1 µF capacitor to GND should be used to decouple the MICBIAS output.
C15
MIC
B14
MICBIAS
1 µF
Figure 36: Micbias decoupling
B.3 Audio outputs
Table 170: Headset
Pin Name
Bump/Pin
Power Domain
Description
Type
HP_L
A5
A3
VDD
headphone output (left)
headphone output (right)
Analogue output
HP_R
VDD
Analogue output
Connection to RING2 on
headset jack
Analogue
input/ground
RING2
C13
B4
VDD_MIC
Analogue
input/ground
RING2_SENSE
SLEEVE
VDD_MIC
VDD_MIC
VDD_MIC
Ring2 sense line
Connection to SLEEVE on
headset jack
Analogue
input/ground
A11
B6
Analogue
input/ground
SLEEVE_SENSE
Sleeve sense line
JACKDET
MIC_P
D16
B16
A15
VDD
VDD
VDD
Jack insertion detect pin
Microphone input (P)
Microphone input (N)
Analogue input
Analogue Input
Analogue Input
MIC_N
A11
SLEEVE
B6
SLEEVE_SENSE
MIC_P
B16
A15
MIC_N
Headset jack
B4
C13
A5
RING2_SENSE
RING2
HP_R
HP_L
A3
JACKDET
D16
Figure 37: Recommended headphone layout
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B.4 Headphone charge pump
Table 171: Headphone charge pump
Pin name
Bump/pin
Power domain
Description
Type
HPCSP
A1
VDD
Charge pump reservoir capacitor (pos)
Charge pump reservoir capacitor (neg)
Charge pump flying capacitor (pos)
Charge pump flying capacitor (neg)
Charge pump
Charge pump
Charge pump
Charge pump
HPCSN
HPCFP
HPCFN
C1
D2
C3
VDD
VDD
VDD
A 1 µF reservoir capacitor is required between the HPCSP and GND and between HPCSN and
GND. For best performance the capacitors should be fitted as near to the device as possible.
A1
HPCSP
1µF
1µF
C1
HPCSN
Figure 38: Charge pump decoupling
A 1 µF flying capacitor is required between HPCFP and HPCFN. For best performance the capacitor
should be fitted as near to the device as possible.
D2
HPCFP
1µF
C3
HPCFN
Figure 39: Charge pump flying capacitor
To ensure stable charge pump operation the effective series resistance of the flying capacitor should
be kept to a minimum. This can be achieved by selecting an appropriate capacitor dielectric (X5R,
X7R) and ensuring that the capacitor is placed as near to the device as possible. Ideally the
connection between the pins and the capacitor should not run through vias (connected on top layer
of PCB only).
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B.5 Digital interfaces
Table 172: Digital interfaces – I2C
Pin name
Bump/pin
Power domain
Description
I2C bidirectional data
Type
SDA
D14
VDD_IO
Digital input /
output
SCL
D12
VDD_IO
I2C clock input
Digital input
The I2C data and clock lines are powered from VDD_IO. Both I2C line require a pull up to VDD_IO.
The value of this pull up is dependent on I2C bus speed, bus length and supply voltage. A 2.2 kΩ
resistor is satisfactory in most applications.
VDD_IO
2k2 Ω
2k2 Ω
D14
D12
SDA
SCL
Figure 40: I2C pull ups
Table 173: Digital interfaces - I2S
Pin name
Bump/pin
Power domain
Description
Type
DATIN
C7
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
DAI data input
Digital output
DATOUT
BCLK
C9
D6
DAI data output
DAI bit clock
Digital input
Digital input / output
Digital input / output
Digital input
WCLK
MCLK
D8
DAI word clock (L/R select)
Master clock
C11
The DAI interface pins should be treated as clock signals and the appropriate layout rules for routing
clocks should be adhered to.
B.6 References
Table 174: References
Pin name
Bump/pin
Power domain
Description
Type
Reference
VMID
A9
VDD
Audio mid-rail reference capacitor
VREF
A7
B8
VDD
VDD
Bandgap reference capacitor
Audio DAC reference capacitor
Reference
Reference
DACREF
A 1 µF capacitor should be connected between each of the references and GND. For best
performance the capacitors should be fitted as near to the device as possible.
A9
VMID
1µF
A7
B8
VREF
1µF
1µF
DACREF
Figure 41: Reference capacitors
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B.7 Supplies
Table 175: Power supplies
Pin name
Bump/pin
Power domain
Description
Type
Supply for analogue & digital
circuits / Supply for headphone
charge pump
Min: 1.71 V
Max: 2.65 V
VDD
C5
Power supply
Power supply
Power supply
Min: 1.71 V
Max: 3.6 V
VDD_IO
D4
Supply for digital interfaces
Supply for microphone bias circuits
Min: 1.8 V *
Max: 3.6 V
VDD_MIC
A13
* Minimum level must be 300 mV
higher than VDD level
Decoupling capacitors are recommended between all supplies and GND. These capacitors should be
located as near to the device as possible.
C5
VDD
1.71 V to 2.65 V
1.71 V to 3.6 V
1.8 V to 3.6 V
1 µF
1 µF
1 µF
D4
VDD_IO
A13
VDD_MIC
Figure 42: Power supply decoupling
B.8 Ground
Table 176: Ground
Pin name
Bump/pin
Power domain
Description
Analogue ground
Type
GND
B10
B12
B2
Power ground
GND_HP
GND_CP
Headphone Ground
Power ground
Power ground
Charge pump/digital ground
GND, GND_HP and GND_CP should be connected directly to the system ground.
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Appendix C PCB layout guidelines
DA7219 uses Dialog Semiconductor’s RouteEasy™ technology allowing the device to be routed
using conventional, low cost, PCB technology. All device balls are routable on the top level and
conventional plated through hole vias can be used throughout.
This design is fully realisable using a 2-layer PCB. For optimum performance it is recommended that
a 4-layer PCB is used with layers 2 and 3 as solid ground planes.
Decoupling and reference capacitors should be located as close to the device as possible and
appropriately sized tracks should be used for all power connections.
Figure 43: DA7219 example layout
C.1 Layout and schematic support
Copies of the evaluation board schematics and layout are available on request to aid in PCB
development. Dialog Semiconductor also offer a schematic and layout review service for all designs
using Dialog’s devices. Please contact your local Dialog Semiconductor Office if you wish to use this
service.
C.2 General recommendations
●
●
●
Appropriate trace width and number of vias should be used for all power supply paths
A common ground plane should be used, which allows proper electrical and thermal performance
Noise-sensitive analogue signals such as feedback lines or clock connections should be kept
away from traces carrying pulsed analogue or digital signals. This can be achieved by separation
(distance) or by shielding with quiet signals or ground traces
●
●
Decoupling capacitors should be X5R ceramics and should be placed as near to the device as
possible
Charge pump capacitors should be X5R ceramics and should be placed as near to the device as
possible
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C.3 Capacitor selection
Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behaviour
over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the
minimum capacitance over the necessary temperature range, dc bias conditions and low Equivalent
Series Resistance (ESR). X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are
recommended for best performance. Y5V and Z5U dielectrics are not recommended for use because
of their poor temperature and dc bias characteristics.
The worst-case capacitance accounting for capacitor variation over temperature, component
tolerance, and voltage is calculated using the following equation:
(
)
퐶퐸ꢀꢀ = 퐶푂푈푇 푥 1 − ꢁꢂ푀푃퐶ꢃ 푥 (1 − ꢁꢃ퐿)
where: CEFF is the effective capacitance at the operating voltage. TEMPCO is the worst-case
capacitor temperature coefficient. TOL is the worst-case component tolerance. These figures can be
found in the manufacturer’s datasheet.
In the example below, the worst-case temperature coefficient (TEMPCO) over −55°C to +85°C is
assumed to be 15%. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT is
0.65 μF at 1.8 V.
Substituting these values in the equation yields
(
)
(
)
퐶퐸ꢀꢀ = 0.65휇퐹 푥 1 − 0.15 푥 1 − 0.1 = 0.497 휇퐹
Below is a table with recommended capacitor types:
Temp.
char.
Rated
voltage
Application
Value
Size
Tolerance
Type
VDD,VDD_IO,
VDD_MIC,
DACREF,
VMID,VREF,
HPCFP/HPCFN,
HPCSP,
X5R +/-
15%
10 x 1 µF
0201
+/-10%
6.3 V
Murata GRM033R60J105M
HPCSN,
MICBIAS
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Status definitions
Revision
Datasheet status
Product status
Definition
1.<n>
Target
Development
This datasheet contains the design specifications for product
development. Specifications may be changed in any manner without
notice.
2.<n>
3.<n>
4.<n>
Preliminary
Final
Qualification
Production
Archived
This datasheet contains the specifications and preliminary
characterisation data for products in pre-production. Specifications
may be changed at any time without notice in order to improve the
design.
This datasheet contains the final specifications for products in
volume production. The specifications may be changed at any time
in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via Customer Product Notifications.
Obsolete
This datasheet contains the specifications for discontinued products.
The information is provided for reference only.
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