DA9318L [DIALOG]
High-Efficiency, 10 A, High-Voltage Direct Charger;
| 型号： | DA9318L |
| 厂家： | 
Dialog Semiconductor |
| 描述： | High-Efficiency, 10 A, High-Voltage Direct Charger |
| 文件： | 总49页 (文件大小：686K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
General Description
DA9318L/M is a direct charger using a high-efficiency current doubler with integrated Analog to
Digital Converter (ADC) for system monitoring. The device is especially optimized to handle high
charging currents and at the same time ensure the safety of the battery and the system. It operates
together with a main charger, which handles the pre-charge and constant voltage charging duties.
The current doubling is achieved with a high-efficiency capacitive divider that provides an output
voltage of VIN/2, which allows the use of standard Type-C™ cables for charging currents up to 6 A.
The peak efficiency of DA9318L/M is 98 %.
Available as two variants, the DA9318L provides a maximum 8 A charging current and 35 W of
charging power, whereas DA9318M provides 10 A output current and 44 W of charging power.
An integrated reverse protection feature blocks current flow in both directions while the device is not
operational. Additionally, the battery is protected by DA9318L/M by six hardware based safety
functions for any over- or under-voltage condition. All safety triggered events lead to an automatic
shutdown and are reported via interrupt to the system.
DA9318L/M features an 8-bit ADC for input and output current and voltage, and junction temperature
monitoring which ensures safety during direct charging. For software supervision a programmable
watchdog timer, and for battery overload protection a safety timer, are included.
An I2C compatible 2-wire interface is provided for the device control.
The DA9318L/M is available in a small WLCSP 3.62 mm × 3.78 mm package.
Key Features
■
■
■
■
■
■
8 A output current (DA9318L)
■
8-bit ADC to measure voltage and current at
the input and output as well as junction
temperature
10 A output current (DA9318M)
98 % efficiency at 2 A
■
■
■
■
■
Safety timer and watchdog
Automatic shutdown in fault condition
Travel adaptor detection
5 % current sense accuracy (DA9318L)
10 % current sense accuracy (DA9318M)
Reverse and forward current protection in
IDLE mode
I2C compatible 2-wire interface
No inductors
WLCSP package: 3.62 mm × 3.78 mm
■
Applications
■
Direct charging in smartphones and tablets, battery packs, and Li-ion powered devices
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
1 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Contents
General Description ............................................................................................................................ 1
Key Features ........................................................................................................................................ 1
Applications ......................................................................................................................................... 1
Contents ............................................................................................................................................... 2
Figures.................................................................................................................................................. 4
Tables ................................................................................................................................................... 4
1
2
3
4
5
6
7
Terms and Definitions................................................................................................................... 6
References ..................................................................................................................................... 6
Block Diagram ............................................................................................................................... 7
Ballout ............................................................................................................................................ 8
Absolute Maximum Ratings ....................................................................................................... 10
Recommended Operating Conditions....................................................................................... 11
Electrical Characteristics ........................................................................................................... 12
7.1 Current Consumption.......................................................................................................... 12
7.2 Travel Adaptor Detection .................................................................................................... 12
7.3 Voltage Protection............................................................................................................... 13
7.3.1
7.3.2
7.3.3
Input Voltage Protection ...................................................................................... 13
Battery Voltage Protection................................................................................... 14
Input to Output Voltage Protection ...................................................................... 15
7.4 Current Sensing .................................................................................................................. 15
7.5 Junction Temperature Monitoring ....................................................................................... 15
7.6 Current Doubler................................................................................................................... 16
7.7 Safety Timer and Watchdog ............................................................................................... 17
7.8 Digital I/O ............................................................................................................................ 17
7.9 Interface Timing .................................................................................................................. 18
7.10 Internal Supplies ................................................................................................................. 19
7.10.1 AVDD................................................................................................................... 19
7.11 Thermal Characteristics ...................................................................................................... 19
8
9
Typical Characteristics............................................................................................................... 20
Functional Description ............................................................................................................... 23
9.1 Current Doubler................................................................................................................... 23
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
Reverse Current Protection ................................................................................. 24
Switching Frequency ........................................................................................... 24
Start-Up................................................................................................................ 24
Current Limit ........................................................................................................ 24
Input-to-Output Voltage Protection...................................................................... 24
9.2 Travel Adaptor Detection .................................................................................................... 24
9.3 Voltage Protection............................................................................................................... 24
9.3.1
9.3.2
9.3.3
Input Voltage Protection ...................................................................................... 25
Battery Voltage Protection................................................................................... 25
Input to Output Voltage Protection ...................................................................... 26
9.4 Current Sensing .................................................................................................................. 26
9.4.1 Over-Current Monitoring...................................................................................... 26
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
2 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
9.5 Junction Temperature Monitoring ....................................................................................... 26
9.6 ADC..................................................................................................................................... 27
9.7 Safety Timer........................................................................................................................ 27
9.8 Watchdog Timer.................................................................................................................. 28
9.9 Control Interface.................................................................................................................. 28
9.9.1
9.9.2
9.9.3
9.9.4
PWREN................................................................................................................ 29
nCPEN................................................................................................................. 29
nFAULT................................................................................................................ 29
nIRQ..................................................................................................................... 30
9.10 2-Wire Interface................................................................................................................... 31
9.10.1 Details of the 2-Wire Protocol.............................................................................. 32
9.11 Internal Supplies ................................................................................................................. 34
9.11.1 AVDD................................................................................................................... 34
9.12 Internal Oscillator ................................................................................................................ 34
9.13 Power Modes ...................................................................................................................... 34
9.13.1 NO-POWER Mode............................................................................................... 35
9.13.2 SHUTDOWN Mode.............................................................................................. 35
9.13.3 INITIALIZATION Mode ........................................................................................ 35
9.13.4 IDLE Mode........................................................................................................... 35
9.13.4.1
LOW-POWER IDLE Mode............................................................... 36
9.13.5 ACTIVE Mode...................................................................................................... 36
9.14 Status Flags ........................................................................................................................ 37
10 Register Definition ...................................................................................................................... 38
10.1 Register Descriptions.......................................................................................................... 39
10.1.1 Status and Event ................................................................................................. 39
10.1.2 Voltage Protection ............................................................................................... 41
10.1.3 Current and Voltage Monitoring........................................................................... 42
10.1.4 Current Doubler ................................................................................................... 42
10.1.5 Junction Temperature.......................................................................................... 42
10.1.6 ADC ..................................................................................................................... 43
10.1.7 Interface Control .................................................................................................. 43
10.1.8 Watchdog and Safety Timers .............................................................................. 44
11 Package Information................................................................................................................... 45
11.1 Package Outline.................................................................................................................. 45
11.2 Moisture Sensitivity Level.................................................................................................... 46
11.3 WLCSP Handling ................................................................................................................ 46
11.4 Soldering Information.......................................................................................................... 46
12 Ordering Information .................................................................................................................. 47
Appendix A Application Information ............................................................................................... 48
A.1 Suggested PCB Layout....................................................................................................... 48
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
3 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Figures
Figure 1: Block Diagram........................................................................................................................ 7
Figure 2: Ballout Diagram...................................................................................................................... 8
Figure 3: Interface Timing.................................................................................................................... 18
Figure 4: DA9318L Efficiency.............................................................................................................. 20
Figure 5: DA9318L IOUT ADC Error vs. IOUT vs. Temperature.............................................................. 20
Figure 6: DA9318L Junction Temperature vs. Output Current............................................................ 21
Figure 7: DA9318M Efficiency............................................................................................................. 21
Figure 8: DA9318M IOUT ADC Error vs. IOUT vs. Temperature............................................................. 22
Figure 9: DA9318M Junction Temperature vs. Output Current........................................................... 22
Figure 10: System Level Block Diagram ............................................................................................. 23
Figure 11: Voltage Protection.............................................................................................................. 25
Figure 12: Control Signals................................................................................................................... 29
Figure 13: nFAULT Operation ............................................................................................................. 30
Figure 14: Interrupt Logic .................................................................................................................... 31
Figure 15: START and STOP Condition Timing.................................................................................. 32
Figure 16: Byte Write........................................................................................................................... 32
Figure 17: Byte Read........................................................................................................................... 33
Figure 18: Page Read ......................................................................................................................... 33
Figure 19: Page Write.......................................................................................................................... 33
Figure 20: Repeated Write .................................................................................................................. 34
Figure 21: Internal Supply ................................................................................................................... 34
Figure 22: Power Modes ..................................................................................................................... 35
Figure 23: Package Outline Drawing................................................................................................... 45
Figure 24: Suggested PCB Layout...................................................................................................... 48
Tables
Table 1: Ball Description........................................................................................................................ 8
Table 2: Ball Type Definition.................................................................................................................. 9
Table 3: Absolute Maximum Ratings................................................................................................... 10
Table 4: Recommended Operating Conditions ................................................................................... 11
Table 5: Current Consumption Characteristics ................................................................................... 12
Table 6: Travel Adaptor Detection Characteristics.............................................................................. 12
Table 7: Input Voltage Protection Characteristics ............................................................................... 13
Table 8: Battery Protection Characteristics......................................................................................... 14
Table 9: Input to Output Voltage Protection Characteristics ............................................................... 15
Table 10: Current Sensing Characteristics.......................................................................................... 15
Table 11: Junction Temperature Monitoring Characteristics............................................................... 15
Table 12: Current Doubler External Components ............................................................................... 16
Table 13: Current Doubler Characteristics.......................................................................................... 16
Table 14: Safety Timer and Watchdog Characteristics....................................................................... 17
Table 15: Digital I/O Characteristics.................................................................................................... 17
Table 16: Interface Timing Characteristics.......................................................................................... 18
Table 17: AVDD External Components............................................................................................... 19
Table 18: AVDD Characteristics.......................................................................................................... 19
Table 19: WLCSP Thermal Ratings .................................................................................................... 19
Table 20: ADC Channels..................................................................................................................... 27
Table 21: Interface Slave Address. ..................................................................................................... 31
Table 22: Status Flags......................................................................................................................... 37
Table 23: Register Overview ............................................................................................................... 38
Table 24: STATUS_A (0x00)............................................................................................................... 39
Table 25: STATUS_B (0x01)............................................................................................................... 40
Table 26: EVENT_A (0x02)................................................................................................................. 40
Table 27: EVENT_B (0x03)................................................................................................................. 40
Table 28: EVENT_C (0x04)................................................................................................................. 40
Table 29: MASK_A (0x05)................................................................................................................... 41
Table 30: MASK_B (0x06)................................................................................................................... 41
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
4 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Table 31: MASK_C (0x07)................................................................................................................... 41
Table 32: VBAT_CTRL_A (0x08) ........................................................................................................ 41
Table 33: VBAT_CTRL_B (0x09) ........................................................................................................ 42
Table 34: IIN_CTRL_A (0x0A) ............................................................................................................ 42
Table 35: CP_CTRL_A (0x0B) ............................................................................................................ 42
Table 36: CP_CTRL_B (0x0C)............................................................................................................ 42
Table 37: TJUNC_CTRL_A (0x0D)..................................................................................................... 42
Table 38: ADC_CTRL_A (0x0E) ......................................................................................................... 43
Table 39: ADC_RES_0 (0x0F) ............................................................................................................ 43
Table 40: ADC_RES_1 (0x10) ............................................................................................................ 43
Table 41: ADC_RES_2 (0x11) ............................................................................................................ 43
Table 42: ADC_RES_3 (0x12) ............................................................................................................ 43
Table 43: ADC_RES_4 (0x13) ............................................................................................................ 43
Table 44: ADC_RES_5 (0x14) ............................................................................................................ 43
Table 45: I2C_CTRL_A (0x15)............................................................................................................ 43
Table 46: I2C_CTRL_B (0x16)............................................................................................................ 44
Table 47: CONFIG_A (0x17)............................................................................................................... 44
Table 48: TIMER_CTRL_A (0x18) ...................................................................................................... 44
Table 49: TIMER_CTRL_B (0x19) ...................................................................................................... 44
Table 50: WD_TIMER_COUNT (0x1A)............................................................................................... 44
Table 51: SAFETY_TIMER_COUNT (0x1B)....................................................................................... 44
Table 52: MSL Classification............................................................................................................... 46
Table 53: Ordering Information ........................................................................................................... 47
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
5 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
1
Terms and Definitions
ADC
DC
Analog to digital converter
Direct current
ESD
FET
Electrostatic discharge
Field effect transistor
Human body model
Inter-integrated circuit (bus)
Most significant bit
HBM
I2C
MSB
OTP
PCB
PMIC
POR
RCP
WLCSP
One-time programable
Printed circuit board
Power management integrated circuit
Power on reset
Reverse current protection
Wafer level chip scale package
2
References
[1] NXP Semiconductors, I2C Bus Specification and User Manual
[2] Universal Serial Bus Power Delivery Specification, Revision 2.0, V1.2. Mar. 2016
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
6 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
3
Block Diagram
CBS1
CF1
CF2
CBS2
CMID1
,
CMID2
DA9318
OUT
VOUTS
COUT1
COUT2
,
Reverse
Current
Protection
2 mΩ
IN
Current
Doubler
CIN
PGND
IIN
Monitoring
SYS
IOUT
Monitoring
CSYS
Control
And
Status
Registers
VIN
Monitoring
VBATP
VBATN
+
-
VBAT
Monitoring
PWREN
nCPEN
nFAULT
nIRQ
SDA
TJUNC
Monitoring
VIN
IIN
VBAT
IBAT
TJUNC
2-wire
Interface
SCL
CC1
CC2
AVDD
AGND
CVAVDD
Figure 1: Block Diagram
The two instances of CMID, CBS, CF, and COUT are placed on opposite sides of the die. See
Figure 24 for details.
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
7 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
4
Ballout
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
MID1
C1P
C1P
BS1
C1N
C1N
MID1
C1P
OUT1
OUT1
C1N
PGND1
MID1
C1P
OUT1
OUT1
CC1
PGND1
D
E
F
nIRQ
AGND
OUT1
OUT1
OUT2
OUT1
OUT1
OUT2
VINS
NC
AVDD
SUB
IN
IN
IN
IN
SCL
SDA
OUT1
OUT2
nCPEN
VOUTS
VBATP
VBATN
IN
G
H
nFAULT
PWREN
SYS
J
K
L
MID2
MID2
C2P
C2P
OUT2
C2P
OUT2
BS2
CC2
C2N
PGND2
C2N
MID2
C2P
OUT2
OUT2
C2N
PGND2
Top view
Power supply
Analog signal
Ground
Digital signal
No connection
Figure 2: Ballout Diagram
Table 1: Ball Description
Ball No.
Ball Name Type (Table 2)
Description
E1, E3, F2, G1,
G3
IN
PS
PS
PS
Input supply, bypass to power ground with CIN
Input to the current doubler, bypass to power ground with
CMID1
A1, B2, C1
J1, K2, L1
MID1
MID2
Input to the current doubler, bypass to power ground with
CMID2
A3, A5, B4, C3
A9, A11, B10
J3, K4, L3, L5
K10, L9, L11
C1P
C1N
C2P
C2N
AIO
AIO
AIO
AIO
CF positive terminal
CF negative terminal
CF positive terminal
CF negative terminal
Gate driver supply of the current doubler, bypass to C1P
with CBS1
A7
L7
BS1
BS2
PS
PS
Gate driver supply of the current doubler, bypass to C2P
with CBS2
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
8 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Ball No.
Ball Name Type (Table 2)
Description
B6, B8, C5, C7,
D6, D8, E7, F6,
F8
Output of current doubler, bypass to power ground with
COUT1
OUT1
OUT2
AO
AO
G7, H6, H8, J5,
J7, K6, K8
Output of current doubler, bypass to power ground with
COUT2
B12, C11
J11, K12
F4
PGND1
PGND2
AGND
SUB
GND
GND
GND
GND
AI
Power ground
Power ground
Analog ground
F12
Substrate ground connection
Output voltage sense
Input voltage sense
G9
VOUTS
VINS
D10
AI
E11
VBATP
VBATN
AI
Positive battery voltage sense
Negative battery voltage sense
G11
AI
Secondary power supply of the AVDD, bypass to analog
ground with CSYS
H12
SYS
AI
D12
H10
AVDD
AIO
DI
Internal supply, bypass to analog ground with CAVDD
Power enable, tie to AVDD if not used
PWREN
Interrupt request, open-drain, active low, connect to an IO
supply via pull-up RPU
D4
E9
H4
nIRQ
DO
DI
nCPEN
nFAULT
Current doubler enable, active low
Fault status, open-drain, active low, connect to an IO
supply via pull-up RPU
DO
G5
E5
SDA
SCL
DIO
DI
2-wire data
2-wire clock
USB Type-C configuration channel, connect to ground if
not used
C9
J9
CC1
CC2
NC
DI
USB Type-C configuration channel, connect to ground if
not used
DI
Not connected. Connect to GND PCB plane (not directly to
power ground)
F10
N/A
Table 2: Ball Type Definition
Ball Type
DI
Description
Digital Input
Digital Output
Ball Type
AI
Description
Analog Input
Analog Output
Analog Input/Output
Ground
DO
AO
DIO
Digital Input/Output
Power Supply
AIO
PS
GND
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
9 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
5
Absolute Maximum Ratings
Table 3: Absolute Maximum Ratings
Conditions
(Note 1)
Parameter
Description
Min
Max
Unit
TS
Storage temperature
-60
-0.3
+150
20
ºC
V
V
V
V
V
V
V
V
V
V
VIN
Input voltage (Note 2)
VINS
VMID
VC1P
VC2P
VC1N
VC2N
VBS1
VBS2
VOUT
Input voltage sense pin (Note 2)
Voltage on pin MID
-0.3
20
VIN – 0.025
VC1N - 0.3
VC2N - 0.3
-0.3
VIN
Maximum voltage across C1P
Maximum voltage across C2P
Maximum voltage across C1N
Maximum voltage across C2N
Maximum voltage across BS1
Maximum voltage across BS2
Output voltage
VC1N + 5.5
VC2N + 5.5
VOUT +0.3
VOUT + 0.3
VC1P + 5.5
VC2P + 5.5
6
Referenced
to PGND
-0.3
VC1P - 0.3
VC2P - 0.3
-0.3
Referenced
to VBATN
VBATP
Voltage on battery positive terminal
-0.3
6
V
VBATN
VOUTS
VSYS
Voltage on battery negative terminal
Output voltage sense pin
System voltage
-0.3
-0.3
-0.3
-0.3
-0.3
0.3
V
V
V
V
V
6
Referenced
to AGND
6
VPWREN
VPIN
Power enable voltage limit
All other pins
VAVDD + 0.3
VAVDD + 0.3
Human Body
Model
VESD_HBM
Electrostatic discharge (ESD) protection
2000
V
(HBM)
Note 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, so functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specification are not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2 dVIN/dt must be slower than 1 V/µs. The device is not operational (charging) above VOV_ACT.
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
10 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
6
Recommended Operating Conditions
Table 4: Recommended Operating Conditions
Parameter Description
Conditions
Min
-40
5.5
4.5
2.4
2.5
Typ
Max
85
Unit
°C
V
TA
Operating temperature
VIN_ACT
VIN_IDLE
VBAT
In ACTIVE mode
In IDLE mode
10.5
13.5
5.5
Input supply voltage
V
Battery voltage
System voltage
V
VSYS
5.5
V
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
11 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
7
Electrical Characteristics
Electrical characteristics table limits are guaranteed by production testing, design, or correlation
using standard statistical quality control methods unless otherwise stated. Typical (Typ)
specifications are mean or average values at 25 ºC and are not guaranteed. Unless otherwise noted,
the parameters listed in Table 5 to Table 16 are valid for TA = -40 ºC to +85 ºC, VIN = 4.5 V to 13.5 V.
7.1 Current Consumption
Table 5: Current Consumption Characteristics
Parameter Description
Conditions
Min
Typ
Max
Unit
IQ_SHIP
Current drawn from OUT1, OUT2,
VOUTS, and VBATP (combined) in
SHIP mode (Note 1)
SHIP mode, VBAT =
3.8 V, VIN = 0 V,
VSYS = 0 V
3
µA
IQ_NO_PWR
IQ_IDLE_LP
IQ_IDLE
Current drawn from SYS in NO-
POWER mode
NO-POWER mode,
VBAT = 3.8 V
25
110
1.4
µA
µA
Current drawn from SYS in IDLE_LP
mode
IDLE_LP mode,
VSYS = 3.8 V
Current draw from VINS in IDLE mode
IDLE mode,
VINS = 8 V
mA
Note 1 In SHIP mode the battery is connected but the system rail and input rails are not powered (= 0 V).
7.2 Travel Adaptor Detection
Table 6: Travel Adaptor Detection Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Unit
VTHR_RISE
Adaptor detection rising threshold
Rising threshold in
IDLE mode (Note 1)
4.07
4.29
4.5
V
VTHR_RISE_ACC Adaptor detection rising threshold
accuracy
-5
+5
%
tDEGLITCH
VTHR_HYS
Adaptor detection deglitch time
Adaptor detection hysteresis
1.25
300
ms
mV
Note 1 The device is only operational when VIN is within the range defined by VIN2OUT_MIN and VIN2OUT_MAX, see
Table 9.
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
12 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
7.3 Voltage Protection
7.3.1
Input Voltage Protection
Table 7: Input Voltage Protection Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Unit
VOV_IDLE
VIN over-voltage threshold
Rising threshold
13.5
14.2
V
in IDLE mode (Note 1)
VOV_ACT
Rising threshold
10.5
V
during current doubler
operation (ACTIVE mode)
(Note 1)
tDEGLITCH_OV
VUV_RISE
VIN over-voltage deglitch
time
10
µs
V
VIN under-voltage threshold Rising threshold, during
current doubler operation
5.5
(ACTIVE mode) (Note 1)
VUV_FALL
Falling threshold, during
current doubler operation
(ACTIVE mode) (Note 1)
5.1
V
tDEGLITCH_UV
VPROT_HYS
VIN under-voltage deglitch
time
10
2
µs
%
VIN protection hysteresis
(applies to VOV_IDLE and
VOV_ACT
)
RPD
IN pull-down
20
kΩ
Note 1 The device is only operational when VIN is within the range defined by VIN2OUT_MIN and VIN2OUT_MAX, see
Table 9.
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
13 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
7.3.2
Battery Voltage Protection
Table 8: Battery Protection Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Unit
Rising threshold
VBAT_OV_THRSH = 0x3C
VOV_HI
5.5
V
Over-voltage threshold
Rising threshold
VBAT_OV_THRSH = 0x0
VOV_LO
4.0
5
V
µs
V
Battery over-voltage
protection deglitch delay
tDEGLITCH_OV
VUV_HI
Falling threshold
VBAT_UV_THRSH = 11
3.0
2.4
2
Under voltage threshold
Falling threshold
VBAT_UV_THRSH = 00
VUV_LO
V
VBAT protection
hysteresis
VBAT_PROT_HYS
%
VBAT_OV (4 V to 5.5 V)
VBAT_UV (2.4 V to 3 V)
-2
-4
+2
+4
%
%
VBAT_PROT_ACC
VBAT protection accuracy
Battery under-voltage
protection deglitch delay
tDEGLITCH_UV
VWARN_HI
5
µs
V
VBAT_WARN_THRSH =
0XF0
5.5
2.4
VBAT warning threshold
VBAT_WARN_THRSH =
0X10
VWARN_LO
V
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
14 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
7.3.3
Input to Output Voltage Protection
Table 9: Input to Output Voltage Protection Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Unit
Minimum input-to-output
voltage
VIN/2 to VOUT
falling threshold
VIN2OUT_MIN
5
mV
Maximum input-to-output
voltage
VIN/2 to VOUT
rising threshold
VIN2OUT_MAX
200
20
mV
VIN2OUT_MAX_ACC Protection accuracy
VIN2OUT_HYS VIN2OUT hysteresis
-20
+20
mV
%
7.4 Current Sensing
Table 10: Current Sensing Characteristics
Parameter
DA9318L
IIN_OC_HI
Description
Conditions
Min
Typ
Max
Unit
IIN over-current threshold
IIN current sensing accuracy
IOUT current sensing accuracy
IIN_OC_THRSH = 0xF0
IIN_OC_THRSH = 0x10
IIN = 2 A to 4 A
4.1
A
IIN_OC_LO
500
mA
%
IIN_ACC_HI
IIN_ACC_LO
IOUT_ACC_HI
IOUT_ACC_LO
DA9318M
IIN_OC_HI
-5
-100
-5
+5
+100
+5
IIN = 500 mA to 2 A
IOUT = 4 A to 8 A
mA
%
IOUT = 1 A to 4 A
-200
+200
mA
IIN over-current threshold
IIN_OC_THRSH = 0xF0
IIN_OC_THRSH = 0x10
IIN = 2 A to 5 A
5.1
A
IIN_OC_LO
500
mA
%
IIN_ACC_HI
IIN_ACC_LO
IOUT_ACC_HI
IOUT_ACC_LO
IIN current sensing accuracy
IOUT current sensing accuracy
-10
-100
-10
+10
+100
+10
IIN = 500 mA to 2 A
IOUT = 4 A to 10 A
mA
%
IOUT = 1 A to 4 A
-200
+200
mA
7.5 Junction Temperature Monitoring
Table 11: Junction Temperature Monitoring Characteristics
Parameter Description
Conditions
Min
Typ
Max
Unit
Power on reset (POR)
temperature threshold
TPOR
Rising threshold
150
°C
TPOR_HYS
TCRIT
POR temperature hysteresis
Critical temperature threshold
Critical temperature hysteresis
5
140
5
°C
°C
°C
Rising threshold
TCRIT_HYS
Rising threshold
TJUNC_WARN_THRSH = 11
TWARN_HI
TWARN_LO
120
70
°C
°C
Warning temperature
threshold
Rising threshold
TJUNC_WARN_THRSH = 00
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
15 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Parameter Description
Warning temperature
Conditions
Min
Typ
Max
Unit
TWARN_HYS
2
°C
hysteresis
Junction temperature
monitoring deglitch delay
tDEGLITCH
Applies to TPOR and TCRIT
2.8
µs
7.6 Current Doubler
The parameters listed in Table 13 are valid with the following external component values, unless
otherwise noted.
Table 12: Current Doubler External Components
Parameter Description
Conditions
Min
Typ
2×47
4.7
Max
Unit
µF
µF
µF
nF
CFLY
COUT
CLOAD
CBS
Flying capacitors
Output capacitors
Load capacitor
470
Bootstrap capacitors
Input capacitor
10
4.7
4.7
CMID
CIN
µF
µF
Input capacitor
Table 13: Current Doubler Characteristics
Parameter
VIN_IDLE
Description
Conditions
Min
4.5
5.5
Typ
Max
13.5
10.5
Unit
V
In IDLE mode
In ACTIVE mode
Supply voltage
VIN_ACTIVE
V
0.5 *
VIN
VOUT
Output voltage
IOUT = 0 A
V
A
Max output current
DA9318L
Continuous output current
8
IOUT_MAX
Max output current
DA9318M
Continuous output current
10
A
A
Cycle-by-cycle peak current
limit of individual switching
FETs
Programmable in 450 mA
steps (CP_ILIM)
ILIM_PK
4.8
11.55
+20
Deglitch time for the peak
current limit
tDEGLITCH_ILIM_PK
ILIM_ACC
10
µs
%
CF1 ≥ 30 µF, CF2 ≥ 30 µF
CF1 = CF2
Peak current limit accuracy
-20
CP_FREQ = 11
1500
1000
500
kHz
kHz
kHz
kHz
CP_FREQ = 10
fSW
Switching frequency
CP_FREQ = 01 (default)
CP_FREQ = 00
250
VOUT = 4.2 V
IOUT = 2 A
η
Current doubler efficiency
98
%
fixed frequency mode
fsw = 500 kHz
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
16 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Parameter
Description
Conditions
Min
Typ
Max
Unit
VOUT = 4.2 V
IOUT = 6 A
η
Current doubler efficiency
97
%
fixed frequency mode
fsw = 500 kHz
Including pin and routing
VIN = 7.4 V
High-side NMOS switch on-
resistance
RDS_ON_HS
20
10
mΩ
mΩ
Including pin and routing
VIN = 7.4 V
Low-side NMOS switch on-
resistance
RDS_ON_LS
Response time of the
reverse current protection
(RCP)
tRCP
3
µs
7.7 Safety Timer and Watchdog
Table 14: Safety Timer and Watchdog Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Unit
Controlled by writing a timeout
value to WD_TIMER_LOAD
tWD
Watchdog period
0
255
s
tSFTY_HI
tSFTY_LO
tACC
SAFETY_TIMER_LOAD = 0xC
SAFETY_TIMER_LOAD = 0x0
18
h
h
Safety timer period
Timer accuracy
0.25
-10
+10
%
7.8 Digital I/O
Table 15: Digital I/O Characteristics
Parameter
VIH
Description
Conditions
Min
Typ
Max
Unit
V
Input high voltage
Input low voltage
Output low voltage
Input capacitance
Deglitch time for inputs
1.26
VIL
0.4
0.3
10
V
VOL
Sink current 5 mA
V
CIN
pF
ms
tDEGLITCH
1.25
2
Minimum pulse width of
nFAULT
tFLT_MIN
ms
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
17 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
7.9 Interface Timing
START
ACK
STOP
tF
tR
70%
SDA
SCL
30%
tSU_STA
tF
tSU_D
tH_D
tHIGH
tVD_D
tVD_ACK
tSU_STO
70%
30%
tH_STA
1/fSCL
tLOW
Figure 3: Interface Timing
Unless otherwise noted, the following is valid for TA = -40 ºC to +85 ºC, VIN = 4.3 V to 11 V, VBAT
2.6 V to 4.4 V.
=
Table 16: Interface Timing Characteristics
Parameter Description
tBUF Bus free time from STOP to START
Test conditions
Min
Max
Unit
0.5
µs
condition
Standard, Fast, and Fast-Plus Modes
CB
Bus line capacitive load
SCL clock frequency
150
400
pF
fSCL
Note 1
0
kHz
tSU_STA
tH_STA
tW_CL
tW_CH
tR
Start condition setup time
Start condition hold time
SCL low time
0.26
0.26
0.5
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
ns
SCL high time
0.26
2-wire SCL and SDA rise time
2-wire SCL and SDA fall time
Data setup time
120
120
tF
tSU_D
tH_D
50
0
Data hold-time
tSU_STO
tVD_D
tVD_ACK
tSP
Stop condition setup time
Data valid time
0.26
0.45
0.45
50
Data valid acknowledge time
Spike suppression (SCL, SDA)
Fast/Fast+ mode
High-Speed Mode
CB
Bus line capacitive load
100
pF
fSCL
SCL clock frequency
Start condition setup time
Start condition hold time
SCL low time
Note 1
0
3400
kHz
tSU_STA
tH_STA
tSCL_LO
tSCL_HI
160
160
160
60
ns
ns
ns
ns
SCL high time
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
18 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Parameter Description
Test conditions
Min
Max
Unit
tR
2-wire SCL and SDA rise time
80
ns
tF
2-wire SCL and SDA fall time
Data setup time
80
ns
ns
ns
ns
ns
tSU_D
tH_D
tSU_STO
tSP
10
0
Data hold-time
Stop condition setup time
Spike suppression (SCL, SDA)
160
10
Note 1 Minimum clock frequency is 10 kHz if I2C_TO_EN = 1.
7.10 Internal Supplies
7.10.1 AVDD
The parameters listed in Table 18 are valid with the following external component values, unless
otherwise noted.
Table 17: AVDD External Components
Parameter Description
Conditions
Min
Min
Typ
Max
Max
Unit
CAVDD
Output capacitors
4.7
µF
Table 18: AVDD Characteristics
Parameter
Description
Conditions
Typ
4.0
Unit
V
VIN_MAX, VSYS_MAX > 4.15 V
VSYS < VIN < 4.15 V
VIN < VSYS < 4.15 V
Rising threshold of VAVDD
Falling threshold of VAVDD
VAVDD
Internal supply
POR threshold
VIN - 0.02
VSYS - 0.02
2.4
V
V
VPOR_RISE
VPOR_FALL
2.5
V
2.20
2.33
V
7.11 Thermal Characteristics
Table 19: WLCSP Thermal Ratings
Parameter Description
Conditions
Min
Typ
Max
Unit
Ambient temperature of
27 °C
Junction-to-ambient
thermal resistance
Device with uniform power
dissipation of 1 W
Device mounted on 4L
Jedec PCB
ƟJA
32.18
°C/W
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
19 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
8
Typical Characteristics
100
98
96
94
92
90
88
86
84
82
80
0
1
2
3
4
5
6
7
8
Battery Charging Current (A)
VOUT = 4.2 V
Figure 4: DA9318L Efficiency
20
15
10
5
0
-5
-10
-15
-20
4
4.5
-25C
5
5.5
0C
6
6.5
45C
7
7.5
8
IOUT (A)
25C
-15C
65C
85C
Figure 5: DA9318L IOUT ADC Error vs. IOUT vs. Temperature
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
20 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
85
75
65
55
45
35
25
15
0
1
2
3
4
5
6
7
8
Output Current (A)
Tjunc
Figure 6: DA9318L Junction Temperature vs. Output Current
100
98
96
94
92
90
88
86
84
82
80
0
1
2
3
4
5
6
7
8
9
10
Battery Charging Current (A)
VOUT = 4.2 V
Figure 7: DA9318M Efficiency
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
21 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
20
15
10
5
0
-5
-10
-15
-20
4
5
6
7
8
9
10
IOUT (A)
-40C
-25C
-15C
0C
5C
25C
45C
65C
85C
Figure 8: DA9318M IOUT ADC Error vs. IOUT vs. Temperature
85
75
65
55
45
35
25
15
0
2
4
6
8
10
Output Current (A)
Tjunc
Figure 9: DA9318M Junction Temperature vs. Output Current
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
22 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
9
Functional Description
CF1
CF2
CBS1
CBS2
CMID1
,
CMID2
VBUS
DA9318
OVP
Current
Doubler
RCP
IIN
Monitoring
Main Charger
Current
Sensing
RCP
IOUT
Monitoring
Control
And
Status
VIN
Monitoring
VBAT
Monitoring
ISYS
Registers
Buck
TJUNC
Monitoring
Control
VIN
IIN
VBAT
IOUT
TJUNC
2-wire
Interface
VBAT
TBAT
VSYS
VBUS
IBUS
Charging
Control
ADC
IBATM
IBAT
Current Bat.
Sensing Sw.
IBATM
IBATS
IBAT
VBAT
Sensing
NTC
Current
Sensing
I2C
VDDIO
SCL
SDA
SoC
Figure 10: System Level Block Diagram
9.1 Current Doubler
The current doubler operates with a fixed duty cycle. Under no-load condition, the output voltage is
half of the input voltage. When a current IOUT is drawn at the VOUT node and the current doubler is
switching at an fSW frequency, the output voltage is determined as:
V
IN
2
V
=
− R
* I
EQ OUT
OUT
REQ is a function of the sum of all resistances in the input/output power path (including the power
device’s on-resistance and the PCB routing resistance) as well as the switching frequency, CFLY
and PCB parasitics.
The dual phase interleaved operation ensures an almost constant input current, thereby highly
improving the application design against noise.
The voltage ripple at VOUT can be first order approximated as the voltage drop due to the discharge of
the CFLY capacitor in half of the period at an fSW switching frequency, plus the discharge voltage of
the output VOUT capacitor during a typical 5 ns short dead time for phase switch.
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
23 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Selecting a good CFLY capacitor is a key factor for a well performing current doubler. Increasing the
switching frequency and the VOUT capacitors to compensate for the DC bias degradation of CFLY may
both result in a worse efficiency. For a list of suggested external components see Table 12.
9.1.1
Reverse Current Protection
RCP is enabled whenever DA9318L/M is not in the ACTIVE mode. The current doubler blocks
current flow from IN to OUT and from OUT to IN. In this mode, the C1P and C2P terminals are
floating.
9.1.2
Switching Frequency
In normal conditions the switching frequency of the current doubler is static and it is defined by the
CP_FREQ register bits.
9.1.3
Start-Up
The current doubler is capable of starting up when VIN is within the accepted range defined by
VIN2OUT_MIN and VIN2OUT_MAX. If VIN is not within the accepted range during start-up, the start-up is
aborted and an event is triggered (E_VIN2OUT_MIN or E_VIN2OUT_MAX).
Resuming normal operation after a start-up fault requires that VIN is within the accepted range and
the event is cleared.
9.1.4
Current Limit
The maximum continuous output current of the current doubler is IOUT_MAX. In addition, individual
switching FETs are protected with cycle-by-cycle peak current limit of ILIM_PK. The configurable
integrated current limit is aimed to protect DA9318L/M power stages and the external components
from excessive current.
When hitting the current limit, a timer is started. If the current limit is exceeded for longer than
tDEGLITCH_ILIM_PK, the current doubler is disabled and an event E_ILIM_OC_CRIT is triggered.
9.1.5
Input-to-Output Voltage Protection
DA9318L/M features an input-to-output voltage protection described in section 9.3.3. The protection
is used to automatically disable the current doubler when the input-to-output voltage ratio is out of the
accepted range defined by VIN2OUT_MIN and VIN2OUT_MAX. When the either of these thresholds is
crossed during current doubler operation an event, E_VIN2OUT_MIN or E_VIN2OUT_MAX, is
triggered and the current doubler is automatically disabled.
9.2 Travel Adaptor Detection
The detection of a travel adaptor insertion is made based on rising VIN voltage. The detection of a
travel adaptor removal is made based on falling VIN voltage.
When VIN exceeds VTHR_RISE the travel adaptor status bit S_VIN_ADP_DET is asserted and the
associated event (E_VIN_ADP_DET) is triggered. The travel adaptor status bit and the current
doubler enable are de-asserted when VIN falls below VTHR_RISE
.
9.3 Voltage Protection
Figure 11 illustrates the voltage protection, including the VIN and VBAT voltage protection levels. All
voltage protection functions have an event associated with them, which is triggered whenever the
comparator trips.
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
24 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
IN
VOUTS
VBATP
S_VIN2OUT_MAX
- +
VIN2OUT_MAX
S_VIN2OUT_MIN
- +
VIN2OUT_MIN
VBAT_OV
Setting
S_VIN_UV
S_VIN_OV
S_VBAT_OV
S_VBAT_UV
VBAT_UV
Setting
AVDD
VBATN
VREF
Figure 11: Voltage Protection
9.3.1
Input Voltage Protection
Input voltage (VIN) protection is used for detecting the presence of an input supply and for disabling
the current doubler when VIN rises too high. Note that the current doubler is only operational when VIN
is within the range defined by VIN2OUT_MIN and VIN2OUT_MAX
.
VIN over-voltage conditions longer than tDEGLITCH_OV will disable the current doubler by disabling
CP_EN and will trigger the event E_VIN_OV. Resuming normal operation after the over-voltage
event is triggered requires that the event is cleared and that the current doubler is re-enabled either
by writing CP_EN or by asserting the nCPEN signal.
Under-voltage conditions longer than tDEGLITCH_UV will disable the current doubler by disabling CP_EN
and trigger the event E_VIN_UV. Resuming normal operation after the under-voltage event is
triggered requires that the event is cleared and that the current doubler is re-enabled either by writing
CP_EN or by asserting the nCPEN signal.
The adaptor detection is made by comparing VIN to a threshold VTHR_RISE. If VIN is above VTHR_RISE, a
supply is assumed to be detected. When VIN falls under the VTHR_RISE – VTHR_HYS, an event E_VIN_UV
is triggered and a pull-down resistor (RPD) is activated. Note that VTHR_RISE is not enough to start the
current doubler, see section 9.1.3. Once the adaptor detection is successful, the threshold of the
comparator is moved to VUV_RISE
.
9.3.2
Battery Voltage Protection
DA9318L/M features differential sense inputs for the battery voltage. The battery voltage is monitored
before enabling the current doubler and during current doubler operation to detect over-voltage and
under-voltage conditions.
Over-voltage conditions longer than tDEGLITCH_OV will disable the current doubler by clearing the
CP_EN register and trigger the event E_VBAT_OV. A 20 kΩ pull-down is applied on the OUT pin as
long as the status bit S_VBAT_OV remains asserted. Resuming normal operation after the over-
voltage event is triggered requires that the event is cleared and that the current doubler is re-enabled
either by writing CP_EN or by asserting the nCPEN signal.
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
25 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Under-voltage conditions longer than tDEGLITCH_UV will disable the current doubler and trigger the event
E_VBAT_UV. Starting the current doubler requires that the event is cleared and that the current
doubler is re-enabled either by writing CP_EN or by asserting the nCPEN signal.
In addition to battery over-voltage and under-voltage, DA9318L/M features a battery voltage
protection based on the ADC results. In the continuous mode of the ADC converter, the result on the
VBAT channel (ADC_VBATT_RESULT) is compared against the threshold programmed in the
VBAT_WARN_THRSH register bits. If the measurement exceeds the threshold, an event
E_VBAT_WARN is triggered. The battery voltage warnings are only enabled in the continuous mode
of the ADC and when the VBAT_WARN_THRSH register bits are programmed with a non-zero
value.
9.3.3
Input to Output Voltage Protection
The purpose of the input to output voltage (VIN2OUT) protection is to detect when the input-to-output
voltage ratio is suitable for the current doubler operation, see section 9.1.5.
Fault conditions lasting longer than tDEGLITCH will disable the current doubler by clearing the CP_EN
register bit and trigger the event E_VIN2OUT_MIN or E_VIN2OUT_MAX. Resuming normal
operation after an event is triggered requires that the event is cleared and that the current doubler is
re-enabled either by writing CP_EN or by asserting the nCPEN signal.
9.4 Current Sensing
DA9318L/M features input and output current reporting based on the internal current sense. The
current sense information is sampled by the ADC and reported via registers ADC_IIN_RESULT and
ADC_IOUT_RESULT. The input and output current sensing does not require an external shunt
resistor. Table 10 defines the range and precision for current sensing.
9.4.1
Over-Current Monitoring
DA9318L/M features a programmable over-current monitoring that uses the ADC reading of the input
current to detect an over-current condition. The monitoring value can be programmed in the
IIN_OC_THRSH register bits. The conversion result (reported via the ADC_IIN_RESULT register
bits) is compared to the IIN_OC_THRSH value and an over-current event (E_IIN_OC) is triggered if
the measurement value exceeds the threshold. The over-current fault can be configured to either
trigger the event, or to trigger the event and clear the current doubler enable (CP_EN). The over-
current monitoring is only enabled in the continuous mode of the ADC (ADC_AUTO_CNVRT = 1)
and if IIN_OC_THRSH is programmed with a non-zero value.
9.5 Junction Temperature Monitoring
To protect DA9318L/M from damage due to excessive power dissipation the junction temperature
(TJUNC) is monitored continuously. The monitoring is split into three temperature ranges TWARN
(programmable via TJUNC_WARN_THRSH from 70 °C to 125 °C), TCRIT (140 °C), and TPOR
(150 °C).
The first level monitoring (TWARN) is implemented by using the ADC. If the junction temperature rises
above the first threshold (TWARN), the event E_TJUNC_WARN is asserted. If the event is not masked,
this will trigger an interrupt. This first level of temperature supervision is intended for non-invasive
temperature control, where the necessary measures for cooling the system down are left to the host
software. The status of the TWARN comparator can be read from S_TJUNC_WARN. An interrupt is
generated when the temperature crosses the threshold from low to high, or from high to low. After the
interrupt, the application processor can read out the comparator status to detect when the
temperature drops below the threshold.
The second level monitoring (TCRIT) is implemented with a comparator. If the junction temperature
continues to rise and crosses the second threshold (TCRIT), an event is triggered (E_TJUNC_CRIT)
and DA9318L/M moves to the IDLE mode. Resuming normal operation requires that the junction
temperature drops below TCRIT
.
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
26 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
The third level monitoring (TPOR) is implemented with a comparator. Crossing the third threshold
causes DA9318L/M to enter SHUTDOWN mode. DA9318L/M stays in SHUTDOWN mode as long as
the junction temperature is above TCRIT
.
9.6 ADC
DA9318L/M features an 8-bit ADC that can be used to monitor VIN, IIN, VBAT, IOUT, and TJUNC. Table 20
summarizes the ADC channels. The ADC is enabled in IDLE and ACTIVE modes. It features two
operational modes: continuous and single shot.
By default, the ADC runs in the continuous mode (ADC_AUTO_CNVRT = 1). In this mode, the ADC
runs continuously through its channels and updates the results registers (ADC_RES_x). The number
of conversions averaged for each result can be controlled using the ADC_AVERAGE register bits. An
event (E_ADC_DONE) is triggered only once in the continuous mode, when the first results are
ready after enabling the ADC or starting the continuous mode.
Measurements can also be taken in single shot mode (ADC_AUTO_CNVRT = 0) via the 2-wire
interface by writing 1 to the ADC_SINGLE_CNVRT register bit. Once a conversion is initiated, the
result register (ADC_RES_x) of each channel is updated using the averaging set in the
ADC_AVERAGE register bits. Once the measurement is done, an event is triggered
(E_ADC_DONE) and the measurement of each channel can be read out from the result registers.
Table 20: ADC Channels
Channel Parameter Description
Range
Equation
1
2
3
VIN
VBAT
IIN
Input voltage
5.5 V to VIN = (ADC_VIN_RESULT - 16) * (8.5 / 224) + 5.5
14 V
Battery voltage
2.4 V to VBAT = (ADC_VBATT_RESULT - 16) * (3.1 / 224) + 2.4
5.5 V
Input current
DA9318L
500 mA IIN = (ADC_IIN_RESULT - 16) * (3.6 / 224) + 0.5
to 4.1 A
Input current
DA9318M
500 mA IIN = (ADC_IIN_RESULT - 16) * (4.6 / 224) + 0.5
to 5.1 A
4
IOUT
Output current
DA9318L
1 A to
8.2 A
IOUT = (ADC_IOUT_RESULT - 16) * (7.2 / 224) + 1
Output current
DA9318M
1 A to
10.2 A
IOUT = (ADC_IOUT_RESULT - 16) * (9.2 / 224) + 1
5
6
VOUT
Output voltage
2.4 V to VOUT = (ADC_VOUT_RESULT - 16 ) * (3.1 / 224 ) + 2.4
5.5 V
(VOUTS
)
TJUNC
Junction
temperature
0 °C to
255 °C
TJUNC = ADC_TJUNC_RESULT
9.7 Safety Timer
A safety timer is running whenever DA9318L/M is in ACTIVE mode. The purpose of the safety timer
is to detect a condition where the battery does not react to charging as expected. For example, if the
voltage of the battery does not rise during constant current charging it is likely that the battery is
damaged. This condition is detected by the safety timer.
The safety timer is automatically enabled whenever DA9318L/M moves to the ACTIVE mode. If the
safety timer expires an event is triggered (E_SAFETY_TIMER) and CP_EN is cleared. Note that the
safety timer count is only reset by writing the SAFETY_TIMER_LOAD register. The
SAFETY_TIMER_LOAD register should be written before the start of a new charging cycle.
Restarting the current doubler after a safety timeout requires that the timeout event is cleared and
that the CP_EN bit is asserted.
The following conditions will disable the safety timer:
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
27 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
●
●
VIN supply removal
Other fault condition (VOV_ACT, VUV_RISE, VBAT_OV_THRSH, VBAT_UV_THRSH, TCRIT
)
9.8 Watchdog Timer
DA9318L/M features a watchdog timer that is intended to monitor the host software during charging
and disable the charger in the event of system malfunction. Some of the automatic charging features
of DA9318L/M, such as battery temperature profiling, can be disabled and implemented in software
instead. Moving the control to software requires tighter supervision than is provided by the charging
timer, therefore a separate watchdog timer is provided.
Whenever the charger is enabled, the watchdog timer is loaded (via I2C) with a pre-programmed
value (WD_TIMER_LOAD) which starts decrementing. In normal operation the application processor
should periodically re-initialize the safety timer by writing a new value to the WD_TIMER_LOAD
register bits. The value of the counter can be read from the WD_TIMER_COUNT register bits.
However, if the timer reaches zero an event (E_WD) is asserted and the charger is automatically
disabled.
The following conditions will disable the watchdog timer:
●
●
VIN supply removal
Other fault condition (VOV_ACT, VUV_RISE, VBAT_OV_THRSH, VBAT_UV_THRSH, TCRIT
)
9.9 Control Interface
All the output signals of DA9318L/M are driven with an open drain stage. The signals have to be
pulled up with external resistors to an IO supply. The inputs are compared to internally generated
references VIH and VIL to detect the high and low levels of the signals, respectively. Figure 12 depicts
the structure of the control signals.
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
28 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
nIRQ
nFAULT
VIH
-
+
SDA
+
-
VIL
VIH
-
+
nCPEN
+
-
VIL
Figure 12: Control Signals
9.9.1
PWREN
PWREN is a master enable for the DA9318L/M internal blocks and 2-wire interface. It is used to
minimize the power consumption of DA9318L/M during NO-POWER mode of the system. It can be
tied to a supply rail driven by the PMIC to allow DA9318L/M enter NO-POWER mode whenever the
PMIC powers down.
9.9.2
nCPEN
nCPEN is an edge sensitive, active low, chip enable signal. It works in conjunction with the CP_EN
register bit. A falling edge of nCPEN sets the CP_EN register bit and a rising edge clears it. The
current doubler can be started by asserting the nCPEN pin or by writing to CP_EN. The current
doubler can be stopped by de-asserting the nCPEN pin or by writing to CP_EN.
9.9.3
nFAULT
nFAULT is an active low, open drain, status output. The assertion of any of the following status bits
results in the assertion of nFAULT:
●
●
●
●
●
●
●
S_VIN_OV
S_VIN_UV
S_VBAT_OV
S_VBAT_UV
S_VIN2OUT_MAX
S_VIN2OUT_MIN
S_TJUNC_CRIT
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
29 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
●
●
S_IIN_OC
S_VBAT_WARN
The removal of the fault condition results in the de-assertion of nFAULT. The minimum length of
nFAULT assertion is tFLT_MIN. This will ensure that the signal passes through the deglitch filter and
synchronizer in the receiving end.
S_VIN_OV
S_VIN_UV
nFAULT
S_VBAT_OV
S_VBAT_UV
Min pulse
(tFLT_MIN)
S_VIN2OUT_MIN
OR
S_VIN2OUT_MAX
S_TJUNC_CRIT
S_IIN_OC
S_VBAT_WARN
S_RAMPUP_FAULT
Figure 13: nFAULT Operation
9.9.4
nIRQ
nIRQ is a level sensitive, active low, interrupt signal. The assertion of an unmasked event results in
the assertion of nIRQ. The nIRQ will not be released until all event registers have been cleared. New
events that occur during an event register read will be held until the event register has been cleared,
ensuring that the host processor does not miss them. By default all mask bits are asserted.
Several sources can generate some events, as depicted in Figure 14. After receiving an interrupt, the
source can be detected by reading the associated status registers.
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
30 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
S_VBAT_OV
S_VBAT_UV
S_VIN_OV
E_VBAT_OV
M_VBAT_OV
E_VBAT_UV
M_VBAT_UV
E_VIN_OV
AND
AND
AND
AND
M_VIN_OV
E_VIN_UV
S_VIN_UV
M_VIN_UV
S_ADP_DET
E_ADP_DET
M_ADP_DET
AND
S_ILIM_WARN
S_RAMPUP_FAULT
S_TJUNC_CRIT
S_TJUNC_WARN
E_ILIM_WARN
M_ILIM_WARN
AND
AND
E_RAMPUP_FAULT
M_RAMPUP_FAULT
E_TJUNC_CRIT
M_TJUNC_CRIT
E_TJUNC_WARN
M_TJUNC_WARN
AND
AND
nIRQ
OR
S_VIN2OUT_MAX
S_VIN2OUT_MIN
S_IIN_OC
E_VIN2OUT_MAX
M_VIN2OUT_MAX
E_VIN2OUT_MIN
M_VIN2OUT_MIN
E_IIN_OC
AND
AND
AND
AND
AND
AND
AND
AND
AND
M_IIN_OC
S_VBAT_WARN
E_VBAT_WARN
M_VBAT_WARN
E_ADC_DONE
M_ADC_DONE
E_SAFETY_TIMER
M_SAFETY_TIMER
E_WD
M_WD
E_ILIM_CRIT
M_ILIM_CRIT
E_TJUNC_POR
M_TJUNC_POR
Figure 14: Interrupt Logic
9.10 2-Wire Interface
The 2-wire interface provides access to control and status registers. The interface supports
operations compatible to Standard, Fast, Fast+ and High-speed mode of the I2C bus specification [6].
Table 21 lists the slave addresses of DA9318L/M.
Table 21: Interface Slave Address.
Device
7-bit Slave Address
8-bit Slave Address
DA9318L/M
0x59
0xB2 (write), 0xB3 (read)
Communication on the 2-wire bus is always between two devices, one acting as the master and the
other as the slave. DA9318L/M will only operate as a slave.
SCL carries the 2-wire clock and SDA carries the bidirectional data. The 2-wire interface is open
drain, supporting multiple devices on a single line. The bus lines have to be pulled high by external
pull-up resistors (2 kΩ to 20 kΩ). These are often shared between multiple devices connected to the
interface. The attached devices only drive the bus lines low by connecting them to ground. As a
result, two devices cannot conflict if they drive the bus simultaneously.
In Standard/Fast mode the highest frequency of the bus is 400 kHz. The exact frequency can be
determined by the application and it does not have any relation to the DA9318L/M internal clock
signals. DA9318L/M will follow the host clock speed within the described limitations and does not
initiate any clock arbitration or slow down. An automatic interface reset can be triggered in case the
clock signal ceases to toggle for > 35 ms (controlled in I2C_TO_EN).
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
31 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Bus clear, if the SDA is stuck, is achieved after receiving nine clock pulses. Operation in High-speed
mode at 3.4 MHz requires a minimum interface supply voltage of 1.8 V and a mode change in order
to enable spike suppression and slope control characteristics compatible to the I2C specification. The
High-speed mode can be enabled on a transfer-by-transfer basis by sending the master code (0000
1XXX) at the beginning of the transfer. DA9318L/M does not make a use of clock stretching and
delivers read data without additional delay up to 3.4 MHz.
Alternatively the interface can be configured to use High-speed mode continuously via I2C_IF_HSM,
so that the master code is not required at the beginning of every transfer. This reduces
communication overhead on the bus, but limits the attachable bus slaves to compatible devices.
9.10.1 Details of the 2-Wire Protocol
All data is transmitted across the 2-wire bus in 8-bit groups. To send a bit the SDA line is driven at
the intended state while the SCL is low. Once the SDA has settled, the SCL line is brought high and
then low. This pulse on SCL clocks the SDA bit into the receiver’s shift register.
A two byte serial protocol is used containing one address byte and one data byte. Data and address
transfer is transmitted MSB first for both read and write operations. All transmission begins with the
START condition from the master during which the bus is in IDLE mode (the bus is free). It is initiated
by a high-to-low transition on the SDA line, while the SCL is in the high state. A low-to-high transition
on the SDA line, while the SCL is in the high state, indicates a STOP condition. Figure 15 illustrates
the START and STOP conditions.
SDA
SCL
START
Transaction
STOP
Figure 15: START and STOP Condition Timing
The 2-wire bus will be monitored by DA9318L/M for a valid slave address whenever the interface is
enabled. It responds immediately when it receives its own slave address. This is acknowledged by
pulling the SDA line low during the following clock cycle (white blocks marked with A in the following
figures).
The protocol for a register write from master to slave consists of a START condition, a slave address,
a read/write-bit, 8-bit address, 8-bit data, and a STOP condition. DA9318L/M responds to all bytes
with an A. Figure 16 illustrates a register write operation.
P
S
SLAVEadr
7-bits
W
A
REGadr
8-bits
A
DATA
8-bits
A
1-bit
Master to Slave
Slave to Master
S = START condition
P = STOP condition
A = Acknowledge (low)
W = Write (low)
Figure 16: Byte Write
When the host reads data from a register it first has to write access DA9318L/M the target register
address and then read access DA9318L/M with a Repeated START, or alternatively a second
START, condition. After receiving the data, the host sends No Acknowledge and terminates the
transmission with a STOP condition, see Figure 17.
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
32 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
A*
P
S
SLAVEadr W
7-bits 1-bit
A
REGadr A Sr SLAVEadr
R
A
DATA
8-bits
1-bit
8-bits
7-bits
S
SLAVEadr W
7-bits 1-bit
A
REGadr
8-bits
A
P
S
SLAVEadr
R
A
DATA
8-bits
A*
P
7-bits 1-bit
Master to Slave
Slave to Master
S = START condition
Sr = Repeated START condition
P = STOP condition
A = Acknowledge (low)
A* = No Acknowledge
W = Write (low)
R = Read (high)
Figure 17: Byte Read
Consecutive (page) read-out mode is initiated from the master by sending an A instead of No
Acknowledge after receiving a byte, see Figure 18. The 2-wire control block then increments the
address pointer to the next register addresses and sends the data to the master. This enables an
unlimited read of data bytes until the master sends No Acknowledge directly after receiving the data,
followed by a subsequent STOP condition. If a non-existent 2-wire address is read out then
DA9318L/M will return code zero.
A*
P
S
SLAVEadr
W
A
REGadr
8-bits
A
Sr SLAVEadr
R
A
DATA
8-bits
A
DATA
8-bits
A
DATA
8-bits
7-bits
1 bit
7-bits 1-bit
S
SLAVEadr
W
A
REGadr
A
P
S
SLAVEadr
R
A
DATA
8-bits
A
DATA
8-bits
A*
P
7-bits
8-bits
7-bits 1-bit
1-bit
Master to Slave
Slave to Master
A
S = START condition
= Acknowledge (low)
Sr = Repeat START condition
P = STOP condition
A* = No Acknowledge
W = Write (low)
R = Read (high)
Figure 18: Page Read
The slave address after the Repeated START condition must be the same as the previous slave
address.
Consecutive (page) write mode is supported if the master sends several data bytes following a slave
register address. The 2-wire control block then increments the address pointer to the next 2-wire
address, stores the received data, and sends an A until the master sends a STOP condition.
Figure 19 illustrates the page write mode.
S
SLAVEadr
W
A
REGadr
8-bits
A
DATA
A
DATA
8-bits
A
DATA
8-bits
A
……….
Repeated writes
A
P
7-bits 1 bit
8-bits 1-bit
Master to Slave
Slave to Master
A
S = START condition
= Acknowledge (low)
Sr = Repeat START condition
P = STOP condition
A* = No Acknowledge
W = Write (low)
R = Read (high)
Figure 19: Page Write
Via control WRITE_MODE, a repeated write mode can be enabled. In this mode, the master can
execute back-to-back write operations to non-consecutive addresses. This is achieved by
transmitting register address and data pairs. The data will be stored in the address specified by the
preceding byte. Figure 20 illustrates the repeated write mode.
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
33 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
S
SLAVEadr
W
A
REGadr
8-bits
A
DATA
A
REGadr
8-bits
A
DATA
8-bits
A
……….
Repeated writes
A
P
7-bits 1 bit
8-bits 1-bit
Master to Slave
Slave to Master
A
S = START condition
= Acknowledge (low)
Sr = Repeat START condition
P = STOP condition
A* = No Acknowledge
W = Write (low)
R = Read (high)
Figure 20: Repeated Write
If a new START or STOP condition occurs within a message, the bus will return to IDLE mode.
9.11 Internal Supplies
The internal supply of DA9318L/M is illustrated in Figure 21, the AVDD regulator is powered from IN
and SYS.
IN
4.5 V to 13.5 V
2.5 V to 5.5 V
SYS
AVDD
AVDD
LDO
CAVDD
POR
AGND
Figure 21: Internal Supply
9.11.1 AVDD
AVDD is an internal supply that is powered from the higher of IN and SYS. During current doubler
operation the input supply to the AVDD regulator is IN and the output voltage is 4 V. If IN is not
supplied, the input supply to the AVDD regulator is SYS. If VSYS is not high enough to supply the
normal 4 V, the pass device of the AVDD regulator operates as a switch. DA9318L/M remains
operational as long as VAVDD is above the POR threshold VPOR_FALL
.
9.12 Internal Oscillator
The internal high-speed oscillator generates a signal at fOSC, the internal 6 MHz clock reference. In
the IDLE_LP mode the oscillator goes in to a low-power state and changes the frequency to 1 MHz.
9.13 Power Modes
Figure 22 illustrates the power modes of DA9318L/M. The following transitions are high priority and
override other transitions in the diagram:
●
●
●
●
Critical junction temperature (TJUNC > TCRIT
)
Transition to IDLE mode
Missing supply (VAVDD < VPOR_FALL
Transition to NO-POWER mode
)
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
34 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
NO-POWER
SHUTDOWN
VAVDD < VPOR ||
! PWREN
VAVDD > VPOR_RISE &&
PWREN
TJUNC > TPOR
Active functions:
Active functions:
·
·
·
·
·
AVDD
RCP
2-wire interface
nFAULT, nIRQ
Adaptor detection
·
·
·
AVDD
POR monitoring
RCP
All states
All states
VTHR_RISE
INIT
TJUNC < TCRIT
CP_EN &&
! VIN2OUT_MIN &&
! VIN2OUT_MAX &&
! VUV_RISE &&
! VIN_OV &&
! VBAT_UV &&
! VBAT_OV &&
TJUNC < TCRIT
IDLE_LP
IDLE
Active functions:
ACTIVE
Active functions:
AVDD
Active functions:
Current doubler
AVDD
·
·
·
·
·
·
·
·
·
·
AVDD
RCP
2-wire interface
nFAULT, nIRQ
Adapter detach
detection
·
·
·
·
·
·
EN_IDLE_LP &&
VUV_RISE &&
RCP
2-wire interface
nFAULT, nIRQ
Adapter detection
RCP
! VTHR_RISE
2-wire interface
nFAULT, nIRQ
Adapter detach
detection
TJUNC monitoring
VIN protection
VIN2OUT protection
VBAT protection
ADC
! EN_IDLE_LP ||
! CP_EN ||
VIN2OUT_MIN ||
VIN2OUT_MAX ||
VUV_RISE ||
·
·
·
·
·
TJUNC monitoring
VIN protection
VIN2OUT protection
VBAT protection
ADC
VTHR_RISE ||
CP_EN
·
·
·
·
·
·
·
VIN_OV ||
VBAT_UV ||
VBAT_OV ||
IIN sensing
IOUT sensing
TJUNC > TCRIT
Figure 22: Power Modes
9.13.1 NO-POWER Mode
DA9318L/M is in NO-POWER mode when VAVDD is below the VPOR_RISE threshold. RCP is active, as
described in section 9.1.1. When IN or SYS is supplied and PWREN is de-asserted, the internal
supply AVDD is automatically enabled and when VAVDD rises above the VPOR_RISE threshold,
DA9318L/M moves to the INIT (initialization) mode.
9.13.2 SHUTDOWN Mode
The SHUTDOWN mode activates the internal oscillator, adaptor detection, 2-wire interface, and
output signals. The 2-wire interface is operational, but as the initialization is not completed, all
registers will return their power-on-reset values. Transition to INIT mode is triggered when a travel
adaptor is detected.
9.13.3 INITIALIZATION Mode
In the INIT mode, the internal reference, oscillator, and clock generator are enabled. RCP is active,
as described in section 9.1.1. DA9318L/M goes through a full initialization including an OTP read.
After the initialization is complete, the status registers and events are updated to match the status of
the internal protections. The junction temperature is checked, and if it is below the critical level
(TCRIT), DA9318L/M moves automatically to the IDLE mode.
9.13.4 IDLE Mode
In the IDLE mode DA9318L/M is fully operational but the current doubler is not enabled. RCP is
active, as described in section 9.1.1.
If the current doubler is enabled (CP_EN = 1), DA9318L/M enables monitoring features and
evaluates the conditions for start-up:
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
35 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
●
●
●
●
Junction over-temperature (junction temperature exceeds TCRIT
Output voltage (VBAT_UV_THRSH < VBAT < VBAT_OV_THRSH)
Input voltage (VUV_RISE < VIN < VOV_ACT
Input to output voltage (VIN2OUT_MIN, VIN2OUT_MAX
)
)
)
If the conditions are met, DA9318L/M soft-starts the current doubler and moves to the ACTIVE mode.
If IN is not supplied, the current doubler is disabled (EN_IDLE_LP = 1) and DA9318L/M moves to the
LOW-POWER IDLE mode.
9.13.4.1
LOW-POWER IDLE Mode
The LOW-POWER IDLE (IDLE_LP) mode is a low power sub-mode of the IDLE mode. In IDLE mode
DA9318L/M is fully operational but the current doubler is not enabled. RCP is active, as described in
section 9.1.1. In IDLE-LP mode, most DA9318L/M features are disabled in order to minimize the
quiescent current. The only active functions are the AVDD regulator, which ensures the preservation
of the logic state, the VTHR_RISE monitoring which detects the assertion of a travel adaptor, and the 2-
wire interface. RCP is active.
The reduced functionality has the consequence that the status bits in the register map are not
automatically updated. Otherwise, IDLE-LP mode is transparent to the system. DA9318L/M reacts
identically to register writes and external events in both modes.
A transition to IDLE mode is triggered if an input supply is attached and the current doubler is
enabled.
The transition to IDLE-LP mode can be also controlled with the EN_IDLE_LP bit. By writing
EN_IDLE_LP = 0, DA9318L/M never transitions to IDLE-LP mode. If already in IDLE-LP mode,
writing EN_IDLE_LP = 0 triggers a transition to IDLE mode.
9.13.5 ACTIVE Mode
In ACTIVE mode the current doubler is enabled. DA9318L/M moves back to IDLE mode in any of the
following circumstances:
●
●
●
●
The current doubler is disabled (CP_EN = 0)
The input supply is outside the supported range
The junction temperature exceeds the critical threshold
The battery voltage is outside the supported range
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
36 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
9.14 Status Flags
The status flags are listed Table 22.
Table 22: Status Flags
Flag
Description
Assert
De-assert
CHARGER
_STATE
Mode of DA9318L/M:
Automatically updated whenever the state machine changes state.
All lower-level states should be mapped to one of the four modes.
000: SHUTDOWN and/or
INIT
001: IDLE
010: IDLE_LP
011: Reserved
100: ACTIVE
S_VBAT_O VBAT over-voltage
comparator status
VBAT exceeds VBAT_OV_THRSH
for longer than tDEGLITCH_OV
VBAT falls below
VBAT_OV_THRSH -
VBAT_PROT_HYS
V
S_VBAT_U VBAT under-voltage
VBAT drops below
VBAT_UV_THRSH for longer than
tDEGLITCH_UV
VBAT rises above
VBAT_UV_THRSH +
VBAT_PROT_HYS
V
comparator status
S_VIN_OV
VIN over-voltage
comparator status
VIN exceeds VOV_IDLE for longer than
tDEGLITCH_OV
VIN falls below VOV_IDLE
VPROT_HYS
–
S_VIN_UV
VIN under-voltage
comparator status
VIN drops below VUV_FALL/RISE
VPROT_HYS for longer than tDEGLITCH_UV
-
VIN rises above VUV_FALL/RISE
S_VIN_AD
P_DET
Adaptor detection
comparator status
VIN rises above VTHR_RISE for longer
than tDEGLITCH_UV
VIN drops below VTHR_RISE
VPROT_HYS
-
S_TJUNC_ TCRIT comparator status
CRIT
TJUNC rises above TCRIT
TJUNC drops below TCRIT
TCRIT_HYS
-
S_TJUNC_ TWARN comparator status
WARN
TJUNC rises above
TJUNC_WARN_THRSH
TJUNC drops below
TJUNC_WARN_THRSH -
TWARN_HYS
S_VIN2OU
T_MAX
VIN/2-VOUT comparator
status
VIN/2 - VOUT rises above VIN2OUT_MAX
for longer than tDEGLITCH
VIN/2-VOUT drops below
VIN2OUT_MAX - VIN2OUT_HYS
S_VIN2OU
T_MIN
VIN/2 - VOUT comparator
status
VIN/2 - VOUT falls below VIN2OUT_MIN
for longer than tDEGLITCH
VIN/2 - VOUT rises above
VIN2OUT_MIN + VIN2OUT_HYS
S_IIN_OC
IIN over-current status
The ADC is in the continuous
measurement mode, the value
programmed in IIN_OC_THRSH is
non-zero, and the ADC result of the
IIN channel is greater than or equal
to IIN_OC_THRSH
The ADC result of the IIN
channel is less than
IIN_OC_THRSH
S_VBAT_
WARN
VBAT monitoring status
The ADC is in the continuous
measurement mode, the value
programmed in
ADC result of the VBAT
channel is greater or smaller
than VBAT_WARN_THRSH
VBAT_WARN_THRSH is non-zero,
and the ADC result of the VBAT
channel is greater than or equal to
VBAT_WARN_THRSH
S_ILIM_OC 80 % of ILIM_PK current
The current exceeds 80 % of ILIM_PK
(set by CP_ILIM) for longer than
tDEGLITCH_ILIM_PK
The current decreases below
80 % of ILIM_PK longer than
tDEGLITCH_ILIM_PK
_WARN
protection warning status
S_RAMPU
P_FAULT
Current doubler ramp-up
was unsuccessful
Current doubler ramp-up time
reached timeout
Current doubler ramped
down and the system goes
back to IDLE
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
37 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
10 Register Definition
Table 23: Register Overview
Status and Events
Register
Addr POR
7
6
5
4
3
2
1
0
S_VIN_ADP_D
ET
STATUS_A
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x00 S_VBAT_OV
S_VBAT_UV
S_VIN_OV
S_VIN_UV
CHARGER_STATE<2:0>
S_ILIM_OC_
S_RAMPUP_F S_TJUNC_CR S_TJUNC_WA S_VIN2OUT_M S_VIN2OUT_
S_VBAT_W
ARN
STATUS_B
EVENT_A
EVENT_B
EVENT_C
MASK_A
MASK_B
MASK_C
0x00
S_IIN_OC
Reserved
E_IIN_OC
WARN
AULT
IT
RN
AX
MIN
E_VIN_ADP_D
ET
0x00 E_VBAT_OV
E_VBAT_UV
E_VIN_OV
E_VIN_UV
Reserved
Reserved
E_ILIM_OC_
E_RAMPUP_F E_TJUNC_CR E_TJUNC_WA E_VIN2OUT_M E_VIN2OUT_
E_VBAT_W
ARN
0x00
WARN
AULT
IT
RN
AX
MIN
E_SAFETY_TI
MER
E_ILIM_OC_C E_TJUNC_
0x00 Reserved
Reserved
Reserved
E_ADC_DONE
E_WD
RIT
POR
M_VIN_ADP_D
ET
0xF0 M_VBAT_OV
M_VBAT_UV
M_VIN_OV
M_VIN_UV
Reserved
Reserved
Reserved
M_ILIM_OC_
M_RAMPUP_F M_TJUNC_C
M_TJUNC_WA M_VIN2OUT_
M_VIN2OUT_
MIN
M_VBAT_W
ARN
0xFF
M_IIN_OC
WARN
AULT
RIT
RN
MAX
M_SAFETY_TI
MER
M_ILIM_OC_C M_TJUNC_
0x1F Reserved
Reserved
Reserved
M_ADC_DONE
M_WD
RIT
POR
Voltage Protections
Register
Addr POR
7
6
5
5
4
3
2
1
0
VBAT_OV_THRSH<5:0>
VBAT_CTR
L_A
0x08
0xF3
VBAT_UV_THRSH<1:0>
Current and Voltage Monitoring ( ADC)
Register
Addr POR
7
6
4
3
2
1
0
VBAT_CTRL
_B
0x09
0xFF VBAT_WARN_THRSH<7:0>
IIN_CTRL_A 0x0A 0xD9 IIN_OC_THRSH<7:0>
Current Doubler
Register
Addr POR
7
6
5
4
3
2
1
0
CP_CTRL_
A
CP_SWITCHIN
G
0x0B
0x0C
0x10
Reserved
CP_FREQ<1:0>
Reserved
Reserved
Reserved
CP_EN
CP_CTRL_
B
0x0F Reserved
Reserved
Reserved
Reserved
CP_ILIM<3:0>
Junction Temperature Monitoring
Register
Add POR
7
6
5
4
3
2
1
0
TJUNC_CT
RL_A
0x0D 0x01
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TJUNC_WARN_THRSH<1:0>
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
38 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
ADC
Register
Addr
POR
7
6
5
4
3
2
1
0
ADC_AUTO_
CNVRT
ADC_SINGL
E_CNVRT
ADC_CTRL_A 0x0E
0x0E Reserved
Reserved
Reserved
Reserved
ADC_AVERAGE<1:0>
ADC_RES_0
ADC_RES_1
ADC_RES_2
ADC_RES_3
ADC_RES_4
ADC_RES_5
0x0F
0x10
0x11
0x12
0x13
0x14
0x00 ADC_VIN_RESULT<7:0>
0x00 ADC_VBATT_RESULT<7:0>
0x00 ADC_IIN_RESULT<7:0>
0x00 ADC_IOUT_RESULT<7:0>
0x00 ADC_TJUNC_RESULT<7:0>
0x00 ADC_VOUT_RESULT<7:0>
Interface Control
Register
Addr
0x15
0x16
POR
7
6
5
4
3
2
1
0
WRITE_MOD
E
I2C_CTRL_A
I2C_CTRL_B
0x02 Reserved
Reserved
Reserved
Reserved
Reserved
I2C_TO_EN
I2C_IF_HSM
Reserved
0xB2 IF_BASE_ADDR1<6:0>
Watchdog and Safety Timers
Register
Addr
POR
7
6
5
4
3
2
1
0
WATCHDOG_ SAFETY_TIM
TIMER_EN ER_EN
CONFIG_A
0x17
0x01 Reserved
0x01 Reserved
Reserved
Reserved
Reserved
Reserved
EN_IDLE_LP
TIMER_CTRL
_A
0x18
0x19
0x1A
0x1B
Reserved
Reserved
Reserved
SAFETY_TIMER_LOAD<3:0>
TIMER_CTRL
_B
0xFF WD_TIMER_LOAD<7:0>
0x00 WD_TIMER_COUNT<7:0>
WD_TIMER_
COUNT
SAFETY_TIM
ER_COUNT
0x00 Reserved
SAFETY_TIMER_COUNT<6:0>
10.1 Register Descriptions
10.1.1 Status and Event
Table 24: STATUS_A (0x00)
Bit Register Bits
Description
Reset
0x0
0x0
0x0
0x0
0x0
0x0
7
6
5
4
3
S_VBAT_OV
S_VBAT_UV
S_VIN_OV
VBAT over-voltage comparator status
VBAT under-voltage comparator status
VIN over-voltage comparator status
VIN under-voltage comparator status
Adaptor detection status
S_VIN_UV
S_VIN_ADP_DET
2:0 CHARGER_STATE
Mode of DA9318L/M:
000: SHUTDOWN
001: IDLE
010: IDLE_LP
011: Reserved
100: ACTIVE
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
39 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Table 25: STATUS_B (0x01)
Bit Register Bits
Description
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
7
6
5
4
3
2
1
0
S_ILIM_OC_WARN
Current protection warning status
Current doubler ramp-up was unsuccessful
TCRIT comparator status
S_RAMPUP_FAULT
S_TJUNC_CRIT
S_TJUNC_WARN
S_VIN2OUT_MAX
S_VIN2OUT_MIN
S_IIN_OC
TWARN comparator status
VIN/2 - VOUT comparator status
VIN/2 - VOUT comparator status
IIN over-current status
S_VBAT_WARN
VBAT monitoring status
Table 26: EVENT_A (0x02)
Bit Register Bits
Description
Reset
0x0
0x0
0x0
0x0
0x0
0x0
7
6
5
4
3
E_VBAT_OV
E_VBAT_UV
E_VIN_OV
VBAT over-voltage event (S_VBAT_OV)
VBAT under-voltage event (S_VBAT_UV)
VIN over-voltage event (S_VIN_OV)
VIN under-voltage event (S_VIN_UV)
Adaptor detection event (S_VIN_ADP_DET)
E_VIN_UV
E_VIN_ADP_DET
2:0 Reserved
Table 27: EVENT_B (0x03)
Bit Register Bits
Description
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
7
6
5
4
3
2
1
0
E_ILIM_OC_WARN
E_RAMPUP_FAULT
E_TJUNC_CRIT
E_TJUNC_WARN
E_VIN2OUT_MAX
E_VIN2OUT_MIN
E_IIN_OC
Current protection warning event (S_ILIM_OC_WARN)
Current doubler ramp-up failure event (S_RAMPUP_FAULT)
Junction temperature monitoring event (S_TJUNC_CRIT)
Junction temperature monitoring event (S_TJUNC_WARN)
Input-to-output voltage monitoring event (S_VIN2OUT_MAX)
Input-to-output voltage monitoring event (S_VIN2OUT_MIN)
IIN over-current event (S_IIN_OC)
E_VBAT_WARN
VBAT monitoring event (S_VBAT_WARN)
Table 28: EVENT_C (0x04)
Bit Register Bits
Description
Reset
0x0
0x0
0x0
0x0
0x0
0x0
7:5 Reserved
4
3
2
1
0
E_ADC_DONE
E_SAFETY_TIMER
E_WD
The ADC measurement was completed
The safety timer expired
The watchdog timer expired
E_ILIM_OC_CRIT
E_TJUNC_POR
The peak current limit was exceeded for longer than tDEGLITCH_ILIM_PK
Junction temperature monitoring event. Reset only in NO-POWER
mode (VAVDD < VPOR_RISE).
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
40 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Table 29: MASK_A (0x05)
Bit Register Bits
Description
Reset
0x1
7
6
5
4
3
M_VBAT_OV
M_VBAT_UV
M_VIN_OV
Masks for interrupts in EVENT_A
0x1
0x1
M_VIN_UV
0x1
M_VIN_ADP_DET
0x0
2:0 Reserved
Table 30: MASK_B (0x06)
Bit Register Bits
Description
Reset
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
7
6
5
4
3
2
1
0
M_ILIM_OC_WARN
M_RAMPUP_FAULT
M_TJUNC_CRIT
M_TJUNC_WARN
M_VIN2OUT_MAX
M_VIN2OUT_MIN
M_IIN_OC
Masks for interrupts in EVENT_B
M_VBAT_WARN
Table 31: MASK_C (0x07)
Bit Register Bits
Description
Reset
7:5 Reserved
Masks for interrupts in EVENT_C
4
3
2
1
0
M_ADC_DONE
M_SAFETY_TIMER
M_WD
0x1
0x1
0x1
0x1
0x1
M_ILIM_OC_CRIT
M_TJUNC_POR
10.1.2 Voltage Protection
Table 32: VBAT_CTRL_A (0x08)
Bit Register Bits
Description
Reset
7:2 VBAT_OV_THRSH
Battery over-voltage threshold (4.0 V to 5.5 V). The maximum value
is 5.5 V (0x3C). Any value greater than the maximum will be stored
in the register but tied to the maximum internally.
0x3C
VBAT_OV_THRSH = 4.0 + N * 0.025 V
Where N = the decimal number represented by the
VBAT_OV_THRSH setting.
1:0 VBAT_UV_THRSH
Battery under-voltage threshold (2.4 V to 3.0 V) :
0x3
00: 2.4 V
01: 2.6 V
10: 2.8 V
11: 3.0 V
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
41 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
10.1.3 Current and Voltage Monitoring
Table 33: VBAT_CTRL_B (0x09)
Bit Register Bits
Description
Reset
7:0 VBAT_WARN_THRSH
Warning threshold for the battery voltage. A value 0x0 will disable
the monitoring.
0xFF
VBAT_WARN_THRSH = 2.1784 + (N * 0.01385) V
Where N = the decimal number represented by the
VBAT_WARN_THRSH setting
Table 34: IIN_CTRL_A (0x0A)
Bit Register Bits
Description
Reset
7:0 IIN_OC_THRSH
Threshold for the input over-current. A value 0x0 will disable the
monitoring.
0xD9
10.1.4 Current Doubler
Table 35: CP_CTRL_A (0x0B)
Bit Register Bits
Description
Reset
7
6
Reserved
CP_SWITCHING
Current doubler is switching
0X0
0X1
5:4 CP_FREQ
Switching frequency of the current doubler:
00: 250 kHz
01: 500 kHz
10: 1 MHz
11: 1.5 MHz
3:1 Reserved
0
CP_EN
Main current doubler enable
0X0
Table 36: CP_CTRL_B (0x0C)
Bit Register Bits
7:4 Reserved
Description
Reset
3:0 CP_ILIM
Current doubler peak current limit (programmable in 450 mA steps):
0xF
0000: 4.8 A
1111: 11.55 A
10.1.5 Junction Temperature
Table 37: TJUNC_CTRL_A (0x0D)
Bit Register Bits
Description
Reset
7:2 Reserved
1:0 TJUNC_WARN_THRSH Threshold for junction temperature warning:
0x1
00: 70 ºC
01: 80 ºC
10: 100 ºC
11: 120 ºC
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
42 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
10.1.6 ADC
Table 38: ADC_CTRL_A (0x0E)
Bit Register Bits
7:4 Reserved
Description
Reset
3:2 ADC_AVERAGE
Defines the number of measurements that are averaged for each
ADC result. ADC_AVERAGE = 2N.
0x3
1
0
ADC_AUTO_CNVRT
ADC_SINGLE_CNVRT
Enables the continuous ADC measurements
0x1
0x0
Triggers the ADC measurement. When this bit is set during a write
access, the MSBs are ignored. When the measurement is done
(E_ADC_DONE) the results can be read from ADC_RES_x.
Table 39: ADC_RES_0 (0x0F)
Bit Register Bits
Description
Reset
7:0 ADC_VIN_RESULT
ADC VIN measurement result
0x0
Table 40: ADC_RES_1 (0x10)
Bit Register Bits
Description
Reset
7:0 ADC_VBATT_RESULT
ADC VBAT measurement result
0x0
Table 41: ADC_RES_2 (0x11)
Bit Register Bits
Description
Reset
7:0 ADC_IIN_RESULT
ADC IIN measurement result
0x0
Table 42: ADC_RES_3 (0x12)
Bit Register Bits
Description
Reset
7:0 ADC_IOUT_RESULT
ADC IOUT measurement result
0x0
Table 43: ADC_RES_4 (0x13)
Bit Register Bits
Description
Reset
7:0 ADC_TJUNC_RESULT
ADC TJUNC measurement result
0x0
Table 44: ADC_RES_5 (0x14)
Bit Register Bits
Description
Reset
7:0 ADC_VOUT_RESULT
ADC VOUT measurement result
0x0
10.1.7 Interface Control
Table 45: I2C_CTRL_A (0x15)
Bit Register Bits
Description
Reset
7:5 Reserved
4
WRITE_MODE
Write mode of the 2-wire interface:
0: Consecutive write mode
1: Repeated write mode
0x0
3:2 Reserved
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
43 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Bit Register Bits
Description
Reset
0x1
1
0
I2C_TO_EN
I2C_IF_HSM
Automatic interface reset
Interface operates continuously in High-speed mode
0x0
Table 46: I2C_CTRL_B (0x16)
Bit Register Bits
Description
Reset
7:1 IF_BASE_ADDR1
0:0 Reserved
Slave address of the device
0x59
10.1.8 Watchdog and Safety Timers
Table 47: CONFIG_A (0x17)
Bit Register Bits
Description
Reset
7:
3
Reserved
2
WATCHDOG_TIMER_E Enables the watchdog timer
N
0x0
1
0
SAFETY_TIMER_EN
EN_IDLE_LP
Enables the pre-charge / CCCV timer
Disables the LOW-POWER IDLE mode
0x0
0x1
Table 48: TIMER_CTRL_A (0x18)
Bit Register Bits
Description
Reset
7:4 Reserved
3:0 SAFETY_TIMER_LOAD Defines safety timer duration (tSFTY)
0x1
Table 49: TIMER_CTRL_B (0x19)
Bit Register Bits
Description
Reset
7:0 WD_TIMER_LOAD
Watchdog timer pre-load and re-load. Writing the register when the
charger is not enabled sets the pre-load value. The pre-load value is
automatically loaded in to WD_TIMER_COUNT the next time the
charger starts. Writing the register during charging loads the written
value in to WD_TIMER_COUNT.
0xFF
Table 50: WD_TIMER_COUNT (0x1A)
Bit Register Bits
Description
Reset
7:0 WD_TIMER_COUNT
Count value of the watchdog timer. Decremented at 1 s intervals
when charging is enabled. Reading the register gives the current
timer value. Writing the register has no affect.
0x0
Table 51: SAFETY_TIMER_COUNT (0x1B)
Bit Register Bits
Description
Reset
7
Reserved
6:
0
SAFETY_TIMER_COU
NT
Count value of the safety timer. Incremented at 15 min intervals
when charging is enabled. Reading the register gives the current
timer value. Writing the register has no affect.
0x0
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
44 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
11 Package Information
11.1 Package Outline
Figure 23: Package Outline Drawing
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
45 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
11.2 Moisture Sensitivity Level
The Moisture Sensitivity Level (MSL) is an indicator for the maximum allowable time period (floor
lifetime) in which a moisture sensitive plastic device, once removed from the dry bag, can be
exposed to an environment with a specified maximum temperature and a maximum relative humidity
before the solder reflow process. Table 52 defines the MSL classification.
For detailed information on MSL levels refer to the IPC/JEDEC standard J-STD-020, which can be
downloaded from http://www.jedec.org.
The WLCSP package is qualified for MSL 1.
Table 52: MSL Classification
MSL Level
MSL 4
Floor Lifetime
72 hours
168 hours
4 weeks
Conditions
30 °C / 60 % RH
30 °C / 60 % RH
30 °C / 60 % RH
30 °C / 60 % RH
30 °C / 85 % RH
MSL 3
MSL 2A
MSL 2
1 year
MSL 1
unlimited
11.3 WLCSP Handling
Manual handling of WLCSP packages should be reduced to the absolute minimum. In cases where it
is still necessary, a vacuum pick-up tool should be used. In extreme cases plastic tweezers could be
used, but metal tweezers are not acceptable, since contact may easily damage the silicon chip.
Removal of a WLCSP package will cause damage to the solder balls. Therefore a removed sample
cannot be reused.
WLCSP packages are sensitive to visible and infrared light. Precautions should be taken to properly
shield the chip in the final product.
11.4 Soldering Information
Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can
be downloaded from http://www.jedec.org.
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
46 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
12 Ordering Information
The ordering number consists of the part number followed by a suffix indicating the packing method.
For details and availability, please consult Dialog Semiconductor’s customer portal or your local sales
representative.
Table 53: Ordering Information
Pack
Quantity
Part Number
Comment
Package
Size (mm)
Shipment Form
8 A output
current
DA9318L-05UF2
DA9318M-06UF2
64 WLCSP
64 WLCSP
3.62 mm x 3.78 mm Tape and reel
3.62 mm x 3.78 mm Tape and reel
7,500
10 A output
current
7,500
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
47 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Appendix A Application Information
A.1 Suggested PCB Layout
CBS
0402
TOP – Switching Power
LYR2 – PGND Plane
LYR3 – VIN/VOUT
CFLY
0603
LYR4 – Signal
LYR5 – AGND
BOT - Signal
CFLY
0603
MID1
C1P
C1P
BS1
C1N
C1N
CMID
MID1
C1P
OUT1
OUT1
C1N
PGND1
0402
MID1
C1P
OUT1
OUT1
CC1
PGND1
CAVDD
0402
nIRQ
OUT1
OUT1
OUT2
OUT1
OUT1
OUT2
VINS
AVDD
SUB
SYS
IN
IN
SCL
OUT1
nCPEN
VBATP
CIN
COUT
0402
IN
AGND
NC
0402
IN
IN
SDA
OUT2
VOUTS
VBATN
nFAULT
PWREN
CSYS
0402
MID2
C2P
OUT2
OUT2
CC2
PGND2
CMID
MID2
C2P
OUT2
OUT2
C2N
PGND2
0402
MID2
C2P
C2P
BS2
C2N
C2N
CFLY
0603
CFLY
0603
CBS
0402
Figure 24: Suggested PCB Layout
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
48 of 49
© 2021 Dialog Semiconductor
DA9318L/M
High-Efficiency, 10 A, High-Voltage Direct Charger
Status Definitions
Revision
Datasheet Status
Product Status
Definition
This datasheet contains the design specifications for product development.
Specifications may be changed in any manner without notice.
1.<n>
Target
Development
This datasheet contains the specifications and preliminary characterization
data for products in pre-production. Specifications may be changed at any
time without notice in order to improve the design.
2.<n>
3.<n>
Preliminary
Qualification
This datasheet contains the final specifications for products in volume
production. The specifications may be changed at any time in order to
improve the design, manufacturing and supply. Major specification changes
are communicated via Customer Product Notifications. Datasheet changes
are communicated via www.dialog-semiconductor.com.
Final
Production
Archived
This datasheet contains the specifications for discontinued products. The
information is provided for reference only.
4.<n>
Obsolete
Disclaimer
Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such information. Dialog Semiconductor furthermore takes no
responsibility whatsoever for the content in this document if provided by any information source outside of Dialog Semiconductor.
Dialog Semiconductor reserves the right to change without notice the information published in this document, including without limitation the
specification and the design of the related semiconductor products, software and applications.
Applications, software, and semiconductor products described in this document are for illustrative purposes only. Dialog Semiconductor makes
no representation or warranty that such applications, software and semiconductor products will be suitable for the specified use without further
testing or modification. Unless otherwise agreed in writing, such testing or modification is the sole responsibility of the customer and Dialog
Semiconductor excludes all liability in this respect.
Customer notes that nothing in this document may be construed as a license for customer to use the Dialog Semiconductor products, software
and applications referred to in this document. Such license must be separately sought by customer with Dialog Semiconductor.
All use of Dialog Semiconductor products, software and applications referred to in this document are subject to Dialog Semiconductor’s Standard
Terms and Conditions of Sale, available on the company website (www.dialog-semiconductor.com) unless otherwise stated.
Dialog and the Dialog logo are trademarks of Dialog Semiconductor plc or its subsidiaries. All other product or service names are the property of
their respective owners.
© 2021 Dialog Semiconductor. All rights reserved.
RoHS Compliance
Dialog Semiconductor’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European
Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our
suppliers are available on request.
Contacting Dialog Semiconductor
United Kingdom (Headquarters)
Dialog Semiconductor (UK) LTD
Phone: +44 1793 757700
North America
Hong Kong
China (Shenzhen)
Dialog Semiconductor Inc.
Phone: +1 408 845 8500
Dialog Semiconductor Hong Kong
Phone: +852 2607 4271
Dialog Semiconductor China
Phone: +86 755 2981 3669
Germany
Japan
Korea
China (Shanghai)
Dialog Semiconductor GmbH
Phone: +49 7021 805-0
Dialog Semiconductor K. K.
Phone: +81 3 5769 5100
Dialog Semiconductor Korea
Phone: +82 2 3469 8200
Dialog Semiconductor China
Phone: +86 21 5424 9058
The Netherlands
Taiwan
Dialog Semiconductor B.V.
Phone: +31 73 640 8822
Dialog Semiconductor Taiwan
Phone: +886 281 786 222
Email:
Web site:
enquiry@diasemi.com
www.dialog-semiconductor.com
Datasheet
Revision 3.1
21-Apr-2021
CFR0011-120-00
49 of 49
© 2021 Dialog Semiconductor
相关型号：
DA945-B-B-B
Toggle Switch, SPST, Latched, Wire Terminal, Bat Type Actuator, Panel Mount-threaded
Carling Techn
DA945-B-B-W
Toggle Switch, SPST, Latched, Wire Terminal, Bat Type Actuator, Panel Mount-threaded
Carling Techn
DA945-B-W-B
Toggle Switch, SPST, Latched, Wire Terminal, Bat Type Actuator, Panel Mount-threaded
Carling Techn
DA945-P-B-B
Toggle Switch, SPST, Latched, Wire Terminal, Paddle Type Actuator, Panel Mount-threaded,
Carling Techn
DA945-P-W-B
Toggle Switch, SPST, Latched, Wire Terminal, Paddle Type Actuator, Panel Mount-threaded
Carling Techn
DA945-P-W-W
Toggle Switch, SPST, Latched, Wire Terminal, Paddle Type Actuator, Panel Mount-threaded
Carling Techn
DAA-11W1P-NMB-K52
Ensuring over 20 years of mission critical communication between two worlds across 250,000,000 milies
ITT
DAA-11W1S-NMB-K52
Ensuring over 20 years of mission critical communication between two worlds across 250,000,000 milies
ITT
©2020 ICPDF网 联系我们和版权申明