SLG47502_技术文档

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

General Description

The SLG47502/03 provides a small, low voltage and low power component for commonly used mixed-signal functions. The

user creates their circuit design by programming the one time programmable (OTP) Non-Volatile Memory (NVM) to configure

the interconnect logic, the IO Pins, and the macrocells of the SLG47502/03. This highly versatile device allows a wide variety of

mixed-signal functions to be designed within a very small, low power single integrated circuit.

Key Features



Two High Speed General Purpose Analog Comparators

(ACMPxH)



Power Supply

1.1 V ≤ V_DD≤ 1.3 V



Integrated Voltage References (Vref)

Fifteen Combination Function Macrocells



Operating Temperature Range: -40 °C to 85 °C

RoHS Compliant/Halogen-Free

Available Package



Three Selectable DFF/LATCH or 2-bit LUTs or Shift

Registers

One Selectable Programmable Pattern Generator or

2-bit LUT

Ten Selectable DFF/LATCH or 3-bit LUTs or

Shift Registers

One Selectable DFF/LATCH or 4-bit LUTs or

Shift Register



12-pin STQFN: 1.6 mm x 1.6 mm x 0.55 mm, 0.4 mm

pitch



16-pin MSTQFN: 1.6 mm x 1.6 mm x 0.55 mm, 0.4 mm

pitch



Eight Multi-Function Macrocells



Seven Selectable DFF/LATCH or 3-bit LUTs + 8-bit

Delay/Counters



One Selectable DFF/LATCH or 4-bit LUT + 16-bit

Delay/Counter

Serial Communications



I²C Protocol Interface



Programmable Delay with Edge Detector Output

Deglitch Filter or Edge Detector

Two Oscillators (OSC)



2.048 kHz Oscillator

25 MHz Oscillator



Analog Temperature Sensor

Power-On Reset (POR) with CRC Check

Read Back Protection (Read Lock)

Applications



Notebook and Tablet PCs

Smartphones and Fitness Bands

Personal Computers and Servers

PC Peripherals

Consumer Electronics

Data Communications Equipment

Handheld and Portable Electronics

Datasheet

16-Jul-2021

Revision 2.0

1 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Contents

General Description.................................................................................................................................................................1

Key Features.............................................................................................................................................................................1

Applications..............................................................................................................................................................................1

1 Block Diagram ......................................................................................................................................................................7

2 Pinout ....................................................................................................................................................................................8

2.1 Pin Configuration - STQFN- 12L ............................................................................................................................8

2.2 Pin Configuration - MSTQFN- 16L .........................................................................................................................9

3 Characteristics ...................................................................................................................................................................13

3.1 Absolute Maximum Ratings .................................................................................................................................13

3.2 Electrostatic Discharge Ratings ...........................................................................................................................13

3.3 Recommended Operating Conditions .................................................................................................................13

3.4 Electrical Characteristics ......................................................................................................................................14

3.5 I²C Pins Electrical Characteristics ........................................................................................................................16

3.6 Macrocells Current Consumption .........................................................................................................................18

3.7 Timing Characteristics ..........................................................................................................................................19

3.8 Counter/Delay Characteristics .............................................................................................................................21

3.9 Oscillator Characteristics .....................................................................................................................................21

3.10 ACMP Characteristics ........................................................................................................................................22

4 User Programmability ........................................................................................................................................................24

5 IO Pins .................................................................................................................................................................................25

5.1 GPIO Pins ............................................................................................................................................................25

5.2 GPI Pin .................................................................................................................................................................25

5.3 Pull-Up/Down Resistors .......................................................................................................................................25

5.4 Fast Pull-up/down during Power-up .....................................................................................................................25

5.5 GPI Structure .......................................................................................................................................................26

5.6 GPIO with I²C Mode IO Structure ........................................................................................................................27

5.7 Matrix OE IO Structure .........................................................................................................................................28

5.8 IO Typical Performance .......................................................................................................................................29

6 Connection Matrix ..............................................................................................................................................................32

6.1 Matrix Input Table ...............................................................................................................................................33

6.2 Matrix Output Table ..............................................................................................................................................35

6.3 Connection Matrix Virtual Inputs ..........................................................................................................................38

7 Combination Function Macrocells ....................................................................................................................................39

7.1 2-Bit LUT or D Flip-Flop or Shift Register Macrocells ..........................................................................................39

7.2 2-bit LUT or Programmable Pattern Generator ....................................................................................................44

7.3 3-Bit LUT or D Flip-Flop with Set/Reset or Shift Register Macrocells ..................................................................46

7.4 4-Bit LUT or D Flip-Flop with Set/Reset or Shift Register Macrocell ....................................................................58

8 Multi-Function Macrocells .................................................................................................................................................62

8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells ..............................................................................62

8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell ..............................................................................71

8.3 CNT/DLY Timing Diagrams ..................................................................................................................................74

8.4 FSM Timing Diagrams .........................................................................................................................................81

8.5 Wake and Sleep Controller ..................................................................................................................................84

9 Analog Comparators ..........................................................................................................................................................89

9.1 ACMP0H Block Diagram ......................................................................................................................................90

9.2 ACMP1H Block Diagram ......................................................................................................................................91

9.3 ACMP Typical Performance .................................................................................................................................92

10 Programmable Delay/Edge Detector ..............................................................................................................................93

10.1 Programmable Delay Timing Diagram - Edge Detector Output .........................................................................93

11 Additional Logic Function. Deglitch Filter .....................................................................................................................94

12 Voltage Reference ............................................................................................................................................................95

12.1 Voltage Reference Overview .............................................................................................................................95

12.2 Vref Selection Table ...........................................................................................................................................95

12.3 Vref Block Diagram ...........................................................................................................................................96

12.4 Vref Typical Performance ...................................................................................................................................97

Datasheet

16-Jul-2021

Revision 2.0

2 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

13 Clocking ..........................................................................................................................................................................100

13.1 OSC General description .................................................................................................................................100

13.2 Oscillator0 (2.048 kHz) .....................................................................................................................................101

13.3 Oscillator1 (25 MHz) ........................................................................................................................................102

13.4 CNT/DLY Clock Scheme ..................................................................................................................................103

13.5 External Clocking .............................................................................................................................................103

13.6 Oscillators Accuracy .........................................................................................................................................104

13.7 Oscillators Settling time ....................................................................................................................................106

14 Power-On Reset ..............................................................................................................................................................108

14.1 General Operation ............................................................................................................................................108

14.2 POR Sequence ................................................................................................................................................109

14.3 Macrocells Output States During POR Sequence ...........................................................................................109

15 I²C Serial Communications Macrocell ..........................................................................................................................112

15.1 I²C Serial Communications Macrocell Overview ..............................................................................................112

15.2 I²C Serial Communications Device Addressing ...............................................................................................112

15.3 I²C Serial General Timing ................................................................................................................................113

15.4 I²C Serial Communications Commands ...........................................................................................................113

15.5 I²C Serial Command Register Map ..................................................................................................................118

16 Analog Temperature Sensor .........................................................................................................................................120

17 Register Definitions .......................................................................................................................................................121

17.1 Register Map ....................................................................................................................................................121

18 Package Top Marking Definitions .................................................................................................................................180

18.1 STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC .........................................................................................180

18.2 MSTQFN 16L 1.6 mm x 1.6 mm x 0.55 mm 0.4P ............................................................................................180

19 Package Information ......................................................................................................................................................181

19.1 Package outlines for STQFN 12L 1.6 mm x 1.6 mm x 0.55 MM 0.4P FC Package .........................................181

19.2 Package outlines for MSTQFN 16L 1.6 mm x 1.6 mm x 0.55 MM 0.4P Package ...........................................182

19.3 Moisture Sensitivity Level .................................................................................................................................183

19.4 STQFN Handling ..............................................................................................................................................183

19.5 Soldering Information .......................................................................................................................................183

20 Ordering Information .....................................................................................................................................................183

20.1 Tape and Reel Specifications ..........................................................................................................................183

20.2 Carrier Tape Drawing and Dimensions ............................................................................................................184

21 Layout Guidelines ..........................................................................................................................................................185

21.1 STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC Package ..........................................................................185

21.2 MSTQFN 16L 1.6 mm x 1.6 mm x 0.55 mm 0.4P Package .............................................................................186

Glossary................................................................................................................................................................................187

Revision History...................................................................................................................................................................190

Datasheet

16-Jul-2021

Revision 2.0

3 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Figures

Figure 1: Block Diagram.............................................................................................................................................................7

Figure 2: Steps to Create a Custom GreenPAK Device...........................................................................................................24

Figure 3: GPI Structure Diagram..............................................................................................................................................26

Figure 4: GPIO with I²C Mode IO Structure Diagram...............................................................................................................27

Figure 5: Matrix OE IO Structure Diagram...............................................................................................................................28

Figure 6: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C.......................................................29

Figure 7: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range......................29

Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C .........................................30

Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range......................30

Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C .......................................31

Figure 11: Connection Matrix...................................................................................................................................................32

Figure 12: Connection Matrix Usage Example.........................................................................................................................32

Figure 13: 2-bit LUT0 or DFF0 or Shift Register0 ....................................................................................................................40

Figure 14: 2-bit LUT1 or DFF1 or Shift Register1 ....................................................................................................................40

Figure 15: 2-bit LUT2 or DFF2 or Shift Register2 ....................................................................................................................41

Figure 16: DFF0 to DFF2 and Shift Register0 to Shift Register2 Operation............................................................................41

Figure 17: DFF0 to DFF2 and Shift Register0 to Shift Register2 Operation with DFF Initial Value = 1...................................42

Figure 18: DFF0 to DFF2 and Shift Register0 to Shift Register2 Operation with Initial Value = b0001...................................43

Figure 19: 2-bit LUT3 or PGen.................................................................................................................................................45

Figure 20: PGen Timing Diagram.............................................................................................................................................45

Figure 21: 3-bit LUT0 or DFF3 or Shift Register 3 ...................................................................................................................47

Figure 22: 3-bit LUT1 or DFF4 or Shift Register 4 ...................................................................................................................48

Figure 23: 3-bit LUT2 or DFF5 or Shift Register 5 ...................................................................................................................48

Figure 24: 3-bit LUT3 or DFF6 or Shift Register 6 ...................................................................................................................49

Figure 25: 3-bit LUT4 or DFF7 or Shift Register 7 ...................................................................................................................49

Figure 26: 3-bit LUT5 or DFF8 or Shift Register 8 ...................................................................................................................50

Figure 27: 3-bit LUT6 or DFF9 or Shift Register 9 ...................................................................................................................50

Figure 28: 3-bit LUT7 or DFF10 or Shift Register 10 ...............................................................................................................51

Figure 29: 3-bit LUT8 or DFF11 or Shift Register 11 ...............................................................................................................51

Figure 30: 3-bit LUT9 or DFF12 or Shift Register 12 ...............................................................................................................52

Figure 31: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation......................................................................52

Figure 32: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nReset, Initial Value: b10011011................53

Figure 33: DFF3 to DFF12 and Shift Register3 to Shift Register12 Operation, nReset, Initial Value: b10011011, Case2......53

Figure 34: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nReset, Initial Value: b00011011................54

Figure 35: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nSet, Initial Value: b00011010....................54

Figure 36: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nSet, Initial Value: b00011010, Case 2.......55

Figure 37: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nSet, Initial Value: b10011010....................55

Figure 38: 4-bit LUT0 or DFF13 or Shift Register 13 ...............................................................................................................58

Figure 39: DFF13 and Shift Register 13 Operation..................................................................................................................59

Figure 40: DFF13 and Shift Register 13 Operation, nSet, Initial Value: xA7B2.......................................................................59

Figure 41: DFF13 and Shift Register 13 Operation, nReset, Initial Value: xA7B2...................................................................60

Figure 42: Possible Connections Inside Multi-Function Macrocell...........................................................................................62

Figure 43: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF15, CNT/DLY1) .................................................63

Figure 44: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF16, CNT/DLY2) .................................................64

Figure 45: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF17, CNT/DLY3) .................................................65

Figure 46: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT13/DFF18, CNT/DLY4) .................................................66

Figure 47: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT14/DFF19, CNT/DLY5) .................................................67

Figure 48: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT15/DFF20, CNT/DLY6) .................................................68

Figure 49: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT16/DFF21, CNT/DLY7) .................................................69

Figure 50: 4-bit LUT1 or CNT/DLY0.........................................................................................................................................72

Figure 51: Delay Macrocell Behavior with Different Oscillators Options (Edge Select: Both, Counter Data: 3).......................74

Figure 52: Delay Mode Timing Diagram (Rising, Falling, and Both Edge Detection)...............................................................75

Figure 53: Counter Mode Timing Diagram without Two DFFs Synced Up ..............................................................................75

Figure 54: Counter Mode Timing Diagram with Two DFFs Synced Up ...................................................................................76

Figure 55: One-Shot Function Timing Diagram........................................................................................................................77

Datasheet

16-Jul-2021

Revision 2.0

4 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Figure 56: Frequency Detection Mode Timing Diagram...........................................................................................................78

Figure 57: Edge Detection Mode Timing Diagram...................................................................................................................79

Figure 58: Delayed Edge Detection Mode Timing Diagram.....................................................................................................80

Figure 59: Counter Value, Counter Data = 3............................................................................................................................81

Figure 60: CNT/FSM Mode Timing Diagram (Reset Rising Edge Mode, OSC is Forced On, UP=0) for CNT Data = 3..........81

Figure 61: CNT/FSM Mode Timing Diagram (Set Rising Edge Mode, OSC is Forced On, UP = 0) for CNT Data = 3............82

Figure 62: CNT/FSM Mode Timing Diagram (Reset Rising Edge Mode, OSC is Forced On, UP = 1) for CNT Data = 3........82

Figure 63: CNT/FSM Mode Timing Diagram (Set Rising Edge Mode, OSC is Forced On, UP = 1) for CNT Data = 3............83

Figure 64: DLY/FSM Mode, Falling Edge Delay, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3 ....................83

Figure 65: One Shot/FSM Mode, Rising Edge, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3.......................83

Figure 66: Freq. Detector/FSM Mode, Rising Edge, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3...............84

Figure 67: Delayed Edge Detector/FSM Mode, Rising Edge, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3.84

Figure 68: Wake/Sleep Controller............................................................................................................................................85

Figure 69: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used ..........................................................86

Figure 70: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used .............................................................86

Figure 71: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used ..............................................................87

Figure 72: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Set is Used .................................................................87

Figure 73: ACMP0H Block Diagram.........................................................................................................................................90

Figure 74: ACMP1H Block Diagram.........................................................................................................................................91

Figure 75: Typical Propagation Delay vs. Vref for ACMPxH at T = 25 °C, V_DD= 1.1 V to 1.3 V, Gain = 1, Hysteresis = 0....92

Figure 76: ACMPxH Input Offset Voltage vs. Vref at T = -40 °C to 85 °C, V_DD= 1.1 V to 1.3 V .............................................92

Figure 77: Programmable Delay ..............................................................................................................................................93

Figure 78: Edge Detector Output .............................................................................................................................................93

Figure 79: Deglitch Filter/Edge Detector Simplified Structure..................................................................................................94

Figure 80: Voltage Reference Block Diagram..........................................................................................................................96

Figure 81: Typical Load Regulation, Vref = 200 mV, T = -40 °C to +85 °C, Buffer - Enable....................................................97

Figure 82: Typical Load Regulation, Vref = 400 mV, T = -40 °C to +85 °C, Buffer - Enable....................................................97

Figure 83: Typical Load Regulation, Vref = 600 mV, T = -40 °C to +85 °C, Buffer - Enable....................................................98

Figure 84: Typical Load Regulation, Vref = 850 mV, T = -40 °C to +85 °C, Buffer - Enable....................................................98

Figure 85: Typical Input Offset Voltage vs. Vref at V_DD= 1.2 V, T = 25 °C .............................................................................99

Figure 86: Oscillator0 Block Diagram.....................................................................................................................................101

Figure 87: Oscillator1 Block Diagram.....................................................................................................................................102

Figure 88: Clock Scheme.......................................................................................................................................................103

Figure 89: Oscillator0 Frequency vs. Temperature, OSC0 = 2.048 kHz................................................................................104

Figure 90: Oscillator1 Frequency vs. Temperature, OSC1 = 25 MHz....................................................................................104

Figure 91: Oscillators Total Error vs. Temperature................................................................................................................105

Figure 92: Oscillator0 Settling Time, V_DD= 1.2 V, T = 25 °C, OSC0 = 2.048 kHz.................................................................106

Figure 93: Oscillator1 Settling Time, V_DD= 1.2 V, T = 25 °C, OSC1 = 25 MHz (Normal Start).............................................106

Figure 94: Oscillator1 Settling Time, V_DD= 1.2 V, T = 25 °C, OSC1 = 25 MHz (Start with Delay)........................................107

Figure 95: POR Sequence.....................................................................................................................................................109

Figure 96: Internal Macrocell States During POR Sequence.................................................................................................110

Figure 97: Power-Down..........................................................................................................................................................111

Figure 98: Basic Command Structure....................................................................................................................................113

Figure 99: I²C General Timing Characteristics.......................................................................................................................113

Figure 100: Byte Write Command, R/W = 0...........................................................................................................................114

Figure 101: Sequential Write Command................................................................................................................................114

Figure 102: Current Address Read Command, R/W = 1........................................................................................................115

Figure 103: Random Read Command ...................................................................................................................................115

Figure 104: Sequential Read Command................................................................................................................................115

Figure 105: Reset Command Timing .....................................................................................................................................116

Figure 106: Example of I²C Byte Write Bit Masking...............................................................................................................117

Figure 107: Analog Temperature Sensor Structure Diagram.................................................................................................120

Datasheet

16-Jul-2021

Revision 2.0

5 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Tables

Table 1: Functional Pin Description............................................................................................................................................9

Table 2: Pin Type Definitions ...................................................................................................................................................12

Table 3: Absolute Maximum Ratings........................................................................................................................................13

Table 4: Electrostatic Discharge Ratings .................................................................................................................................13

Table 5: Recommended Operating Conditions........................................................................................................................13

Table 6: EC at T = -40 °C to +85 °C, V_DD= 1.1 V to 1.3 V Unless Otherwise Noted ..............................................................14

Table 7: EC of the I²C Pins for DI Mode at T = -40 °C to +85 °C, Full V_DDRange Unless Otherwise Noted..........................16

Table 8: EC of the I²C Pins for DILV Mode at T = -40 °C to +85 °C, Full V_DDRange Unless Otherwise Noted......................16

Table 9: I²C Pins Timing Characteristics for DI Mode, T = -40 °C to +85 °C, Full V_DDRange Unless Otherwise Noted ........17

Table 10: I²C Pins Timing Characteristics for DILV Mode, T = -40 °C to +85 °C, Full V_DDRange Unless Otherwise Noted..17

Table 11: Typical Current Estimated for Each Macrocell at T = 25 °C, V_DD= 1.2 V ...............................................................18

Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C, V_DD= 1.2 V...................................................................19

Table 13: Programmable Delay Expected Typical Delays and Pulse Widths at T = 25 °C, V_DD= 1.2 V ...............................20

Table 14: Typical Filter Pulse Width, V_DD= 1.2 V ...................................................................................................................21

Table 15: Typical Counter/Delay Offset at T = 25 °C, V_DD= 1.2 V .........................................................................................21

Table 16: Oscillators Frequency Limits, V_DD= 1.1 V to 1.3 V ................................................................................................21

Table 17: Oscillators Power-On Delay at T = 25 °C, V_DD= 1.1 V to 1.3 V, OSC Power Setting: "Auto Power-On"................22

Table 18: ACMP Specifications at T = -40 °C to +85 °C, V_DD= 1.1 V to 1.3 V Unless Otherwise Noted................................22

Table 19: Matrix Input Table.....................................................................................................................................................33

Table 20: Matrix Output Table..................................................................................................................................................35

Table 21: Connection Matrix Virtual Inputs ..............................................................................................................................38

Table 22: 2-bit LUT2_0 to 2-bit LUT2_2 Truth Table ...............................................................................................................44

Table 23: 2-bit LUT Standard Digital Functions .......................................................................................................................44

Table 24: 2-bit LUT2_3 Truth Table.........................................................................................................................................46

Table 25: 2-bit LUT Standard Digital Functions .......................................................................................................................46

Table 26: 3-bit LUT3_0 to 3-bit LUT3_9 Truth Table ...............................................................................................................56

Table 27: 3-bit LUT Standard Digital Functions .......................................................................................................................56

Table 28: 4-bit LUT0 Truth Table.............................................................................................................................................60

Table 29: 4-bit LUT Standard Digital Functions .......................................................................................................................61

Table 30: 3-bit LUT10 to 3-bit LUT16 Truth Table ...................................................................................................................70

Table 31: 4-bit LUT1 Truth Table.............................................................................................................................................73

Table 32: 4-bit LUT Standard Digital Functions .......................................................................................................................73

Table 33: ACMP Input Selection..............................................................................................................................................89

Table 34: Vref Selection Table.................................................................................................................................................95

Table 35: Oscillator Operation Mode Configuration Settings.................................................................................................100

Table 36: Read/Write Protection Options...............................................................................................................................118

Table 37: Register Map..........................................................................................................................................................121

Table 38: MSL Classification..................................................................................................................................................183

Datasheet

16-Jul-2021

Revision 2.0

6 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

1

Block Diagram

GPIO12*

GPIO11*

GPIO10*

Combination Function Macrocell

High Speed

Analog

V_DD

GPIO9*

Vref0

2-bit LUT2_0

or DFF0

or Shift_Reg0

2-bit LUT2_1

or DFF1

or Shift_Reg1

2-bit LUT2_2

or DFF2

or Shift_Reg2

2-bit

LUT2_3

or PGEN

3-bit LUT3_0

or DFF3

or Shift_Reg3

3-bit LUT3_1

or DFF4

or Shift_Reg4

3-bit LUT3_2

or DFF5

or Shift_Reg5

3-bit LUT3_3

or DFF6

or Shift_Reg6

ACMP0H

ACMP1H

GPI

GPIO8

3-bit LUT3_4

or DFF7

or Shift_Reg7

3-bit LUT3_5

or DFF8

or Shift_Reg8

3-bit LUT3_6

or DFF9

or Shift_Reg9

3-bit LUT3_7

or DFF10

or Shift_Reg10

3-bit LUT3_8

or DFF11

or Shift_Reg11

4-bit LUT4_0

or DFF13

or Shift_Reg13

3-bit LUT3_9

or DFF12

or Shift_Reg12

GPIO0

GPIO7

I²C_SCL

ACMP1_H+

Temperature

Sensor

I²C Serial

Communication

Filter with Edge

Multi - Function Macrocell

Detect

3-bit

GPIO1

GPIO6

LUT3_10/

DFF15+8bit

CNT/DLY1

LUT3_11/

DFF16+8bit

CNT/DLY2

LUT3_12/

DFF17+8bit

CNT/DLY3

LUT3_13/

DFF18+8bit

CNT/DLY4

Oscillators

I²C_SDA

ACMP0_H+

Programmable

Delay

2.048kHz

25MHz

3-bit

4-bit

LUT3_14/

DFF19+8bit

CNT/DLY5

LUT3_15/

DFF20+8bit

CNT/DLY6

LUT3_16/

DFF21+8bit

CNT/DLY7

LUT4_1/

DFF14+16bit

CNT/DLY0

POR with CRC

GPIO5

Vref0 Out

TS Out

GPIO2

GPIO3

EXT_Vref0

GPIO4

EXT_Vref1

GND

Note *: GPIO 9, 10, 11, and 12 are available in 16-pin package only.

Figure 1: Block Diagram

Datasheet

16-Jul-2021

Revision 2.0

7 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

2

Pinout

2.1 PIN CONFIGURATION - STQFN- 12L

Pin # Pin Name Pin Functions

1

2

V_DD

Power Supply

GPI

GPI, SLA_0

3

GPIO0

GPIO1

GPIO2

GPIO3

GND

GPIO, I²C SCL

GPIO, I²C SDA

4

5

GPIO with OE, EXT_OSC1_IN

6

GPIO with OE, EXT_Vref0, SLA_1

Ground

7

12 11

GPIO6

GPIO5

GPIO4

GND

V_DD

1

8

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO with OE, EXT_Vref1, SLA_2

GPIO with OE, Vref_OUT, TS_OUT

GPIO with OE, ACMP0_H+

GPIO with OE, ACMP1_H+

GPIO with OE, SLA_3, EXT_OSC0_IN

10

9

GPI

GPIO0

GPIO1

2

3

4

9

8

7

10

11

12

5

6

Legend:

OE: Output Enable

ACMPx+: ACMPx Positive Input

ACMPx-: ACMPx Negative Input

I²C SCL: I²C Clock Input

I²C SDA: I²C Data Input/Output

Vref: Voltage Reference Output

EXT_CLKx: External Clock Input

SLA: Slave Address

STQFN-12L

(Top View)

TS_OUT: Temperature Output

Datasheet

16-Jul-2021

Revision 2.0

8 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

2.2 PIN CONFIGURATION - MSTQFN- 16L

Pin # Pin Name Pin Functions

1

2

V_DD

Power Supply

GPI

GPI, SLA_0

3

GPIO0

GPIO1

GPIO2

GPIO3

GND

GPIO, I²C SCL

GPIO, I²C SDA

4

5

GPIO with OE, EXT_OSC1_IN

6

GPIO with OE, EXT_Vref0, SLA_1

Ground

7

12 11

GPIO6

V_DD

GPI

1

8

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO with OE, EXT_Vref1, SLA_2

GPIO with OE, Vref_OUT, TS_OUT

GPIO with OE, ACMP0_H+

GPIO with OE, ACMP1_H+

GPIO with OE, SLA_3, EXT_OSC0_IN

GPIO with OE

10

9

16

13

GPIO5

GPIO4

GND

2

3

4

10

11

12

13

14

15

16

GPIO0

GPIO1

8

14

15

7

GPIO with OE

5

6

GPIO with OE

Legend:

OE: Output Enable

MSTQFN-16L

(Top View)

ACMPx+: ACMPx Positive Input

ACMPx-: ACMPx Negative Input

I²C SCL: I²C Clock Input

I²C SDA: I²C Data Input/Output

Vref: Voltage Reference Output

EXT_CLKx: External Clock Input

SLA: Slave Address

TS_OUT: Temperature Output

Table 1: Functional Pin Description

Pin #

Signal

Name

Input

Options

Output

Options

Function

Name

STQFN-12L

MSTQFN-16L

1

V_DD

Power Supply

--

Digital Input

without Schmitt Trigger

GPI

General Purpose Input

Digital Input

with Schmitt Trigger

--

2

GPI

Low Voltage Digital Input

I²C Slave

Address 0

--

Open-Drain

NMOS

(1x)

Digital Input

without Schmitt Trigger

General Purpose IO

GPIO0

(Note 1)

Digital Input

with Schmitt Trigger

3

GPIO0

Low Voltage Digital Input

--

Digital Input

without Schmitt Trigger

I²C SCL

I²C Serial Clock

Low Voltage Digital Input

Datasheet

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Revision 2.0

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 1: Functional Pin Description (Continued)

Pin #

Name

Signal

Name

Input

Options

Output

Options

Function

STQFN-12L

MSTQFN-16L

Open-Drain

NMOS

(1x)

Digital Input

without Schmitt Trigger

GPIO1

General Purpose IO

Digital Input

with Schmitt Trigger

4

GPIO1

Low Voltage Digital Input

Digital Input

without Schmitt Trigger

--

I²C SDA

I²C Serial Data

Low Voltage Digital Input

Digital Input

without Schmitt Trigger

Push-Pull (1x)

(2x)

General Purpose IO

with OE (Note 1)

Open-Drain

NMOS

(1x) (2x)

GPIO2

EXT_OSC1_IN

GPIO3

Digital Input

with Schmitt Trigger

5

GPIO2

Low Voltage Digital Input

--

External Clock

Connection

--

Digital Input

without Schmitt Trigger

Push-Pull (1x)

(2x)

General Purpose IO

with OE (Note 1)

Open-Drain

NMOS

(1x) (2x)

Digital Input

with Schmitt Trigger

6

GPIO3

Low Voltage Digital Input

Analog

--

Analog Comparator

Negative Input

EXT_VREF0

--

I²C Slave

Address 1

--

7

8

7

8

GND

Power Supply

Digital Input

without Schmitt Trigger

Push-Pull (1x)

(2x)

General Purpose IO

with OE

Open-Drain

NMOS

(1x) (2x)

GPIO4

Digital Input

with Schmitt Trigger

Low Voltage Digital Input

Analog

Analog Comparator

Negative Input

EXT_VREF1

--

8

9

8

9

I²C Slave

Address 2

--

Digital Input

without Schmitt Trigger

Push-Pull (1x)

(2x)

General Purpose IO

with OE (Note 1)

Open-Drain

NMOS

(1x) (2x)

GPIO5

Digital Input

with Schmitt Trigger

GPIO5

Low Voltage Digital Input

Analog

--

Vref0

Vref0 Output

Temperature Sensor

Output

TS_OUT

Analog

--

Datasheet

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 1: Functional Pin Description (Continued)

Pin #

Name

Signal

Name

Input

Options

Output

Options

Function

STQFN-12L

MSTQFN-16L

Digital Input

without Schmitt Trigger

Push-Pull (1x)

(2x)

General Purpose IO

with OE (Note 1)

Open-Drain

NMOS

(1x) (2x)

GPIO6

ACMP0_H+

GPIO7

Digital Input

with Schmitt Trigger

10

GPIO6

Low Voltage Digital Input

Analog

--

Analog Comparator

0_H Positive Input

--

Digital Input

without Schmitt Trigger

Push-Pull (1x)

(2x)

General Purpose IO

with OE (Note 1)

Open-Drain

NMOS

(1x) (2x)

Digital Input

with Schmitt Trigger

11

GPIO7

Low Voltage Digital Input

Analog

--

Analog Comparator

1_H Positive Input

ACMP1_H+

GPIO8

--

Digital Input

without Schmitt Trigger

Push-Pull (1x)

(2x)

General Purpose IO

with OE (Note 1)

Open-Drain

NMOS

(1x) (2x)

Digital Input

with Schmitt Trigger

12

GPIO8

Low Voltage Digital Input

--

I²C Slave

Address 3

--

External Clock

Connection

EXT_OSC0_IN

--

Digital Input

without Schmitt Trigger

Push-Pull (1x)

(2x)

General Purpose IO

with OE (Note 1)

Open-Drain

NMOS

(1x) (2x)

--

13

14

15

GPIO9

GPIO10

GPIO11

GPIO9

Digital Input

with Schmitt Trigger

Low Voltage Digital Input

--

Digital Input

without Schmitt Trigger

Push-Pull (1x)

(2x)

General Purpose IO

with OE (Note 1)

Open-Drain

NMOS

(1x) (2x)

GPIO10

GPIO11

Digital Input

with Schmitt Trigger

Low Voltage Digital Input

--

Digital Input

without Schmitt Trigger

Push-Pull (1x)

(2x)

General Purpose IO

with OE (Note 1)

Open-Drain

NMOS

(1x) (2x)

Digital Input

with Schmitt Trigger

Low Voltage Digital Input

--

Datasheet

16-Jul-2021

Revision 2.0

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 1: Functional Pin Description (Continued)

Pin #

Name

Signal

Name

Input

Options

Output

Options

Function

STQFN-12L

MSTQFN-16L

Digital Input

without Schmitt Trigger

Push-Pull (1x)

(2x)

General Purpose IO

with OE (Note 1)

Open-Drain

NMOS

(1x) (2x)

--

16

GPIO12

Digital Input

with Schmitt Trigger

Low Voltage Digital Input

--

Note 1 General Purpose IO's with OE can be used to implement bidirectional signals under user control via

Connection Matrix to OE signal in IO structure or as a 3-state output.

Table 2: Pin Type Definitions

Pin Type

V_DD

Description

Power Supply

GPI

General Purpose Input

General Purpose Input/Output

Ground

GPIO

GND

Datasheet

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

3

Characteristics

3.1 ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational

sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect

device reliability.

Table 3: Absolute Maximum Ratings

Parameter

Supply Voltage on V_DDrelative to GND

DC Input Voltage

Min

Max

Unit

V

-0.3

2.2

GND - 0.5 V V_DD+ 0.5 V

V

Maximum Average or DC Current

(Through V_DDor GND pin)

--

90

mA

Push-Pull 1x

--

11

16

Push-Pull 2x

OD 1x

Maximum Average or DC Current

(Through pin)

--

11

OD 2x

--

21

Current at Input Pin

-1.0

--

1.0

1000

150

mA

nA

°C

Input Leakage Current (Absolute Value)

Storage Temperature Range

Junction Temperature

-65

--

°C

Moisture Sensitive Level

1

3.2 ELECTROSTATIC DISCHARGE RATINGS

Table 4: Electrostatic Discharge Ratings

Parameter

Min

2000

1000

Max

--

Unit

V

ESD Protection (Human Body Model)

ESD Protection (Charged Device Model)

--

V

3.3 RECOMMENDED OPERATING CONDITIONS

Table 5: Recommended Operating Conditions

Parameter

Condition

Min

1.1

-40

Max

1.3

85

Unit

V

Supply Voltage (V_DD

)

Operating Temperature

°C

Maximal Voltage Applied to any PIN in High

Impedance State

V_DD+

0.3

--

V

Typical Capacitor Value at V_DD

0.1

0

--

µF

Analog Input Common Mode Range

Allowable Input Voltage atAnalog Pins

V_DD

V

Datasheet

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

3.4 ELECTRICAL CHARACTERISTICS

Table 6: EC at T = -40 °C to +85 °C, V_DD= 1.1 V to 1.3 V Unless Otherwise Noted

Parameter Description

Condition

Min

Typ

Max

V_DD

Unit

+

0.65x

V_DD

Logic Input (Note 1)

--

V

0.3

V_DD

0.3

+

0.52x

V_DD

Logic Input with 10 kΩ Pull-up (Note 1)

--

V

Logic Input with 10 kΩ Pull-down

(Note 1)

0.83x

V_DD

V_DD+

0.3

Logic Input with Schmitt Trigger

(PositiveGoingThresholdVoltage min=

0.7x

V_DD

0.3

+

--

V

0.4xV_DD; max = 0.7xV_DD

)

Logic Input with Schmitt Trigger

(PositiveGoingThresholdVoltage min=

0.4xV_DD; max = 0.7xV_DD), with 10 kΩ

Pull-up

V_DD+

V_IH

HIGH-Level Input Voltage

0.62x

V_DD

0.3

Logic Input with Schmitt Trigger

(PositiveGoingThresholdVoltage min=

0.4xV_DD; max = 0.7xV_DD), with 10 kΩ

Pull-down

V_DD

0.3

+

0.88x

V_DD

--

V

Low-Level Logic Input (Note 1)

0.6

--

V

Low-Level Logic Input with 10 kΩ

Pull-up (Note 1)

0.44

Low-Level Logic Input with 10 kΩ

Pull-down (Note 1)

0.75

--

V

V_DD

-

0.3x

V_DD

Logic Input (Note 1)

0.3

V_DD

0.3

0.19x

V_DD

Logic Input with 10 kΩ Pull-up (Note 1)

Logic Input with 10 kΩ Pull-down

(Note 1)

V_DD

0.3

0.37x

V_DD

Logic Input with Schmitt Trigger

(Negative Going Threshold Voltage min

V_DD

0.3

-

0.3x

V_DD

--

V

= 0.3xV_DD; max = 0.6xV_DD

)

Logic Input with Schmitt Trigger

(Negative Going Threshold Voltage min

= 0.3xV_DD; max = 0.6xV_DD),

with 10 kΩ Pull-up

V_DD

0.3

-

0.16x

V_DD

V_IL

LOW-Level Input Voltage

Logic Input with Schmitt Trigger

(Negative Going Threshold Voltage min

= 0.3xV_DD; max = 0.6xV_DD),

with 10 kΩ Pull-down

V_DD

0.3

-

0.37x

V_DD

--

V

V_DD

0.3

-

Low-Level Logic Input (Note 1)

--

0.27

0.08

0.33

V

Low-Level Logic Input with 10 kΩ

Pull-up (Note 1)

V_DD

0.3

Low-Level Logic Input with 10 kΩ

Pull-down (Note 1)

V_DD

0.3

Schmitt Trigger Hysteresis

Voltage

0.075x

V_DD

0.2x

V_DD

0.29x

V_DD

V_HYS

Datasheet

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Revision 2.0

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 6: EC at T = -40 °C to +85 °C, V_DD= 1.1 V to 1.3 V Unless Otherwise Noted (Continued)

Parameter Description

Condition

Min

Typ

Max

Unit

0.09x

V_DD

0.25x

V_DD

0.36x

V_DD

With 10 kΩ Pull-up/Pull-down

V

0.13x

V_DD

0.22x

V_DD

0.29x

V_DD

V_DD= 1.1 V

V

Schmitt Trigger Hysteresis

Voltage

V_HYS

0.1x

V_DD

0.2x

V_DD

0.27x

V_DD

V

_DD= 1.2 V

0.075x

V_DD

0.18x

V_DD

0.25x

V_DD

V_DD= 1.3 V

Push-Pull, 1x Drive, I_OH= 100 µA

Push-Pull, 1x Drive, I_OH= 2 mA

V_DD-0.1

--

V

0.8x

V_DD

V_OH

HIGH-Level Output Voltage

V_DD

0.05

-

Push-Pull, 2x Drive, I_OH= 100 µA

--

V

0.9x

V_DD

Push-Pull, 2x Drive, I_OH= 2 mA

Push-Pull, 1x Drive, I_OL= 100 µA

Push-Pull, 1x Drive, I_OL= 2 mA

Push-Pull, 2x Drive, I_OH= 100 µA

Push-Pull, 2x Drive, I_OH= 2 mA

NMOS OD, 1x Drive, I_OL= 100 µA

NMOS OD, 1x Drive, I_OL= 2 mA

NMOS OD, 2x Drive, I_OL= 100 µA

NMOS OD, 2x Drive, I_OL= 2 mA

--

V

--

0.007

0.2x

V_DD

0.004

0.1x

V_DD

V_OL

LOW-Level Output Voltage

0.004

0.1x

V_DD

0.002

0.1x

V_DD

Push-Pull, 1x Drive, V_OH= 0.8x

V_DD

2.9

5.6

2.3

4.5

4.7

9.0

3.8

7.6

4.6

8.9

7.3

14.1

5.9

mA

HIGH-Level Output Pulse

Current (Note 2)

I_OH

Push-Pull, 2x Drive, V_OH= 0.8x

V_DD

Push-Pull, 1x Drive, V_OL= 0.2x

V_DD

Push-Pull, 2x Drive, V_OL= 0.2x

V_DD

11.8

7.1

LOW-Level Output Pulse

Current (Note 2)

I_OL

NMOS OD, 1x Drive, V_OL= 0.1x

V_DD

2.7

5.3

NMOS OD, 2x Drive, V_OL= 0.1x

V_DD

14.0

From V_DDrising past PON_THR

t_RAMP= 1 µs

,

T_SU

Startup Time

1.885

2.087

0.888

0.502

3.288

1.078

0.735

ms

V

PON_THR

Power-On Threshold

V_DDLevel Required to Start Up the Chip 0.710

V_DDLevel Required to Switch Off the

Chip

POFF_THRPower-Off Threshold

0.393

V

Datasheet

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Revision 2.0

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 6: EC at T = -40 °C to +85 °C, V_DD= 1.1 V to 1.3 V Unless Otherwise Noted (Continued)

Parameter Description

Condition

Min

Typ

Max

1.262

Unit

1 M for Pull-up: V_IN= GND;

for Pull-down: V_IN= V_DD

0.831

1.019

MΩ

Pull-up or Pull-down

Resistance

100 k for Pull-up: V_IN= GND;

for Pull-down: V_IN= V_DD

R_PULL

90.197 102.269 126.064

kΩ

10 k For Pull-up: V_IN= GND;

for Pull-down: V_IN= V_DD

9.088

10.274

3.2

12.556

kΩ

C_IN

Input Capacitance

pF

Note 1 No hysteresis.

Note 2 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.

3.5 I²C PINS ELECTRICAL CHARACTERISTICS

Table 7: EC of the I²C Pins for DI Mode at T = -40 °C to +85 °C, Full V_DDRange Unless Otherwise Noted

Fast-Mode

Fast-Mode Plus

Parameter Description

Condition

Unit

Min

Max

Min

Max

LOW-level Input

Voltage

V_IL

-0.5

0.3xV_DD

-0.5

0.3xV_DD

V

HIGH-level Input

Voltage

V_IH

0.7xV_DD

V_DD

0.7xV_DD

V_DD

Hysteresis of

V_HYS

Schmitt Trigger

Inputs

0.05xV_DD

--

0.05xV_DD

--

V

Open-Drain at 2 mA sink

current

0

--

3

0.2xV_DD

0

--

0.2xV_DD

V

LOW-Level Output Open-Drain at 3 mA sink

V_OL

0.4

--

0.31

--

Voltage

current

Open-Drain at 20 mA sink

current

0

V

LOW-Level Output

Current

I_OL

V

_DD= 1.2 V, V_OL= 0.2 V

--

20

mA

Output Fall Time

from V_IHminto

V_ILmax

t_of

--

250

--

120

ns

Input Current each

IO Pin

I_i

0.1xV_DD< V_I< 0.9xV_DDmax

T = 25 °C, V_DD= 1.2 V

-10

--

+10

10

-10

--

+10

10

mA

pF

Capacitance for

each IO Pin

C_i

Note 1 For Fast-mode Plus SDA pin must be configured as NMOS 2x Open-Drain, see register [1328] in section 17.

Table 8: EC of the I²C Pins for DILV Mode at T = -40 °C to +85 °C, Full V_DDRange Unless Otherwise Noted

Fast-Mode

Parameter Description

Condition

Unit

Min

Max

0.3xV_DD

V_DD

V_IL

LOW-level Input Voltage

-0.5

V

V_IH

HIGH-level Input Voltage

0.7xV_DD

Open-Drain at 2 mA sink current

Open-Drain at 3 mA sink current

0

0.2xV_DD

0.4

V_OL

LOW-Level Output Voltage

Datasheet

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Revision 2.0

16 of 191

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 8: EC of the I²C Pins for DILV Mode at T = -40 °C to +85 °C, Full V_DDRange Unless Otherwise Noted (Continued)

Fast-Mode

Parameter Description

I_OLLOW-Level Output Current

t_of

Condition

Unit

Min

Max

V_DD= 1.2 V, V_OL= 0.2 V

3

--

mA

ns

Output Fall Time from V_IHminto

V_ILmax

--

250

I_i

Input Current each IO Pin

0.1xV_DD< V_I< 0.9xV_DDmax

-10

--

+10

10

mA

pF

C_i

Capacitance for each IO Pin

Table 9: I²C Pins Timing Characteristics for DI Mode, T = -40 °C to +85 °C, Full V_DDRange Unless Otherwise Noted

Speed

Parameter Description

Condition

400 kHz

1 MHz

Unit

Min

Max

400

--

Min

Max

1000

--

F_SCL

t_LOW

t_HIGH

Clock Frequency, SCL

--

kHz

ns

Clock Pulse Width Low

Clock Pulse Width High

1300

600

500

260

--

ns

Input Filter Spike Suppression

(SCL, SDA)

t_I

50

--

900

--

50

--

450

--

ns

t_{VD_ACK}

t_BUF

Data Valid Acknowledge Time

Bus Free Time between Stop and

Start

1300

500

t_{HD_STA}

t_{SU_STA}

t_{HD_DAT}

t_{SU_DAT}

t_R

Start Hold Time

600

55

100

--

260

55

50

--

ns

Start Set-up Time

Data Hold Time (Note 1)

Data Set-up Time

Inputs Rise Time

Inputs Fall Time

--

300

--

120

--

t_F

--

t_{SU_STO}

t_{VD_DAT}

Stop Set-up Time

600

260

Data Valid Time

--

900

--

450

Note 1 Does not meet standard I²C specifications: t_{HD_DAT}= 0 ns (min) for Fast-Mode and Fast-Mode Plus.

Note 2 Timing diagram can be found in Figure 99.

Table 10: I²C Pins Timing Characteristics for DILV Mode, T = -40 °C to +85 °C, Full V_DDRange Unless Otherwise Noted

Speed

Parameter Description

Condition

400 kHz

Unit

Min

--

Max

400

--

F_SCL

t_LOW

t_HIGH

Clock Frequency, SCL

kHz

ns

Clock Pulse Width Low

Clock Pulse Width High

1300

600

--

ns

Input Filter Spike Suppression (SCL,

SDA)

t_I

50

--

ns

t_{VD_ACK}

t_BUF

Data Valid Acknowledge Time

--

900

--

ns

Bus Free Time between Stop and Start

1300

Datasheet

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 10: I²C Pins Timing Characteristics for DILV Mode, T = -40 °C to +85 °C, Full V_DDRange Unless Otherwise Noted

Speed

Parameter Description

Condition

400 kHz

Unit

Min

600

180

200

--

Max

--

t_{HD_STA}

t_{SU_STA}

t_{HD_DAT}

t_{SU_DAT}

t_R

Start Hold Time

ns

Start Set-up Time

Data Hold Time (Note 1)

Data Set-up Time (Note 1)

Inputs Rise Time

--

300

--

t_F

Inputs Fall Time

--

t_{SU_STO}

t_{VD_DAT}

Stop Set-up Time

Data Valid Time

600

--

900

Note 1 Does not meet standard I²C specifications: t_{HD_DAT}= 0 ns (min), t_{SU_DAT}= 100 ns (min).

Note 2 Timing diagram can be found in Figure 99.

3.6 MACROCELLS CURRENT CONSUMPTION

Table 11: Typical Current Estimated for Each Macrocell at T = 25 °C, V_DD= 1.2 V

Parameter

Description

Note

Typ

Unit

PDET+I²C

PDET+BG+I²C

0.395

0.927

µA

PDET+BG+I_BIAS+Vref Source+Buffer

(Buffer Selection: Any ACMPxH Vref)

15.06

8.169

15.86

µA

PDET+BG+I_BIAS+Buffer+Vref Source

(Vref Source - External,

Buffer Selection: Any ACMPxH Vref)

Temperature Sensor+PDET+BG+I_BIAS+ Vref

Source+TPS+Buffer

OSC1+BG+PDET, Pre-divider = 1

OSC1+BG+PDET, Pre-divider = 4

OSC1+BG+PDET, Pre-divider = 8

OSC0+BG+PDET, Pre-divider = 1

OSC0+BG+PDET, Pre-divider = 4

OSC0+BG+PDET, Pre-divider = 8

79.492

82.364

80.911

1.177

µA

I_DD

Current

1.176

PDET+BG+I_BIAS+ACMPH0+ACMPH1 +Vref Source

(Vref Source - Internal,

18.228

µA

V_IN+= V_DD

,

V_IN-= 25 mV)

PDET+BG+I_BIAS+ACMPH0+ACMPH1

(V_IN+= V_DD,

11.222

6.277

µA

External Vref = 650 mV)

PDET+BG+I_BIAS+ACMPH0

(V_IN+= V_DD,

External Vref = 650 mV)

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Mixed-Signal Matrix

3.7 TIMING CHARACTERISTICS

Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C, V_DD= 1.2 V

Parameter

Description

Note

Unit

Rising

11

Falling

11

tpd

Delay

Digital Input to PP 1x

Digital Input to PP 2x

ns

11

tpd

Delay

Digital Input with Schmitt Trigger to PP 1x

11

ns

tpd

tw

Delay

Width

Delay

Low Voltage Digital Input to PP 1x

Digital input to NMOS 1x

Digital input to NMOS 2x

Output enable from Pin, OE Hi-Z to 1

Output enable from Pin, OE Hi-Z to 0

PP 1x 3 State Hi-Z to 1

PP 1x 3 State Hi-Z to 0

PP 2x 3 State Hi-Z to 1

PP 2x 3 State Hi-Z to 0

LATCH Q

11

--

11

10

--

ns

--

12

--

12

--

12

--

12

--

11

--

11

9

LATCH nQ

9

LATCH nRESET High Q

LATCH nRESET High nQ

LATCH nRESET Low Q

LATCH nRESET Low nQ

LATCH nSET High Q

9

10

9

LATCH nSET High nQ

LATCH nSET Low Q

9

10

9

10

9

LATCH nSET Low nQ

Multi-Function LATCH Q

Multi-Function LATCH nQ

Multi-Function LATCH nRESET Q

Multi-Function LATCH nRESET nQ

Multi-Function LATCH nSET Q

Multi-Function LATCH nSET nQ

2-bit LUT

9

6

3-bit LUT

9

8

4-bit LUT

8

Multi-Function 3-bit LUT

Multi-Function 3-bit LUT, CNT Delay

Multi-Function 4-bit LUT

Multi-Function 4-bit LUT, CNT Delay

Edge detect

9

14

8

13

8

13

6

13

6

Edge detect

171

176

175

181

tpd

Edge detect Delayed

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C, V_DD= 1.2 V(Continued)

Parameter

Description

Note

Rising

10

9

Falling

9

tpd

tw

Delay

Width

Delay

DFF Q

ns

DFF nQ

10

--

DFF nRESET High Q

--

DFF nRESET High nQ

10

--

DFF nRESET Low Q

10

--

DFF nRESET Low nQ

10

--

DFF nSET High Q

--

DFF nSET High nQ

10

--

DFF nSET Low Q

10

--

DFF nSET Low nQ

10

8

Multi-Function DFF Q

8

Multi-Function DFF nQ

8

Multi-Function DFF nRESET Q

Multi-Function DFF nRESET nQ

Multi-Function DFF nSET Q

Multi-Function DFF nSET nQ

Shift Registers Q

--

10

--

9

--

10

12

--

10

12

10

--

Shift Registers nQ

Multi-Function Reset CNT Q

Multi-Function Reset CNT nQ

Multi-Function CNT Delay Q

Multi-Function CNT Delay nQ

Multi-Function CNT Edge Detect Q

Multi-Function CNT Edge Detect nQ

Multi-Function CNT Edge Detect Q

Multi-Function CNT Edge Detect nQ

Multi-Function CNT Frequency Detect Q

Multi-Function CNT Frequency Detect nQ

Multi-Function CNT One Shot Q

Multi-Function CNT One Short nQ

PGen CLK

13

16

11

--

16

11

9

--

9

107

--

tw

107

20

--

tpd

22

11

--

11

6

PGen nRESET Hi-Z to 0

PGen nRESET Hi-Z to 1

Filter Q

--

7

--

62

99

62

108

Filter nQ

Table 13: Programmable Delay Expected Typical Delays and Pulse Widths at T = 25 °C, V_DD= 1.2 V

Parameter

Description

Note

Typ

Unit

tw1

Pulse Width, 1 cell

mode: (any) edge detect, edge detect output

175

ns

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Mixed-Signal Matrix

Table 13: Programmable Delay Expected Typical Delays and Pulse Widths at T = 25 °C, V_DD= 1.2 V (Continued)

Parameter

tw2

Description

Pulse Width, 2 cell

Pulse Width, 3 cell

Pulse Width, 4 cell

Delay, 1 cell

Note

Typ

347

520

695

6

Unit

ns

mode: (any) edge detect, edge detect output

mode: both edge delay, edge detect output

tw3

tw4

time1

time2

Delay, 2 cell

6

Delay, 3 cell

6

Delay, 4 cell

6

Delay, 1 cell

180

357

533

710

Delay, 2 cell

Delay, 3 cell

Delay, 4 cell

Table 14: Typical Filter Pulse Width, V_DD= 1.2 V

Parameter

Condition

Typ

< 45

< 37

< 28

Unit

T = 25 °C, V_DD= 1.2 V

ns

Filtered Pulse Width, t_block

T = -40 °C to +85 °C, V_DD= 1.2 V

T = -40 °C to +85 °C, V_DD= 1.2 V ± 0.1 V

3.8 COUNTER/DELAY CHARACTERISTICS

Table 15: Typical Counter/Delay Offset at T = 25 °C, V_DD= 1.2 V

Parameter

OSC Freq

25 MHz

OSC Power

auto

Typ

0.05

Unit

µs

Power-On time

2.048 kHz

25 MHz

auto

570

µs

frequency settling time

variable (CLK period)

auto

0.828

963

µs

2.048 kHz

25 MHz

auto

µs

forced

0-40.6

0-490

ns

2.048 kHz

µs

3.9 OSCILLATOR CHARACTERISTICS

Table 16: Oscillators Frequency Limits, V_DD= 1.1 V to 1.3 V

Temperature Range

+25 °C

Parameter

Minimum

Value, kHz

Maximum Value, kHz

Error, %

+1.3

-1.3

+2.1

-2.1

2.048 kHz RC OSC0

25 MHz RC OSC1

2.0205

24475

2.0754

25525

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Mixed-Signal Matrix

3.9.1 OSC Power-On Delay

Table 17: Oscillators Power-On Delay at T = 25 °C, V_DD= 1.1 V to 1.3 V, OSC Power Setting: "Auto Power-On"

OSC1 25 MHz

Start with Delay

OSC0 2.048 kHz

OSC1 25 MHz

Typical

Value, µs

Maximum

Value, µs

Typical

Value, ns

Maximum

Value, ns

Typical

Value, ns

Maximum

Value, ns

476

--

40.21

48.40

150

--

3.10 ACMP CHARACTERISTICS

Table 18: ACMP Specifications at T = -40 °C to +85 °C, V_DD= 1.1 V to 1.3 V Unless Otherwise Noted

Parameter Description

Note

Condition

Min

0

Typ

--

Max

V_DD

Unit

Positive Input

Negative Input

V

ACMP Input Voltage

V_ACMP

Range

0

--

Vhys = 0 mV,

Gain = 1,

Vref = 25 mV to 850 mV

V_offset

I_LKG

ACMP Input Offset

-7.0

--

5

7.1

mV

nA

ACMP Input Leakage

199

ACMPxH Power-Ondelay,

Minimal required wake

time for the "Wake and

Sleep function"

t_start

ACMP Startup Time

BG always On

--

77

µs

V_HYS= 25 mV

V_HYS= 150 mV

V_HYS= 25 mV

T = 25 °C

22.0

147.4

19.2

24.6

149.7

24.6

26.6

152.4

28.8

mV

ACMP0H, ACMP1H

Built-in Hysteresis

(Note 1)

V_HYS

V_HYS= 150 mV

Gain = 1x

133.8

--

149.4

3.3

162.1

--

mV

GΩ

MΩ

Series Input

Resistance

R_sin

Gain = 0.5x

1.0

1.2

1.5

Gain = 1,

Vref = 25 mV to 850mV,

Overdrive = 100 mV

Low to High

High to Low

Low to High

High to Low

--

0.6

0.8

0.6

0.7

1.5

1.8

1.4

1.2

µs

PROP

Propagation Delay,

Response Time

Gain = 1,

Vref = 250 mV to 650mV,

Overdrive = 100 mV

G = 1

1

G

Gain error

G = 0.5

Vref > 250 mV

0.495

0.500

0.504

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Mixed-Signal Matrix

Table 18: ACMP Specifications at T = -40 °C to +85 °C, V_DD= 1.1 V to 1.3 V Unless Otherwise Noted (Continued)

Parameter Description

Note

Condition

Min

-1.65

-8.17

-1.65

-8.17

-1.27

-7.87

-0.81

-7.46

-0.61

-7.15

-1.53

-8.19

-0.90

-7.33

-27.18

Typ

--

Max

1.49

4.42

1.49

4.42

1.37

4.27

0.72

3.67

0.68

3.61

1.73

5.01

1.05

3.92

31.20

3.64

7.75

6.51

7.83

6.55

9.79

Unit

%

T = 25 °C

Vref = 25 mV

--

%

T = 25 °C

V_DD= 1.2 V

--

%

Vref = 25 mV to 850 mV

Vref = 50 mV to 850 mV

Vref = 250 mV to 850 mV

Vref = 850 mV

--

%

--

%

Vref Accuracy,

Buffer Disabled

--

%

--

%

--

%

Vref = 250 mV to 850 mV

%

Vref

Vref = 850 mV

Vref Output Error,

%

Buffer Enabled

Vref = 25 mV to 850 mV

%

T = 25 °C, V_DD= 1.2 V -2.82

%

Vref = 200 mV to 850 mV,

Load Current = 1 µA

V_DD= 1.2 V

T = 25 °C

-7.81

-5.36

-6.10

-5.87

-9.06

%

mV

Vref = 25 mV

Vref Output Buffer

Offset

T = 25 °C

Vref = 25 mV to 850 mV

Load Resistance =

1 MΩ,

Vref = 25 mV to 850 mV

--

50

pF

Vref Output

Capacitance Loading

Load Resistance =

1 kΩ,

200

Vref = 25mV to 850 mV

Note 1 V_IL= Vin - V_HYS, V_IH= Vin.

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Mixed-Signal Matrix

4

User Programmability

The SLG47502/03 is a user programmable device with one time programmable (OTP) memory elements that are able to

configure the connection matrix and macrocells. A programming development kit allows the user the ability to create initial

devices. Once the design is finalized, the programming code (.gpx file) is forwarded to Dialog Semiconductor to integrate into a

production process.

Product

Definition

E-mail Product Idea, Definition, Drawing or

Customer creates their own design in

Schematic to

GreenPAK Designer

CMBUGreenPAK@diasemi.com

Dialog Semiconductor Applications

Engineer will review design specifications

with customer

Customer verifies GreenPAK in system

design

GreenPAK Design

approved

Samples, Design and Characterization

Report send to customer

GreenPAK Design

approved

Customers verifies GreenPAK design

GreenPAK Design

approved in system test

Custom GreenPAK part enters production

Figure 2: Steps to Create a Custom GreenPAK Device

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Mixed-Signal Matrix

5

IO Pins

The SLG47502/03 has a total of 9 GPIOs (13 GPIOs for 16-PIN version) which can operate as Input or Output, and 1 GPI Pin

which can operate as Input, as well as serve as a special function (such as outputting the voltage reference).

5.1 GPIO PINS

Pins from GPIO0 to GPIO12 serve as General Purpose IO Pins.

5.2 GPI PIN

GPI serves as a General Purpose Input Pin.

5.3 PULL-UP/DOWN RESISTORS

All IO Pins, except GPI, have the option for user selectable resistors connected to the input structure. The selectable values on

these resistors are 10 kΩ, 100 kΩ, and 1 MΩ. The internal resistors can be configured as either Pull-up or Pull-downs.

5.4 FAST PULL-UP/DOWN DURING POWER-UP

During power-up, IO Pull-up/down resistance will switch to 2.6 kΩ initially and then it will switch to normal setting value. This

function is enabled by register [1426].

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Mixed-Signal Matrix

5.5 GPI STRUCTURE

5.5.1 GPI Structure (for GPI)

Non-Schmitt

Trigger Input

Input Mode [1:0]

00: Digital In without Schmitt Trigger, wosmt_en = 1, OE=0

01: Digital In with Schmitt Trigger, smt_en = 1, OE = 0

10: Low Voltage Digital In mode, lv_en = 1, OE = 0

11: Reserved

WOSMT_EN

SMT_EN

OE

Schmitt

Trigger Input

Digital In

Note 1: OE cannot be selected by user

Note 2: OE is Matrix output, Digital In is Matrix input

Low Voltage

Input

LV_EN

OE

PAD

Figure 3: GPI Structure Diagram

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Mixed-Signal Matrix

5.6 GPIO WITH I²C MODE IO STRUCTURE

5.6.1 GPIO with I²C Mode Structure (for GPIO0 and GPIO1)

Non-Schmitt

Trigger Input

GPIO0, GPIO1 Mode [2:0]

00: Digital Input without Schmitt Trigger

01: Reserved

10: Low Voltage Digital Input

11: Reserved

WOSMT_EN

OE

Digital In

Low Voltage

Input

Note 1: OE cannot be selected by user and

is controlled by register. Digital In is Matrix input.

Note 2: GPIO0 and GPIO1 do not support

Push-Pull and PMOS Open-Drain modes.

Note 3: Can be varied over PVT, for reference

only.

LV_EN

Analog IO

Floating

s0

s1

s2

s3

2 kΩ

(Note 3)

s1

s0

900 kΩ

90 kΩ

8 kΩ

Res_sel [1:0]

00: Floating

01: 10 kΩ

Pull-up_EN

10: 100 kΩ

11: 1 MΩ

Digital OUT

I²C_EN register [31]

V_DD

Digital OUT

I²C_EN register [31]

GPIO0/1_OD_EN register [1313]/[1329]

PAD

FAST_MODE_EN register [1312]/[1328]

I²C_EN register [31]

Figure 4: GPIO with I²C Mode IO Structure Diagram

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Mixed-Signal Matrix

5.7 MATRIX OE IO STRUCTURE

5.7.1 Matrix OE IO Structure (from GPIO0 to GPIO11)

Non-Schmitt

Trigger Input

Input Mode [1:0]

00: Digital In without Schmitt Trigger, wosmt_en = 1

01: Digital In with Schmitt Trigger, smt_en = 1

10: Low Voltage Digital In mode, lv_en = 1

11: analog IO mode

WOSMT_EN

SMT_EN

Schmitt

Trigger Input

Digital IN

Output Mode [1:0]

00: Push-Pull 1x mode, pp1x_en = 1

01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1

10: NMOS 1x Open-Drain mode, od1x_en = 1

11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1

Low Voltage

Input

Note 1: Digital Out and OE are Matrix Output, Digital In is Matrix Input

Note 2: Can be varied over PVT, for reference only.

LV_EN

Analog IO

Floating

s0

V_DD

s1

s2

s3

s1

s0

2 kΩ

(Note 2)

900 kΩ

90 kΩ

8 kΩ

V_DD

Res_sel [1:0]

00: Floating

01: 10 kΩ

Pull-up_EN

10: 100 kΩ

11: 1 MΩ

Digital OUT

OE

OD1x_EN

PP1x_EN

V_DD

PAD

V_DD

Digital OUT

OE

OD2x_EN

PP2x_EN

Figure 5: Matrix OE IO Structure Diagram

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Mixed-Signal Matrix

5.8 IO TYPICAL PERFORMANCE

18

Push-Pull 2x @ VDD = 1.3 V

Push-Pull 1x @ VDD = 1.3 V

Push-Pull 2x @ VDD = 1.2 V

Push-Pull 1x @ VDD = 1.2 V

Push-Pull 2x @ VDD = 1.1 V

Push-Pull 1x @ VDD = 1.1 V

16

14

12

10

8

6

4

2

0

1.3

1.2

1.1

1

0.9

V_OH(V)

0.8

0.7

0.6

0.5

Figure 6: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C

20

18

16

14

12

10

8

Open Drain 1x @ VDD = 1.3 V

Open Drain 1x @ VDD = 1.2 V

Open Drain 1x @ VDD = 1.1 V

Push-Pull 1x @ VDD = 1.3 V

Push-Pull 1x @ VDD = 1.2 V

Push-Pull 1x @ VDD = 1.1 V

6

4

2

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

V_OL(V)

Figure 7: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range

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Mixed-Signal Matrix

16

Open Drain 1x @ VDD = 1.3 V

14

12

10

8

Open Drain 1x @ VDD = 1.2 V

Open Drain 1x @ VDD = 1.1 V

Push-Pull 1x @ VDD = 1.3 V

Push-Pull 1x @ VDD = 1.2 V

Push-Pull 1x @ VDD = 1.1 V

6

4

2

0

0.05

0.1

0.15

0.2

V_OL(V)

Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C

26

24

22

20

18

16

14

12

10

8

Open Drain 2x @ VDD = 1.3 V

Open Drain 2x @ VDD = 1.2 V

Open Drain 2x @ VDD = 1.1 V

Push-Pull 2x @ VDD = 1.3 V

Push-Pull 2x @ VDD = 1.2 V

Push-Pull 2x @ VDD = 1.1 V

6

4

2

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

V_OL(V)

Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range

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Mixed-Signal Matrix

16

Open Drain 2x @ VDD = 1.3 V

Open Drain 2x @ VDD = 1.2 V

14

Open Drain 2x @ VDD = 1.1 V

Push-Pull 2x @ VDD = 1.3 V

12

Push-Pull 2x @ VDD = 1.2 V

Push-Pull 2x @ VDD = 1.1 V

10

8

6

4

2

0

0.05

0.1

0.15

0.2

V_OL(V)

Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C

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Mixed-Signal Matrix

6

Connection Matrix

The Connection Matrix in the SLG47502/03 is used to create an internal routing for internal functional macrocells of the device

once it is programmed. The registers are programmed from the one time programmable (OTP) NVM cell during Test Mode

Operation. The output of each functional macrocell within the SLG47502/03 has a specific digital bit code assigned to it, that is

either set to active “High” or inactive “Low”, based on the design that is created. Once the 2048 register bits within the SLG47502/

03 are programmed, a fully custom circuit will be created.

The Connection Matrix has 64 inputs and 98 outputs. Each of the 64 inputs to the Connection Matrix is hard-wired to the digital

output of a particular source macrocell, including IO pins, LUTs, analog comparators, other digital resources, such as V_DDand

GND. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines.

For a complete list of the SLG47502/03’s register table, see Section 17.

Matrix Input Signal

N

Functions

GND

0

1

2

3

LUT2_0/DFF0 output/

Shift_Reg0 output

LUT2_1/DFF1 output/

Shift_Reg1 output

LUT2_2/DFF2 output/

Shift_Reg2 output

POR

V_DD

62

63

Matrix Inputs

0

1

2

97

N

Registers

registers [45:40]

registers [51:46]

registers [57:52]

Matrix Out: IN0 of

registers [627:622]

Matrix OUT: IN0 of

Matrix OUT: IN1 of

Matrix Out: Oscillator1

ENABLE

LUT2_0 or Clock In- LUT2_0 or Data In- LUT2_1 or Clock In-

put of DFF0 or Clock put of DFF0 or Data put of DFF1 or Clock

Input of Shift_Reg0 Input of Shift_Reg0 Input of Shift_Reg1

Function

Matrix Outputs

Figure 11: Connection Matrix

Function

Connection Matrix

GPIO8

GPIO7

LUT

GPIO7

GPIO8

GPIO9

LUT

GPIO9

Figure 12: Connection Matrix Usage Example

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Mixed-Signal Matrix

6.1 MATRIX INPUT TABLE

Table 19: Matrix Input Table

Matrix Decode

Matrix Input

Matrix Input Signal Function

Number

5

0

1

4

0

1

0

3

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

GND

1

LUT2_0/DFF0 output/Shift_Reg0 output

LUT2_1/DFF1 output/Shift_Reg1 output

LUT2_2/DFF2 output/Shift_Reg2 output

LUT2_3/PGen output

2

3

4

5

LUT3_0/DFF3 output/Shift_Reg3 output

LUT3_1/DFF4 output/Shift_Reg4 output

LUT3_2/DFF5 output/Shift_Reg5 output

LUT3_3/DFF6 output/Shift_Reg6 output

LUT3_4/DFF7 output/Shift_Reg7 output

LUT3_5/DFF8 output/Shift_Reg8 output

LUT3_6/DFF9 output/Shift_Reg9 output

LUT3_7/DFF10 output/Shift_Reg10 output

LUT3_8/DFF11 output/Shift_Reg11 output

LUT3_9/DFF12 output/Shift_Reg12 output

LUT4_0/DFF13 output/Shift_Reg13 output

CNT0 output

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

MLT0_LUT4_1/DFF14_OUT

CNT1 output

MLT1_LUT3_10/DFF15_OUT

CNT2 output

MLT2_LUT3_11/DFF16_OUT

CNT3 output

MLT3_LUT3_12/DFF17_OUT

CNT4 output

MLT4_LUT3_13/DFF18_OUT

CNT5 output

MLT5_LUT3_14/DFF19_OUT

CNT6 output

MLT6_LUT3_15/DFF20_OUT

CNT7 output

MLT7_LUT3_16/DFF21_OUT

GPIO0 digital input or I²C_virtual_0 Input

GPIO1 digital input or I²C_virtual_1 Input

I²C_virtual_2 Input

33

34

1

0

1

0

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 19: Matrix Input Table (Continued)

Matrix Decode

Matrix Input

Matrix Input Signal Function

Number

5

1

4

0

3

0

2

0

1

0

1

0

1

0

1

0

1

I²C_virtual_3 Input

35

I²C_virtual_4 Input

36

I²C_virtual_5 Input

37

I²C_virtual_6 Input

38

I²C_virtual_7 Input

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Programmable Delay Edge Detect Output

Edge Detect Filter Output

GPI Digital Input

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GPIO2 Digital Input

GPIO3 Digital Input

GPIO4 Digital Input

GPIO5 Digital Input

GPIO6 Digital Input

GPIO7 Digital Input

GPIO8 Digital Input

GPIO9 Digital Input (Note 1)

GPIO10 Digital Input (Note 1)

GPIO11 Digital Input (Note 1)

GPIO12 Digital Input (Note 1)

Reserved

Oscillator0 output 0

Oscillator0 output 1

Oscillator1 output

ACMP0H Output

ACMP1H Output

POR

V_DD

Note 1 GPIO 9, 10, 11, and 12 are available in 16-pin package only.

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

6.2 MATRIX OUTPUT TABLE

Table 20: Matrix Output Table

Register Bit

Matrix Output

Number

Matrix Output Signal Function

Address

[45:40]

[51:46]

IN0 of LUT2_0 or Clock Input of DFF0 or Clock Input of Shift_Reg0

0

IN1 of LUT2_0 or Data Input of DFF0 or Data Input of Shift_Reg0

IN0 of LUT2_1 or Clock Input of DFF1 or Clock Input of Shift_Reg1

IN1 of LUT2_1 or Data Input of DFF1 or Data Input of Shift_Reg1

IN0 of LUT2_2 or Clock Input of DFF2 or Clock Input of Shift_Reg2

IN1 of LUT2_2 or Data Input of DFF2 or Data Input of Shift_Reg2

IN0 of LUT2_3 or Clock Input of PGen

1

[57:52]

2

[63:58]

3

[69:64]

4

[75:70]

5

[81:76]

6

[87:82]

IN1 of LUT2_3 or nRST of PGen

7

[93:88]

IN0 of LUT3_0 or Clock Input of DFF3 or Clock Input of Shift_Reg3

IN1 of LUT3_0 or Data Input of DFF3 or Data Input of Shift_Reg3

IN2 of LUT3_0 or nRST(nSET) of DFF3 or nRST(nSET) of Shift_Reg3

IN0 of LUT3_1 or Clock Input of DFF4 or Clock Input of Shift_Reg4

IN1 of LUT3_1 or Data Input of DFF4 or Data Input of Shift_Reg4

IN2 of LUT3_1 or nRST(nSET) of DFF4 or nRST(nSET) of Shift_Reg4

IN0 of LUT3_2 or Clock Input of DFF5 or Clock Input of Shift_Reg5

IN1 of LUT3_2 or Data Input of DFF5 or Data Input of Shift_Reg5

IN2 of LUT3_2 or nRST(nSET) of DFF5 or nRST(nSET) of Shift_Reg5

IN0 of LUT3_3 or Clock Input of DFF6 or Clock Input of Shift_Reg6

IN1 of LUT3_3 or Data Input of DFF6 or Data Input of Shift_Reg6

IN2 of LUT3_3 or nRST(nSET) of DFF6 or nRST(nSET) of Shift_Reg6

IN0 of LUT3_4 or Clock Input of DFF7 or Clock Input of Shift_Reg7

IN1 of LUT3_4 or Data Input of DFF7 or Data Input of Shift_Reg7

IN2 of LUT3_4 or nRST(nSET) of DFF7 or nRST(nSET) of Shift_Reg7

IN0 of LUT3_5 or Clock Input of DFF8 or Clock Input of Shift_Reg8

IN1 of LUT3_5 or Data Input of DFF8 or Data Input of Shift_Reg8

IN2 of LUT3_5 or nRST(nSET) of DFF8 or nRST(nSET) of Shift_Reg8

IN0 of LUT3_6 or Clock Input of DFF9 or Clock Input of Shift_Reg9

IN1 of LUT3_6 or Data Input of DFF9 or Data Input of Shift_Reg9

IN2 of LUT3_6 or nRST(nSET) of DFF9 or nRST(nSET) of Shift_Reg9

IN0 of LUT3_7 or Clock Input of DFF10 or Clock Input of Shift_Reg10

IN1 of LUT3_7 or Data Input of DFF10 or Data Input of Shift_Reg10

IN2 of LUT3_7 or nRST(nSET) of DFF10 or nRST(nSET) of Shift_Reg10

IN0 of LUT3_8 or Clock Input of DFF11 or Clock Input of Shift_Reg11

IN1 of LUT3_8 or Data Input of DFF11 or Data Input of Shift_Reg11

IN2 of LUT3_8 or nRST(nSET) of DFF11 or nRST(nSET) of Shift_Reg11

IN0 of LUT3_9 or Clock Input of DFF12 or Clock Input of Shift_Reg12

8

[99:94]

9

[105:100]

[111:106]

[117:112]

[123:118]

[129:124]

[135:130]

[141:136]

[147:142]

[153:148]

[159:154]

[165:160]

[171:166]

[177:172]

[183:178]

[189:184]

[195:190]

[201:196]

[207:202]

[213:208]

[219:214]

[225:220]

[231:226]

[237:232]

[243:238]

[249:244]

[255:250]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 20: Matrix Output Table (Continued)

Register Bit

Matrix Output

Number

Matrix Output Signal Function

Address

[261:256]

[267:262]

[273:268]

[279:274]

[285:280]

[291:286]

IN1 of LUT3_9 or Data Input of DFF12 or Data Input of Shift_Reg12

36

37

38

39

40

41

42

IN2 of LUT3_9 or nRST(nSET) of DFF12 or nRST(nSET) of Shift_Reg12

IN0 of LUT4_0 or Clock Input of DFF13 or Clock Input of Shift_Reg13

IN1 of LUT4_0 or Data Input of DFF13 or Data Input of Shift_Reg13

IN2 of LUT4_0 or nRST(nSET) of DFF13 or nRST(nSET) of Shift_Reg13

IN3 of LUT4_0 or Clock Enable of DFF13 or Clock Enable of Shift_Reg13

IN0 of MLT0_LUT4_1 or Clock Input of DFF14 or

Delay0 Input (or Counter0 nRST Input)

[297:292]

[303:298]

IN1 of MLT0_LUT4_1 or nRST (nSET) of DFF14 or

Delay0 Input (or Counter0 nRST Input or External Clock Source)

43

44

IN2 of MLT0_LUT4_1 or Data Input of DFF14 or

Delay0 Input (or Counter0 nRST Input)

[309:304]

[315:310]

[321:316]

IN3 of MLT0_LUT4_1

45

46

IN0 of MLT1_LUT3_10 or Clock Input of DFF15 or

Delay1 Input (or Counter1 nRST Input)

IN1 of MLT1_LUT3_10 or nRST (nSET) of DFF15 or

47

48

49

50

51

52

53

54

55

56

57

58

59

60

[327:322]

[333:328]

[339:334]

[345:340]

[351:346]

[357:352]

[363:358]

[369:364]

[375:370]

[381:376]

[387:382]

[393:388]

[399:394]

[405:400]

Delay1 Input (or Counter1 nRST Input or External Clock Source)

IN2 of MLT1_LUT3_10 or Data Input of DFF15 or

Delay1 Input (or Counter1 nRST Input)

IN0 of MLT2_LUT3_11 or Clock Input of DFF16 or

Delay2 Input (or Counter2 nRST Input)

IN1 of MLT2_LUT3_11 or nRST (nSET) of DFF16 or

Delay2 Input (or Counter2 nRST Input or External Clock Source)

IN2 of MLT2_LUT3_11 or Data Input of DFF16 or

Delay2 Input (or Counter2 nRST Input)

IN0 of MLT3_LUT3_12 or Clock Input of DFF17 or

Delay3 Input (or Counter3 nRST Input)

IN1 of MLT3_LUT3_12 or nRST (nSET) of DFF17 or

Delay3 Input (or Counter3 nRST Input or External Clock Source)

IN2 of MLT3_LUT3_12 or Data Input of DFF17 or

Delay3 Input (or Counter3 nRST Input)

IN0 of MLT4_LUT3_13 or Clock Input of DFF18 or

Delay4 Input (or Counter4 nRST Input)

IN1 of MLT4_LUT3_13 or nRST (nSET) of DFF18 or

Delay4 Input (or Counter4 nRST Input or External Clock Source)

IN2 of MLT4_LUT3_13 or Data Input of DFF18 or

Delay4 Input (or Counter4 nRST Input)

IN0 of MLT5_LUT3_14 or Clock Input of DFF19 or

Delay5 Input (or Counter5 nRST Input)

IN1 of MLT5_LUT3_14 or nRST (nSET) of DFF19 or

Delay5 Input (or Counter5 nRST Input or External Clock Source)

IN2 of MLT5_LUT3_14 or Data Input of DFF19 or

Delay5 Input (or Counter5 nRST Input)

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 20: Matrix Output Table (Continued)

Register Bit

Matrix Output

Number

Matrix Output Signal Function

Address

IN0 of MLT6_LUT3_15 or Clock Input of DFF20 or

61

62

63

64

65

66

[411:406]

[417:412]

[423:418]

[429:424]

[435:430]

[441:436]

Delay6 Input (or Counter6 nRST Input)

IN1 of MLT6_LUT3_15 or nRST (nSET) of DFF20 or

Delay6 Input (or Counter6 nRST Input or External Clock Source)

IN2 of MLT6_LUT3_15 or Data Input of DFF20 or

Delay6 Input (or Counter6 nRST Input)

IN0 of MLT7_LUT3_16 or Clock Input of DFF21 or

Delay7 Input (or Counter7 nRST Input)

IN1 of MLT7_LUT3_16 or nRST (nSET) of DFF21 or

Delay7 Input (or Counter7 nRST Input or External Clock Source)

IN2 of MLT7_LUT3_16 or Data Input of DFF21 or

Delay7 Input (or Counter7 nRST Input)

[447:442]

[453:448]

[459:454]

[465:460]

[471:466]

[477:472]

[483:478]

[489:484]

[495:490]

[501:496]

[507:502]

[513:508]

[519:514]

[525:520]

[531:526]

[537:532]

[543:538]

[549:544]

[555:550]

[561:556]

[567:562]

[573:568]

[579:574]

[585:580]

[591:586]

[597:592]

[603:598]

GPIO0 Digital Output

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

GPIO1 Digital Output

GPIO2 Digital Output OE

GPIO2 Digital Output

GPIO3 Digital Output OE

GPIO3 Digital Output

GPIO4 Digital Output OE

GPIO4 Digital Output

GPIO5 Digital Output OE

GPIO5 Digital Output

GPIO6 Digital Output OE

GPIO6 Digital Output

GPIO7 Digital Output OE

GPIO7 Digital Output

GPIO8 Digital Output OE

GPIO8 Digital Output

GPIO9 Digital Output OE (Note 2)

GPIO9 Digital Output (Note 2)

GPIO10 Digital Output OE (Note 2)

GPIO10 Digital Output (Note 2)

GPIO11 Digital Output OE (Note 2)

GPIO11 Digital Output (Note 2)

GPIO12 Digital Output OE (Note 2)

GPIO12 Digital Output (Note 2)

Filter/Edge Detect Input

Programmable Delay/Edge Detect Input

PWR UP of ACMP0_H

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 20: Matrix Output Table (Continued)

Register Bit

Matrix Output

Number

Matrix Output Signal Function

Address

[609:604]

[615:610]

[621:616]

[627:622]

PWR UP of ACMP1_H

Temp sensor, Vref Out_0 Power Up

Oscillator0 ENABLE

94

95

96

97

Oscillator1 ENABLE

Note 1 For each Address, the two most significant bits are unused.

Note 2 GPIO 9, 10, 11, and 12 are available in 16-pin package only.

6.3 CONNECTION MATRIX VIRTUAL INPUTS

As mentioned previously, the Connection Matrix inputs come from the outputs of various digital macrocells on the device. Eight

of the Connection Matrix inputs have the special characteristic that the state of these signal lines comes from a corresponding

data bit written as a register value via I²C. This gives the user the ability to write data via the serial channel, and have this

information translated into signals that can be driven into the Connection Matrix and from the Connection Matrix to the digital

inputs of other macrocells on the device. The I²C address for reading and writing these register values is at byte 0x1.

Six of the eight Connection Matrix Virtual Inputs are dedicated to this virtual input function. An I²C write command to these register

bits will set the signal values going into the Connection Matrix to the desired state. A read command to these register bits will

read either the original data values coming from the NVM memory bits (that were loaded during the initial device startup), or the

values from a previous write command (if that has happened).

Two of the eight Connection Matrix Virtual Inputs are shared with Pin digital inputs (GPIO0 Digital or I²C_virtual_0 Input), and

(GPIO1 Digital or I²C_virtual_1 Input). If the virtual input mode is selected, an I²C write command to these register bits will set

the signal values going into the Connection Matrix to the desired state. A read command to these register bits will read either the

original data values coming from the NVM memory bits (that were loaded during the initial device startup), or the values from a

previous write command (if that has happened). The I²C disable/enable register bit [31] selects whether the Connection Matrix

input comes from the Pin input or from the virtual register:



Select SCL & Virtual Input 0 or GPIO0

Select SDA & Virtual Input 1 or GPIO1

See Table 21 for Connection Matrix Virtual Inputs.

Table 21: Connection Matrix Virtual Inputs

Register Bit

Addresses (d)

Matrix Input Number

Matrix Input Signal Function

32

33

34

35

36

37

38

39

I²C_virtual_0 Input

I²C_virtual_1 Input

I²C_virtual_2 Input

I²C_virtual_3 Input

I²C_virtual_4 Input

I²C_virtual_5 Input

I²C_virtual_6 Input

I²C_virtual_7 Input

[8]

[9]

[10]

[11]

[12]

[13]

[14]

[15]

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

7

Combination Function Macrocells

The SLG47502/03 has 15 combination function macrocells that can serve as more than one logic or timing function. In each case,

they can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be

implemented in these macrocells.



Three macrocells that can serve as 2-bit LUT or as D Flip-Flop, or as Shift Register

Ten macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset Input, or as Shift Register

One macrocell that can serve as either 2-bit LUT or as Programmable Pattern Generator (PGen)

One macrocell that can serve as either 4-bit LUT or as D Flip-Flop with Set/Reset Input, or as Shift Register

Inputs/Outputs for the 15 combination function macrocells are configured from the connection matrix with specific logic functions

being defined by the state of configuration bits.

When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined

function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).

7.1 2-BIT LUT OR D FLIP-FLOP OR SHIFT REGISTER MACROCELLS

There are three macrocells that can serve as 2-bit LUT or as DFF/LATCH, or as Shift Register. It is also possible to define the

active level (Q or nQ) for the macrocell’s output by registers [748], [753], [758]. DFF/Shift Register or LUT are selected by registers

[744], [749], [754]. When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection matrix

and produce a single output, which goes back into the connection matrix.

When used to implement Shift Register, the two input signals from the connection matrix go to the data (D_in), clock (CLK) inputs

for the Shift Register, with the output going back to the connection matrix. The input data (D_in) writes into LSB. The Shift Register

length (up to 4 bits/memory cells) is selected by registers [746:745], [751:750], [756:755], when these registers = 0 DFF/LATCH

function is selected.

When used to implement DFF/LATCH function, the two input signals from the connection matrix go to the data (D_in), clock (CLK)

inputs for the Flip-Flop, with the output going back to the connection matrix. LATCH or DFF configuration is selected by registers

[747], [752], [757].

The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:

DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change.

LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK

is High).

It's possible to read/write the Shift Register content via I²C. See section 15.4.10 for more information.

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

From Connectinon

Matrix Output [1]

LUT IN1

4 memory cells

S1

S0

D_in

DFF data in

ShRg data in

From Connectinon

Matrix Output [0]

LUT IN0

S1

S0

Clk

DFF CLK

ShRg CLK

LATCH/DFF_sel

Out[3:0]

4

2-bit LUT

[3]

[0]

To Connection

Matrix Input [1]

11

.

S0

S1

2

00

S0

S1

LUT config

ShRg/LUT_sel

1-bit NVM

ShRg_length [1:0]

2

4

2

nQ/Q_sel

4-bit NVM

Figure 13: 2-bit LUT0 or DFF0 or Shift Register0

From Connectinon

Matrix Output [3]

LUT IN1

4 memory cells

S1

S0

D_in

DFF data in

ShRg data in

From Connectinon

Matrix Output [2]

LUT IN0

S1

S0

Clk

DFF CLK

ShRg CLK

LATCH/DFF_sel

Out[3:0]

4

2-bit LUT

[3]

[0]

To Connection

Matrix Input [2]

11

.

S0

S1

2

00

S0

S1

LUT config

ShRg/LUT_sel

1-bit NVM

ShRg_length [1:0]

2

4

2

nQ/Q_sel

4-bit NVM

Figure 14: 2-bit LUT1 or DFF1 or Shift Register1

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

From Connectinon

Matrix Output [5]

LUT IN1

4 memory cells

S1

S0

D_in

DFF data in

ShRg data in

From Connectinon

Matrix Output [4]

LUT IN0

S1

S0

Clk

DFF CLK

ShRg CLK

LATCH/DFF_sel

Out[3:0]

4

2-bit LUT

[3]

[0]

To Connection

Matrix Input [3]

11

.

S0

S1

2

00

S0

S1

LUT config

ShRg/LUT_sel

1-bit NVM

ShRg_length [1:0]

2

4

2

nQ/Q_sel

4-bit NVM

Figure 15: 2-bit LUT2 or DFF2 or Shift Register2

Inital Value is loaded from NVM to Shift Register

V_DD

Data

Clk

POR

ShReg_Out[3:0]

Initial Value 1001 (x9)

0011

0111

1110

1100

1000

0000

0001

0011

0111

1111

(Internal Signal)

Q=ShReg_Out[0]

(see note 1)

Q=ShReg_Out[3]

MSB

LSB

(see note 2)

x9

Initial Value is transmitted

Input Data are transmitted

Note1 : Macrocell is configured as DFF

Note2 : Macrocell is configured as 4-bit Shift Register

Figure 16: DFF0 to DFF2 and Shift Register0 to Shift Register2 Operation

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Inital Value is loaded from NVM to Shift Register

V_DD

Data

Clk

ShReg_Out[3:0]

(Internal Signal)

Initial Value 1001 (x9)

0010

0101

1010

0101

1011

0111

POR

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[3]

(see note 3)

4 Clk pulses

Note1 : DFF Setting “Initial Value: 1”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 4-bits ShReg

Figure 17: DFF0 to DFF2 and Shift Register0 to Shift Register2 Operation with DFF Initial Value = 1

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Inital Value is loaded from NVM to Shift Register

V_DD

Data

Clk

ShReg_Out[3:0]

(Internal Signal)

Initial Value 0001 (x1)

0010

0101

1010

0101

1011

0111

POR

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[3]

(see note 3)

4 Clk pulses

Note1 : DFF Setting “Initial Value: 1”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 4-bits ShReg

Figure 18: DFF0 to DFF2 and Shift Register0 to Shift Register2 Operation with Initial Value = b0001

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT

This Macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:

2-Bit LUT0 is defined by registers [635:632]

2-Bit LUT1 is defined by registers [639:636]

2-Bit LUT2 is defined by registers [643:640]

Table 22: 2-bit LUT2_0 to 2-bit LUT2_2 Truth Table

IN1

0

IN0

0

OUT LUT0

register [632

register [633

register [634

register [635

OUT LUT1

register [636

register [637

register [638

register [639

OUT LUT2

register [640

register [641

register [642

register [643

]

LSB

0

1

0

1

MSB

Table 23 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created

within each of the 2-bit LUT logic cells.

Table 23: 2-bit LUT Standard Digital Functions

Function

AND-2

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-2

OR-2

NOR-2

XOR-2

XNOR-2

7.2 2-BIT LUT OR PROGRAMMABLE PATTERN GENERATOR

The SLG47502/03 has one combination function macrocell that can serve as a logic or a timing function. This macrocell can serve

as a Look Up Table (LUT), or a Programmable Pattern Generator (PGen).

When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection matrix and produces a single

output, which goes back into the connection matrix. When used as a LUT to implement combinatorial logic functions, the outputs

of the LUT can be configured to any user defined function, including the following standard digital logic devices (AND, NAND,

OR, NOR, XOR, XNOR). The user can also define the combinatorial relationship between inputs and outputs to be any selectable

function.

It is possible to define the RST level for the PGen macrocell. There are both high level reset (RST) and a low level reset (nRST)

options available, which are selected by register [760]. When operating as the Programmable Pattern Generator, the output of

the macrocell will clock out a sequence of two to sixteen bits that are user selectable in their bit values, and user selectable in

the number of bits (up to sixteen) that are output before the pattern repeats.

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

From Connection Matrix Output [6]

From Connection Matrix Output [7]

In0

In1

OUT

2-bit LUT3

LUT Truth

Table

To Connection Matrix Input [4]

S0

S1

registers [647:644]

0: 2-bit LUT3 OUT

1: PGen OUT

Pattern

size

nRST/RST

CLK

PGen

OUT

PGen

Data

register [759]

registers [871:856]

Figure 19: 2-bit LUT3 or PGen

V

DD

t

nRST

CLK

OUT

1

2

6

8

16 17

3

5

7

0

4

9

10 11

14 15

12 13

t

D7

D6

D5

D10

D8

D4

D3

D2

D1

D15

D0

D9

D0

D15

D14

D13

D12

D11

D0

t

Figure 20: PGen Timing Diagram

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Mixed-Signal Matrix

Table 24: 2-bit LUT2_3 Truth Table

IN1

0

IN0

0

OUT

register [647]

register [646]

register [645]

register [644]

LSB

0

1

0

1

MSB

This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:

2-Bit LUT2_3 is defined by registers [647:644]

Table 25 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created

within each of the 2-bit LUT logic cells.

Table 25: 2-bit LUT Standard Digital Functions

Function

AND-2

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-2

OR-2

NOR-2

XOR-2

XNOR-2

7.3 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET OR SHIFT REGISTER MACROCELLS

There are ten macrocells that can serve as 3-bit LUT or as DFF/LATCH, or as Shift Register. It is also possible to define the active

level (Q or nQ) for the macrocell’s output by registers [766], [774], [782], [790], [798], [806], [814], [822], [830], [838]. DFF/Shift

Register or LUT are selected by registers [761], [769], [777], [785], [793], [801], [809], [817], [825], [833]. When used to implement

LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a single output, which goes

back into the connection matrix.

When used to implement Shift Register, the three input signals from the connection matrix go to the data (D_in), clock (CLK), and

Set/Reset (nSET/nRST) inputs for the Shift Register, with the output going back to the connection matrix. It is possible to define

the active level for the Set/Reset input of Shift Register macrocell which is selected by registers [768], [776], [784], [792], [800],

[808], [816], [824], [832], [840]. The input data (D_in) writes into LSB. The Shift Register length (up to 8 bits/memory cells) is

selected by registers [764:762], [772:770], [780:778], [788:786], [796:794], [804:802]. [812:810], [820:818], [828:826], [836:834],

[845:842], when these registers = 0 DFF/LATCH function is selected.

When used to implement D Flip-Flop/LATCH function, the three input signals from the connection matrix go to the data (D_in),

clock (CLK), and Set/Reset (nSET/nRST) inputs for the Flip-Flop/LATCH, with the output going back to the connection matrix. It

is possible to define the active level for the Set/Reset input (nSET/nRST_sel which is selected by register [767], [775], [783],

[791], [799], [807], [815], [823], [831], [839]) of DFF/LATCH macrocell. LATCH or DFF configuration is selected by registers [765],

[773], [781], [789], [797], [805], [813], [821], [829], [837].

The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:

DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change.

LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK

is High)

.

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

It's possible to read/write the Shift Register content via I²C. See section 15.4.10 for more information.

LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [9]

8 memory cells

S1

S0

D_in

Clk

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [8]

S1

S0

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

From Connectinon

Matrix Output [10]

nSET/nRST_sel Out[7:0]

SET/RST_act_level LATCH/DFF_sel

8

3-bit LUT

[7]

To Connection

Matrix Input [5]

111

000

.

S0

S1

3

] 0 [

LUT config

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_length [2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 21: 3-bit LUT0 or DFF3 or Shift Register 3

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Mixed-Signal Matrix

LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [12]

8 memory cells

S1

S0

D_in

Clk

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [11]

S1

S0

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

From Connectinon

Matrix Output [13]

nSET/nRST_sel Out[7:0]

SET/RST_act_level LATCH/DFF_sel

8

3-bit LUT

[7]

To Connection

Matrix Input [6]

111

000

.

S0

S1

3

] 0 [

LUT config

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_length [2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 22: 3-bit LUT1 or DFF4 or Shift Register 4

LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [15]

8 memory cells

S1

S0

D_in

Clk

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [14]

S1

S0

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

From Connectinon

Matrix Output [16]

LATCH/DFF_sel

nSET/nRST_sel Out[7:0]

SET/RST_act_level

8

3-bit LUT

To Connection

Matrix Input [7]

[7]

111

000

.

S0

S1

3

] 0 [

LUT config

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_length [2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 23: 3-bit LUT2 or DFF5 or Shift Register 5

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [18]

8 memory cells

S1

S0

D_in

Clk

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [17]

S1

S0

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

From Connectinon

Matrix Output [19]

LATCH/DFF_sel

nSET/nRST_sel Out[7:0]

SET/RST_act_level

8

3-bit LUT

[7]

To Connection

Matrix Input [8]

111

000

.

S0

S1

3

] 0 [

LUT config

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_length [2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 24: 3-bit LUT3 or DFF6 or Shift Register 6

LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [21]

8 memory cells

S1

S0

D_in

Clk

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [20]

S1

S0

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

From Connectinon

Matrix Output [22]

LATCH/DFF_sel

nSET/nRST_sel Out[7:0]

SET/RST_act_level

8

3-bit LUT

[7]

To Connection

Matrix Input [9]

111

000

.

S0

S1

3

] 0 [

LUT config

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_length [2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 25: 3-bit LUT4 or DFF7 or Shift Register 7

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [24]

8 memory cells

S1

S0

D_in

Clk

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [23]

S1

S0

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

From Connectinon

Matrix Output [25]

nSET/nRST_sel Out[7:0]

SET/RST_act_level LATCH/DFF_sel

8

3-bit LUT

[7]

To Connection

Matrix Input [10]

111

000

.

S0

S1

3

] 0 [

LUT config

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_length [2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 26: 3-bit LUT5 or DFF8 or Shift Register 8

LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [27]

8 memory cells

S1

S0

D_in

Clk

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [26]

S1

S0

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

From Connectinon

Matrix Output [28]

nSET/nRST_sel Out[7:0]

SET/RST_act_level LATCH/DFF_sel

8

3-bit LUT

[7]

To Connection

111

Matrix Input [11]

.

S0

S1

3

] 0 [

LUT config

000

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_length [2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 27: 3-bit LUT6 or DFF9 or Shift Register 9

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [30]

8 memory cells

S1

S0

D_in

Clk

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [29]

S1

S0

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

From Connectinon

Matrix Output [31]

nSET/nRST_sel Out[7:0]

SET/RST_act_level LATCH/DFF_sel

8

3-bit LUT

[7]

To Connection

Matrix Input [12]

111

000

.

S0

S1

3

] 0 [

LUT config

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_length [2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 28: 3-bit LUT7 or DFF10 or Shift Register 10

LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [33]

8 memory cells

S1

S0

D_in

Clk

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [32]

S1

S0

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

From Connectinon

Matrix Output [34]

nSET/nRST_sel Out[7:0]

SET/RST_act_level LATCH/DFF_sel

8

3-bit LUT

[7]

To Connection

111

Matrix Input [13]

.

S0

S1

3

] 0 [

LUT config

000

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_length [2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 29: 3-bit LUT8 or DFF11 or Shift Register 11

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [36]

8 memory cells

S1

S0

D_in

Clk

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [35]

S1

S0

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

From Connectinon

Matrix Output [37]

nSET/nRST_sel Out[7:0]

SET/RST_act_level LATCH/DFF_sel

8

3-bit LUT

To Connection

Matrix Input [14]

[7]

111

000

.

S0

S1

3

] 0 [

LUT config

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_length [2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 30: 3-bit LUT9 or DFF12 or Shift Register 12

Inital Value is loaded from NVM to Shift Register

V_DD

Data

Clk

POR

ShReg_Out[7:0]

Initial Value 10011011 (x9B)

00110111 01101111 11011110 10111100 01111000 11110000 11100000 11000001 10000011 00000111 00001111

(Internal Signal)

Q=ShReg_Out[0]

(see note 1)

Q=ShReg_Out[7]

(see note 2)

MSB

LSB

x9

xB

Initial Value is transmitted (x9B)

Input Data are transmitted

Note1 : Macrocell is configured as DFF

Note2 : Macrocell is configured as 8-bit Shift Register

Figure 31: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Inital Value is loaded from NVM to Shift Register

V_DD

Data

Clk

POR

ShReg_Out[7:0]

(Internal Signal)

Initial Value 10011011 (x9B)

00000010 00000101 00001010 00010100 00101000 01010000 10100000

00000000

00000000 00000001

nReset

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[7]

(see note 3)

8 Clk pulses

Note1 : DFF Setting “Initial Value: 1”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 8-bits

Figure 32: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nReset, Initial Value: b10011011

Inital Value is loaded from NVM to Shift Register

V_DD

Data

Clk

POR

ShReg_Out[7:0]

(Internal Signal)

Initial Value 10011011

00000010 00000101

00000001

00000000

00000001 00000011 00000111

00000000

nReset

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[7]

(see note 3)

Note1 : DFF Setting “Initial Value: 1”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 8-bits

Figure 33: DFF3 to DFF12 and Shift Register3 to Shift Register12 Operation, nReset, Initial Value: b10011011, Case2

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Mixed-Signal Matrix

Inital Value is loaded from NVM to Shift Register

V_DD

Data

Clk

POR

ShReg_Out[7:0]

Initial Value 00011011

11011110 10111101

00000000

00000001 00000011 00000111

00110111 01101111

(Internal Signal)

nReset

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[7]

(see note 3)

Note1 : DFF Setting “Initial Value: 1”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 8-bits

Figure 34: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nReset, Initial Value: b00011011

Inital Value is loaded from NVM to Shift Register

V_DD

Data

Clk

POR

ShReg_Out[7:0]

Initial Value 00011010 (x1A)

11111100 11111001 11110010 11100100 11001000 10010000 00100000 11111111 11111111

11111111 11111110

(Internal Signal)

nSet

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[7]

(see note 3)

8 Clk pulses

Note1 : DFF Setting “Initial Value: 0”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 8-bits

Figure 35: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nSet, Initial Value: b00011010

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Mixed-Signal Matrix

Inital Value is loaded from NVM to Shift Register

V_DD

Data

Clk

POR

ShReg_Out[7:0]

(Internal Signal)

Initial Value 00011010

11111111

11111100 11111001

11111111

11111110 11111100 11111000

11111110

nSet

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[7]

(see note 3)

Note1 : DFF Setting “Initial Value: 0”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 8-bits

Figure 36: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nSet, Initial Value: b00011010, Case 2

Inital Value is loaded from NVM to Shift Register

V_DD

Data

Clk

POR

ShReg_Out[7:0]

Initial Value 10011010

00110101

11010100 10101001

11111111

11111110 11111100 11111000

01101010

(Internal Signal)

nSet

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[7]

(see note 3)

Note1 : DFF Setting “Initial Value: 0”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 8-bits

Figure 37: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nSet, Initial Value: b10011010

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Mixed-Signal Matrix

7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs

Each macrocell, when programmed for a LUT function, uses an 8-bit register to define their output function:

3-Bit LUT3_0 is defined by registers [655:648]

3-Bit LUT3_1 is defined by registers [663:656]

3-Bit LUT3_2 is defined by registers [671:664]

3-Bit LUT3_3 is defined by registers [679:672]

3-Bit LUT3_4 is defined by registers [687:680]

3-Bit LUT3_5 is defined by registers [695:688]

3-Bit LUT3_6 is defined by registers [703:696]

3-Bit LUT3_7 is defined by registers [711:704]

3-Bit LUT3_8 is defined by registers [719:712]

3-Bit LUT3_9 is defined by registers [727:720]

Table 26: 3-bit LUT3_0 to 3-bit LUT3_9 Truth Table

0

1

0

1

0

1

0

1

0

1

0

1

0

1

register register register register register register register register register register

[648] [656] [664] [672] [680] [688] [696] [704] [712] [720]

LSB

register register register register register register register register register register

[649] [657] [665] [673] [681] [689] [697] [705] [713] [721]

register register register register register register register register register register

[650] [658] [666] [674] [682] [690] [698] [706] [714] [722]

register register register register register register register register register register

[651] [659] [667] [675] [683] [691] [699] [707] [715] [723]

register register register register register register register register register register

[652] [660] [668] [676] [684] [692] [700] [708] [716] [724]

register register register register register register register register register register

[653] [661] [669] [677] [685] [693] [701] [709] [717] [725]

register register register register register register register register register register

[654] [662] [670] [678] [686] [694] [702] [710] [718] [726]

register register register register register register register register register register

[655] [663] [671] [679] [687] [695] [703] [711] [719] [727]

MSB

Table 27 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created

within each of the four 3-bit LUT logic cells.

Table 27: 3-bit LUT Standard Digital Functions

Function

AND-3

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

NAND-3

OR-3

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Mixed-Signal Matrix

Table 27: 3-bit LUT Standard Digital Functions (Continued)

Function

NOR-3

MSB

LSB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

XOR-3

XNOR-3

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Mixed-Signal Matrix

7.4 4-BIT LUT OR D FLIP-FLOP WITH SET/RESET OR SHIFT REGISTER MACROCELL

There is one macrocell that can serve as 4-bit LUT or as DFF/LATCH, or as Shift Register. It is also possible to define the active

level (Q or nQ) for the macrocell’s output by register [847]. DFF/Shift Register or LUT are selected by register [841]. When used

to implement LUT functions, the 4-bit LUT takes in four input signals from the connection matrix and produces a single output,

which goes back into the connection matrix.

When used to implement Shift Register, the four input signals from the connection matrix go to the data (D_in), clock (CLK),

clock enable (CLK_enable), and Set/Reset (nSET/nRST) inputs for the Shift Register, with the output going back to the

connection matrix. It is possible to define the active level for the reset/set input of Shift Register macrocell which is selected by

register [849]. The input data (D_in) writes into LSB. The Shift Register length (up to 16 bits/memory cells) is selected by register

[845:842]. Register [845:842] = 0 means that DFF/LATCH function is selected.

When used to implement D Flip-Flop function, the four input signals from the connection matrix go to the data (D_in), clock

(CLK), clock enable (CLK_enable), and Set/Reset (nSET/nRST) inputs for the Flip-Flop, with the output going back to the

connection matrix. Macrocell in LATCH configuration have three input signals: data (D_in), clock (CLK), and Set/Reset (nSET/

nRST). It is possible to define the active level for the reset/set input (nSET/nRST_sel which are selected by register [848]) of

DFF/LATCH macrocell. LATCH or DFF configuration is selected by register [846].

The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:

DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change. When clock enable (CLK_enable) is low, macrocell

doesn't react to any pulses at clock (CLK) input.

LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is

High).

It's possible to read/write the Shift Register content via I²C. See section 15.4.10 for more information.

LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [39]

16 memory cells

S1

S0

D_in

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [38]

S1

S0

Clk

From Connectinon

Matrix Output [40]

Clk_enable

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

nSET/nRST_sel Out[15:0] SET/RST_act_level LATCH/DFF_sel

16

4-bit LUT

From Connectinon

Matrix Output [41]

S1

S0

[15]

LUT IN3

DFF CLK Enable

ShRg CLK Enable

To Connection

Matrix Input [15]

1111

.

LUT config

S0

S1

.

4

] 0 [

.

0000

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_length [3:0]

4

8

4

nQ/Q_sel

8-bit NVM

Figure 38: 4-bit LUT0 or DFF13 or Shift Register 13

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Mixed-Signal Matrix

Inital Value is loaded from NVM to Shift Register

V_DD

Data

Clk

POR

CLK_En

Initial Value (xA7B2)

10100111/10110010

01001111 10011110 00111101 01111011 11110110 11101100 11011001 10110010 01100101 11001011 10010110 00101100 01011000 10110000 01100000 11000001 10000011 00000111

01100101 11001011 10010110 00101100 01011000 10110000 01100000 11000001 10000011 00000111 00001111 00011111 00111110 01111100 11111001 11110011 11100110 11001100

MSB

LSB

xA

x7

xB

Initial Value is transmitted (xA7B2)

x2

Input Data

is transmitted

Note1 : Macrocell is configured as DFF

Note2 : Macrocell is configured as 16-bit Shift Register

Figure 39: DFF13 and Shift Register 13 Operation

Inital Value is loaded from NVM to Shift Register

V_DD

Data

Clk

POR

CLK_En

Initial Value (xA7B2)

10100111/10110010

11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111110 11111100 11111000 11110000 11100000 11000001 10000011 00000111

11111111 11111111 11111110 11111100 11111000 11110000 11100000 11000001 10000011 00000111 00001111 00011111 00111110 01111100 11111001 11110011 11100110 11001100

ShReg_Out[15:0]

(Internal Signal)

nSet

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[15]

(see note 3)

16 Clk pulses

Note1 : DFF Setting “Initial Value: 0”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 16-bits ShReg

Figure 40: DFF13 and Shift Register 13 Operation, nSet, Initial Value: xA7B2

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Inital Value is loaded from NVM to Shift Register

V_DD

Data

Clk

POR

CLK_En

ShReg_Out[15:0]

(Internal Signal)

Initial Value (xA7B2)

10100111/10110010

00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000010 00000100 00001000 00010000 00100000 01000001 10000011 00000111

00000000 00000001 00000010 00000100 00001000 00010000 00100000 01000001 10000011 00000111 00001111 00011111 00111110 01111100 11111001 11110011 11100110 11001100

nReset

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[15]

(see note 3)

16 Clk pulses

Note1 : DFF Setting “Initial Value: 0”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 16-bits ShReg

Figure 41: DFF13 and Shift Register 13 Operation, nReset, Initial Value: xA7B2

7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT

Table 28: 4-bit LUT0 Truth Table

IN3

0

IN2

0

IN1

0

IN0

0

OUT

register [728]

register [729]

register [730]

register [731]

register [732]

register [733]

register [734]

register [735]

register [736]

register [737]

register [738]

register [739]

register [740]

register [741]

register [742]

register [743]

LSB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

This macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:

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Mixed-Signal Matrix

4-Bit LUT0 is defined by registers [743:728]

Table 29: 4-bit LUT Standard Digital Functions

Function

AND-4

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-4

OR-4

NOR-4

XOR-4

XNOR-4

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Mixed-Signal Matrix

8

Multi-Function Macrocells

The SLG47502/03 has 8 Multi-Function macrocells that can serve as more than one logic or timing function. In each case, they

can serve as a LUT, DFF with flexible settings, or as CNT/DLY with multiple modes such as One Shot, Frequency Detect, Edge

Detect, and others. Also, the macrocell is capable to combine those functions: LUT/DFF connected to CNT/DLY or CNT/DLY

connected to LUT/DFF, see Figure 42.

See the list below for the functions that can be implemented in these macrocells:



Seven macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays

One macrocell that can serve as a 4-bit LUT/D Flip-Flop and as 16-Bit Counter/Delay/FSM

To Connection Matrix

From Connection

Matrix

To Connection

Matrix

From Connection

Matrix

To Connection

Matrix

LUT

or

DFF

LUT

or

DFF

CNT/DLY

Figure 42: Possible Connections Inside Multi-Function Macrocell

Inputs/Outputs for the 8 Multi-Function function macrocells are configured from the connection matrix with specific logic functions

being defined by the state of NVM bits.

When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined

function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).

8.1 3-BIT LUT OR DFF/LATCH WITH 8-BIT COUNTER/DELAY MACROCELLS

There are seven macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays.

When used to implement LUT functions, the 3-bit LUTs each takes in three input signals from the connection matrix and produces

a single output, which goes back into the connection matrix or can be connected to CNT/DLY's input.

When used to implement D Flip-Flop function, the three input signals from the connection matrix go to the data (D), clock (CLK),

and Set/Reset (nRST/nSET) inputs of the Flip-Flop, with the output going back to the connection matrix or to the CNT/DLY's input.

The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:

DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change.

LATCH: when CLK is High, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK

is Low).

When used to implement Counter/Delays, each macrocell has a dedicated matrix input connection. For flexibility, each of these

macrocells has a large selection of internal and external clock sources, as well as the option to chain from the output of the

previous (N-1) CNT/DLY macrocell, to implement longer count/delay circuits. These macrocells can also operate in a One-Shot

mode, which will generate an output pulse of user-defined width. They can also operate in a Frequency Detection or Edge

Detection mode.

Counter/Delay macrocell has an initial value, which define its initial value after GPAK is powered up. It is possible to select initial

Low or initial High, as well as initial value defined by a Delay In signal.

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Mixed-Signal Matrix

For example, in case initial LOW option is used, the rising edge delay will start operation.

For timing diagrams refer to sections 7.1 and 8.3.

Note: After two DFF – counters initialize with counter data = 0 after POR.

Initial state = 1 – counters initialize with counter data = 0 after POR.

Initial state = 0 And After two DFF is bypass – counters initialize with counter data after POR.

CNT6 and CNT7 current count value can be read via I²C. However, it is possible to change the counter data (value counter starts

operating from) for any macrocell using I²C write commands. In this mode, it is possible to load count data immediately (after two

DFF) or after counter ends counting. See Section 15.4.8 for further details.

8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams

register [960] DFF or Latch Select

register [961] Output Select (Q or

From Connection

nQ)

Matrix Output A [48]

register [962] DFF Initial Polarity

Select

register [963] (nRST or nSET) from

matrix Output

IN2

IN1

IN0

S0

S1

3-bit LUT10

S0

S1

OUT

LUT Truth

Table

From Connection

Matrix Output B [47]

To Connection

S0

S1

S0

S1

Matrix Input [19]

8-bits NVM

registers [967:960]

S1

DFF

Registers

D

From Connection

Matrix Output C [46]

S0

S1

S0

S1

nRST/nSET

CLK

DFF/

Latch15

Q/nQ

register [972]

LUT/DFF Sel

registers [999:992]

registers [979:976]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [18]

0

S0

OUT

CNT/DLY1

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [987:984], [981:980], [975:973], [971:968]

Figure 43: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF15, CNT/DLY1)

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Mixed-Signal Matrix

register [1008] DFF or Latch Select

register [1009] Output Select (Q or

nQ)

From Connection

Matrix Output [51]

register [1110] DFF Initial Polarity

Select

IN2

IN1

IN0

S0

3-bit LUT11

S0

register [1111] (nRST or nSET) from

matrix Output

OUT

S1

LUT Truth

Table

From Connection

Matrix Output [50]

To Connection

S0

S1

S0

S1

Matrix Input [21]

8-bits NVM

registers [1015:1008]

S1

DFF

Registers

D

From Connection

Matrix Output [49]

S0

S1

S0

S1

DFF/

Latch16

nRST/nSET

CLK

Q/nQ

register [1020]

LUT/DFF Sel

registers [1047:1040]

registers [1027:1024]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [20]

0

S0

OUT

CNT/DLY2

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1047:1040], [1029:1027], [1023:1021], [1019:1016]

Figure 44: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF16, CNT/DLY2)

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Mixed-Signal Matrix

register [1056] DFF or Latch Select

register [1057] Output Select (Q or

nQ)

From Connection

Matrix Output [54]

register [1058] DFF Initial Polarity

Select

IN2

IN1

IN0

S0

3-bit LUT12

S0

register [1059] (nRST or nSET)

from matrix Output

OUT

S1

LUT Truth

Table

From Connection

Matrix Output [53]

To Connection

S0

S1

S0

S1

Matrix Input [23]

8-bits NVM

registers [1063:1056]

S1

DFF

Registers

D

From Connection

Matrix Output [52]

S0

S1

S0

S1

DFF/

Latch17

nRST/nSET

Q/nQ

CLK

register [1068]

LUT/DFF Sel

registers [1095:1088]

registers [1075:1072]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [22]

0

S0

OUT

CNT/DLY3

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1083:1080], [1077:1076], [1071:1069], [1067:1064]

Figure 45: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF17, CNT/DLY3)

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Mixed-Signal Matrix

register [1104] DFF or Latch Select

register [1105] Output Select (Q or

nQ)

register [1106] DFF Initial Polarity

Select

register [1107] (nRST or nSET) from

matrix Output

From Connection

Matrix Output [57]

IN2

IN1

IN0

S0

3-bit LUT13

S0

OUT

S1

LUT Truth

Table

From Connection

Matrix Output [56]

To Connection

S0

S1

S0

S1

Matrix Input [25]

8-bits NVM

registers [1110:1104]

S1

DFF

Registers

D

From Connection

Matrix Output [55]

S0

S1

S0

S1

_nRST/nSETDFF/

Q/nQ

Latch18

CLK

register [1116]

LUT/DFF Sel

registers [1143:1136]

registers [1123:1122]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [24]

0

S0

OUT

CNT/DLY4

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1131:1128], [1125:1124], [1119:1117], [1115:1112]

Figure 46: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT13/DFF18, CNT/DLY4)

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Mixed-Signal Matrix

register [1152] DFF or Latch Select

register [1153] Output Select (Q or

nQ)

register [1154] DFF Initial Polarity

Select

register [1155] (nRST or nSET) from

matrix Output

From Connection

Matrix Output [60]

IN2

IN1

IN0

S0

3-bit LUT14

S0

OUT

S1

LUT Truth

Table

From Connection

Matrix Output [59]

To Connection

S0

S1

S0

S1

Matrix Input [27]

8-bits NVM

registers [1158:1152]

S1

DFF

Registers

D

From Connection

Matrix Output [58]

S0

S1

S0

S1

DFF/

Latch19

nRST/nSET

Q/nQ

CLK

register [1164]

LUT/DFF Sel

registers [1171:1168]

Mode Sel

registers [1191:1184]

CNT

Data

ext_CLK

To Connection

Matrix Input [26]

0

S0

OUT

CNT/DLY5

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1179:1176], [1173:1172], [1167:1165], [1162:1159]

Figure 47: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT14/DFF19, CNT/DLY5)

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Mixed-Signal Matrix

register [1200] DFF or Latch Select

register [1201] Output Select (Q or

nQ)

From Connection

Matrix Output [63]

register [1202] DFF Initial Polarity

Select

IN2

IN1

IN0

S0

3-bit LUT15

S0

register [1203] (nRST or nSET)

from matrix Output

OUT

S1

LUT Truth

Table

From Connection

Matrix Output [62]

To Connection

S0

S1

S0

S1

Matrix Input [29]

8-bits NVM

registers [1206:1200]

S1

DFF

Registers

D

From Connection

Matrix Output [61]

S0

S1

S0

S1

DFF/

Latch20

nRST/nSET

Q/nQ

CLK

register [1212]

LUT/DFF Sel

registers [1239:1232]

registers [1219:1216]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [28]

0

S0

OUT

CNT/DLY6

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1227:1224], [1221:1220], [1215:1213], [1211:1207]

Figure 48: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT15/DFF20, CNT/DLY6)

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Mixed-Signal Matrix

register [1248] DFF or Latch Select

register [1249] Output Select (Q or

nQ)

From Connection

Matrix Output [66]

register [1250] DFF Initial Polarity Se

lect

-

IN2

IN1

IN0

S0

3-bit LUT16

S0

register [1251] (nRST or nSET) from

matrix Output

OUT

S1

LUT Truth

Table

From Connection

Matrix Output [65]

To Connection

S0

S1

S0

S1

Matrix Input [31]

8-bits NVM

registers [1255:1248]

S1

DFF

Registers

D

From Connection

Matrix Output [64]

S0

S1

S0

S1

DFF/

Latch21

nRST/nSET

CLK

Q/nQ

register [1260]

LUT/DFF Sel

registers [1287:1280]

registers [1267:1264]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [30]

0

S0

OUT

CNT/DLY7

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1275:1272], [1269:1268], [1263:1261], [1259:1255]

Figure 49: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT16/DFF21, CNT/DLY7)

As shown in Figures 22-28 there is a possibility to use LUT/DFF and CNT/DLY simultaneously.

Note: It is not possible to use LUT and DFF at once, one of these macrocells must be selected.



Case 1. LUT/DFF in front of CNT/DLY. Three input signals from the connection matrix go to previously selected LUT or DFF's

inputs and produce a single output which goes to a CND/DLY input. In its turn Counter/Delay's output goes back to the matrix.

Case 2. CNT/DLY in front of LUT/DFF. Two input signals from the connection matrix go to CND/DLY's inputs (IN and CLK).

Its output signal can be connected to any input of previously selected LUT or DFF, after which the signal goes back to the

matrix.



Case 3. Single LUT/DFF or CNT/DLY. Also, it is possible to use a standalone LUT/DFF or CNT/DLY. In this case, all inputs

and output of the macrocell are connected to the matrix.

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Mixed-Signal Matrix

8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs

Table 30: 3-bit LUT10 to 3-bit LUT16 Truth Table

0

1

0

1

0

1

0

1

0

1

0

1

0

1

register

[960]

register

[1008]

register

[1056]

register

[1104]

register

[1152]

register

[1200]

register

[1248]

LSB

register

[961]

register

[1009]

register

[1057]

register

[1105]

register

[1153]

register

[1201]

register

[1249]

register

[962]

register

[1010]

register

[1058]

register

[1106]

register

[1154]

register

[1202]

register

[1250]

register

[963]

register

[1011]

register

[1059]

register

[1107]

register

[1155]

register

[1203]

register

[1251]

register

[964]

register

[1012]

register

[1060]

register

[1108]

register

[1156]

register

[1204]

register

[1252]

register

[965]

register

[1013]

register

[1061]

register

[1109]

register

[1157]

register

[1205]

register

[1253]

register

[966]

register

[1014]

register

[1062]

register

[1110]

register

[1158]

register

[1206]

register

[1254]

register

[967]

register

[1015]

register

[1063]

register

[1111]

register

[1159]

register

[1207]

register

[1255]

MSB

Each macrocell, when programmed for a LUT function, uses an 8-bit register to define their output function:

3-Bit LUT10 is defined by registers [967:960]

3-Bit LUT11 is defined by registers [1015:1008]

3-Bit LUT12 is defined by registers [1063:1056]

3-Bit LUT13 is defined by registers [1111:1104]

3-Bit LUT14 is defined by registers [1159:1152]

3-Bit LUT15 is defined by registers [1207:1200]

3-Bit LUT16 is defined by registers [1255:1248]

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

8.2 4-BIT LUT OR DFF/LATCH WITH 16-BIT COUNTER/DELAY MACROCELL

There is one macrocell that can serve as either 4-bit LUT or as 16-bit Counter/Delay. When used to implement LUT function, the

4-bit LUT takes in four input signals from the Connection Matrix and produces a single output, which goes back into the Connection

Matrix. When used to implement 16-Bit Counter/Delay function, two of the four input signals from the connection matrix go to the

external clock (EXT_CLK) and reset (DLY_IN/CNT Reset) for the counter/delay, with the output going back to the connection

matrix.

This macrocell has an optional Finite State Machine (FSM) function. There are two additional matrix inputs for Up and Keep to

support FSM functionality. FSM has an option to reset its counted value either to 0 or to user defined data.

The behavior of FSM macrocell is described below:



FSM output Q goes to 1 if counter value reaches 0;

FSM Set Selection Mode sets the initial counter value to counter data;

RST Selection Mode sets the initial counter value to 0;

Counter value reaches maximum and overloads, after that counting starts from 0. Otherwise, in case of counting down from

maximum to 0, after overloading counter starts from 65535;

Mode signal synchronization (available for thee inputs) adds two extra clocks to avoid metastability issue.

This macrocell can also operate in a one-shot mode, which will generate an output pulse of user-defined width.

This macrocell can also operate in a frequency detection or edge detection mode.

This macrocell can have its active count value read via I²C. See Section 15.4.8 for further details.

Note: After two DFF – counters initialize with counter data = 0 after POR.

Initial state = 1 – counters initialize with counter data = 0 after POR.

Initial state = 0 And After two DFF is bypass – counters initialize with counter data after POR.

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram

From Connection

Matrix Output A [45]

register [872] DFF or Latch Select

register [873] DFF Output Select

(Q or nQ)

register [874] DFF Initial Polarity

Select

IN3

S0

S1

S0

S1

IN2

IN1

From Connection

Matrix Output B [44]

0

4-bit LUT1

S0

S1

S0

S1

S0

0

OUT

IN0

LUT Truth

Table

From Connection

Matrix Output C [43]

S0

S1

To Connection

S0

S1

S0

Matrix Input [17]

registers [897:896] =

00, 10, 11

16-bits NVM

registers [887:872]

1

S1

From Connection

Matrix Output D [42]

DFF

D

S0

S1

Registers

S0

S1

S0

nSET

Q/nQ

DFF14

1

nRST

CLK

LUT/DFF Sel

register [892]

registers [903:902]

registers [927:912]

CNT

registers [899:896]

0

S0

S1

S2

S3

Data

ext_CLK

CMO* [44]

CMO* [43]

S1

S0

To Connection

Matrix Input [16]

S0

0

S0

S1

S2

S3

CMO* [45]

CMO* [44]

CMO* [43]

CMO* [42]

S1

S2

S3

OUT

CNT/DLY0

DLY_IN/CNT Reset

CMO* [43]

S1

S0

From Connection

Matrix Output [44]

0

KEEP

UP

From Connection

Matrix Output [45]

FSM

S1

S0

Config

Data

0

Note: CMO - Connection Matrix Output

registers [897:896] = 01

registers [907:904], [901:900], [895:893], [891:888]

Figure 50: 4-bit LUT1 or CNT/DLY0

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Mixed-Signal Matrix

8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs

Table 31: 4-bit LUT1 Truth Table

IN3

0

IN2

0

IN1

0

IN0

0

OUT

register [872]

register [873]

register [874]

register [875]

register [876]

register [877]

register [878]

register [879]

register [880]

register [881]

register [882]

register [883]

register [884]

register [885]

register [886]

register [887]

LSB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

This macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:

4-Bit LUT1 is defined by registers [887:872]

Table 32: 4-bit LUT Standard Digital Functions

Function

AND-4

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-4

OR-4

NOR-4

XOR-4

XNOR-4

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Mixed-Signal Matrix

8.3 CNT/DLY TIMING DIAGRAMS

8.3.1 Delay Mode CNT/DLY0 to CNT/DLY7

Delay macrocell can automatically start/stop oscillator (Figure 51).

Delay In

Asynchronous delay variable

OSC: force power-on

(always running)

Delay Output

delay = period x (counter data + 1) + variable

variable is from 0 to 1 clock period

delay = period x (counter data + 1) + variable

variable is from 0 to 1 clock period

Delay In

offset

OSC: auto power-on

(powers up from delay in)

Delay Output

delay = offset + period x (counter data + 1)

See offset in table 11

delay = offset + period x (counter data + 1)

See offset in table 11

Figure 51: Delay Macrocell Behavior with Different Oscillators Options (Edge Select: Both, Counter Data: 3)

The macrocell shifts the respective edge to a set time and restarts by appropriate edge. It works as a filter if the input signal is

shorter than the delay time.

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

Delay Function

Rising Edge Detection

Delay Function

Falling Edge Detection

t

Delay Function

Both Edge Detection

Figure 52: Delay Mode Timing Diagram (Rising, Falling, and Both Edge Detection)

8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY7

RESET_IN

CLK

Counter OUT

4 CLK period pulse

Count start in first rising edge CLK

Figure 53: Counter Mode Timing Diagram without Two DFFs Synced Up

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Mixed-Signal Matrix

.

RESET_IN

CLK

Counter OUT

4 CLK period pulse

Count start in 0 CLK after reset

Figure 54: Counter Mode Timing Diagram with Two DFFs Synced Up

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY7

This macrocell will generate a pulse whenever a selected edge is detected on its input. Register bits set the edge selection. The

pulse width is determined by counter data and clock selection properties. The output pulse polarity (non-inverted or inverted) is

selected by register bit. Any incoming edges will be ignored during the pulse width generation. The following diagram shows

one-shot function for non-inverted output.

Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

One-Shot Function

Rising Edge Detection

t

One-Shot Function

Falling Edge Detection

t

One-Shot Function

Both Edge Detection

t

Figure 55: One-Shot Function Timing Diagram

This macrocell generates a high level pulse with a set width (defined by counter data) when detecting the respective edge. It does

not restart while pulse is high.

8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY7

Rising Edge: The output goes high if the time between two successive edges is less than the delay. The output goes low if the

second rising edge has not come after the last rising edge in specified time.

Falling Edge: The output goes high if the time between two falling edges is less than the set time. The output goes low if the

second falling edge has not come after the last falling edge in specified time.

Both Edge: The output goes high if the time between the rising and falling edges is less than the set time, which is equivalent to

the length of the pulse. The output goes low if after the last rising/falling edge and specified time, the second edge has not come.

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

Frequency Detector Function

Rising Edge Detection

Frequency Detector Function

Falling Edge Detection

t

Frequency Detector Function

Both Edge Detection

Figure 56: Frequency Detection Mode Timing Diagram

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY7

The macrocell generates high level short pulse when detecting the respective edge. See Table 11.

Delay time

One-Shot/Freq. DET/Delay IN

t

Edge Detector Function

Rising Edge Detection

Edge Detector Function

Falling Edge Detection

t

Edge Detector Function

Both Edge Detection

Figure 57: Edge Detection Mode Timing Diagram

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY7

In Delayed Edge Detection Mode, High level short pulses are generated on the macrocell output after the configured delay time,

if the corresponding edge was detected on the input.

If the input signal is changed during the set delay time, the pulse will not be generated. See Figure 58.

Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

Delayed Edge Detector Function

Rising Edge Detection

Delayed Edge Detector Function

Falling Edge Detection

t

Delayed Edge Detector Function

Both Edge Detection

Figure 58: Delayed Edge Detection Mode Timing Diagram

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

8.3.7 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes

There is a difference in counter value for Counter and Delay/One-Shot/Frequency Detect modes. Compared to Counter mode,

in Delay/One-Shot/Frequency Detect modes the counter value is shifted for two rising edges of the clock signal. See Figure 59:

One-Shot/Freq. SET/Delay IN

CLK

CNT Out

3

2

1

0

3

CNT Data

2

DLY Out

3

2

Delay Data

1

3

One-Shot Out

One-Shot Data

3

2

3

1

3

Figure 59: Counter Value, Counter Data = 3

8.4 FSM TIMING DIAGRAMS

RESET IN

KEEP

COUNT END

CLK

3

2

1

0

3

2

1

0

3

2

1

3

2

1

0

Q

Note: Q = current counter value

Figure 60: CNT/FSM Mode Timing Diagram (Reset Rising Edge Mode, OSC is Forced On, UP=0) for CNT Data = 3

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Mixed-Signal Matrix

SET IN

KEEP

COUNT END

CLK

2

1

0

3

2

1

0

3

2

1

2

1

0

3

Q

Note: Q = current counter value

Figure 61: CNT/FSM Mode Timing Diagram (Set Rising Edge Mode, OSC is Forced On, UP = 0) for CNT Data = 3

RESET IN

KEEP

COUNT END

CLK

65534 65535

0

7

8

9

10 11

3

4

5

3

4

5

3

4

5

6

0

Q

Note: Q = current counter value

Figure 62: CNT/FSM Mode Timing Diagram (Reset Rising Edge Mode, OSC is Forced On, UP = 1) for CNT Data = 3

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Mixed-Signal Matrix

SET IN

KEEP

COUNT END

CLK

65534 65535

0

8

9

10 11 12

3

4

5

3

4

5

4

5

6

7

3

Q

Note: Q = current counter value

Figure 63: CNT/FSM Mode Timing Diagram (Set Rising Edge Mode, OSC is Forced On, UP = 1) for CNT Data = 3

Two extra clocks

Delay In

Clk

Keep

3

2

1

3

2

1

3

Internal Counter

Q

Figure 64: DLY/FSM Mode, Falling Edge Delay, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3

Two extra clocks

Delay In

Clk

Keep

3

2

1

3

2

1

3

Internal Counter

Q

Figure 65: One Shot/FSM Mode, Rising Edge, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Two extra clocks

Delay In

Clk

Keep

3

2

3

2

3

2

1

3

Internal Counter

Q

Less than

3 clk

between

2 rising edges

Figure 66: Freq. Detector/FSM Mode, Rising Edge, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3

Time less than CNT Data

doesn’t cause any change

Two extra clocks

Delay In

Clk

Keep

3

2

1

3

2

1

Internal Counter

3

Q

Figure 67: Delayed Edge Detector/FSM Mode, Rising Edge, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3

8.5 WAKE AND SLEEP CONTROLLER

SLG47502/03 has a Wake and Sleep function for all ACMPs. The macrocell CNT/DLY0 can be reconfigured for this purpose

registers [953:952] = 11 and register [948] = 1. The WS serves for power saving, it allows to switch on and off selected ACMPs

on selected bit of 16-bit counter.

Note 1: BG/Analog_Good time is long and should be considered in wake and sleep timing in case it dynamically powers on/off.

Note 2: Wake time should be long enough to make sure ACMP and Vref have enough time to get a sample before going to sleep.

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Power Control

From Connection Matrix Output [96] for 2 kHz OSC0

WS Controller

OSC

CNT0_out

CNT_end

CNT

To Connection Matrix Input [16]

ck

CK_OSC

Divider

Analog Control Block

ACMPx WS EN:

registers [953:952]

2

bg/regulator

pdb

From Connection

Matrix Output [94:93]

WS_out

WS_PD

(from OSC PD)

ACMPs_PD

WS_out

WS_PD to W&S out

state selection register [947]

registers [907:904]

WS clock freq. selection

registers [927:912]

WS ratio control data

ACMPs

register [949]

WS mode: normal or short wake

Note: WS_PD is High at WS OSC

ACMPH0,1 OUT

2

+

-

0

1

(2 kHz OSC0) power-down

2

To Connection

Matrix Input

[60, 61]

ACMPs_PD

WS_out

BG/Analog_Good

Figure 68: Wake/Sleep Controller

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

time between Reset goes low

and 1st WS clock rsing edge

Force Wake

CNT_RST

(From Connection Matrix)

ACMP_PD is High

(From Connection Matrix)

CNT0_out

(To Connection Matrix)

WS_out

(internal signal)

Data is latched

BG/Analog_Good

(internal signal)

Sleep Mode

ACMP Latches Last Data

Normal ACMP

Sleep Mode

ACMP Latches New Data

Normal ACMP

Sleep Mode

ACMP Latches

New Data

Operation

ACMP follows input

BG/Analog

Startup time*

BG/Analog

Startup time*

Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.

Figure 69: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used

time between Reset goes low

and 1st WS clock rsing edge

Force Wake

CNT_RST

(From Connection Matrix)

ACMP_PD is High

(From Connection Matrix)

CNT0_out

(To Connection Matrix)

WS_out

(internal signal)

Data is latched

BG/Analog_Good

(internal signal)

Sleep Mode

ACMP Latches Last Data

Sleep Mode

ACMP Latches New Data

Normal ACMP

Operation for short time

ACMP follows inout

Sleep Mode

ACMP Latches

New Data

Normal ACMP

Operation for short time

ACMP follows inout

BG/Analog

Startup time*

BG/Analog

Startup time*

Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.

Figure 70: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

time between Reset goes low

and 1st WS clock rsing edge

Force Sleep

CNT_SET

(From Connection Matrix)

ACMP_PD is High

(From Connection Matrix)

CNT0_out

(To Connection Matrix)

WS_out

(internal signal)

Data is latched

BG/Analog_Good

(internal signal)

Sleep Mode

ACMP Latches Last Data

Normal ACMP

Sleep Mode

ACMP Latches New Data

Operation

ACMP follows input

BG/Analog

Startup time*

Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.

Figure 71: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used

time between Reset goes low

and 1st WS clock rsing edge

Force Sleep

CNT_RST

(From Connection Matrix)

ACMP_PD is High

(From Connection Matrix)

CNT0_out

(To Connection Matrix)

WS_out

(internal signal)

Data is latched

BG/Analog_Good

(internal signal)

Sleep Mode

ACMP Latches New Data

ACMP Latches Last Data

Normal ACMP

Operation for short time

ACMP follows inout

BG/Analog

Startup time*

Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.

Figure 72: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Set is Used

Note: If low power BG is powered on/off by WS, the wake time should be longer than 2.1 ms. The BG/analog start up time will

take maximal 2 ms. Therefore, 8 periods of the Oscillator0 is recommended for the wake time, when BG is configured to Auto

Power mode. If low power BG is always on, Oscillator0 period is longer than required wake time. The BG/analog start up time will

take maximal 450 us for ACMP0/1. The short wake mode can be used to reduce the current consumption.

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Mixed-Signal Matrix

To use any ACMP under WS controller, the following settings must be done:



ACMP Power Up Input from matrix = 1 (for each ACMP separately);

CNT/DLY0 must be set to Wake and Sleep Controller function (for all ACMP);

Register WS → enable (for each ACMP separately);

CNT/DLY0 set/reset input = 0 (for all ACMP).

The user can select a period of time while the ACMP is sleeping in a range of 1 - 65535 clock cycles. Before they are sent to

sleep their outputs are latched, so the ACMPs remain their state (High or Low) while sleeping.

WS controller has the following settings:



Wake and Sleep Output State (High/Low)

If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = High, the

ACMP is continuously on.

If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = Low, the

ACMP is continuously off.

Both cases WS function is turned off.



Counter Data (Range: 1 - 65535)

User can select wake and sleep ratio of the ACMP; counter data = sleep time, one clock = wake time.

Q mode - defines the state of WS counter data when Set/Reset signal appears Reset - when active signal appears, the WS

counter will reset to zero and High level signal on its output will turn on the ACMPs. When Reset signal goes out, the WS

counter will go Low and turn off the ACMP until the counter counts up to the end. Set - when active signal appears, the WS

counter will stop and Low level signal on its output will turn off the ACMP. When Set signal goes out, the WS counter will go on

counting and High level signal will turn on the ACMP while counter is counting up to the end.

Note: The OSC0 matrix power-down to control ACMP WS is not supported for short wait time option.

Edge Select defines the edge for Q mode. High level Set/Reset - switches mode Set/Reset when level is High.

Note: Q mode operates only in case of "High Level Set/Reset”.



Wake time selection - time required for wake signal to turn the ACMPxH on.

Normal Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on until

WS signal is Low again. Wake time is one clock period. It should be longer than BG turn on time and minimal required com-

paring time of the ACMP.

Short Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on for 1 µs

and turn off regardless of WS signal. The WS signal width does not matter.



Keep - pauses counting while Keep = 1

Up - reverses counting

If Up = 1, CNT is counting up from user selected value to 65535.

If Up = 0, CNT is counting down from user selected value to 0.

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Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

9

Analog Comparators

There are two High Speed Rail-to-Rail General Purpose Analog Comparators (ACMP) macrocells in the SLG47502/03. For the

ACMP cells to be used in a GreenPAK design, the power up signals (ACMP0H PWR UP and ACMP1H PWR UP) need to be

active. By connecting to signals coming from the Connection Matrix, it is possible to have each ACMP be ON continuously, OFF

continuously, or switched on periodically, based on a digital signal coming from the Connection Matrix. When ACMP is powered

down, its output is low. It is possible to decrease Power-On time of ACMP by forcing internal bias current generator, register

[1532] = 1.

Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources, and can also have a

selectable gain stage (1x, 0.5x) before connection to the analog comparator. The gain divider is unbuffered and has input

resistance of 1.2 MΩ (typ.) for 0.5x and 100 MΩ for 1x. Each of the ACMP cells has a negative input signal that is either created

from an internal Vref or provided by any external source (GPIO 2). Note that the external Vref signal is filtered with a 2nd order

low pass filter with 300 kHz typical bandwidth, see Figure 73 to Figure 74.

Input bias current < 1 nA (typ).

PWR UP = 1 => ACMP is powered up.

PWR UP = 0 => ACMP is powered down.

During power-up, the ACMP output will remain LOW, and then becomes valid after power up signal goes high for ACMP0H and

ACMP1H (see parameter tstart in Table 18).

It is possible to enable Low Pass Filter (LPF) either onACMP IN+ or onACMP out, registers [1497:1496] and register [1513:1512].

Each cell also has a hysteresis selection, to offer hysteresis of (0, 25, 50, 150) mV. The hysteresis option is available when using

an internal Vref only.

ACMP0H IN+ options are GPIO and V_DD

.

ACMP1H IN+ options are GPIO, ACMP0H IN+ MUX output, Temperature Sensor.

See Table 33 for ACMP Inputs selection.

Table 33: ACMP Input Selection

Register

[1530]

Register

[1500]

Register

[1516]

ACMP0H Positive Input

ACMP1H Positive Input

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ACMP0H+ PIN

V_DD

ACMP1H+ PIN

ACMP0H+ PIN

ACMP1H+ PIN

V_DD

ACMP0H+ PIN

V_DD

Temp Sensor

V_DD

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Mixed-Signal Matrix

9.1 ACMP0H BLOCK DIAGRAM

Registers [1495:1494]

to ACMP1H input MUX

Hysteresis

Selection

ACMP

Ready

Registers [1499:1498]

GPIOx: ACMP0H+

V_DD

High Speed

ACMP

0

1

Selectable

Gain

0

1

to Connection

Matrix Input [60]

GPIOx in analog IO mode;

Registers [1500]

Pwr Up

LATCH

from Connection

Matrix Output [93]

W/S Control

Registers [953:952]

Ext. Vref0

Low Pass

Filter*

111111

Vref

34 100001

...

Internal Vref

000000

Registers [1493:1488]

Note*: 2^ndorder low pass filter

typical bandwidth is 300 kHz

Figure 73: ACMP0H Block Diagram

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9.2 ACMP1H BLOCK DIAGRAM

Registers [1511:1510]

Hysteresis

Selection

ACMP

Ready

Registers

[1515:1514]

GPIOx: ACMP1H+

00

High Speed

ACMP

From ACMP0H IN+ MUX Output ⁰¹

Selectable

Gain

10

0

1

Temperature sensor out

to Connection

Matrix Input [61]

11

Pwr Up

LATCH

2

GPIOx in analog IO mode;

Registers [1526:1525]

from Connection

Matrix Output [94]

W/S Control

Ext Vref0 input

Register [953:952]

1

0

Low Pass

Filter*

111111

Ext Vref1 input

Register [1517]

34 100001

...

Internal Vref

000000

Registers [1509:1504]

Note*: 2^ndorder low pass filter

typical bandwidth is 300 kHz

Figure 74: ACMP1H Block Diagram

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9.3 ACMP TYPICAL PERFORMANCE

3

High To Low, Overdrive = 10 mV

Low to High, Overdrive = 10 mV

Low to High, Overdrive = 100 mV

High to Low, Overdrive = 100 mV

2.5

2

1.5

1

0.5

0

25

250

425

650

850

Vref (mV)

Figure 75: Typical Propagation Delay vs. Vref for ACMPxH at T = 25 °C, V_DD= 1.1 V to 1.3 V, Gain = 1, Hysteresis = 0

8

6

4

2

0

-2

-4

-6

-8

25

250

425

650

850

Vref (mV)

Figure 76: ACMPxH Input Offset Voltage vs. Vref at T = -40 °C to 85 °C, V_DD= 1.1 V to 1.3 V

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10 Programmable Delay/Edge Detector

The SLG47502/03 has a programmable time delay logic cell that can generate a delay that is selectable from one of four timings

configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay patterns, rising

edge detection, falling edge detection, both edge detection, and both edge delay. These four patterns can be further modified

with the addition of delayed edge detection, which adds an extra unit of delay, as well as glitch rejection during the delay period.

See Figure 77 and Figure 78 for further information.

Note: The input signal must be longer than the delay, otherwise it will be filtered out.

registers [1443:1442]

Delay Value Selection

registers [1441:1440]

Edge Mode Selection

To Connection

Matrix Input [40]

Programmable

From Connection Matrix Output [92]

IN

OUT

Delay

Figure 77: Programmable Delay

10.1 PROGRAMMABLE DELAY TIMING DIAGRAM - EDGE DETECTOR OUTPUT

width

IN

time1

Rising Edge Detector

time1

Falling Edge Detector

Edge Detector

Output

Both Edge Detector

Both Edge Delay

time2

time1 is a fixed value

time2 delay value is selected via register

Figure 78: Edge Detector Output

Please refer to Table 11.

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11 Additional Logic Function. Deglitch Filter

The SLG47502/03 has one Deglitch Filter macrocell with inverter function that is connected directly to the Connection Matrix

inputs and outputs. The filter blocks the input signal for pulse width < t_block(at typical temperature 25 °C. See Table 14) and pass

the input signal for pulse width > t_pass(at typical temperature 25 °C). For width in between, the output pulse width will be reduced.

The SLG47502/03 has one Deglitch Filter macrocell with inverter function that is connected directly to the Connection Matrix

inputs and outputs.

In addition, this macrocell can be configured as an Edge Detector, with the following settings:



Rising Edge Detector

Falling Edge Detector

Both Edge Detector

Both Edge Delay

Filter

R

From Connection Matrix

Output [91]

0

1

C

0

1

To Connection Matrix

Input [41]

Edge

Detector

Logic

register [1435]

registers [1434:1433]

register [1432]

Figure 79: Deglitch Filter/Edge Detector Simplified Structure

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12 Voltage Reference

12.1 VOLTAGE REFERENCE OVERVIEW

The SLG47502/03 has a Voltage Reference (Vref) macrocell to provide references to the two analog comparators. This macrocell

can supply a user selection of fixed voltage references, or temperature sensor output. The macrocell also has the option to output

reference voltages on GPIO. See Table 34 for the available selections for each analog comparator.

When changing power-down source settings or power-down register settings in a Voltage Reference block, similar changes of

these settings automatically occur in an Analog Temperature Sensor block.

Also see Figure 80, which shows the reference output structure.

12.2 VREF SELECTION TABLE

Table 34: Vref Selection Table

SEL[5:0]

Vref

0.025

0.05

0.075

0.1

SEL[5:0]

18

Vref

0.475

0.5

0

1

19

2

20

0.525

0.55

3

21

4

0.125

0.15

0.175

0.2

22

0.575

0.6

5

23

6

24

0.625

0.65

7

25

8

0.225

0.25

0.275

0.3

26

0.675

0.7

9

27

10

11

12

13

14

15

16

17

28

0.725

0.75

29

0.325

0.35

0.375

0.4

30

0.775

0.8

31

32

0.825

0.850

Ext. Vref

33

0.425

0.45

34 to 62

63

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12.3 VREF BLOCK DIAGRAM

register [1521]

register [1531]

register [1528]

0

1

From analog

macrocells

0

1

From Connectinon

Matrix Output [95]

Ext Vref0 ref

selection

register [1529]

register [1522]

PwrUp

Ext Vref0 input

111111

0.850

111110

none

Vref_Buf

PwrUp

Bandgap

S0

0.850

0.825

0.850

0.825

Vref_Out

aio_en

100001

100000

S1

S2

S1

S0

6-bit

divider

Vref

S3

0.050

0.025

0.050

0.025

register[1523]

000001

000000

registers [1526:1525]

Temp

registers [1493:1488]

Sensor

Ext Vref1 ref

selection

1

0

Ext Vref1 input

111111

0.850

111110

register [1517]

0.850

100001

0.825

100000

0.050

000001

0.025

000000

registers [1509:1504]

Figure 80: Voltage Reference Block Diagram

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12.4 VREF TYPICAL PERFORMANCE

Note 1 It is not recommended to use Vref connected to external pin without buffer.

250

200

150

100

50

VDD = 1.3 V

VDD = 1.2 V

VDD = 1.1 V

0

1

2

3

4

5

6

7

8

9

10

I, mA

Figure 81: Typical Load Regulation, Vref = 200 mV, T = -40 °C to +85 °C, Buffer - Enable

450

VDD = 1.3 V

400

VDD = 1.2 V

VDD = 1.1 V

350

300

250

200

150

100

50

0

1

2

3

4

5

6

7

8

9

10

I, mA

Figure 82: Typical Load Regulation, Vref = 400 mV, T = -40 °C to +85 °C, Buffer - Enable

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700

600

500

400

300

200

100

0

VDD = 1.3 V

VDD = 1.2 V

VDD = 1.1 V

0

1

2

3

4

5

6

7

8

9

10

I, mA

Figure 83: Typical Load Regulation, Vref = 600 mV, T = -40 °C to +85 °C, Buffer - Enable

900

VDD = 1.3 V

800

VDD = 1.2 V

VDD = 1.1 V

700

600

500

400

300

200

100

0

1

2

3

4

5

6

7

8

9

10

I, mA

Figure 84: Typical Load Regulation, Vref = 850 mV, T = -40 °C to +85 °C, Buffer - Enable

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1.20

1.10

1.00

0.90

0.80

0.70

0.60

0.50

25

75

125

175

225

275

325

375

425

475

525

575

625

675

725

775

825

Vref (mV)

Figure 85: Typical Input Offset Voltage vs. Vref at V_DD= 1.2 V, T = 25 °C

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13 Clocking

13.1 OSC GENERAL DESCRIPTION

The SLG47502/03 has two internal oscillators to support a variety of applications:



Oscillator0 (2.048 kHz)

Oscillator1 (25 MHz).

There are two divider stages for each oscillator that give the user flexibility for introducing clock signals to connection matrix, as

well as various other macrocells. The pre-divider (first stage) for Oscillator0 allows the selection of /1, /2, /4, or /8 to divide down

frequency from the fundamental. The pre-divider (first stage) for Oscillator1 allows the selection of /1, /2, /4, /8, /12, /24, /48, /96

to divide down frequency from the fundamental. The second stage divider of oscillators has an input of frequency from the pre-

divider, and outputs one of eight different frequencies divided by /1, /2, /3, /4, /8, /12, /24, or /64 on Connection Matrix Input lines

[57], [58] and [59]. Please see Figure 86, Figure 87, and Figure 88 for more details on the SLG47502/03 clock scheme.

Oscillator1 (25 MHz) has an additional function of 100 ns delayed startup, which can be enabled/disabled by register [1480]. This

function is recommended to use when analog blocks are used along with the Oscillator.

The Matrix Power-down/Force On function allows switching off or force on the oscillator using an external pin. The Matrix Power-

down/Force On (Connection Matrix Output [96], [97]) signal has the highest priority. The OSC operates according to the following

table:

Table 35: Oscillator Operation Mode Configuration Settings

OSC

Register:

Auto

Signal

From

Connection

Matrix

Enable

Signalfrom Operation

CNT/DLY

Macrocells

OSC

External

Clock

Selection

Power-Down

POR

or Force On Power-On

by Matrix

Input

or

Mode

Force On

0

1

X

1

X

OFF

Internal

OSC is

OFF, logic

X

is ON

1

0

1

0

X

OFF

1

0

1

0

1

X

1

X

ON

X

CNT/DLY

requires

OSC

1

0

X

0

ON

CNT/DLY

does not

require

OSC

1

0

OFF

Note 1 The OSC will run only when any macrocell that uses OSC is powered on.

To avoid metastability issue user can select synchronization type for Power-down signal:



registers [1483:1482], [1487:1486] = 00 – two-DFF synchronization. Oscillator will have from 1 to 2 output pulses after Power-

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down.



registers [1483:1482], [1487:1486] = 01 – one-DFF synchronization by clock falling edge. When Oscillator Power-down signal

comes, Oscillator generates full output pulse and then stops.

registers [1483:1482], [1487:1486] = 10 or 11 – without synchronization (asynchronous reset). When Oscillator Power-down

signal comes, Oscillator output goes low immediately.

If I²C is used to change the synchronization mode there will be a pulse at the Oscillator output when the synchronization mode

is changed from 10 or 11 (asynchronous reset).

13.2 OSCILLATOR0 (2.048 KHZ)

from Connection Matrix

Output [96]

PWR DOWN/Force On

to CNT/DLYs Clock Scheme

Matrix Output control register [1449]

OSC Power Mode

register [1450]

PWR DOWN/

FORCEON

2.048 kHz Pre-divider Clock

registers [1454:1453]

OSC0

(2.048 kHz)

Auto Power On

OUT

0

1

Force Power On

0

1

2

DIV /1 /2 /4/8

Ext. Clock

/2

/3

1

Predivider

OSC0 matrix out0 enable reg [1451]

to Connection Matrix

Ext. CLK Sel register [1448]

/4

3

4

5

6

7

OUT0

Input [57]

/8

to Connection Matrix

Input [58]

OUT1

/12

/24

/64

OSC0 matrix out1 enable reg [1452]

registers [1466:1464]

registers [1470:1468]

Second Stage

Divider

Figure 86: Oscillator0 Block Diagram

Note: It's highly recommended to use OSC0 without the startup delay (register[1484] = 1).

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13.3 OSCILLATOR1 (25 MHZ)

from Connection Matrix

Output [97]

PWR DOWN/Force On

to CNT/DLYs Clock Scheme

25 MHz Pre-divider Clock

Matrix Output control register [1457]

OSC Power Mode

PWR DOWN/

register [1458]

FORCE ON

registers [1462:1460]

OSC1

(25 MHz)

Auto Power On

OUT

0

1

Force Power On

DIV/1 /2 /4/8 /

12 /24 /48 /96

Startup delay

0

1

2

register [1480]

/2

/3

1

Predivider

Ext. Clock

OSC1 matrix out enable reg [1459]

Ext. CLK Sel register [1456]

/4

3

4

5

6

7

to Connection Matrix

/8

Input [59]

/12

/24

/64

registers [1474:1472]

Second Stage

Divider

Figure 87: Oscillator1 Block Diagram

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13.4 CNT/DLY CLOCK SCHEME

Each CNT/DLY within Multi-Function macrocell has its own additional clock divider connected to oscillators pre-divider. Available

dividers are:



OSC0/1, OSC0/8, OSC0/64, OSC0/512, OSC0/4096, OSC0/32768, OSC0/262144

OSC1/1, OSC1/4, OSC1/8, OSC1/64, OSC1/512

registers [3:0]

0

from 25 MHz Pre-divided clock

1

/4

/8

2

3

4

5

6

7

8

/64

/512

CNT/DLY/

ONESHOT/

FREQ_DET/

from 2.048 kHz Pre-divided clock

/8

/64

DLY_EDGE_DET

/512

/4096

/32768

/262144

9

CNT overflow

10

11

12

13

14

15

CNT (x-1) overflow

from Connection Matrix out

(separate for each CNT/DLY macrocell)

reserved

CNT0/CNT1/CNT2/CNT3/

CNT4/CNT5/CNT6/CNT7

Figure 88: Clock Scheme

13.5 EXTERNAL CLOCKING

The SLG47502/03 supports several ways to use an external, higher accuracy clock as a reference source for internal operations.

13.5.1 GPIO Source for Oscillator0 (2.048 kHz)

When register [1448] is set to 1, an external clocking signal on GPIOx will be routed in place of the internal oscillator derived

2.048 kHz clock source. See Figure 86. The low and high limits for external frequency that can be selected are 0 MHz and 10 MHz.

13.5.2 GPIO Source for Oscillator1 (25 MHz)

When register [1456] is set to 1, an external clocking signal on GPIOx will be routed in place of the internal oscillator derived

25 MHz clock source. See Figure 87. The external frequency range is 0 MHz to 20 MHz at V_DD= 1.1 V, 30 MHz at V_DD= 1.2 V,

50 MHz at V_DD= 1.3 V.

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13.6 OSCILLATORS ACCURACY

Note: OSC power setting: Force Power-On; Clock to matrix input - enable; Bandgap: turn on by register - enable.

2.15

2.1

2.05

2

1.95

1.9

Fmax @ VDD = 1.1 V to 1.3 V

1.85

Ftyp @ VDD = 1.2 V

Fmin @ VDD = 1.1 V to 1.3 V

1.8

1.75

T (°C)

Figure 89: Oscillator0 Frequency vs. Temperature, OSC0 = 2.048 kHz

26

25.5

25

24.5

24

Fmax @ VDD = 1.1 V to 1.3 V

Ftyp @ VDD = 1.2 V

23.5

Fmin @ VDD = 1.1 V to 1.3 V

23

T (°C)

Figure 90: Oscillator1 Frequency vs. Temperature, OSC1 = 25 MHz

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Note: For more information see Section 3.9.

12

2.048 kHz Total Error @ VDD = 1.1 V to 1.3 V

25 MHz Total Error @ VDD = 1.1 V to 1.3 V

10

8

6

4

2

0

T (°C)

Figure 91: Oscillators Total Error vs. Temperature

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13.7 OSCILLATORS SETTLING TIME

490

488

486

484

482

480

478

476

474

472

470

0

1

2

3

4

Period

Figure 92: Oscillator0 Settling Time, V_DD= 1.2 V, T = 25 °C, OSC0 = 2.048 kHz

90

80

70

60

50

40

30

20

0

1

2

3

4

5

6

7

8

Period

Figure 93: Oscillator1 Settling Time, V_DD= 1.2 V, T = 25 °C, OSC1 = 25 MHz (Normal Start)

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160

140

120

100

80

60

40

20

0

1

2

3

4

5

6

7

8

Period

Figure 94: Oscillator1 Settling Time, V_DD= 1.2 V, T = 25 °C, OSC1 = 25 MHz (Start with Delay)

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14 Power-On Reset

The SLG47502/03 has a Power-On Reset (POR) macrocell to ensure correct device initialization and operation of all macrocells

in the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the V_DDpower is first

ramping to the device, and also while the V_DDis falling during power-down. To accomplish this goal, the POR drives a defined

sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of

the IOs.

14.1 GENERAL OPERATION

The SLG47502/03 is guaranteed to be powered down and non-operational when the V_DDvoltage (voltage on PIN1) is less than

Power-Off Threshold (see in Table 6), but not less than -0.6 V. Another essential condition for the chip to be powered down is

that no voltage higher (Note) than the V_DDvoltage is applied to any other PIN. For example, if V_DDvoltage is 0.3 V, applying a

voltage higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior.

Note: There is a 0.6 V margin due to forward drop voltage of the ESD protection diodes.

To start the POR sequence in the SLG47502/03, the voltage applied on the V_DDshould be higher than the Power-On Threshold

(Note). The full operational V_DDrange for the SLG47502/03 is 1.1 V to 1.3 V. This means that the V_DDvoltage must ramp up to

the operational voltage value, but the POR sequence will start earlier, as soon as the V_DDvoltage rises to the Power-On Thresh-

old. After the POR sequence has started, the SLG47502/03 will have a typical period of time to go through all the steps in the

sequence (noted in the datasheet for that device) and will be ready and completely operational after the POR sequence is

complete.

Note: The Power-On Threshold is defined in Table 5.

To power down the chip the V_DDvoltage should be lower than the operational and to guarantee that chip is powered down it

should be less than Power-Off Threshold.

All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step

in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin

configuration at this point in time is defined by the design programmed into the chip. Also, as it was mentioned before the voltage

on PINs can’t be bigger than the V_DD, this rule also applies to the case when the chip is powered on.

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14.2 POR SEQUENCE

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 95.

V_DD

t

POR_NVM

(reset for NVM)

NVM_ready_out

POR_GPI

(reset for input enable)

POR_LUT

(reset for LUT/FILTER)

POR_CORE

(reset for DLY/OSC/DFF/

LATCH/ACMP/

Edge Detector in Filter)

POR_OUT

(generate low to high to matrix)

POR_GPO

(reset for output enable)

Figure 95: POR Sequence

As can be seen from Figure 95 after the V_DDhas start ramping up and crosses the Power-On Threshold, first, the on-chip NVM

memory is reset. Next, the chip reads the data from NVM, and transfers this information to a CMOS LATCH, that serves to con-

figure each macrocell, and the Connection Matrix which routes signals between macrocells. The third stage causes the reset of

the input pins, and then to enable them. After that, the LUTs are reset and become active. After LUTs the Delay cells, RC OSC,

DFFs, and LATCHES are initialized. Only after all macrocells are initialized internal POR signal (POR macrocell output) goes

from LOW to HIGH. The last portion of the device to be initialized are the output pins, which transition from high impedance to

active at this point.

The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many

environmental factors, such as: slew rate, V_DDvalue, temperature, and even will vary from chip to chip (process influence).

14.3 MACROCELLS OUTPUT STATES DURING POR SEQUENCE

To have a full picture of SLG47502/03 operation during powering and POR sequence, review the overview the macrocell output

states during the POR sequence (Figure 96 describes the output signals states).

First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output pins which are in high

impedance state). On the next step, some of the macrocells start initialization: input pins output state becomes LOW; LUTs also

output LOW. Only P DLY macrocell configured as edge detector becomes active at this time. After that input pins are enabled.

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Next, only LUTs are configured. Next, all other macrocells are initialized. After macrocells are initialized, internal POR matrix

signal switches from LOW to HIGH. The last are output pins that become active and determined by the input signals.

V_DD

Guaranteed HIGH before POR_GPI

Unpredictable

t

V_DD_out

to matrix

t

Input PIN _out

to matrix

Unpredictable

Determined by External Signal

Determined by Input signals

LUT/FILTER_out

to matrix

Determined by input signals

OUT = IN without Delay

t

Programmable Delay_out

to matrix

Determined by Input signals

Starts to detect input edges

Determined by initial state

DFF/LATCH/ACMP/

Edge Detector in

Filter_out to matrix

Determined by Input signals

Determined by input signals

OUT = IN without Delay

Delay_out

to matrix

Determined by Input signals

Starts to detect input edges

POR_out

to matrix

Unpredictable

Ext. GPO

Tri-state

Determined by input signals

Output State Unpredictable

Figure 96: Internal Macrocell States During POR Sequence

14.3.1 Initialization

All internal macrocells by default have initial low level. Starting from indicated power-up time of 0.811 V to 1.078 V, macrocells in

SLG47502/03 are powered on while forced to the reset state. All outputs are in Hi-Z and chip starts loading data from NVM. Then

the reset signal is released for internal macrocells and they start to initialize according to the following sequence:

1. Input pins, ACMP, Pull-up/down.

2. LUTs.

3. DFFs, Delays/Counters.

4. POR output to matrix.

5. Output pin corresponds to the internal logic.

The Vref output pin driving signal can precede POR output signal going high by 3 µs to 5 µs. The POR signal going high indicates

the mentioned power-up sequence is complete.

Note: The maximum voltage applied to any pin should not be higher than the V_DDlevel. There are ESD Diodes between pin

→V_DDand pin → GND on each pin. So, if the input signal applied to pin is higher than V_DD, then current will sink through the

diode to V_DD. Exceeding V_DDresults in leakage current on the input pin, and V_DDwill be pulled up, following the voltage on the

input pin.There is no effect from input pin when input voltage is applied at the same time as V_DD

.

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14.3.2 Power-Down

V_DD(V)

2 V

1 V

0.735 V

0.393 V

Time

Not guaranteed output state

Figure 97: Power-Down

During Power-down, macrocells in SLG47502/03 are powered off after V_DDfalling down below Power-Off Threshold. Please note

that during a slow rampdown, outputs can possibly switch state during this time.

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2

15 I C Serial Communications Macrocell

15.1 I²C SERIAL COMMUNICATIONS MACROCELL OVERVIEW

In the standard use case for the GreenPAK devices, the configuration choices made by the user are stored as bit settings in the

Non-Volatile Memory (NVM), and this information is transferred at startup time to volatile RAM registers that enable the configu-

ration of the macrocells. Other RAM registers in the device are responsible for setting the connections in the Connection Matrix

to route signals in the manner most appropriate for the user’s application.

The I²C Serial Communications Macrocell in this device allows an I²C bus Master to read and write this information via a serial

channel directly to the RAM registers, allowing the remote re-configuration of macrocells, and remote changes to signal chains

within the device.

The I²C bus Master is also able to read and write other register bits that are not associated with NVM memory.

The user has the flexibility to control read access and write access via registers bits registers [1723:1720]. See Section 15.5 for

more details on I²C read/write memory protection.

It is possible to use I²C in Standard/fast mode or Fast mode+. To use I²C in Fast mode+ registers [1312], [1328] should be enabled.

Note that extra current consumption can occur if I²C transaction was corrupted and Stop condition was not received. Next correct

I²C transaction restores normal current consumption.

15.2 I²C SERIAL COMMUNICATIONS DEVICE ADDRESSING

Each command to the I²C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are

shown in Figure 98. After the Start bit, the first four bits are a control code. Each bit in a control code can be sourced independently

from the register or by value defined externally by GPI, GPIO3, GPIO4, and GPIO8. The LSB of the control code is defined by

the value of GPI, while the MSB is defined by the value of GPIO8. The address source (either register bit or PIN) for each bit in

the control code is defined by registers [30:24]. This gives the user flexibility on the chip level addressing of this device and other

devices on the same I²C bus. The Block Address is the next three bits (A10, A9, A8), which will define the most significant bits

in the addressing of the data to be read or written by the command. The last bit in the Control Byte is the R/W bit, which selects

whether a read command or write command is requested, with a “1” selecting for a Read command, and a “0” selecting for a Write

command. This Control Byte will be followed by an Acknowledge bit (ACK), which is sent by this device to indicate successful

communication of the Control Byte data.

In the I²C -bus specification and user manual, there are two groups of eight addresses (0000 xxx and 1111 xxx) that are reserved

for the special functions, such as a system General Call address. If the user of this device choses to set the Control Code to either

“1111” or “0000” in a system with other slave device, please consult the I²C-bus specification and user manual to understand the

addressing and implementation of these special functions, to ensure reliable operation.

In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of

information, resulting in a total address space of 2K bytes. Of this 2K byte address space, the valid addresses accessible to the

I²C Macrocell on the SLG47502/03 are in the range from 0 (0x00) to 255 (0xFF). The MSB address bits (A10, A9, and A8) will

be “0” for all commands to the SLG47502/03.

With the exception of the Current Address Read command, all commands will have the Control Byte followed by the Word

Address. Figure 98 shows this basic command structure.

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Start

bit

Acknowledge

bit

Control Byte

Word Address

A

10

A

9

A

8

A

7

A

0

S

X

R/W ACK

Control

Code

Block

Address

Not used, set to

0

Read/Write bit

(1 = Read, 0 = Write)

Figure 98: Basic Command Structure

15.3 I²C SERIAL GENERAL TIMING

General timing characteristics for the I²C Serial Communications macrocell are shown in Figure 99. Timing specifications can be

found in the AC Characteristics section.

t_HIGH

t_F

t_R

t_LOW

SCL

t_{SU_STA}

t_{HD_DAT}

t_{HD_STA}

t_{SU_DAT}

t_{SU_STO}

SDA IN

t_BUF

t_{VD_ACK}

t_{VD_DAT}

SDA OUT

Figure 99: I²C General Timing Characteristics

15.4 I²C SERIAL COMMUNICATIONS COMMANDS

15.4.1 Byte Write Command

Following the Start condition from the Master, the Control Code [4 bits], the Block Address [3 bits], and the R/W bit (set to “0”),

are placed onto the I²C bus by the Master. After the SLG47502/03 sends an Acknowledge bit (ACK), the next byte transmitted

by the Master is the Word Address. The Block Address (A10, A9, A8), combined with the Word Address (A7 through A0), together

set the internal address pointer in the SLG47502/03, where the data byte is to be written. After the SLG47502/03 sends another

Acknowledge bit, the Master will transmit the data byte to be written into the addressed memory location. The SLG47502/03 again

provides an Acknowledge bit and then the Master generates a Stop condition. The internal write cycle for the data will take place

at the time that the SLG47502/03 generates the Acknowledge bit.

It is possible to latch all IOs during I²C write command, register [1425] = 1 - Enable. It means that IOs will remain their state until

the write command is done.

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Acknowledge

bit

Acknowledge

Start

bit

Acknowledge

Bus Activity

bit

Control Byte

bit

Word Address

Data

A

10

A

9

A

8

A

7

A

0

D

7

D

0

S

X

W

ACK

SDA LINE

P

Control

Code

Block

Address

Stop

bit

Not used, set to

0

R/W bit = 0

Figure 100: Byte Write Command, R/W = 0

15.4.2 Sequential Write Command

The write Control Byte, Word Address and the first data byte are transmitted to the SLG47502/03 in the same way as in a Byte

Write command. However, instead of generating a Stop condition, the Bus Master continues to transmit data bytes to the

SLG47502/03. Each subsequent data byte will increment the internal address counter, and will be written into the next higher

byte in the command addressing. As in the case of the Byte Write command, the internal write cycle will take place at the time

that the SLG47502/03 generates the Acknowledge bit.

Acknowledge

bit

Start

bit

Bus Activity

Data (n + 1)

Data (n + x)

Control Byte

Word Address (n)

Data (n)

A

10

A

9

A

8

ACK

P

SDA LINE

S

X

W

ACK

Control

Code

Block

Address

Stop

bit

Not used, set

to 0

Write bit

Figure 101: Sequential Write Command

15.4.3 Current Address Read Command

The Current Address Read Command reads from the current pointer address location. The address pointer is incremented at the

first STOP bit following any write control byte. For example, if a Sequential Read command (which contains a write control byte)

reads data up to address n, the address pointer would get incremented to n + 1 upon the STOP of that command. Subsequently,

a Current Address Read that follows would start reading data at n + 1. The Current Address Read Command contains the Control

Byte sent by the Master, with the R/W bit = “1”. The SLG47502/03 will issue an Acknowledge bit, and then transmit eight data

bits for the requested byte. The Master will not issue an Acknowledge bit, and follow immediately with a Stop condition.

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Start

bit

Acknowledge

bit

Stop

bit

Bus Activity

Control Byte

Data (n)

A

10

A

9

A

8

S

X

R

ACK

SDA LINE

P

Control

Code

Block

Address

No ACK

bit

Not used, set to 0

R/W bit = 1

Figure 102: Current Address Read Command, R/W = 1

15.4.4 Random Read Command

The Random Read command starts with a Control Byte (with R/W bit set to “0”, indicating a write command) and Word Address

to set the internal byte address, followed by a Start bit, and then the Control Byte for the read (exactly the same as the Byte Write

command). The Start bit in the middle of the command will halt the decoding of a Write command, but will set the internal address

counter in preparation for the second half of the command. After the Start bit, the Bus Master issues a second control byte with

the R/W bit set to “1”, after which the SLG47502/03 issues an Acknowledge bit, followed by the requested eight data bits.

Acknowledge

Stop

bit

Start

bit

Bus Activity

SDA LINE

Not used, s

Data (n)

Control Byte

Word Address (n)

Control Byte

A

9

A

8

A

9

A

8

R

ACK

P

S

ACK

X

W

ACK

S

X

10

Control

Code

Block

Address

Control

Code

Block

Address

No ACK

bit

et to 0

Write bit

Read bit

Figure 103: Random Read Command

15.4.5 Sequential Read Command

The Sequential Read command is initiated in the same way as a Random Read command, except that once the SLG47502/03

transmits the first data byte, the Bus Master issues an Acknowledge bit as opposed to a Stop condition in a random read. The

Bus Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition.

Acknowledge

Start

bit

Bus Activity

Data (n + 2)

Data (n + x)

Control Byte

Data (n)

Data (n + 1)

A

10

A

9

A

8

ACK

P

SDA LINE

S

X

R

ACK

Control

Code

Block

Address

Stop

bit

No ACK

bit

Read bit

Figure 104: Sequential Read Command

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15.4.6 I²C Serial Reset Command

If I²C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including

configuration of all macrocells, and all connections provided by the Connection Matrix. This is implemented by setting

register [17:16] I²C reset bit to “1”, which causes the device to re-enable the Power-On Reset (POR) sequence, including the

reload of all register data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has

taken place, the contents of register [17:16] will be set to “0” automatically. Figure 105 illustrates the sequence of events for this

reset function.

Acknowledge

bit

Acknowledge

bit

Start

bit

Acknowledge

bit

Bus Activity

Control Byte

Word Address

Data

A

10

A

9

A

8

A

7

A

0

D

7

D

0

S

X

W

ACK

SDA LINE

P

Internal Reset bit

Control

Code

Block

Address

Stop

bit

Not used, set to 0

Write bit

by I2C Stop Signal

Reset-bit register output

DFF output gated by stop signal

Internal POR for core only

Figure 105: Reset Command Timing

15.4.7 I²C Additional Options

When Output latching during I²C write, register [1425] = 1 allows all PINs output value to be latched until I²C write is done. It will

protect the output change due to configuration process during I²C write in case multiple register bytes are changed. Inputs and

internal macrocells retain their status during I²C write.

If the user sets GPIO0 and GPIO1 function to a selection other than SDA and SCL, all access via I²C will be disabled.

Note: Any write commands that come to the device via I²C that are not blocked, based on the protection bits, will change the

contents of the RAM register bits that mirror the NVM bits. These write commands will not change the NVM bits themselves, and

a POR event will restore the register bits to original programmed contents of the NVM.

See Section 17 for detailed information on all registers.

15.4.8 Reading Counter Data via I²C

The current count value in all counters in the device can be read via I²C.

15.4.9 I²C Byte Write Bit Masking

The I²C macrocell inside SLG47502/03 supports masking of individual bits within a byte that is written to the RAM memory space.

This function is supported across the entire RAM memory space. To implement this function, the user performs a Byte Write

Command (see Section 15.4.1 for details) on the I²C Byte Write Mask Register (address 0F6H) with the desired bit mask pattern.

This sets a bit mask pattern for the target memory location that will take effect on the next Byte Write Command to this register

byte. Any bit in the mask that is set to “1” in the I²C Byte Write Mask Register will mask the effect of changing that particular bit

in the target register, during the next Byte Write Command. The contents of the I²C Byte Write Mask Register are reset (set to

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00h) after valid Byte Write Command. If the next command received by the device is not a Byte Write Command, the effect of the

bit masking function will be aborted, and the I²C Byte Write Mask Register will be reset with no effect. Figure 106 shows an

example of this function.

User Actions



Byte Write Command, Address = F6h, Data = 11110000b [sets mask bits]

Byte Write Command, Address = 74h, Data = 10101010b [writes data with mask]

Memory Address 74h (original contents)

Mask to choose bit from new

write command

1

0

1

0

Mask to choose bit from

original register contents

Memory Address 74h (new data in write command)

0 1

1

0

1

0

Bit from new write command

Memory Address F6h (mask register)

1

0

Bit from original register

contents

Memory Address 74h (new contents after write command)

1

0

1

0

1

0

Figure 106: Example of I²C Byte Write Bit Masking

15.4.10 Writing a New Value to the Shift Register via I²C

The new value can be written to the Shift Register if low logic level presents at the CLK input of the macrocell. Otherwise, if the

logic level at CLK input is high, the new value will be ignored.

It’s recommended to perform the following actions to write the new value to the Shift Register:



Read Shift Register value (Old_Value);

Write new Shift Register value;

Read Shift Register value (New_Value) and compare it with the result of the last read (Old_Value). If New_Value isn’t equal to

the Old_Value, the writing procedure was successful. Otherwise, if New_Value is equal to the Old_Value, the content of the

Shift Register hasn’t been updated (the logic level at the CLK input is high). I²C master should perform the following steps:



Connect the CLK input of the Shift Register to the GND (connect the corresponding matrix output to the matrix input x00);

Analyze the LSB, if the new value to be written to the Shift Register, for example xxxx xxx(y). y is the LSB of the 8-bit value

to be written to the Shift Register.



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If (y) is 0, then connect D input of the Shift Register to GND (connect the corresponding matrix output to the matrix input x00);

If (y) is 1, then connect D input of the Shift Register to V_DD(connect the corresponding matrix output to the matrix input x3F);



Shift the new value to one bit right and write it to the Shift Register, for example if the data to be written to the Shift Register

is x5A (1010 0101), then the I²C master should write x52 (01010010) to the Shift Register.

Connect CLK input of the Shift Register to its original source (change the matrix output setting from x00 to original source

code). This will clock the Shift Register to one bit left.

Connect D input of the Shift Register to its original source (change the matrix output setting from V_DD(x3F) or GND (x00)

to the original source code).

15.5 I²C SERIAL COMMAND REGISTER MAP

There are seven read/write protect modes for the design sequence from being corrupted or copied. See Table 36 for details.

Table 36: Read/Write Protection Options

Protection Modes Configuration

Partly

Lock

Partly

Lock Read&

Configurations

Data

Output ter Ad-

From

Regis-

Partly

Lock

Read

Partly

Lock

Write

Lock Read& Partly

Lock

Read/

Write

Unlock

Read/

Write

Lock

Write

Lock

Write

Lock

Read

Lock

Write

dress

RPR[1:0]

WPR[1:0]

00

01

00

01

10

01

10

00

10

I²C Write Mask

ControlRegister

(section 15.4.9)

I²C Virtual Input

Control Register

(section 6.3)

I²C Reset

Control Register

(section 15.4.6)

R/W

W

R/W

R

R/W

R

R/W

R

R/W

R

R/W

W

R/W

R

R/W

R

Memory

00

01

02

Macro-

cell

Memory

I²C

Configuration

Register

Memory 03~04

Memory 05~4E

Matrix Output

Configuration

(section 6.2)

R

-

R

-

Combination

Function

Macrocell

R/W

W

R

-

W

R

-

Memory 4F~6C

Configuration

Multi-Function

Macrocell

Configuration

R/W

W

R

-

W

R

-

Memory 6D~A1

Memory A2~B2

Memory B3~C0

IO Configuration

OSC, ACMP,

Vref

Configuration

R/W

W

R

Allow Read and Write Data

Allow Write Data Only

Allow Read Data Only

-

The Data is protected for Read and Write

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It is possible to read some data from macrocells, such as counter current value, connection matrix, and connection matrix virtual

inputs. The I²C write will not have any impact on data in case data comes from macrocell output, except Connection Matrix Virtual

Inputs. The silicon identification service bits allows identifying silicon family, its revision, and others.

See Section 17 for detailed information on all registers.

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16 Analog Temperature Sensor

The SLG47502/03 has an Analog Temperature Sensor (TS) with an output voltage linearly-proportional to the Centigrade tem-

perature. The TS cell shares buffer with Vref 0, so it is impossible to use both cells simultaneously, its output can be connected

directly to the GPIO or to the ACPM1_H positive input. Using buffer causes low-output impedance, linear output and makes

interfacing to readout or control circuitry especially easy. The TS is rated to operate over a -40 °C to 85 °C temperature range.

The error in the whole temperature range does not exceed ±2.5 %. TS output voltage variation over V_DDat constant temperature

is less than ±1.5 %. When changing power-down source settings or enable temperature sensor settings in the Analog Tempera-

ture Sensor block, similar changes of these settings automatically occur in the Voltage Reference block. For more details refer to

section 4.

The equation below calculates the typical analog voltage passed from the TS to the ACMPs' IN+ source input. It is important to

note that there will be a chip to chip variation of about ±2 °C.

V_TS= -1.95 x T + 734

where:

_TS(mV) - TS Output Voltage

V

T (°C) - Temperature

Temperature hysteresis can be setup by enabling the GreenPAK's internal ACMP hysteresis.

From Connectinon

Matrix Output [95]

TS

V

DD

TS Power Up

Buf_sel[1526:1525]

GPIO

register [1528] = 1

OUT

11

10

01

00

ACMP1H Vref

ACMP0H Vref

Reserved

Figure 107: Analog Temperature Sensor Structure Diagram

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17 Register Definitions

17.1 REGISTER MAP

Table 37: Register Map

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

Matrix Output

0

1

2

3

4

Host write data bit-mask:

0: write

1: mask (don't change)

0

I²C Write Mask Control

(This mask does not effect on NVM write and masks register

update)

5

6

7

8

9

10

11

Host Virtual Input Bit 0

Host Virtual Input Bit 1

Host Virtual Input Bit 2

Host Virtual Input Bit 3

Host Virtual Input Bit 4

Host Virtual Input Bit 5

Host Virtual Input Bit 6

Host Virtual Input Bit 7

1

I²C Virtual Input Control

12

13

14

15

0: Normal

1: Reset

16

(Self-Clear Bit. Shuts down device (simulates a Chip POR))

Reserved

17

I²C Reset Control

18

2

Reserved

19

20

21

22

23

24

25

26

27

Bit[6:3] can be optional selected to GPIOx with

I2C_CONTROL_CODE_BITx_SEL configuration

I²C Interfaces Base Address

I²C Mode Enable

3

28

29

30

0: I2C mode disable

1: I2C mode enable

31

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Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: Used I2C_CONTROL_CODE Value

1: Use SLA_0 Value

0: Used I2C_CONTROL_CODE Value

1: Use SLA_0 Value

0: Used I2C_CONTROL_CODE Value

1: Use SLA_0 Value

0: Used I2C_CONTROL_CODE Value

1: Use SLA_0 Value

32

33

34

35

I²C CONTROL CODE BIT3 SEL

I²C CONTROL CODE BIT4 SEL

I²C CONTROL CODE BIT5 SEL

I²C CONTROL CODE BIT6 SEL

4

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

Reserved

OUT0:

IN0 of LUT2_0 or Clock Input of DFF0 or Clock Input of

Shift_Reg0

5

LUT2_0 & DFF0

OUT1:

IN1 of LUT2_0 or Data Input of DFF0 or Data Input of

Shift_Reg0

6

OUT2:

IN0 of LUT2_1 or Clock Input of DFF1 or Clock Input of

Shift_Reg1

LUT2_1 & DFF1

7

8

OUT3:

IN1 of LUT2_1 or Data Input of DFF1 or Data Input of

Shift_Reg1

OUT4:

LUT2_2 & DFF2

IN0 of LUT2_2 or Clock Input of DFF2 or Clock Input of

Shift_Reg2

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Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

70

Byte

8

71

72

73

74

OUT5:

LUT2_2 & DFF2

IN1 of LUT2_2 or Data Input of DFF2 or Data Input of

Shift_Reg2

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

9

A

B

C

D

OUT6:

IN0 of LUT2_3 or Clock Input of PGen0

LUT2_3 & PGen

OUT7:

IN1 of LUT2_3 or nRST of PGen0

OUT8:

IN0 of LUT3_0 or Clock Input of DFF3 or Clock Input of

Shift_Reg3

OUT9:

LUT3_0 & DFF3

IN1 of LUT3_0 or Data Input of DFF3 or Data Input of

Shift_Reg3

99

100

101

102

103

104

105

106

107

108

109

110

111

OUT10:

IN2 of LUT3_0 or nRST(nSET) of DFF3 or nRST (nSET) of

Shift_Reg3

OUT11:

LUT3_1 & DFF4

IN0 of LUT3_1 or Clock Input of DFF4 or Clock Input of

Shift_Reg4

Datasheet

16-Jul-2021

Revision 2.0

123 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

OUT12:

IN1 of LUT3_1 or Data Input of DFF4 or Data Input of

Shift_Reg4

E

LUT3_1 & DFF4

OUT13:

IN2 of LUT3_1 or nRST (nSET) of DFF4 or nRST(nSET) of

Shift_Reg4

F

OUT14:

IN0 of LUT3_2 or Clock Input of DFF5 or Clock Input of

Shift_Reg5

10

11

12

13

OUT15:

LUT3_2 & DFF5

IN1 of LUT3_2 or Data Input of DFF5 or Data Input of

Shift_Reg5

OUT16:

IN2 of LUT3_2 or nRST(nSET) of DFF5 or nRST(nSET) of

Shift_Reg5

OUT17:

IN0 of LUT3_3 or Clock Input of DFF6 or Clock Input of

Shift_Reg6

OUT18:

LUT3_3 & DFF6

IN1 of LUT3_3 or Data Input of DFF6 or Data Input of

Shift_Reg6

OUT19:

IN2 of LUT3_3 or nRST(nSET) of DFF6 or nRST(nSET) of

Shift_Reg6

Datasheet

16-Jul-2021

Revision 2.0

124 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

OUT20:

IN0 of LUT3_4 or Clock Input of DFF7 or Clock Input of

Shift_Reg7

14

OUT21:

LUT3_4 & DFF7

IN1 of LUT3_4 or Data Input of DFF7 or Data Input of

Shift_Reg7

15

16

17

18

19

OUT22:

IN2 of LUT3_4 or nRST(nSET) of DFF7 or nRST(nSET) of

Shift_Reg7

OUT23:

IN0 of LUT3_5 or Clock Input of DFF8 or Clock Input of

Shift_Reg8

OUT24:

LUT3_5 & DFF8

IN1 of LUT3_5 or Data Input of DFF8 or Data Input of

Shift_Reg8

OUT25:

IN2 of LUT3_5 or nRST(nSET) of DFF8 or nRST(nSET) of

Shift_Reg8

OUT26:

IN0 of LUT3_6 or Clock Input of DFF9 or Clock Input of

Shift_Reg9

LUT3_6 & DFF9

OUT27:

IN1 of LUT3_6 or Data Input of DFF9 or Data Input of

Shift_Reg9

Datasheet

16-Jul-2021

Revision 2.0

125 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

OUT28:

LUT3_6 & DFF9

IN2 of LUT3_6 or nRST(nSET) of DFF9 or nRST(nSET) of

Shift_Reg9

1A

OUT29:

IN0 of LUT3_7 or Clock Input of DFF10 or Clock Input of

Shift_Reg10

1B

1C

1D

OUT30:

LUT3_7 & DFF10

IN1 of LUT3_7 or Data Input of DFF10 or Data Input of

Shift_Reg10

OUT31:

IN2 of LUT3_7 or nRST(nSET) of DFF10 or nRST(nSET) of

Shift_Reg10

OUT32:

IN0 of LUT3_8 or Clock Input of DFF11 or Clock Input of

Shift_Reg11

OUT33:

LUT3_8 & DFF11

IN1 of LUT3_8 or Data Input of DFF11 or Data Input of

Shift_Reg11

1E

1F

OUT34:

IN2 of LUT3_8 or nRST(nSET) of DFF11 or nRST(nSET) of

Shift_Reg11

Datasheet

16-Jul-2021

Revision 2.0

126 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

OUT35:

1F

IN0 of LUT3_9 or Clock Input of DFF12 or Clock Input of

Shift_Reg12

OUT36:

LUT3_9 & DFF12

IN1 of LUT3_9 or Data Input of DFF12 or Data Input of

Shift_Reg12

20

21

22

OUT37:

IN2 of LUT3_9 or nRST(nSET) of DFF12 or nRST(nSET) of

Shift_Reg12

OUT38:

IN0 of LUT4_0 or Clock Input of DFF13 or Clock Input of

Shift_Reg13

OUT39:

IN1 of LUT4_0 or Data Input of DFF13 or Data Input of

Shift_Reg13

LUT4_0 & DFF13

OUT40:

IN2 of LUT4_0 or nRST(nSET) of DFF13 or nRST(nSET) of

Shift_Reg13

23

24

OUT41:

IN3 of LUT4_0 or Clock Enable of DFF13 or Clock Enable of

Shift_Reg13

Datasheet

16-Jul-2021

Revision 2.0

127 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

24

OUT42:

IN0 of MLT0_LUT4_1 or Clock Input of DFF14 or Delay0 Input

(or Counter0 nRST Input)

25

26

27

28

OUT43:

IN1 of MLT0_LUT4_1 or nRST of DFF14 or Delay0 Input (or

Counter0 nRST Input or External Clock Source)

Multi-function0

OUT44:

IN2 of IN2 of MLT0_LUT4_1 or nSET of DFF14 or KEEP of

Delay0/Counter0

OUT45:

IN3 of MLT0_LUT4_1 or Data Input of DFF14 or UPof Delay0/

Counter0

OUT46:

IN0 of MLT1_LUT3_10 or Clock Input of DFF15 or Delay1

Input (or Counter1 nRST Input)

Multi-function1

OUT47:

IN1 of MLT1_LUT3_10 or nRST(nSET) of DFF15 or Delay1

Input (or Counter1 nRST Input or External Clock Source)

Datasheet

16-Jul-2021

Revision 2.0

128 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

OUT48:

Multi-function1

IN2ofMLT1_LUT3_10orDataInputofDFF15orDelay1Input

(or Counter1 nRST Input)

29

OUT49:

IN0 of MLT2_LUT3_11 or Clock Input of DFF16 or Delay2

Input (or Counter2 nRST Input)

2A

2B

2C

2D

2E

OUT50:

Multi-function2

IN1 of MLT2_LUT3_11 or nRST(nSET) of DFF16 or Delay2

Input (or Counter2 nRST Input or External Clock Source

OUT51:

IN2ofMLT2_LUT3_11or DataInputofDFF16orDelay2 Input

(or Counter2 nRST Input)

OUT52:

IN0 of MLT3_LUT3_12 or Clock Input of DFF17 or Delay3

Input (or Counter3 nRST Input)

OUT53:

Multi-function3

IN1 of MLT3_LUT3_12 or nRST(nSET) of DFF17 or Delay3

Input (or Counter3 nRST Input or External Clock Source)

OUT54:

IN2ofMLT3_LUT3_12orDataInputofDFF17orDelay3Input

(or Counter3 nRST Input)

OUT55:

Multi-function4

IN0 of MLT4_LUT3_13 or Clock Input of DFF18 or Delay4

Input (or Counter4 nRST Input)

Datasheet

16-Jul-2021

Revision 2.0

129 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

OUT56:

IN1 of MLT4_LUT3_13 or nRST(nSET) of DFF18 or Delay4

Input (or Counter4 nRST Input or External Clock Source

2F

Multi-function4

OUT57:

IN2ofMLT4_LUT3_13orDataInputofDFF18orDelay4Input

(or Counter4 nRST Input)

30

31

32

33

34

OUT58:

IN0 of MLT5_LUT3_14 or Clock Input of DFF19 or Delay5

Input (or Counter5 nRST Input)

OUT59:

Multi-function5

IN1 of MLT5_LUT3_14 or nRST(nSET) of DFF19 or Delay5

Input (or Counter5 nRST Input or External Clock Source)

OUT60:

IN2ofMLT5_LUT3_14orDataInputofDFF19orDelay5Input

(or Counter5 nRST Input)

OUT61:

IN0 of MLT6_LUT3_15 or Clock Input of DFF20 or Delay6

Input (or Counter6 nRST Input)

OUT62:

Multi-function6

IN1 of MLT6_LUT3_15 or nRST(nSET) of DFF20 or Delay6

Input (or Counter6 nRST Input or External Clock Source)

OUT63:

IN2ofMLT6_LUT3_15orDataInputofDFF20orDelay6Input

(or Counter6 nRST Input)

Datasheet

16-Jul-2021

Revision 2.0

130 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

452

453

454

455

456

457

458

459

460

461

462

463

464

465

466

467

468

469

470

471

OUT64:

IN0 of MLT7_LUT3_16 or Clock Input of DFF21 or Delay7

Input (or Counter7 nRST Input)

35

OUT65:

Multi-function7

IN1 of MLT7_LUT3_16 or nRST(nSET) of DFF21 or Delay7

Input (or Counter7 nRST Input or External Clock Source)

36

37

38

39

3A

OUT66:

IN2ofMLT7_LUT3_16orDataInputofDFF21orDelay7Input

(or Counter7 nRST Input)

OUT67:

GPIO0 Digital Output

GPIO0

GPIO1

OUT68:

GPIO1 Digital Output

OUT69:

GPIO2 Digital Output OE

GPIO2

OUT70:

GPIO2 Digital Output

OUT71:

GPIO3 Digital Output OE

GPIO3

Datasheet

16-Jul-2021

Revision 2.0

131 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

472

473

474

475

476

477

478

479

480

481

482

483

484

485

486

487

488

489

490

491

492

493

494

495

496

497

498

499

500

501

502

503

504

505

506

507

508

509

510

511

512

513

514

515

516

517

518

519

OUT72:

GPIO3 Digital Output

GPIO3

3B

OUT73:

GPIO4 Digital Output OE

3C

3D

3E

3F

40

GPIO4

OUT74:

GPIO4 Digital Output

OUT75:

GPIO5 Digital Output OE

GPIO5

OUT76:

GPIO5 Digital Output

OUT77:

GPIO6 Digital Output OE

GPIO6

OUT78:

GPIO6 Digital Output

OUT79:

GPIO7 Digital Output OE

GPIO7

Datasheet

16-Jul-2021

Revision 2.0

132 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

520

521

522

523

524

525

526

527

528

529

530

531

532

533

534

535

536

537

538

539

540

541

542

543

544

545

546

547

548

549

550

551

552

553

554

555

556

557

558

559

560

561

562

563

564

565

566

567

OUT80:

GPIO7 Digital Output

GPIO7

41

OUT81:

GPIO8 Digital Output OE

42

43

44

45

46

GPIO8

OUT82:

GPIO8 Digital Output

OUT83:

GPIO9 Digital Output OE (16-PIN Version)

GPIO9

OUT84:

GPIO9 Digital Output (16-PIN Version)

OUT85:

GPIO10 Digital Output OE (16-PIN Version)

GPIO10

OUT86:

GPIO10 Digital Output (16-PIN Version)

OUT87:

GPIO11

GPIO11 Digital Output OE (16-PIN Version)

Datasheet

16-Jul-2021

Revision 2.0

133 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

568

569

570

571

572

573

574

575

576

577

578

579

580

581

582

583

584

585

586

587

588

589

590

591

592

593

594

595

596

597

598

599

600

601

602

603

604

605

606

607

608

609

610

611

612

613

614

615

OUT88:

GPIO11

GPIO11 Digital Output (16-PIN Version)

47

OUT89:

GPIO12 Digital Output OE (16-PIN Version)

48

49

4A

4B

4C

GPIO12

OUT90:

GPIO12 Digital Output (16-PIN Version)

OUT91:

Filter/Edge detect input

Filter/Edge detect

Programmable delay/edge detect

ACMP0H

OUT92:

Programmable delay/edge detect input

OUT93:

Power Up of ACMP0_H

OUT94:

Power Up of ACMP1_H

ACMP1H

OUT95:

Temp sensor

Temp sensor, Vref Out_0 Power Up

Datasheet

16-Jul-2021

Revision 2.0

134 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

616

617

618

619

620

621

622

623

624

625

626

627

628

629

630

631

632

633

634

635

636

637

638

639

640

641

642

643

644

645

646

647

648

649

650

651

652

653

654

655

656

657

658

659

660

661

662

663

OUT96:

OSC0

Oscillator0 (LFOSC) ENABLE

4D

OUT97:

OSC1

Oscillator1 (RINGOSC) ENABLE

4E

4F

50

51

52

Reserved

LUT2_0 bit[0]/Shift_Reg0 bit[0]

LUT2_0 bit[1]/Shift_Reg0 bit[1]

LUT2_0 bit[2]/Shift_Reg0 bit[2]

LUT2_0 bit[3]/DFF0 /Shift_Reg0 bit[3]

LUT2_1 bit[0]/Shift_Reg1 bit[0]

LUT2_1 bit[1]/Shift_Reg1 bit[1]

LUT2_1 bit[2]/Shift_Reg1 bit[2]

LUT2_1 bit[3]/DFF1 /Shift_Reg1 bit[3]

LUT2_2 bit[0]/Shift_Reg2 bit[0]

LUT2_2 bit[1]/Shift_Reg2 bit[1]

LUT2_2 bit[2]/Shift_Reg2 bit[2]

LUT2_2 bit[3]/DFF2 /Shift_Reg2 bit[3]

LUT2_3 bit[0]/PGEN0 Size bit [0]

LUT2_3 bit[1]/PGEN0 Size bit [1]

LUT2_3 bit[2]/PGEN0 Size bit [2]

LUT2_3 bit[3]/PGEN0 Size bit [3]

LUT3_0 bit[0]/Shift_Reg3 bit[0]

LUT3_0 bit[1]/Shift_Reg3 bit[1]

LUT3_0 bit[2]/Shift_Reg3 bit[2]

LUT3_0 bit[3]/Shift_Reg3 bit[3]

LUT3_0 bit[4]/Shift_Reg3 bit[4]

LUT3_0 bit[5]/Shift_Reg3 bit[5]

LUT3_0 bit[6]/Shift_Reg3 bit[6]

LUT3_0 bit[7]/DFF3/Shift_Reg3 bit[7]

LUT3_1 bit[0]/Shift_Reg4 bit[0]

LUT3_1 bit[1]/Shift_Reg4 bit[1]

LUT3_1 bit[2]/Shift_Reg4 bit[2]

LUT3_1 bit[3]/Shift_Reg4 bit[3]

LUT3_1 bit[4]/Shift_Reg4 bit[4]

LUT3_1 bit[5]/Shift_Reg4 bit[5]

LUT3_1 bit[6]/Shift_Reg4 bit[6]

LUT3_1 bit[7]/DFF4/Shift_Reg4 bit[7]

LUT2_0_DFF0_SHR0

LUT2_1_DFF1_SHR1

LUT2_2_ DFF2_SHR2

LUT2_3_PGEN0

LUT3_0_DFF3_SHR3

LUT3_1_DFF4_SHR4

Datasheet

16-Jul-2021

Revision 2.0

135 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

664

665

666

667

668

669

670

671

672

673

674

675

676

677

678

679

680

681

682

683

684

685

686

687

688

689

690

691

692

693

694

695

696

697

698

699

700

701

702

703

704

705

706

707

708

709

710

711

LUT3_2 bit[0]/Shift_Reg5 bit[0]

LUT3_2 bit[1]/Shift_Reg5 bit[1]

LUT3_2 bit[2]/Shift_Reg5 bit[2]

LUT3_2 bit[3]/Shift_Reg5 bit[3]

LUT3_2 bit[4]/Shift_Reg5 bit[4]

LUT3_2 bit[5]/Shift_Reg5 bit[5]

LUT3_2 bit[6]/Shift_Reg5 bit[6]

LUT3_2 bit[7]/DFF5/Shift_Reg5 bit[7]

LUT3_3 bit[0]/Shift_Reg6 bit[0]

LUT3_3 bit[1]/Shift_Reg6 bit[1]

LUT3_3 bit[2]/Shift_Reg6 bit[2]

LUT3_3 bit[3]/Shift_Reg6 bit[3]

LUT3_3 bit[4]/Shift_Reg6 bit[4]

LUT3_3 bit[5]/Shift_Reg6 bit[5]

LUT3_3 bit[6]/Shift_Reg6 bit[6]

LUT3_3 bit[7]/DFF6/Shift_Reg6 bit[7]

LUT3_4 bit[0]/Shift_Reg7 bit[0]

LUT3_4 bit[1]/Shift_Reg7 bit[1]

LUT3_4 bit[2]/Shift_Reg7 bit[2]

LUT3_4 bit[3]/Shift_Reg7 bit[3]

LUT3_4 bit[4]/Shift_Reg7 bit[4]

LUT3_4 bit[5]/Shift_Reg7 bit[5]

LUT3_4 bit[6]/Shift_Reg7 bit[6]

LUT3_4 bit[7]/DFF7/Shift_Reg7 bit[7]

LUT3_5 bit[0]/Shift_Reg8 bit[0]

LUT3_5 bit[1]/Shift_Reg8 bit[1]

LUT3_5 bit[2]/Shift_Reg8 bit[2]

LUT3_5 bit[3]/Shift_Reg8 bit[3]

LUT3_5 bit[4]/Shift_Reg8 bit[4]

LUT3_5 bit[5]/Shift_Reg8 bit[5]

LUT3_5 bit[6]/Shift_Reg8 bit[6]

LUT3_5 bit[7]/DFF8/Shift_Reg8 bit[7]

LUT3_6 bit[0]/Shift_Reg9 bit[0]

LUT3_6 bit[1]/Shift_Reg9 bit[1]

LUT3_6 bit[2]/Shift_Reg9 bit[2]

LUT3_6 bit[3]/Shift_Reg9 bit[3]

LUT3_6 bit[4]/Shift_Reg9 bit[4]

LUT3_6 bit[5]/Shift_Reg9 bit[5]

LUT3_6 bit[6]/Shift_Reg9 bit[6]

LUT3_6 bit[7]/DFF9 /Shift_Reg9 bit[7]

LUT3_7 bit[0]/Shift_Reg10 bit[0]

LUT3_7 bit[1]/Shift_Reg10 bit[1]

LUT3_7 bit[2]/Shift_Reg10 bit[2]

LUT3_7 bit[3]/Shift_Reg10 bit[3]

LUT3_7 bit[4]/Shift_Reg10 bit[4]

LUT3_7 bit[5]/Shift_Reg10 bit[5]

LUT3_7 bit[6]/Shift_Reg10 bit[6]

LUT3_7 bit[7]/DFF10/Shift_Reg10 bit[7]

53

LUT3_2_DFF5_SHR5

54

55

56

57

58

LUT3_3_DFF6_SHR6

LUT3_4_DFF7_SHR7

LUT3_5_DFF8_SHR8

LUT3_6_DFF9_SHR9

LUT3_7_DFF10_SHR10

Datasheet

16-Jul-2021

Revision 2.0

136 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

712

713

714

715

716

717

718

719

720

721

722

723

724

725

726

727

728

729

730

731

732

733

734

735

736

737

738

739

740

741

742

743

LUT3_8 bit[0]/Shift_Reg11 bit[0]

LUT3_8 bit[1]/Shift_Reg11 bit[1]

LUT3_8 bit[2]/Shift_Reg11 bit[2]

LUT3_8 bit[3]/Shift_Reg11 bit[3]

LUT3_8 bit[4]/Shift_Reg11 bit[4]

LUT3_8 bit[5]/Shift_Reg11 bit[5]

LUT3_8 bit[6]/Shift_Reg11 bit[6]

LUT3_8 bit[7]/DFF11/Shift_Reg11 bit[7]

LUT3_9 bit[0]/Shift_Reg12 bit[0]

LUT3_9 bit[1]/Shift_Reg12 bit[1]

LUT3_9 bit[2]/Shift_Reg12 bit[2]

LUT3_9 bit[3]/Shift_Reg12 bit[3]

LUT3_9 bit[4]/Shift_Reg12 bit[4]

LUT3_9 bit[5]/Shift_Reg12 bit[5]

LUT3_9 bit[6]/Shift_Reg12 bit[6]

LUT3_9 bit[7]/DFF12/Shift_Reg12 bit[7]

LUT4_0 bit[0]/Shift_Reg13 bit[0]

LUT4_0 bit[1]/Shift_Reg13 bit[1]

LUT4_0 bit[2]/Shift_Reg13 bit[2]

LUT4_0 bit[3]/Shift_Reg13 bit[3]

LUT4_0 bit[4]/Shift_Reg13 bit[4]

LUT4_0 bit[5]/Shift_Reg13 bit[5]

LUT4_0 bit[6]/Shift_Reg13 bit[6]

LUT4_0 bit[7]/Shift_Reg13 bit[7]

LUT4_0 bit[8]/Shift_Reg13 bit[8]

LUT4_0 bit[9]/Shift_Reg13 bit[9]

LUT4_0 bit[10]/Shift_Reg13 bit[10]

LUT4_0 bit[11]/Shift_Reg13 bit[11]

LUT4_0 bit[12]/Shift_Reg13 bit[12]

LUT4_0 bit[13]/Shift_Reg13 bit[13]

LUT4_0 bit[14]/Shift_Reg13 bit[14]

LUT4_0 bit[15]/DFF13/Shift_Reg13 bit[15]

59

LUT3_8_DFF11_SHR11

5A

5B

5C

LUT3_9_DFF12_SHR12

LUT4_0_DFF13_SHR13

LUT2_0_DFF0_SHR0 DFF/Latch/Shift or LUT 0: LUT

744

745

Select

1: DFF/Latch/Shift Register

Value=0 DFF/Latch Mode,

Value=1 Length=2,

Value=2 Length=3,

LUT2_0_DFF0_SHR0 Shift Register Length

746

Value=3 Length=4...

0: DFF

747

748

LUT2_0_DFF0_SHR0 DFF or Latch Select

LUT2_0_DFF0_SHR0 Output Polarity Select

1: Latch

(Only valid when LUT_SEL=0 and SHR_LEN=0)

0: Non-inverted

1: Inverted

5D

LUT2_1_DFF1_SHR1 DFF/Latch/Shift or LUT 0: LUT

749

750

Select

1: DFF/Latch/Shift Register

Value=0 DFF/Latch Mode,

Value=1 Length=2,

LUT2_1_DFF1_SHR1 Shift Register Length

Value=2 Length=3,

751

Value=3 Length=4...

Datasheet

16-Jul-2021

Revision 2.0

137 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: DFF

LUT2_1_DFF1_SHR1 DFF or Latch Select

752

753

1: Latch

(Only valid when LUT_SEL=0 and SHR_LEN=0)

0: Non-inverted

1: Inverted

LUT2_1_DFF1_SHR1 Output Polarity Select

LUT2_2_DFF2_SHR2 DFF/Latch/Shift or LUT 0: LUT

754

755

Select

1: DFF/Latch/Shift Register

Value=0 DFF/Latch Mode,

Value=1 Length=2,

Value=2 Length=3,

5E

LUT2_2_DFF2_SHR2 Shift Register Length

756

757

Value=3 Length=4...

0: DFF

1: Latch

LUT2_2_DFF2_SHR2 DFF or Latch Select

(Only valid when LUT_SEL=0 and SHR_LEN=0)

0: Non-inverted

1: Inverted

0: LUT

1: Pattern Generator

0: Active Low Level for reset/set

1: Active High Level for reset/set

758

759

760

761

LUT2_2_DFF2_SHR2 Output Polarity Select

LUT2_3_PGEN0 Function Select

LUT2_3_PGEN0 Active Level Selection for

RST/SET

LUT3_0_DFF3_SHR3 DFF/Latch/Shift or LUT 0: LUT

Select

1: DFF/Latch/Shift Register

762

763

Value=0 DFF/Latch Mode,

Value=1 Length=2,

Value=2 Length=3,

LUT3_0_DFF3_SHR3 Shift Register Length

764

Value=3 Length=4...

5F

0: DFF

765

LUT3_0_DFF3_SHR3 DFF or Latch Select

LUT3_0_DFF3_SHR3 Output Polarity Select

LUT3_0_DFF3_SHR3 nRST/nSet Select

1: Latch

(Only valid when LUT_SEL=0 and SHR_LEN=0)

0: Non-inverted

1: Inverted

0: DFF/SHR use nRST

1: DFF/SHR use nSET

(Only valid in DFF/Latch mode)

766

767

0: Active Low

1: Active High

0: LUT

LUT3_0_DFF3_SHR3 Set/Reset active level

select

768

769

LUT3_1_DFF4_SHR4 DFF/Latch/Shift or LUT

Select

1: DFF/Latch/Shift Register

770

771

Value=0 DFF/Latch Mode,

Value=1 Length=2,

Value=2 Length=3,

LUT3_1_DFF4_SHR4 Shift Register Length

772

Value=3 Length=4...

60

0: DFF

1: Latch

LUT3_1_DFF4_SHR4 DFF or Latch Select.

Only valid when LUT_SEL=0 and SHR_LEN=0

773

(Only valid when LUT_SEL=0 and SHR_LEN=0)

0: Non-inverted

1: Inverted

0: DFF/SHR use nRST

1: DFF/SHR use nSET

(Only valid in DFF/Latch mode)

774

775

LUT3_1_DFF4_SHR4 Output Polarity Select

LUT3_1_DFF4_SHR4 nRST/nSet Select

Datasheet

16-Jul-2021

Revision 2.0

138 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: Active Low

1: Active High

LUT3_2_DFF5_SHR5 DFF/Latch/Shift or LUT 0: LUT

LUT3_1_DFF4_SHR4 Set/Reset active level

select

776

777

Select

1: DFF/Latch/Shift Register

778

779

Value=0 DFF/Latch Mode,

Value=1 Length=2,

Value=2 Length=3,

LUT3_2_DFF5_SHR5 Shift Register Length

780

Value=3 Length=4...

61

0: DFF

781

LUT3_2_DFF5_SHR5 DFF or Latch Select

LUT3_2_DFF5_SHR5 Output Polarity Select

LUT3_2_DFF5_SHR5 nRST/nSet Select

1: Latch

(Only valid when LUT_SEL=0 and SHR_LEN=0)

0: Non-inverted

1: Inverted

0: DFF/SHR use nRST

1: DFF/SHR use nSET

(Only valid in DFF/Latch mode)

782

783

0: Active Low

1: Active High

0: LUT

LUT3_2_DFF5_SHR5 Set/Reset active level

select

784

785

LUT3_3_DFF6_SHR6 DFF/Latch/Shift or LUT

Select

1: DFF/Latch/Shift Register

786

787

Value=0 DFF/Latch Mode,

Value=1 Length=2,

Value=2 Length=3,

LUT3_3_DFF6_SHR6 Shift Register Length

788

Value=3 Length=4...

62

0: DFF

789

LUT3_3_DFF6_SHR6 DFF or Latch Select

LUT3_3_DFF6_SHR6 Output Polarity Select

LUT3_3_DFF6_SHR6 nRST/nSet Select

1: Latch

(Only valid when LUT_SEL=0 and SHR_LEN=0)

0: Non-inverted

1: Inverted

0: DFF/SHR use nRST

1: DFF/SHR use nSET

(Only valid in DFF/Latch mode)

790

791

LUT3_3_DFF6_SHR6 Set/Reset active level 0: Active Low

792

793

select

1: Active High

0: LUT

LUT3_4_DFF7_SHR7 DFF/Latch/Shift or LUT

Select

1: DFF/Latch/Shift Register

794

795

Value=0 DFF/Latch Mode,

Value=1 Length=2,

Value=2 Length=3,

LUT3_4_DFF7_SHR7 Shift Register Length

796

Value=3 Length=4...

63

0: DFF

797

LUT3_4_DFF7_SHR7 DFF or Latch Select

LUT3_4_DFF7_SHR7 Output Polarity Select

LUT3_4_DFF7_SHR7 nRST/nSet Select

1: Latch

(Only valid when LUT_SEL=0 and SHR_LEN=0)

0: Non-inverted

1: Inverted

0: DFF/SHR use nRST

1: DFF/SHR use nSET

(Only valid in DFF/Latch mode)

798

799

800

0: Active Low

1: Active High

LUT3_4_DFF7_SHR7 Set/Reset active level

select

64

Datasheet

16-Jul-2021

Revision 2.0

139 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

LUT3_5_DFF8_SHR8 DFF/Latch/Shift or LUT 0: LUT

801

Select

1: DFF/Latch/Shift Register

802

803

Value=0 DFF/Latch Mode,

Value=1 Length=2,

Value=2 Length=3,

LUT3_5_DFF8_SHR8 Shift Register Length

804

Value=3 Length=4...

0: DFF

1: Latch

64

805

LUT3_5_DFF8_SHR8 DFF or Latch Select.

LUT3_5_DFF8_SHR8 Output Polarity Select

LUT3_5_DFF8_SHR8 nRST/nSet Select

(Only valid when LUT_SEL=0 and SHR_LEN=0)

0: Non-inverted

1: Inverted

0: DFF/SHR use nRST

1: DFF/SHR use nSET

(Only valid in DFF/Latch mode)

806

807

LUT3_5_DFF8_SHR8 Set/Reset active level 0: Active Low

808

809

select

1: Active High

0: LUT

LUT3_6_DFF9_SHR9 DFF/Latch/Shift or LUT

Select

1: DFF/Latch/Shift Register

810

811

Value=0 DFF/Latch Mode,

Value=1 Length=2,

Value=2 Length=3,

LUT3_6_DFF9_SHR9 Shift Register Length

812

Value=3 Length=4...

65

0: DFF

813

LUT3_6_DFF9_SHR9 DFF or Latch Select

LUT3_6_DFF9_SHR9 Output Polarity Select

LUT3_6_DFF9_SHR9 nRST/nSet Select

1: Latch

(Only valid when LUT_SEL=0 and SHR_LEN=0)

0: Non-inverted

1: Inverted

0: DFF/SHR use nRST

1: DFF/SHR use nSET

(Only valid in DFF/Latch mode)

814

815

0: Active Low

1: Active High

0: LUT

LUT3_6_DFF9_SHR9 Set/Reset active level

select

816

817

LUT3_7_DFF10_SHR10 DFF/Latch/Shift or

LUT Select

1: DFF/Latch/Shift Register

818

819

Value=0 DFF/Latch Mode,

Value=1 Length=2,

Value=2 Length=3,

LUT3_7_DFF10_SHR10 Shift Register Length

820

Value=3 Length=4...

66

0: DFF

821

LUT3_7_DFF10_SHR10 DFF or Latch Select 1: Latch

(Only valid when LUT_SEL=0 and SHR_LEN=0)

LUT3_7_DFF10_SHR10 Output Polarity Se- 0: Non-inverted

822

823

lect

1: Inverted

0: DFF/SHR use nRST

1: DFF/SHR use nSET

(Only valid in DFF/Latch mode)

LUT3_7_DFF10_SHR10 nRST/nSet Select

0: Active Low

1: Active High

0: LUT

LUT3_7_DFF10_SHR10Set/Resetactivelevel

select

824

825

67

LUT3_8_DFF11_SHR11 DFF/Latch/Shift or

LUT Select

1: DFF/Latch/Shift Register

Datasheet

16-Jul-2021

Revision 2.0

140 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

826

827

Value=0 DFF/Latch Mode,

Value=1 Length=2,

Value=2 Length=3,

LUT3_8_DFF11_SHR11 Shift Register Length

828

Value=3 Length=4...

0: DFF

829

LUT3_8_DFF11_SHR11 DFF or Latch Select 1: Latch

(Only valid when LUT_SEL=0 and SHR_LEN=0)

67

0: Non-inverted

1: Inverted

0: DFF/SHR use nRST

1: DFF/SHR use nSET

(Only valid in DFF/Latch mode)

830

831

LUT3_8_DFF11_SHR11 OutputPolarity Select

LUT3_8_DFF11_SHR11 nRST/nSet Select

LUT3_8_DFF11_SHR11 Set/Reset active level 0: Active Low

832

833

select

1: Active High

0: LUT

LUT3_9_DFF12_SHR12 DFF/Latch/Shift or

LUT Select

1: DFF/Latch/Shift Register

834

835

Value=0 DFF/Latch Mode,

Value=1 Length=2,

Value=2 Length=3,

LUT3_9_DFF12_SHR12 Shift Register Length

836

Value=3 Length=4...

68

0: DFF

837

LUT3_9_DFF12_SHR12 DFF or Latch Select 1: Latch

(Only valid when LUT_SEL=0 and SHR_LEN=0)

0: Non-inverted

1: Inverted

0: DFF/SHR use nRST

1: DFF/SHR use nSET

(Only valid in DFF/Latch mode)

LUT3_9_DFF12_SHR12 Output Polarity Se-

838

839

lect

LUT3_9_DFF12_SHR12 nRST/nSet Select

0: Active Low

1: Active High

0: LUT

LUT3_9_DFF12_SHR12Set/Resetactivelevel

select

840

841

LUT4_0_DFF13_SHR13 DFF/Latch/Shift or

LUT Select

1: DFF/Latch/Shift Register

842

843

844

845

Value=0 DFF/Latch Mode,

Value=1 Length=2,

Value=2 Length=3,

LUT4_0_DFF13_SHR13 Shift Register Length

69

Value=3 Length=4...

0: DFF

846

847

848

849

LUT4_0_DFF13_SHR13 DFF or Latch Select 1: Latch

(Only valid when LUT_SEL=0 and SHR_LEN=0)

0: Non-inverted

1: Inverted

0: DFF/SHR use nRST

1: DFF/SHR use nSET

(Only valid in DFF/Latch mode)

LUT4_0_DFF13_SHR13 Output Polarity Se-

lect

LUT4_0_DFF13_SHR13 nRST/nSet Select

LUT4_0_DFF13_SHR13Set/Resetactivelevel 0: Active Low

select

1: Active High

6A

850

851

852

853

854

855

Reserved

Datasheet

16-Jul-2021

Revision 2.0

141 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

856

857

858

859

860

861

862

863

864

865

866

867

868

869

870

871

6B

LUT2_3_PGEN0_DATA_LSB[7:0]

Pattern Data LSB

6C

6D

6E

LUT2_3_PGEN0_DATA_MSB[7:0]

Pattern Data MSB

MLT0_LUT4_1 bit[0]/DFF14 DFF or Latch Select:

0: LUT: LUT[0]; DFF: DFF function

1: LUT: LUT[0]; DFF: Latch function

MLT0_LUT4_1 bit[1]/DFF14 Output Select:

0: LUT: LUT[1]; DFF: Q output

1: LUT: LUT[1]; DFF: QB output

MLT0_LUT4_1 bit[2]/DFF14 Initial Polarity Select:

0: LUT: LUT[2]; DFF: Low

1: LUT: LUT[2]; DFF: High

MLT0_LUT4_1 bit[3]

MLT0_LUT4_1 bit[4]

MLT0_LUT4_1 bit[5]

MLT0_LUT4_1 bit[6]

MLT0_LUT4_1 bit[7]

MLT0_LUT4_1 bit[8]

MLT0_LUT4_1 bit[9]

MLT0_LUT4_1 bit[10]

MLT0_LUT4_1 bit[11]

MLT0_LUT4_1 bit[12]

MLT0_LUT4_1 bit[13]

MLT0_LUT4_1 bit[14]

MLT0_LUT4_1 bit[15]

872

873

874

875

876

877

878

879

880

881

882

883

884

885

886

887

LUT4_1_DFF14_CNTDLY0

Datasheet

16-Jul-2021

Revision 2.0

142 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

888

889

890

0000: Both edge Delay

0001: Falling edge Delay

0010: Rising edge Delay

0011: Prohibited

0100: Both edge One Shot

0101: Falling edge One Shot

0110: Rising edge One Shot

0111: Prohibited

1000: Both edge frequency detect

1001: Falling edge frequency detect

1010: Rising edge frequency detect

1011: Prohibited

CNTDLY0 Function and Edge mode selection

891

1100: Both edge reset CNT

1101: Falling edge reset CNT

1110: Rising edge reset CNT

1111: High level reset CNT

6F

MLT0_LUT4_1_DFF14 LUT/DFF Function Se- 0: LUT

892

893

894

lect

1: DFF/Latch

0: Default Output

1: Inverted Output

CNT0 CNT/DLY output Polarity selection

0: Normal

CNT0 DLY mode edge detection selection

CNT0 CNT mode synchronizer selection

1: Enable DLY mode edge detection

0: Bypass synchronizer

1: Enable synchronizer (after two DFFs)

895

896

00: Single LUT or DFF (DLY input is low)

LUT4_1_DFF14_CNTDLY0 Multi function se- 01: Single CNT/DLY (DLY output connect to LUT/DFF)

lection

10: CNT/DLY connected to LUT or DFF

11: LUT or DFF connected to CNT/DLY

897

898

00: DLY input from matrix A;

DLY output connected to LUT's In3 or DFF's D

01: DLY input from matrix B;

MLT0_LUT4_1_DFF14_CNTDLY0 CNT/DLY

and LUT or DFF connection

(only works when multi_func_sel_reg is 2'b10)

DLY output connected to LUT's In2 or DFF's nSET

10: DLY input from matrix C;

899

DLY output connected to LUT's In1 or DFF's nRST

11: DLY input from matrix D;

70

DLY output connected to LUT's In0 or DFF's CLK

900

901

902

903

00: Bypass the initial

01: Bypass the initial

10: Initial 0

CNT0 CNT/DLY initial value selection

11: Initial 1

00: Connected to LOW

01: Form matrix B

CNT0 CNT external clock selection

(only works when multi_func_sel_reg is not

2'b00)

10: From matrix C

11: Connected to LOW

Datasheet

16-Jul-2021

Revision 2.0

143 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

904

905

906

0000: RingOSC(25 MHz)

0001: RingOSC(25 MHz)/4

0010: RingOSC(25 MHz)/8

0011: RingOSC(25 MHz)/64

0100: RingOSC(25 MHz)/512

0101: LFOSC(2 kHz)

0110: LFOSC(2 kHz)/8

0111: LFOSC(2 kHz)/64

1000: LFOSC(2KkHz)/512

1001: LFOSC(2 kHz)/4096

1010: LFOSC(2 kHz)/32768

1011: LFOSC(2 kHz)/262144

1100: CNTx_END

CNT0 CNT/DLY clock source selection

907

71

1101: External

1110: Not used

1111: Not used

908

909

910

911

912

913

914

915

916

917

918

919

920

921

922

923

924

925

926

927

928

929

930

931

932

933

934

935

936

937

938

939

940

941

942

943

Reserved

72

73

74

75

CNT0 MSB of CNT Data

Data [15:8]

Data [7:0]

Data [15:8]

Data [7:0]

CNT0 LSB of CNT Data

CNT0 MSB of Current CNT Value

CNT0 LSB of Current CNT Value

Datasheet

16-Jul-2021

Revision 2.0

144 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: Reset to 0

1: Set to data

0: Bypass synchronizer

1: Enable synchronizer (after two DFFs)

0: Bypass synchronizer

1: Enable synchronizer (after two DFFs)

0: Low

1: High

944

945

946

947

CNT0 CNT set or rest selection

CNT0 CNT up signal synchronizer selection

CNT0 CNT keep signal synchronizer selection

CNT0 Wake sleep power-down state selection

76

0: Default mode

948

CNT0 CNT wake sleep mode selection

CNT0 ACMP Wake/Sleep time selection

1: Wake-up sleep mode

(func_sel_reg configure as CNT mode)

0: Normal

1: Short Time

0: Disable

1: Enable

949

950

951

952

953

CNT0 Allow short wake-up signal

Reserved

0: Disable

1: Enable

0: Disable

1: Enable

ACMP0 wake sleep enable

ACMP1 wake sleep enable

954

955

956

957

958

959

Reserved

77

MLT1_LUT3_10 bit[0]/DFF15 DFF or Latch Select:

0: LUT: LUT[0]; DFF: DFF function

960

961

962

963

1: LUT: LUT[0]; DFF: Latch function

MLT1_LUT3_10 bit[1]/DFF15 Output Select:

0: LUT: LUT[1]; DFF: Q output

1: LUT: LUT[1]; DFF: QB output

MLT1_LUT3_10 bit[2]/DFF15 Initial Polarity Select:

0: LUT: LUT[2]; DFF: Low

1: LUT: LUT[2]; DFF: High

MLT1_LUT3_10 bit[3]/DFF15 nRST or nSET Select:

0: LUT: LUT[3]; DFF: nRST

1: LUT: LUT[3]; DFF: nSET

78

LUT3_10_DFF15_CNTDLY1

964

965

966

967

MLT1_LUT3_10 bit[4]

MLT1_LUT3_10 bit[5]

MLT1_LUT3_10 bit[6]

MLT1_LUT3_10 bit[7]

Datasheet

16-Jul-2021

Revision 2.0

145 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

968

969

970

0000: both edge Delay

0001: falling edge Delay

0010: rising edge Delay

0011: both edge One Shot

0100: falling edge One Shot

0101: rising edge One Shot

0110: both edge freq detect

0111: falling edge freq detect

1000: rising edge freq detect

1001: both edge detect

1010: falling edge detect

1011: rising edge detect

1100: both edge reset CNT

1101: falling edge reset CNT

1110: rising edge reset CNT

1111: high level reset CNT

CNTDLY1 Function and Edge mode selection

971

79

MLT1_LUT3_10_DFF15 LUT/DFF Function

Select

0: LUT

972

973

974

1: DFF/Latch

0: Default Output

1: Inverted Output

0: Normal

1: Enable DLY mode edge detection

0: Bypass synchronizer

1: Enable synchronizer (after two DFFs)

00: Single LUT or DFF (DLY input is low)

CNT1 CNT/DLY output Polarity selection

CNT1 DLY mode edge detection selection

CNT1 CNT mode synchronizer selection

975

976

LUT3_10_DFF15_CNTDLY1 Multi function se- 01: Single CNT/DLY (DLY output connect to LUT/DFF)

lection

10: CNT/DLY connected to LUT or DFF

11: LUT or DFF connected to CNT/DLY

977

978

00: DLY input from matrix A;

DLY output connected to LUT's In2 or DFF's D

MLT1_LUT3_10_DFF15_CNTDLY1 CNT/DLY 01: DLY input from matrix B;

and LUT or DFF connection

DLY output connected to LUT's In1 or DFF's nSET/nRST

979

(only works when multi_func_sel_reg is 2'b10) 10: DLY input from matrix C;

7A

DLY output connected to LUT's In0 or DFF's CLK

11: Prohibited

980

981

00: Bypass the initial

01: Bypass the initial

10: Initial 0

CNT1 CNT/DLY initial value selection

11: Initial 1

982

983

984

985

986

Reserved

0000: RingOSC(25 MHz)

0001: RingOSC(25 MHz)/4

0010: RingOSC(25 MHz)/8

0011: RingOSC(25 MHz)/64

0100: RingOSC(25 MHz)/512

0101: LFOSC(2 kHz)

0110: LFOSC(2 kHz)/8

0111: LFOSC(2 kHz)/64

1000: LFOSC(2 kHz)/512

1001: LFOSC(2 kHz)/4096

1010: LFOSC(2 kHz)/32768

1011:LFOSC(2 kHz)/262144

1100: CNTx_END

7B

CNT1 CNT/DLY clock source selection

987

1101: External

1110: Not used

1111: Not used

Datasheet

16-Jul-2021

Revision 2.0

146 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

988

989

990

991

Reserved

7B

992

993

994

995

996

7C

CNT1 CNT Data

Data [7:0]

997

998

999

1000

1001

1002

1003

1004

1005

1006

1007

7D

CNT1 Current CNT Value

Data [7:0]

MLT2_LUT3_11 bit[0]/DFF16 DFF or Latch Select:

0: LUT: LUT[0]; DFF: DFF function

1008

1009

1010

1011

1: LUT: LUT[0]; DFF: Latch function

MLT2_LUT3_11 bit[1]/DFF16 Output Select:

0: LUT: LUT[1]; DFF: Q output

1: LUT: LUT[1]; DFF: QB output

MLT2_LUT3_11 bit[2]/DFF16 Initial Polarity Select:

0: LUT: LUT[2]; DFF: Low

1: LUT: LUT[2]; DFF: High

MLT2_LUT3_11 bit[3]/DFF16 nRST or nSET Select:

0: LUT: LUT[3]; DFF: nRST

1: LUT: LUT[3]; DFF: nSET

7E

LUT3_11_DFF16_CNTDLY2

1012

1013

1014

1015

MLT2_LUT3_11 bit[4]

MLT2_LUT3_11 bit[5]

MLT2_LUT3_11 bit[6]

MLT2_LUT3_11 bit[7]

Datasheet

16-Jul-2021

Revision 2.0

147 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1016

1017

1018

0000: both edge Delay

0001: falling edge delay

0010: rising edge delay

0011: both edge One Shot

0100: falling edge One Shot

0101: rising edge One Shot

0110: both edge freq detect

0111: falling edge freq detect

1000: rising edge freq detect

1001: both edge detect

1010: falling edge detect

1011: rising edge detect

1100: both edge reset CNT

1101: falling edge reset CNT

1110: rising edge reset CNT

1111: high level reset CNT

CNTDLY2 Function and Edge mode selection

1019

7F

MLT2_LUT3_11_DFF16 LUT/DFF Function

Select

0: LUT

1020

1021

1022

1: DFF/Latch

0: Default Output

1: Inverted Output

0: Normal

1: Enable DLY mode edge detection

0: Bypass synchronizer

1: Enable synchronizer (after two DFFs)

00: Single LUT or DFF (DLY input is low)

CNT2 CNT/DLY output Polarity selection

CNT2 DLY mode edge detection selection

CNT2 CNT mode synchronizer selection

1023

1024

LUT3_11_DFF16_CNTDLY2 Multi function se- 01: Single CNT/DLY (DLY output connect to LUT/DFF)

lection

10: CNT/DLY connected to LUT or DFF

11: LUT or DFF connected to CNT/DLY

1025

1026

00: DLY input from matrix A;

DLY output connected to LUT's In2 or DFF's D

MLT2_LUT3_11_DFF16_CNTDLY2 CNT/DLY 01: DLY input from matrix B;

and LUT or DFF connection

DLY output connected to LUT's In1 or DFF's nSET/nRST

1027

(only works when multi_func_sel_reg is 2'b10) 10: DLY input from matrix C;

80

DLY output connected to LUT's In0 or DFF's CLK

11: Prohibited

1027

1029

00: Bypass the initial

01: Bypass the initial

10: Initial 0

CNT2 CNT/DLY initial value selection

11: Initial 1

1030

1031

1032

1033

1034

Reserved

0000: RingOSC(25 MHz)

0001: RingOSC(25 MHz)/4

0010: RingOSC(25 MHz)/8

0011: RingOSC(25 MHz)/64

0100: RingOSC(25MHz)/512

0101: LFOSC(2 kHz)

0110: LFOSC(2 kHz)/8

0111: LFOSC(2 kHz)/64

1000: LFOSC(2 kHz)/512

1001: LFOSC(2 kHz)/4096

1010: LFOSC(2 kHz)/32768

1011: LFOSC(2 kHz)/262144

1100: CNTx_END

81

Matrix Divider Ratio Control

1035

1101: External

1110: Not used

1111: Not used

Datasheet

16-Jul-2021

Revision 2.0

148 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1036

1037

1038

1039

1040

1041

1042

1043

1044

1045

1046

1047

1048

1049

1050

1051

1052

1053

1054

1055

Reserved

81

82

CNT2 CNT Data

Data [7:0]

83

CNT2 Current CNT Value

Data [7:0]

MLT3_LUT3_12 bit[0]/DFF17 DFF or Latch Select:

0: LUT: LUT[0]; DFF: DFF function

1056

1057

1058

1059

1: LUT: LUT[0]; DFF: Latch function

MLT3_LUT3_12 bit[1]/DFF17 Output Select:

0: LUT: LUT[1]; DFF: Q output

1: LUT: LUT[1]; DFF: QB output

MLT3_LUT3_12 bit[2]/DFF17 Initial Polarity Select:

0: LUT: LUT[2]; DFF: Low

1: LUT: LUT[2]; DFF: High

MLT3_LUT3_12 bit[3]/DFF17 nRST or nSET Select:

0: LUT: LUT[3]; DFF: nRST

1: LUT: LUT[3]; DFF: nSET

84

LUT3_12_DFF17_CNTDLY3

1060

1061

1062

1063

MLT3_LUT3_12 bit[4]

MLT3_LUT3_12 bit[5]

MLT3_LUT3_12 bit[6]

MLT3_LUT3_12 bit[7]

Datasheet

16-Jul-2021

Revision 2.0

149 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1064

1065

1066

0000: both edge Delay

0001: falling edge Delay

0010: rising edge Delay

0011: both edge One Shot

0100: falling edge One Shot

0101: rising edge One Shot

0110: both edge freq detect

0111: falling edge freq detect

1000: rising edge freq detect

1001: both edge detect

1010: falling edge detect

1011: rising edge detect

1100: both edge reset CNT

1101: falling edge reset CNT

1110: rising edge reset CNT

1111: high level reset CNT

CNTDLY3 Function and Edge mode selection

1067

85

MLT3_LUT3_12_DFF17 LUT/DFF Function

Select

0: LUT

1068

1069

1070

1: DFF/Latch

0: Default Output

1: Inverted Output

0: Normal

1: Enable DLY mode edge detection

0: Bypass synchronizer

1: Enable synchronizer (after two DFFs)

00: Single LUT or DFF (DLY input is low)

CNT3 CNT/DLY output Polarity selection

CNT3 DLY mode edge detection selection

CNT3 CNT mode synchronizer selection

1071

1072

LUT3_12_DFF17_CNTDLY3 Multi function se- 01: Single CNT/DLY (DLY output connect to LUT/DFF)

lection

10: CNT/DLY connected to LUT or DFF

11: LUT or DFF connected to CNT/DLY

1073

1074

00: DLY input from matrix A;

DLY output connected to LUT's In2 or DFF's D

MLT3_LUT3_12_DFF17_CNTDLY3 CNT/DLY 01: DLY input from matrix B;

and LUT or DFF connection

DLY output connected to LUT's In1 or DFF's nSET/nRST

1075

(only works when multi_func_sel_reg is 2'b10) 10: DLY input from matrix C;

86

DLY output connected to LUT's In0 or DFF's CLK

11: Prohibited

1076

1077

00: Bypass the initial

01: Bypass the initial

10: Initial 0

CNT3 CNT/DLY initial value selection

11: Initial 1

1078

1079

Reserved

Datasheet

16-Jul-2021

Revision 2.0

150 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1080

1081

1082

0000: RingOSC(25 MHz)

0001: RingOSC(25 MHz)/4

0010: RingOSC(25 MHz)/8

0011:RingOSC(25 MHz)/64

0100: RingOSC(25 MHz)/512

0101: LFOSC(2 kHz)

0110: LFOSC(2 kHz)/8

0111: LFOSC(2 kHz)/64

1000:LFOSC(2 kHz)/512

1001: LFOSC(2 kHz)/4096

1010: LFOSC(2 kHz)/32768

1011:LFOSC(2 kHz)/262144

1100: CNTx_END

CNT3 CNT/DLY clock source selection

1083

87

1101: External

1110: Not used

1111: Not used

1084

1085

1086

1087

1088

1089

1090

1091

1092

1093

1094

1095

1096

1097

1098

1099

1100

1101

1102

1103

Reserved

88

CNT3 CNT Data

Data [7:0]

89

CNT3 Current CNT Value

Data [7:0]

MLT4_LUT3_13 bit[0]/DFF18 DFF or Latch Select:

0: LUT: LUT[0]; DFF: DFF function

1104

1105

1106

1107

1: LUT: LUT[0]; DFF: Latch function

MLT4_LUT3_13 bit[1]/DFF18 Output Select:

0: LUT: LUT[1]; DFF: Q output

1: LUT: LUT[1]; DFF: QB output

MLT4_LUT3_13 bit[2]/DFF18 Initial Polarity Select:

0: LUT: LUT[2]; DFF: Low

1: LUT: LUT[2]; DFF: High

MLT4_LUT3_13 bit[3]/DFF18 nRST or nSET Select:

0: LUT: LUT[3]; DFF: nRST

1: LUT: LUT[3]; DFF: nSET

MLT4_LUT3_13 bit[4]

MLT4_LUT3_13 bit[5]

MLT4_LUT3_13 bit[6]

MLT4_LUT3_13 bit[7]

8A

LUT3_13_DFF18_CNTDLY4

1108

1109

1110

1111

Datasheet

16-Jul-2021

Revision 2.0

151 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1112

1113

1114

0000: both edge Delay

0001: falling edge Delay

0010: rising edge Delay

0011: both edge One Shot

0100: falling edge One Shot

0101: rising edge One Shot

0110: both edge freq detect

CNTDLY4 Function and Edge mode selection 0111: falling edge freq detect

1000: rising edge freq detect

1001: both edge detect

1115

1010: falling edge detect

1011: rising edge detect

1100: both edge reset CNT

8B

1101: falling edge reset CNT

1110: rising edge reset CNT

1111: high level reset CNT

MLT4_LUT3_13_DFF18 LUT/DFF Function

Select

0: LUT

1116

1117

1118

1: DFF/Latch

0: Default Output

1: Inverted Output

0: Normal

1: Enable DLY mode edge detection

0: Bypass synchronizer

1: Enable synchronizer (after two DFFs)

00: Single LUT or DFF (DLY input is low)

CNT4 CNT/DLY output Polarity selection

CNT4 DLY mode edge detection selection

CNT4 CNT mode synchronizer selection

1119

1120

LUT3_13_DFF18_CNTDLY4 Multi function se- 01: Single CNT/DLY (DLY output connect to LUT/DFF)

lection

10: CNT/DLY connected to LUT or DFF

11: LUT or DFF connected to CNT/DLY

00: DLY input from matrix A;

DLY output connected to LUT's In2 or DFF's D

01: DLY input from matrix B;

DLY output connected to LUT's In1 or DFF's nSET/nRST

10: DLY input from matrix C;

DLY output connected to LUT's In0 or DFF's CLK

11: Prohibited

1121

1122

MLT4_LUT3_13_DFF18_CNTDLY4 CNT/DLY

and LUT or DFF connection

(only works when multi_func_sel_reg is 2'b10)

1123

8C

1124

1125

00: Bypass the initial

01: Bypass the initial

10: Initial 0

CNT4 CNT/DLY initial value selection

11: Initial 1

1126

1127

Reserved

Datasheet

16-Jul-2021

Revision 2.0

152 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1128

1129

1130

0000: RingOSC(25 MHz)

0001: RingOSC(25 MHz)/4

0010: RingOSC(25 MHz)/8

0011:RingOSC(25 MHz)/64

0100: RingOSC(25 MHz)/512

0101: LFOSC(2 kHz)

0110: LFOSC(2 kHz)/8

0111: LFOSC(2 kHz)/64

1000:LFOSC(2 kHz)/512

1001: LFOSC(2 kHz)/4096

1010: LFOSC(2 kHz)/32768

1011:LFOSC(2 kHz)/262144

1100: CNTx_END

CNT4 CNT/DLY clock source selection

1131

8D

1101: External

1110: Not used

1111: Not used

1132

1133

1134

1135

1136

1137

1138

1139

1140

1141

1142

1143

1144

1145

1146

1147

1148

1149

1150

1151

Reserved

8E

CNT4 CNT Data

Data [7:0]

8F

CNT4 Current CNT Value

Data [7:0]

MLT5_LUT3_14 bit[0]/DFF19 DFF or Latch Select:

0: LUT: LUT[0]; DFF: DFF function

1152

1153

1154

1155

1: LUT: LUT[0]; DFF: Latch function

MLT5_LUT3_14 bit[1]/DFF19 Output Select:

0: LUT: LUT[1]; DFF: Q output

1: LUT: LUT[1]; DFF: QB output

MLT5_LUT3_14 bit[2]/DFF19 Initial Polarity Select:

0: LUT: LUT[2]; DFF: Low

1: LUT: LUT[2]; DFF: High

MLT5_LUT3_14 bit[3]/DFF19 nRST or nSET Select:

0: LUT: LUT[3]; DFF: nRST

1: LUT: LUT[3]; DFF: nSET

MLT5_LUT3_14 bit[4]

MLT5_LUT3_14 bit[5]

MLT5_LUT3_14 bit[6]

MLT5_LUT3_14 bit[7]

90

LUT3_14_DFF19_CNTDLY5

1156

1157

1158

1159

Datasheet

16-Jul-2021

Revision 2.0

153 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1160

1161

1162

0000: both edge Delay

0001: falling edge Delay

0010: rising edge Delay

0011: both edge One Shot

0100: falling edge One Shot

0101: rising edge One Shot

0110: both edge freq detect

0111: falling edge freq detect

1000: rising edge freq detect

1001: both edge detect

1010: falling edge detect

1011: rising edge detect

1100: both edge reset CNT

1101: falling edge reset CNT

1110: rising edge reset CNT

1111: high level reset CNT

CNTDLY5 Function and Edge mode selection

1163

91

MLT5_LUT3_14_DFF19 LUT/DFF Function

Select

0: LUT

1164

1165

1166

1: DFF/Latch

0: Default Output

1: Inverted Output

0: Normal

1: Enable DLY mode edge detection

0: Bypass synchronizer

1: Enable synchronizer (after two DFFs)

00: Single LUT or DFF (DLY input is low)

CNT5 CNT/DLY output Polarity selection

CNT5 DLY mode edge detection selection

CNT5 CNT mode synchronizer selection

1167

1168

LUT3_14_DFF19_CNTDLY5 Multi function se-

lection

01: Single CNT/DLY (DLY output connect to LUT/DFF)

10: CNT/DLY connected to LUT or DFF

11: LUT or DFF connected to CNT/DLY

1169

1170

00: DLY input from matrix A;

DLY output connected to LUT's In2 or DFF's D

MLT5_LUT3_14_DFF19_CNTDLY5 CNT/DLY 01: DLY input from matrix B;

and LUT or DFF connection

DLY output connected to LUT's In1 or DFF's nSET/nRST

1171

(only works when multi_func_sel_reg is 2'b10) 10: DLY input from matrix C;

92

DLY output connected to LUT's In0 or DFF's CLK

11: Prohibited

1172

1173

00: Bypass the initial

01: Bypass the initial

10: Initial 0

CNT5 CNT/DLY initial value selection

11: Initial 1

1174

1175

Reserved

Datasheet

16-Jul-2021

Revision 2.0

154 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1176

1177

1178

0000: RingOSC(25 MHz)

0001: RingOSC(25 MHz)/4

0010: RingOSC(25 MHz)/8

0011:RingOSC(25 MHz)/64

0100: RingOSC(25 MHz)/512

0101: LFOSC(2 kHz)

0110: LFOSC(2 kHz)/8

0111: LFOSC(2 kHz)/64

1000:LFOSC(2 kHz)/512

1001: LFOSC(2 kHz)/4096

1010: LFOSC(2 kHz)/32768

1011:LFOSC(2 kHz)/262144

1100: CNTx_END

CNT5 CNT/DLY clock source selection

1179

93

1101: External

1110: Not used

1111: Not used

1180

1181

1182

1183

1184

1185

1186

1187

1188

1189

1190

1191

1192

1193

1194

1195

1196

1197

1198

1199

Reserved

94

CNT5 CNT Data

Data [7:0]

95

CNT5 Current CNT Value

Data [7:0]

MLT6_LUT3_15 bit[0]/DFF20 DFF or Latch Select:

0: LUT: LUT[0]; DFF: DFF function

1200

1201

1202

1203

1: LUT: LUT[0]; DFF: Latch function

MLT6_LUT3_15 bit[1]/DFF20 Output Select:

0: LUT: LUT[1]; DFF: Q output

1: LUT: LUT[1]; DFF: QB output

MLT6_LUT3_15 bit[2]/DFF20 Initial Polarity Select:

0: LUT: LUT[2]; DFF: Low

1: LUT: LUT[2]; DFF: High

MLT6_LUT3_15 bit[3]/DFF20 nRST or nSET Select:

0: LUT: LUT[3]; DFF: nRST

1: LUT: LUT[3]; DFF: nSET

MLT6_LUT3_15 bit[4]

MLT6_LUT3_15 bit[5]

MLT6_LUT3_15 bit[6]

MLT6_LUT3_15 bit[7]

96

LUT3_15_DFF20_CNTDLY6

1204

1205

1206

1207

Datasheet

16-Jul-2021

Revision 2.0

155 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1208

1209

1210

0000: both edge Delay

0001: falling edge Delay

0010: rising edge Delay

0011: both edge One Shot

0100: falling edge One Shot

0101: rising edge One Shot

0110: both edge freq detect

0111: falling edge freq detect

1000: rising edge freq detect

1001: both edge detect

1010: falling edge detect

1011: rising edge detect

1100: both edge reset CNT

1101: falling edge reset CNT

1110: rising edge reset CNT

1111: high level reset CNT

CNTDLY6 Function and Edge mode selection

1211

97

MLT6_LUT3_15_DFF20 LUT/DFF Function

Select

0: LUT

1212

1213

1214

1: DFF/Latch

0: Default Output

1: Inverted Output

0: Normal

1: Enable DLY mode edge detection

0: Bypass synchronizer

1: Enable synchronizer (after two DFFs)

00: Single LUT or DFF (DLY input is low)

CNT6 CNT/DLY output Polarity selection

CNT6 DLY mode edge detection selection

CNT6 CNT mode synchronizer selection

1215

1216

LUT3_15_DFF20_CNTDLY6 Multi function se- 01: Single CNT/DLY (DLY output connect to LUT/DFF)

lection

10: CNT/DLY connected to LUT or DFF

11: LUT or DFF connected to CNT/DLY

00: DLY input from matrix A;

DLY output connected to LUT's In2 or DFF's D

01: DLY input from matrix B;

DLY output connected to LUT's In1 or DFF's nSET/nRST

10: DLY input from matrix C;

DLY output connected to LUT's In0 or DFF's CLK

11: Prohibited

1217

1218

MLT6_LUT3_15_DFF20_CNTDLY6 CNT/DLY

and LUT or DFF connection (only works when

multi_func_sel_reg is 2'b10)

1219

98

1220

1221

00: Bypass the initial

01: Bypass the initial

10: Initial 0

CNT6 CNT/DLY initial value selection

11: Initial 1

1222

1223

Reserved

Datasheet

16-Jul-2021

Revision 2.0

156 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1224

1225

1226

0000: RingOSC(25 MHz)

0001: RingOSC(25 MHz)/4

0010: RingOSC(25 MHz)/8

0011:RingOSC(25 MHz)/64

0100: RingOSC(25 MHz)/512

0101: LFOSC(2 kHz)

0110: LFOSC(2 kHz)/8

0111: LFOSC(2 kHz)/64

1000:LFOSC(2 kHz)/512

1001: LFOSC(2 kHz)/4096

1010: LFOSC(2 kHz)/32768

1011:LFOSC(2 kHz)/262144

1100: CNTx_END

CNT6 CNT/DLY clock source selection

1227

99

1101: External

1110: Not used

1111: Not used

1228

1229

1230

1231

1232

1233

1234

1235

1236

1237

1238

1239

1240

1241

1242

1243

1244

1245

1246

1247

Reserved

9A

CNT6 CNT Data

Data [7:0]

9B

CNT6 Current CNT Value

Data [7:0]

MLT7_LUT3_16 bit[0]/DFF21 DFF or Latch Select:

0: LUT: LUT[0]; DFF: DFF function

1248

1249

1250

1251

1: LUT: LUT[0]; DFF: Latch function

MLT7_LUT3_16 bit[1]/DFF21 Output Select:

0: LUT: LUT[1]; DFF: Q output

1: LUT: LUT[1]; DFF: QB output

MLT7_LUT3_16 bit[2]/DFF21 Initial Polarity Select:

0: LUT: LUT[2]; DFF: Low

1: LUT: LUT[2]; DFF: High

MLT7_LUT3_16 bit[3]/DFF21 nRST or nSET Select:

0: LUT: LUT[3]; DFF: nRST

1: LUT: LUT[3]; DFF: nSET

MLT7_LUT3_16 bit[4]

MLT7_LUT3_16 bit[5]

MLT7_LUT3_16 bit[6]

MLT7_LUT3_16 bit[7]

9C

LUT3_16_DFF21_CNTDLY7

1252

1253

1254

1255

Datasheet

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Revision 2.0

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SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1256

1257

1258

0000: both edge Delay

0001: falling edge Delay

0010: rising edge Delay

0011: both edge One Shot

0100: falling edge One Shot

0101: rising edge One Shot

0110: both edge freq detect

0111: falling edge freq detect

1000: rising edge freq detect

1001: both edge detect

1010: falling edge detect

1011: rising edge detect

1100: both edge reset CNT

1101: falling edge reset CNT

1110: rising edge reset CNT

1111: high level reset CNT

CNTDLY7 Function and Edge mode selection

1259

9D

MLT7_LUT3_16_DFF21 LUT/DFF Function

Select

0: LUT

1260

1261

1262

1: DFF/Latch

0: Default Output

1: Inverted Output

0: Normal

1: Enable DLY mode edge detection

0: Bypass synchronizer

1: Enable synchronizer (after two DFFs)

00: Single LUT or DFF (DLY input is low)

CNT7 CNT/DLY output Polarity selection

CNT7 DLY mode edge detection selection

CNT7 CNT mode synchronizer selection

1263

1264

LUT3_16_DFF21_CNTDLY7 Multi function se- 01: Single CNT/DLY (DLY output connect to LUT/DFF)

lection

10: CNT/DLY connected to LUT or DFF

11: LUT or DFF connected to CNT/DLY

00: DLY input from matrix A;

DLY output connected to LUT's In2 or DFF's D

01: DLY input from matrix B;

DLY output connected to LUT's In1 or DFF's nSET/nRST

10: DLY input from matrix C;

DLY output connected to LUT's In0 or DFF's CLK

11: Prohibited

1265

1266

MLT7_LUT3_16_DFF21_CNTDLY7 CNT/DLY

and LUT or DFF connection

(only works when multi_func_sel_reg is 2'b10)

1267

9E

1268

1269

00: Bypass the initial

01: Bypass the initial

10: Initial 0

CNT7 CNT/DLY initial value selection

11: Initial 1

1270

1271

Reserved

Datasheet

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Revision 2.0

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Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1272

1273

1274

0000: RingOSC(25 MHz)

0001: RingOSC(25 MHz)/4

0010: RingOSC(25 MHz)/8

0011:RingOSC(25 MHz)/64

0100: RingOSC(25 MHz)/512

0101: LFOSC(2 kHz)

0110: LFOSC(2 kHz)/8

0111: LFOSC(2kHz)/64

1000:LFOSC(2 kHz)/512

1001: LFOSC(2 kHz)/4096

1010: LFOSC(2 kHz)/32768

1011:LFOSC(2 kHz)/262144

1100: CNTx_END

CNT7 CNT/DLY clock source selection

1275

9F

1101: External

1110: Not used

1111: Not used

1276

1277

1278

1279

1280

1281

1282

1283

1284

1285

1286

1287

1288

1289

1290

1291

1292

1293

1294

1295

1296

Reserved

A0

CNT7 CNT Data

Data [7:0]

A1

CNT7 Current CNT Value

Data [7:0]

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

GPI0 input mode configuration

1297

1298

1299

1300

1301

1302

1303

Reserved

A2

Reserved

Datasheet

16-Jul-2021

Revision 2.0

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SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1304

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

GPIO0 input mode configuration

1305

1306

1307

1308

1309

Reserved

A3

00: Floating (disconnected)

01: 10 kΩ

GPIO0 Pull-up or Pull-down resistor selection

10: 100 kΩ

1310

11: 1 MΩ

0: Pull-down

1: Pull-up

0: enable

1: disable

1311

1312

GPIO0 Pull-up or Pull-down mode selection

GPIO0 I²C fast mode plus enable

0: disable (Output = HiZ)

1: enable

1313

GPIO0 Open-Drain mode enable

(Applicable only when i2c_en = 0 )

1314

1315

1316

1317

1318

1319

1320

Reserved

A4

A5

A6

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

GPIO1 input mode configuration

1321

1322

1323

1324

1325

Reserved

00: Floating (disconnected)

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

0: Pull-down

1: Pull-up

0: enable

1: disable

0: disable (Output = HiZ)

1: enable

(Applicable only when i2c_en = 0)

GPIO1 Pull-up or Pull-down resistor selection

1326

1327

1328

GPIO1 Pull-up or Pull-down mode selection

GPIO1 I²C fast mode plus enable

1329

GPIO1 Open-Drain mode enable

1330

1331

1332

1333

1334

1335

Reserved

Datasheet

16-Jul-2021

Revision 2.0

160 of 191

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SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1336

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

00: 1x Push-Pull

01: 2x Push-Pull

10: 1x Open-Drain pull down

11: 2x Open-Drain pull down

GPIO2 input mode configuration

1337

1338

1339

GPIO2 output mode configuration

Reserved

A7

1340

1341

00: Floating (disconnected)

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

GPIO2 Pull-up or Pull-down resistor selection

1342

0: Pull-down

1: Pull-up

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

00: 1x Push-Pull

01: 2x Push-Pull

10: 1x Open-Drain pull down

11: 2x Open-Drain pull down

1343

1344

GPIO2 Pull-up or Pull-down mode selection

GPIO3 input mode configuration

1345

1346

1347

GPIO3 output mode configuration

Reserved

A8

1348

1349

00: Floating (disconnected)

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

GPIO3 Pull-up or Pull-down resistor selection

1350

0: Pull-down

1: Pull-up

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

00: 1x Push-Pull

01: 2x Push-Pull

10: 1x Open-Drain pull down

11: 2x Open-Drain pull down

1351

1352

GPIO3 Pull-up or Pull-down mode selection

GPIO4 input mode configuration

1353

1354

1355

GPIO4 output mode configuration

Reserved

A9

1356

1357

00: Floating (disconnected)

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

0: Pull-down

1: Pull-up

GPIO4 Pull-up or Pull-down resistor selection

1358

1359

GPIO4 Pull-up or Pull-down mode selection

Datasheet

16-Jul-2021

Revision 2.0

161 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1360

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

00: 1x Push-Pull

01: 2x Push-Pull

10: 1x Open-Drain pull down

11: 2x Open-Drain pull down

GPIO5 input mode configuration

1361

1362

1363

GPIO5 output mode configuration

Reserved

AA

1364

1365

00: Floating (disconnected)

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

GPIO5 Pull-up or Pull-down resistor selection

1366

0: Pull-down

1: Pull-up

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

00: 1x Push-Pull

01: 2x Push-Pull

10: 1x Open-Drain pull down

11: 2x Open-Drain pull down

1367

1368

GPIO5 Pull-up or Pull-down mode selection

GPIO6 input mode configuration

1369

1370

1371

GPIO6 output mode configuration

Reserved

AB

1372

1373

00: Floating (disconnected)

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

GPIO6 Pull-up or Pull-down resistor selection

1374

0: Pull-down

1: Pull-up

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

00: 1x Push-Pull

01: 2x Push-Pull

10: 1x Open-Drain pull down

11: 2x Open-Drain pull down

1375

1376

GPIO6 Pull-up or Pull-down mode selection

GPIO7 input mode configuration

1377

1378

1379

GPIO7 output mode configuration

Reserved

AC

1380

1381

00: Floating (disconnected)

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

0: Pull-down

1: Pull-up

GPIO7 Pull-up or Pull-down resistor selection

1382

1383

GPIO7 Pull-up or Pull-down mode selection

Datasheet

16-Jul-2021

Revision 2.0

162 of 191

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SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1384

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

00: 1x Push-Pull

01: 2x Push-Pull

10: 1x Open-Drain pull down

11: 2x Open-Drain pull down

GPIO8 input mode configuration

1385

1386

1387

GPIO8 output mode configuration

Reserved

AD

1388

1389

00: Floating (disconnected)

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

GPIO8 Pull-up or Pull-down resistor selection

1390

0: Pull-down

1: Pull-up

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

00: 1x Push-Pull

01: 2x Push-Pull

10: 1x Open-Drain pull down

11: 2x Open-Drain pull down

1391

1392

GPIO8 Pull-up or Pull-down mode selection

GPIO9 input mode configuration

1393

1394

1395

GPIO9 output mode configuration

Reserved

AE

1396

1397

00: Floating (disconnected)

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

GPIO9 Pull-up or Pull-down resistor selection

1398

0: Pull-down

1: Pull-up

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

00: 1x Push-Pull

01: 2x Push-Pull

10: 1x Open-Drain pull down

11: 2x Open-Drain pull down

1399

1400

GPIO9 Pull-up or Pull-down mode selection

GPIO10 input mode configuration

1401

1402

1403

GPIO10 output mode configuration

Reserved

AF

1404

1405

00: Floating (disconnected)

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

0: Pull-down

1: Pull-up

GPIO10 Pull-up or Pull-down resistor selection

1406

1407

GPIO10 Pull-up or Pull-down mode selection

Datasheet

16-Jul-2021

Revision 2.0

163 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1408

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

00: 1x Push-Pull

01: 2x Push-Pull

10: 1x Open-Drain pull down

11: 2x Open-Drain pull down

GPIO11 input mode configuration

1409

1410

1411

GPIO11 output mode configuration

Reserved

B0

1412

1413

00: Floating (disconnected)

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

GPIO11 Pull-up or Pull-down resistor selection

1414

0: Pull-down

1: Pull-up

00: Digital in without Schmitt Trigger

01: Digital in with Schmitt Trigger

10: Low voltage digital in mode

11: Reserved/Analog IO

00: 1x Push-Pull

01: 2x Push-Pull

10: 1x Open-Drain pull down

11: 2x Open-Drain pull down

1415

1416

GPIO11 Pull-up or Pull-down mode selection

GPIO12 input mode configuration

1417

1418

1419

GPIO12 output mode configuration

Reserved

B1

1420

1421

00: Floating (disconnected)

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

GPIO12 Pull-up or Pull-down resistor selection

1422

0: Pull-down

1: Pull-up

0: Turn on I2C open drain fast

1: Turn on I2C open drain slow

1423

1424

1425

GPIO12 Pull-up or Pull-down mode selection

Turn on I²C open drain fast or slow

0: Disable

IO Latching Enable During Host Write

1: Pad digital output latches at previous state

0: Disable

1: Enable

1426

1427

Fast pull up or pull down during power up

Pull pad to high when gpi_from_pad is high

(During power-up, GPIO Pull-up/down resistance will switch

to 2.6 kΩ initially and then it will switch to normal setting value)

0: Disable

1: Enable

B2

1428

1429

1430

1431

Reserved

0: Non-inverted

1: Inverted

00: Rising Edge Detector

01: Falling Edge Detector

10: Both Edge Detector

11: Both Edge Delay

1432

1433

Filter/Edge Detector Output Polarity

Edge Detect Mode

1434

B3

0: Filter

1: Edge Detect

1435

Edge Detect Filter Function Select

1436

1437

1438

1439

Reserved

Datasheet

16-Jul-2021

Revision 2.0

164 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1440

00: Rising Edge Detector

01: Falling Edge Detector

10: Both Edge Detector

11: Both Edge Delay

00: 125 ns

01: 250 ns

10: 375 ns

11: 500 ns

Edge Detect Mode

1441

1442

1443

Programmable Delay Selection

B4

1444

1445

1446

1447

Reserved

0: Use OSC

1: Use External Clock Source

0: Matrix Down

1: Matrix On

0: Auto on by Multi-Func CNT

1: Always On

0: Disable

1: Enable

0: Disable

1: Enable

00: DIV1

01: DIV2

10: DIV4

11: DIV8

1448

1449

1450

1451

OSC0 Divider Clock Source

OSC0 Matrix power down or on selection

OSC0 turn on by register

OSC0 Divider Output0 control by matrix

OSC0 Divider Output1 control by matrix

B5

1452

1453

OSC0 Pre-Divider Selection

1454

1455

1456

Reserved

0: Use OSC

1: Use External Clock Source

OSC1 Divider Clock Source

0: Matrix Down

1: Matrix On

0: Auto on by Multi-Func CNT

1: Always On

0: Disable

1: Enable

1457

1458

1459

OSC1 Matrix power down or on selection

OSC1 turn on by register

B6

OSC1 Divider Output0 control by matrix

1460

1461

000: DIV1

001: DIV2

010: DIV4

011: DIV8

100: DIV12

101: DIV24

110: DIV48

111: DIV96

OSC1 Pre-Divider Selection

Reserved

B6

1462

1463

Datasheet

16-Jul-2021

Revision 2.0

165 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1464

1465

000: DIV1

001: DIV2

010: DIV3

011: DIV4

100: DIV8

101: DIV12

110: DIV24

111: DIV64

OSC0 OUT0 Post-Divider Selection

Reserved

1466

1467

1468

1469

B7

000: DIV1

001: DIV2

010: DIV3

011: DIV4

100: DIV8

101: DIV12

110: DIV24

111: DIV64

OSC0 OUT1 Post-Divider Selection

Reserved

1470

1471

1472

1473

000: DIV1

001: DIV2

010: DIV3

011: DIV4

100: DIV8

101: DIV12

110: DIV24

111: DIV64

OSC1 OUT0 Post-Divider Selection

1474

B8

1475

1476

1477

1478

1479

Reserved

0: no delay

1: 100 ns delay

1480

OSC1 Enable 100 ns delay

0: Enable

1: Disable

1481

1482

OSC1 Enable startup 1st edge function

00: OSC will have 1-2 output pulses after Power Down

01: When OSC Power Down signal comes, OSC generates

full output pulse and then stops

10: When OSC Power Down signal comes, OSC output goes

low immediately

11: When OSC Power Down signal comes, OSC output goes

low immediately

B9

OSC1 output synchronous type select

1483

0: 500 µs delay

1: no delay

1484

OSC0 Enable 500 µs delay

1485

1486

Reserved

00: OSC will have 1-2 output pulses after Power Down

01: When OSC Power Down signal comes, OSC generates

full output pulse and then stops

B9

10: When OSC Power Down signal comes, OSC output goes

low immediately

OSC0 output synchronous type select

1487

11: When OSC Power Down signal comes, OSC output goes

low immediately

Datasheet

16-Jul-2021

Revision 2.0

166 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1488

1489

1490

1491

1492

000000: 25 mV

000001: 50 mV

011110: 775 mV

011111: 800 mV

100000: 825 mV

100001: 850 mV

100010~111110: Reserved

111111: external Vref

(Default 25 mV)

ACMP0 Vref Selection

BA

1493

1494

00: 0 mV

01: 25 mV

10: 50 mV

11: 150 mV

ACMP0 Hysteresis selection

1495

1496

1497

1498

Reserved

00: 1x

01: 0.5x

ACMPH0 Input Divider

10: Reserved

11: Reserved

1499

BB

0: Do not pull

1: Pull to V_DD

(Pull positive input up to V_DD

1500

ACMP0 Input tie to V_DDEnable

)

1501

1502

1503

1504

1505

1506

1507

1508

Reserved

000000: 25 mV

000001: 50 mV

011110: 775 mV

011111: 800 mV

100000: 825 mV

100001: 850 mV

100010~111110: Reserved

111111: external Vref

(Default: 25 mV)

BC

ACMPH1 Vref Selection

1509

1510

00: 0 mV

01: 25 mV

10: 50 mV

11: 150 mV

ACMP1 Hysteresis selection

1511

1512

1513

1514

Reserved

00: 1x

01: 0.5x

ACMPH1 Input Divider

10: Reserved

11: Reserved

1515

0: Do not pull

1: Pull to input of ACMPH0

(Pull positive input of ACMPH1 as the input of ACMPH0)

0: Vinn of ACMPH1 from Pin

1: Vinn of ACMPH1 from Vinn of ACMPH0

BD

1516

1517

ACMPH1 Input tie to ACMPH0 Enable

ACMP1 External Vref Select

1518

1519

Reserved

Datasheet

16-Jul-2021

Revision 2.0

167 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: Disable

1: Enable

0: Disable

1: Enable

0: Enable by reg_buf_en

1: Enable by tempsense_en

0: Disable and pass input voltage directly to output

1: Enable and apply UGB

0: Disable discharge PIN9, GPIO5

1: Enable discharge PIN9, GPIO5

00: Reserved (GND)

01: avref_acmph0

10: avref_acmph1

11: Tempsense Output

1520

1521

1522

1523

ACMP reference voltage generator enable

ACMP Buffer Enable

ACMP Buffer Enable Selection

ACMP Unit-gain-buffer enable

ACMP Buffer Discharge

BE

1524

1525

ACMP Buffer Select

1526

1527

1528

Reserved

0: Do not select tempsense output as buffer out

1: Select tempsense output as buffer out

ACMP Temp Sensor Enable

0: Enable by tempsense_en

1529

1530

1531

1532

ACMP Temp Sensor Enable Select

Pass buffer output to ACMPH1 input

Bandgap control

1: Enable by tempsense_en_matrix

0: Do not pass

1: Pass

0: BG always wake, non sleep

1: Sleep when w/s sleep

0: No change in ibias_en

1: Force ibias_en equal to bg_en

BF

Option of Ibias enable

1533

1534

1535

Reserved

0: With hysteresis 0.1V

1: without hysteresis

1536

V_DDdetector hysteresis selection

0: Enable BG Vref gen and ACMP at same time

1: Enable BG first. After BG_ok, enable Vrefgen;After BG_ok

and Vref_ok, enable ACMP

BG, Vref gen and ACMP wake up sequence se-

lection

1537

1538

1539

1540

1541

1542

1543

1544

1545

1546

1547

1548

1549

1550

1551

Reserved

C0

C1

Datasheet

16-Jul-2021

Revision 2.0

168 of 191

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SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1552

1553

1554

1555

1556

1557

1558

1559

1560

1561

1562

1563

1564

1565

1566

1567

1568

1569

1570

1571

1572

1573

1574

1575

1576

1577

1578

1579

1580

1581

1582

1583

1584

1585

1586

1587

1588

1589

1590

1591

1592

1593

1594

1595

1596

1597

1598

1599

C2

Reserved

C3

C4

C5

Reserved

C6

Reserved

C7

Reserved

Datasheet

16-Jul-2021

Revision 2.0

169 of 191

CFR0011-120-00

SLG47502/03

Preliminary

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1600

1601

1602

1603

1604

1605

1606

1607

1608

1609

1610

1611

1612

1613

1614

1615

1616

1617

1618

1619

1620

1621

1622

1623

1624

1625

1626

1627

1628

1629

1630

1631

1632

1633

1634

1635

1636

1637

1638

1639

1640

1641

1642

1643

1644

1645

1646

1647

Reserved

C8

C9

CA

Reserved

CB

Reserved

CC

CD

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Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1648

1649

1650

1651

1652

1653

1654

1655

1656

1657

1658

1659

1660

1661

1662

1663

1664

1665

1666

1667

1668

1669

1670

1671

1672

1673

1674

1675

1676

1677

1678

1679

1680

1681

1682

1683

1684

1685

1686

1687

1688

1689

1690

1691

1692

1693

1694

1695

Reserved

CE

Reserved

CF

D0

D1

D2

D3

Reserved

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Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1696

1697

1698

1699

1700

1701

1702

1703

1704

1705

1706

1707

1708

1709

1710

1711

1712

1713

1714

1715

1716

1717

1718

1719

1720

Reserved

D4

Reserved

D5

Reserved

D6

Reserved

Registers Read Protection Register.

Valid only when PROTECT_EN is 1

00: 1K register data is unprotected for read

01: 1K register data is partly protected for read

10: 1K register data is fully protected for read

11: 1K register data is fully protected for read

Registers Write Protection Register.

Valid only when PROTECT_EN is 1

00: 1K register data is unprotected for write

01: 1K register data is partly protected for write

10: 1K register data is fully protected for write

11: 1K register data is fully protected for write

RPR

1721

1722

1723

D7

WPR

1724

1725

1726

1727

1728

1729

1730

1731

1732

1733

1734

1735

Reserved

D8

Reserved

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Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1736

1737

1738

1739

1740

1741

1742

1743

1744

1745

1746

1747

1748

1749

1750

1751

1752

1753

1754

1755

1756

1757

1758

1759

1760

1761

1762

1763

1764

1765

1766

1767

1768

1769

1770

1771

1772

1773

1774

1775

1776

1777

1778

1779

1780

1781

1782

1783

D9

Reserved

DA

DB

DC

DD

DE

Reserved

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Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1784

1785

1786

1787

1788

1789

1790

1791

1792

1793

1794

1795

1796

1797

1798

1799

1800

1801

1802

1803

1804

1805

1806

1807

1808

1809

1810

1811

1812

1813

1814

1815

1816

1817

1818

1819

1820

1821

1822

1823

1824

1825

1826

1827

1828

1829

1830

1831

Reserved

DF

E0

E1

E2

E3

E4

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Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1832

1833

1834

1835

1836

1837

1838

1839

1840

1841

1842

1843

1844

1845

1846

1847

1848

1849

1850

1851

1852

1853

1854

1855

1856

1857

1858

1859

1860

1861

1862

1863

1864

1865

1866

1867

1868

1869

1870

1871

1872

1873

1874

1875

1876

1877

1878

1879

Reserved

E5

E6

E7

E8

E9

EA

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Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1880

1881

1882

1883

1884

1885

1886

1887

1888

1889

1890

1891

1892

1893

1894

1895

1896

1897

1898

1899

1900

1901

1902

1903

1904

1905

1906

1907

1908

1909

1910

1911

1912

1913

1914

1915

1916

1917

1918

1919

1920

1921

1922

1923

1924

1925

1926

1927

Reserved

EB

EC

ED

EE

EF

F0

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Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1928

1929

1930

1931

1932

1933

1934

1935

1936

1937

1938

1939

1940

1941

1942

1943

1944

1945

1946

1947

1948

1949

1950

1951

1952

1953

Reserved

F1

F2

F3

1954

Reserved

1955

1956

1957

1958

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

Reserved

F4

F5

F6

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Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1976

1977

1978

1979

1980

1981

1982

1983

1984

1985

1986

1987

1988

1989

1990

1991

1992

1993

1994

1995

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

2019

2020

2021

2022

2023

Reserved

F7

F8

F9

FA

FB

FC

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Table 37: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

2024

2025

2026

2027

2028

2029

2030

2031

2032

2033

2034

2035

2036

2037

2038

2039

2040

2041

2042

2043

2044

2045

2046

2047

Reserved

FD

FE

FF

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18 Package Top Marking Definitions

18.1 STQFN 12L 1.6 MM X 1.6 MM X 0.55 MM 0.4P FC

PPP

WWR

NN

Part Code

Date Code +

Revision Code

Pin 1 Identifier

Serial Number Code

18.2 MSTQFN 16L 1.6 MM X 1.6 MM X 0.55 MM 0.4P

PPP

WWR

NN

Part Code

Date Code +

Revision Code

Pin 1 Identifier

Serial Number Code

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19 Package Information

19.1 PACKAGE OUTLINES FOR STQFN 12L 1.6 MM X 1.6 MM X 0.55 MM 0.4P FC PACKAGE

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Mixed-Signal Matrix

19.2 PACKAGE OUTLINES FOR MSTQFN 16L 1.6 MM X 1.6 MM X 0.55 MM 0.4P PACKAGE

Bottom View

Side View

Top View

Controlling Dimensions: mm

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19.3 MOISTURE SENSITIVITY LEVEL

The Moisture Sensitivity Level (MSL) is an indicator for the maximum allowable time period (floor lifetime) in which a moisture

sensitive plastic device, once removed from the dry bag, can be exposed to an environment with a specified maximum

temperature and a maximum relative humidity before the solder reflow process. The MSL classification is defined in Table 38.

For detailed information on MSL levels refer to the IPC/JEDEC standard J-STD-020, which can be downloaded from http://

www.jedec.org.

The <PACKAGE_NAME> package is qualified for MSL <n>.

Table 38: MSL Classification

MSL Level

Floor Lifetime

Conditions

MSL 4

MSL 3

MSL 2A

MSL 2

MSL 1

72 hours

168 hours

4 weeks

1 year

30 °C / 60 % RH

Unlimited

19.4 STQFN HANDLING

Be sure to handle STQFN package only in a clean, ESD-safe environment. Tweezers or vacuum pick-up tools are suitable for

handling. Do not handle STQFN package with fingers as this can contaminate the package pins and interface with solder reflow.

19.5 SOLDERING INFORMATION

Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can be downloaded from http://

www.jedec.org.

20 Ordering Information

The ordering number consists of the part number followed by a suffix indicating the packing method. For details and availability,

please consult Dialog Semiconductor’s customer support portal or your local sales representative.

Part Number

SLG47502V

Type

12-pin STQFN

SLG47502VTR

SLG47503M

SLG47503MTR

12-pin STQFN - Tape and Reel (3k units)

16-pin MSTQFN

16-pin MSTQFN - Tape and Reel (3k units)

20.1 TAPE AND REEL SPECIFICATIONS

Max Units

Leader (min)

Length

Trailer (min)

Length

Nominal

# of

Pins

Reel &

Hub Size

(mm)

Tape Part

Width Pitch

(mm) (mm)

Package Type

Package Size

(mm)

per Reel per Box

Pockets

(mm)

STQFN 12L

1.6 mm x 1.6 mm x

0.55 mm, 0.4P FCA

Green

12

1.6x1.6x0.55

3000

178/60

100

400

100

400

8

4

MSTQFN 16L

1.6 mm x 1.6 mm x

0.55 mm, 0.4P FCA

Green

16

400

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Mixed-Signal Matrix

20.2 CARRIER TAPE DRAWING AND DIMENSIONS

Index Hole Index Hole

PocketBTMPocketBTM Pocket IndexHole Pocket Index Hole

Tape

Width

(mm)

to Tape

Edge

(mm)

to Pocket

Center

(mm)

Length

(mm)

Width

(mm)

Depth

(mm)

Pitch

(mm)

Pitch Diameter

Package Type

(mm)

P1

(mm)

D0

A0

B0

K0

P0

E

F

W

STQFN 12L

1.6 mm x 1.6 mm x

1.80

0.70

4

1.5

1.75

3.5

8

0.55 mm, 0.4P FCA ±0.05 mm ±0.05 mm ±0.05 mm

Green

MSTQFN 16L

1.6 mm x 1.6 mm x

1.80

0.70

4

1.75

3.5

8

0.55 mm, 0.4P FCA ±0.05 mm ±0.05 mm ±0.05 mm

Green

Datasheet

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21 Layout Guidelines

21.1 STQFN 12L 1.6 MM X 1.6 MM X 0.55 MM 0.4P FC PACKAGE

Units: µm

Datasheet

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Mixed-Signal Matrix

21.2 MSTQFN 16L 1.6 MM X 1.6 MM X 0.55 MM 0.4P PACKAGE

Unit: µm

Datasheet

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Mixed-Signal Matrix

Glossary

A

ACK

Acknowledge bit

ACMP

ACMPH

ACMPL

Analog Comparator

Analog Comparator High Speed

Analog Comparator Low Power

B

BG

Bandgap

C

CLK

CMO

CNT

Clock

Connection matrix output

Counter

D

DFF

DLY

D Flip-Flop

Delay

E

ESD

EV

Electrostatic discharge

End Value

F

FSM

Finite State Machine

G

GPI

GPIO

GPO

General Purpose Input

General Purpose Input/Output

General Purpose Output

I

IN

IO

Input

Input/Output

L

LPF

LSB

LUT

Low Pass Filter

Least Significant Bit

Look Up Table

Datasheet

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Mixed-Signal Matrix

LV

Low Voltage

M

MSB

MUX

Most Significant Bit

Multiplexer

N

NPR

nRST

NVM

Non-Volatile Memory Read/Write/Erase Protection

Reset

Non-Volatile Memory

O

OD

Open-Drain

OE

Output Enable

Oscillator

OSC

OTP

OUT

One Time Programmable

Output

P

PD

Power-down

PGen

POR

PP

Pattern Generator

Power-On Reset

Push-Pull

PWR

P DLY

Power

Programmable Delay

R

R/W

Read/Write

S

SCL

SDA

SLA

SMT

SV

I²C Clock Input

I²C Data Input/Output

Slave Address

With Schmitt Trigger

nSET Value

T

TS

Temperature Sensor

Datasheet

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V

Vref

Voltage Reference

W

WOSMT

WS

Without Schmitt Trigger

Wake and Sleep Controller

Datasheet

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Revision History

Revision

Date

Description

2.0

16-Jul-2021

Preliminary version

Datasheet

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Status Definitions

Revision Datasheet Status

Product Status

Definition

1.<n>

Target

Development

This datasheet contains the design specifications for product development.

Specifications may change in any manner without notice.

2.<n>

Preliminary

Qualification

Production

This datasheet contains the specifications and preliminary characterization

data for products in pre-production. Specifications may be changed at any

time without notice in order to improve the design.

3.<n>

4.<n>

Final

This datasheet contains the final specifications for products in volume

production. The specifications may be changed at any time in order to

improve the design, manufacturing and supply. Major specification

changes are communicated via Customer Product Notifications. Datasheet

changes are communicated via www.dialog-semiconductor.com.

Obsolete

Archived

This datasheet contains the specifications for discontinued products. The

information is provided for reference only.

Disclaimer

Unless otherwise agreed in writing, the Dialog Semiconductor products (and any associated software) referred to in this document are not designed, authorized or warranted

to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Dialog Semiconductor product (or

associated software) can reasonably be expected to result in personal injury, death or severe property or environmental damage. Dialog Semiconductor and its suppliers

accept no liability for inclusion and/or use of Dialog Semiconductor products (and any associated software) in such equipment or applications and therefore such inclusion

and/or use is at the customer's own risk.

Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or warranties, express or implied, as

to the accuracy or completeness of such information. Dialog Semiconductor furthermore takes no responsibility whatsoever for the content in this document if provided by any

information source outside of Dialog Semiconductor.

Dialog Semiconductor reserves the right to change without notice the information published in this document, including, without limitation, the specification and the design of

the related semiconductor products, software and applications. Notwithstanding the foregoing, for any automotive grade version of the device, Dialog Semiconductor

reserves the right to change the information published in this document, including, without limitation, the specification and the design of the related semiconductor products,

software and applications, in accordance with its standard automotive change notification process.

Applications, software, and semiconductor products described in this document are for illustrative purposes only. Dialog Semiconductor makes no representation or warranty

that such applications, software and semiconductor products will be suitable for the specified use without further testing or modification. Unless otherwise agreed in writing,

such testing or modification is the sole responsibility of the customer and Dialog Semiconductor excludes all liability in this respect.

Nothing in this document may be construed as a license for customer to use the Dialog Semiconductor products, software and applications referred to in this document. Such

license must be separately sought by customer with Dialog Semiconductor.

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of Sale, available on the company website (www.dialog-semiconductor.com) unless otherwise stated.

Dialog, Dialog Semiconductor and the Dialog logo are trademarks of Dialog Semiconductor Plc or its subsidiaries. All other product or service names and marks are

the property of their respective owners.

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Dialog Semiconductor's suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction

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Datasheet

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型号：	SLG47502
厂家：	Dialog Semiconductor
描述：	Low Voltage GreenPAK Programmable Mixed-Signal Matrix
文件：	总191页 (文件大小：2867K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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