SLG55022-200030VTR [DIALOG]

GreenFETTM High Voltage Gate Driver;


型号：	SLG55022-200030VTR
厂家：	Dialog Semiconductor
描述：	GreenFETTM High Voltage Gate Driver 栅
文件：	总9页 (文件大小：256K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SLG55022-200030

GreenFET High Voltage Gate Driver

Features

Pin Configuration

•

12V Power supply

Drain Voltage Range 1.0V to 20V

Internal Gate Voltage Charge Pump

Controlled Turn on Delay

VCC

GND

Controlled Load Discharge Rate

Controlled Turn on Slew Rate

2mm x 2mm TDFN-8 Package

Pb-Free / Halogen-Free / RoHS compliant

8-pin TDFN

(Top View)

Applications

•

Power Rail Switches

Hot Plugging Applications

Soft Switching

Personal computers and Servers

Data Communications Equipment

•

Block Diagram

_CC= 12V

V_D= 20V Max

Q-PUMP

Timing & Logic

Discharge

V_S

Load

GND

Datasheet

10-Jul-2018

Revision 1.03

Page 1 of 9

@ 2018 Dialog Semiconductor

CFR0011-120-01

SLG55022-200030

GreenFET High Voltage Gate Driver

Pin Description

Pin #

VCC

GND

Pin Name

Type

Power

Input

Pin Description

Supply Voltage

CMOS Logic Level. High True

No Connect.

GND

Input

Output

Ground.

FET Drain Connection

Source Connection

FET Gate Drive

Output CMOS Open Drain - Power Good, indicates external FET fully on. Pull-up resistor

greater than 300k recommended.

Output

Overview

The SLG55022 N-Channel FET Gate Driver is used for controlling a delayed turn on and ramping slew rate of the source voltage

on N-Channel FET switches from a CMOS logic level input. Intended as a supporting control element for switched voltage rails

in energy efficient, advanced power management systems, the SLG55022 also integrates circuits to discharge opened switched

voltage rails. The gate driver is available in a variety of configurations supporting a range of turn-on slew rates from 0.80V/ms

up to 4V/ms which, depending on load supplying source voltages in the range of 1.0V to 20V results in ramp times from 200s

to over 20ms(see Application Section). Delays until the ramp begins are source voltage independent and range from 250s to

5ms. A power good condition is output to indicate that the ramp-up slew of the source voltage is finished. Additionally, an internal

discharge circuit provides a controlled path to remove charge from open power rails. The SLG55022 gate drive is packaged in

an 8 pin DFN package.

When used with external N-Channel FETs, the SLG55022 supports low transient, energy efficient switching of high current loads

at source voltages ranging from 1.0V to 20V.

Ordering Information

Part Number

Type

TDFN-8

SLG55022-200030V

SLG55022-200030VTR

TDFN-8 - Tape and Reel (3k units)

Datasheet

10-Jul-2018

Revision 1.03

Page 2 of 9

CFR0011-120-01

SLG55022-200030

GreenFET High Voltage Gate Driver

Absolute Maximum Ratings

Parameter

Min.

-0.3

-1.0

-65

Max.

40.0

6.5

Unit

V_Dor V_Sto GND

Voltage at Logic Input pins

Current at input pin

1.0

°C

Storage temperature range

Junction temperature

ESD Human Body Model

ESD Machine Model

Moisture Sensitivity Level

150

2000

200

Electrical Characteristics

T_A= -10 °C to 75 °C

Parameter Description

Conditions

Min.

11.5

0.25

Typ.

12.0

Max.

12.5

Unit

V_CC

Supply Voltage

T_{VCC_RAMP}V_CCRamp-up Rate

See Note 1

V/ms

V_Gnot ramping

FET = ON

A

I_q

Quiescent Current

V_Gnot ramping

FET = OFF

0.1

V_D

V_GS

FET Drain Voltage

1.0

8.0

500

11.5

Gate-Source Voltage

FET Gate Capacitance

Ramp Delay Range

FET Turn on Slew Rate

C_G

8000

750

2.8

T_DELAY

T_SLEW

1.5ms Default, 500s step

500

2.0

s

1.2

V/ms

Nominal discharge time of ~100ms

10mA max rate

I_DISCHARGEInternal Discharge Resistor

180

300

420



V_IH

V_IL

HIGH-level input voltage

LOW-level Input voltage

HIGH-level output voltage

ON (200mV Hysteresis)

PG Open Drain

2.4

5.5

0.4

5.5

V_OH

I_{OL_LOGIC}Logic LOW level output

PG Sink Current

V_IH= 3.3V

A

I_IH

HIGH-level input current

<1.0

Notes:

1. If T_{VCC_RAMP}> 5V/ms and ON is asserted, Gate charging will begin after 1ms.

Datasheet

10-Jul-2018

Revision 1.03

Page 3 of 9

CFR0011-120-01

SLG55022-200030

GreenFET High Voltage Gate Driver

Device Operation

In a typical application, de-asserting ON (low) turns off the external power N-FET. When the FET is turned off, the voltage at the

load is discharged through a resistor (300 Ohms) internal to the SLG55022. When ON is asserted (high), the device will not begin

driving the gate of the external power FET unless the voltage at the drain of the device is at or above 0.8V (e.g. V_D 0.8) to

prevent a ‘shootthrough’ situation to the FET’s source load. Gate voltage is not applied to the gate of the external power N-FET

after DLY_t then the gate source (Vgs) voltage is ramped up to 11.5V above the source voltage V_Sat a slew rate determined by

the internal slew rate control element internal to the SLG55022. Monotonic rise of Vs is maintained even as ID increases dramat-

ically after the load device turn on threshold voltage is reached. After the source voltage has ramped up to its maximum steady

state value, the Open Drain PG (Power Good) signal is asserted. PG may be used as the ON control of a second SLG55022

thereby providing power on sequence control of a number of switched power rails, or used in a ‘wired and’ with other PG signals

to indicate all switched power rails are in a power good condition.

The waveforms shown illustrate the monotonic rise of the source voltage of a FET as gate voltage is controlled to accommodate

for variations in load current as the voltage is applied.

Datasheet

10-Jul-2018

Revision 1.03

Page 4 of 9

CFR0011-120-01

SLG55022-200030

GreenFET High Voltage Gate Driver

Delay Time and Slew Rates

The two components of controlling the application of FET source voltage to the load are a fixed time delay before beginning turn

on of the FET (DLY_t below) and the Slew Time of the source voltage (Slew_t below).

Discharge_t

Slew_t

DLY_t

Having control over the Slew Rate of the FET’s source voltage as the FET is turning on is important in controlling dv/dt caused

transients. A power FET, for example, switching a 5V rail which has a total of 500F of decoupling, fully on in 10s will generate

a 250A current surge which is very undesirable. If the FET turn on time can be stretched to 1ms, the current surge to charge the

decoupling capacitors is reduced to 2.5A. The SLG55022 controls slew rate of a FET’s source voltage as it is turned on. A range

of slew rates are available as device order options. Obviously the time to fully slew the source voltage to fully on is a function of

the drain supply voltage. The table and graph below shows source voltage ramp times for various slew rates supported by the

SLG55022 for a range of specific source voltages.

Ramp Times (ms) vs. Source Voltages (V)

Slew Rates

(V/ms)

1.1V

1.5V

1.8V

3.3V

5.0V

12V

18.5V

2.00

0.55

0.75

0.90

1.65

2.50

6.00

9.25

* The minimum time that ON can be de-asserted between switching cycles is 100ms.

Datasheet

10-Jul-2018

Revision 1.03

Page 5 of 9

CFR0011-120-01

SLG55022-200030

GreenFET High Voltage Gate Driver

Ramp Times (ms) vs. Source Voltage for Various Slew Rates (v/ms)

2.00

1.1

1.5

1.8

3.3

5.0

12.0

18.5

Source Voltage

Package Top Marking System Definition

Part ID

Assembly Code

Datecode

Lot

Revision

XX – Part ID Field: identifies the specific device configuration

– Assembly Code Field: Assembly Location of the device.

DD – Date Code Field: Coded date of manufacture

– Lot Code: Designates Lot #

– Revision Code: Device Revision

Datasheet

10-Jul-2018

Revision 1.03

Page 6 of 9

CFR0011-120-01

SLG55022-200030

GreenFET High Voltage Gate Driver

Package Drawing and Dimensions

8 Lead TDFN Package

Datasheet

10-Jul-2018

Revision 1.03

Page 7 of 9

CFR0011-120-01

SLG55022-200030

GreenFET High Voltage Gate Driver

Tape and Reel Specifications

Max Units

Nominal

Leader (min)

Length

Trailer (min)

Reel &

Hub Size

[mm]

Tape

Width Pitch

[mm]

Part

Package # of

Package Size

Length

[mm]

Type

Pins

per Reel per Box

3,000 3,000

Pockets

[mm]

TDFN 8L

Green

2 x 2 x 0.75

178 / 60

100

400

100

400

Carrier Tape Drawing and Dimensions

Index Hole Index Hole

PocketBTMPocketBTM Pocket Index Hole Pocket Index Hole

to Tape

Edge

to Pocket Tape Width

Center

Package

Type

Length

Width

Depth

Pitch

Diameter

TDFN 8L

Green

2.3

1.05

1.55

1.75

3.5

Section Y-Y

Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.00 mm³(nominal). More

information can be found at www.jedec.org.

Datasheet

10-Jul-2018

Revision 1.03

Page 8 of 9

CFR0011-120-01

SLG55022-200030

GreenFET High Voltage Gate Driver

Revision History

Date

Version

Change

7/10/2018

1.03

Updated style and formatting

Added Pb-Free/Halogen Free/RoHS compliance

Added MSL

7/29/2017

1.02

Datasheet

10-Jul-2018

Revision 1.03

Page 9 of 9

CFR0011-120-01

SLG55022-200030VTR [DIALOG]

相关型号：

UL1042

ZXFV201

ZXFV201N14

ZXFV201N14TA

ZXFV201N14TC

ZXFV202E5

ZXFV202N8

ZXFV203N14

ZXFV301N16(1)

ZXFV302N16

ZXFV4089

ZXFV4089N8