SLG55221-120010V [DIALOG]

2 Rail GreenFETTM High Voltage Gate Driver;


型号：	SLG55221-120010V
厂家：	Dialog Semiconductor
描述：	2 Rail GreenFETTM High Voltage Gate Driver 栅
文件：	总9页 (文件大小：253K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SLG55221-120010

SLG55220-120010

2 Rail GreenFET High Voltage Gate Driver

Features

Pin Configuration

•

5V Power supply

VCC

Drain Voltage Range 1.0V to 20V

Internal Gate Voltage Charge Pump

Controlled Load Discharge Rate

Controlled Turn on Slew Rate

TDFN-8 Package

G1/G2

S/DIS1

DIS2

GND

Thermal Pad

connected to GND

TDFN-8

(Top View)

Applications

Environmental

•

Power Supply Sequencing with ramp/delay/discharge

control

•

Pb-Free / RoHS compliant

Halogen Free

•

Power Rail “Soft” Switch

Hot Plugging Applications

Low Transient Load Switching

Target Application Products

•

Notebook & Netbook Battery Packs

Notebook & Netbook Sleep Mode Circuits

Server Load Switches

•

Replace high cost P-channel MOSFETs with lower cost

N-channel MOSFETs

Gaming Sleep Mode Power Switches

Communications Power Switches

Block Diagram

V_D= 20V Max

VCC = 5V

3.3V

Q-PUMP

G1/G2

FET1

FET2

Timing & Logic

DIS2

Discharge

S/DIS1

LOAD1

LOAD2

GND

The highest V_Dbeing switched must be at FET1 and pin 5 of

the SLG55221 and SLG55220

SLG55221

V_Gis pumped to V_D+ 8V

SLG55220

V_Gis pumped to V_D+ 4V min

Datasheet

10-Jul-2018

Revision 1.01

Page 1 of 9

@ 2018 Dialog Semiconductor

CFR0011-120-01

SLG55221-120010

SLG55220-120010

2 Rail GreenFET High Voltage Gate Driver

Pin Description

Pin #

Pin Name

Type

Power

Input

Pin Description

VCC

Supply Voltage

DIS2

GND

CMOS Logic Level. See SLG55251 for Control Input ON# instead of ON.

Discharge Connection for Load2

Output

GND

Ground

Input

FET Drain Connection (Connect to FET with highest V_Dvoltage)

Source Connection,

Discharge Connection for Load1

S/DIS1

Input/Output

G1/G2

Output

FET Gate Drive for FET1, FET2

CMOS Power Good Signal

Exposed

Bottom

Pad

GND

Ground

Overview

The SLG55221/220 N-Channel FET Gate Drivers are used for controlling and ramping slew rate of the source voltage on N-Chan-

nel FET switches from a CMOS logic level input. Intended as a supporting control element for switched voltage rails in energy

efficient, advanced power management systems, the SLG55221/220 also integrates circuits to discharge opened switched volt-

age rails. The gate driver is available in a variety of configurations supporting a range of turn-on slew rates from 0.80V/ms up to

2V/ms which, depending on load supplying source voltages in the range of 1.0V to 20V results in ramp times from 200s to over

20ms (see Application Section). Additionally, an internal discharge circuit provides a controlled path to remove charge from open

power rails. The SLG55221/220 gate drive is packaged in an 8 pin DFN package. A power good (PG) signal is asserted when

FET1 is fully ON.

When used with external N-Channel FETs, the SLG55221 supports low transient, energy efficient switching of high current loads

at source voltages ranging from 1.0V to 20V.

A ‘Low Drive’ version of the device, is available to support applications where FET Vgs cannot exceed 8V.

Ordering Information

Ramp Slew

Rate

Discharge

Resistor

(ohms)

Delay Time

(ms)

Part Number

(Volts/ms)

Package Type

TDFN-8

SLG55220 -120010V

SLG55221-120010V

SLG55220 -120010VTR

SLG55221-120010VTR

1.30

0.50

200

TDFN-8

TDFN-8 - Tape and Reel (3k units)

Datasheet

10-Jul-2018

Revision 1.01

Page 2 of 9

CFR0011-120-01

SLG55221-120010

SLG55220-120010

2 Rail GreenFET High Voltage Gate Driver

Absolute Maximum Ratings

Parameter

Min.

-0.3

-1.0

-65

-55

Max.

40.0

6.5

Unit

V_Dor V_Sto GND

Voltage at Logic Input pins

Current at input pin

1.0

°C

Storage temperature range

Operating temperature range

Junction temperature

ESD Human Body Model

ESD Machine Model

150

125

150

2000

200

Electrical Characteristics

T_A= -10 °C to 75 °C

Parameter Description

Conditions

Min.

4.75

0.25

Typ.

5.0

Max.

5.25

Unit

V_CC

Supply Voltage

T_{VCC_RAMP}V_CCRamp-up Rate

See Note 1

V/ms

V_Gnot ramping

FET = ON

A

V_Gnot ramping

FET = OFF

I_q

Quiescent Current

0.1

600

V_Gramping

FET = OFF to ON

1500

SLG55220

SLG55221

SLG55220

SLG55221

0.95

1.0

5.25

V_D

FET Drain Voltage

4.0

4.7

6.0

V_GS

Gate-Source Voltage

8.0

C_G

FET Gate Capacitance

Ramp Delay Range

500

0.25

0.91

18000

0.75

1.69

V/ms

T_DELAY

T_SLEW

0.5

1.30

FET Turn on Slew Rate

Nominal discharge time of ~100ms

10mA max rate

I_DISCHARGEInternal Discharge Resistor

140

200

260



V_IH

V_IL

HIGH-level input voltage

LOW-level Input voltage

HIGH-level output voltage

LOW-level output voltage

ON (200mV Hysteresis)

2.4

5.5

0.4

ON (200mV Hysteresis)

V_OH

V_OL

4.0

0.7

I_{OL_LOGIC}Logic LOW level output

PG Sink Current

A

I_{G_OL}

I_{G_OH}

I_{D_IH}

I_{S_IH}

Gate Drive Sink Current

Gate Drive Source Current

Drain Pin Current

400

V_D= 20V in Standby

V_S= 20V

<1.0

Source Pin Current Quiesent

Notes:

1. If T_{VCC_RAMP}> 5V/ms and ON is asserted, Gate charging will begin after 1ms.

Datasheet

10-Jul-2018

Revision 1.01

Page 3 of 9

CFR0011-120-01

SLG55221-120010

SLG55220-120010

2 Rail GreenFET High Voltage Gate Driver

Application Example

In a typical application, de-asserting ON (low) or turns off the external power N-FET. When the FET is turned off, the voltage at

the load is discharged through a resistor (400 Ohms to 1000 Ohms or Open) internal to the SLG55221/220 with the discharge

current limited to a maximum of 10mA. When ON is asserted (high), gate voltage is not applied to the gate of the external power

N-FET until after DLY_t then the gate source (Vgs) voltage is ramped up to 11.5V above the source voltage V_Sat a slew rate

determined by the internal slew rate control element internal to the SLG55221/220. Monotonic rise of Vs is maintained even as

ID increases dramatically after the load device turn on threshold voltage is reached. After the source voltage has ramped up to

its maximum steady state value, PG (Power Good) is asserted. PG may be used as the ON control of a second SLG55221/220

thereby providing power on sequence control of a number of switched power rails.

The devices will not operate if Vcc is below 3.5V and will not operate until V_Dreaches 0.8V.

The waveforms shown illustrate the monotonic rise of the source voltage of a FET as gate voltage is controlled to accommodate

for variations in load current as the voltage is applied.

Datasheet

10-Jul-2018

Revision 1.01

Page 4 of 9

CFR0011-120-01

SLG55221-120010

SLG55220-120010

2 Rail GreenFET High Voltage Gate Driver

Delay Time and Slew Rates

The two components of controlling the application of FET source voltage to the load are a fixed time delay before beginning turn

on of the FET (DLY_t below) and the Slew Time of the source voltage (Slew_t below). The Delay Time before gate voltage to the

FET is applied is 250s independent of FET drain voltage, source voltage or SLG55221/220 supply voltage.

Discharge_t

Slew_t

DLY_t

Having control over the Slew Rate of the FET’s source voltage as the FET is turning on is important in controlling dv/dt caused

transients. A power FET, for example, switching a 5V rail which has a total of 500F of decoupling, fully on in 10s will generate

a 250A current surge which is very undesirable. If the FET turn on time can be stretched to 1ms, the current surge to charge the

decoupling capacitors is reduced to 2.5A. The SLG55221/220 controls slew rate of a FET’s source voltage as it is turned on. A

range of slew rates are available as device order options. Obviously the time to fully slew the source voltage to fully on is a

function of the drain supply voltage. The table and graph below shows source voltage ramp times for various slew rates supported

by the SLG55221/220 for a range of specific source voltages.

Ramp Times (ms) vs. Source Voltages (V)

Slew Rates

(V/ms)

1.1V

1.5V

1.8V

3.3V

5.0V

1.30

0.83

1.13

1.35

2.48

3.75

* The minimum time that ON can be de-asserted between switching cycles is 100ms.

Datasheet

10-Jul-2018

Revision 1.01

Page 5 of 9

CFR0011-120-01

SLG55221-120010

SLG55220-120010

2 Rail GreenFET High Voltage Gate Driver

Package Top Marking System Definition

Part ID

Assembly Code

Datecode

Lot

Revision

XX – Part ID Field: identifies the specific device configuration

– Assembly Code Field: Assembly Location of the device.

DD – Date Code Field: Coded date of manufacture

– Lot Code: Designates Lot #

– Revision Code: Device Revision

Datasheet

10-Jul-2018

Revision 1.01

Page 6 of 9

CFR0011-120-01

SLG55221-120010

SLG55220-120010

2 Rail GreenFET High Voltage Gate Driver

Package Drawing and Dimensions

8 Lead TDFN Package

Datasheet

10-Jul-2018

Revision 1.01

Page 7 of 9

CFR0011-120-01

SLG55221-120010

SLG55220-120010

2 Rail GreenFET High Voltage Gate Driver

Tape and Reel Specifications

Max Units

Leader (min)

Length

Trailer (min)

Nominal

Package Size

[mm]

Reel &

Hub Size

[mm]

Tape

Width Pitch

[mm]

Part

Package # of

Length

[mm]

Type

Pins

per Reel per Box

3,000 3,000

Pockets

[mm]

TDFN 8L

Green

2 x 2 x 0.75

178 / 60

100

400

100

400

Carrier Tape Drawing and Dimensions

Index Hole Index Hole

PocketBTMPocketBTM Pocket Index Hole Pocket Index Hole

to Tape

Edge

to Pocket Tape Width

Center

Package

Type

Length

Width

Depth

Pitch

Diameter

TDFN 8L

Green

2.3

1.05

1.55

1.75

3.5

Section Y-Y

Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.00 mm³(nominal). More

information can be found at www.jedec.org.

Datasheet

10-Jul-2018

Revision 1.01

Page 8 of 9

CFR0011-120-01

SLG55221-120010

SLG55220-120010

2 Rail GreenFET High Voltage Gate Driver

Revision History

Date

Version

Change

7/10/2018

1.01

Updated style and formatting

Datasheet

10-Jul-2018

Revision 1.01

Page 9 of 9

CFR0011-120-01

SLG55221-120010V [DIALOG]

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