SLG7NT408V [DIALOG]
Ultra-small 7.8 mΩ, 4 A Integrated Power Switch;
| 型号： | SLG7NT408V |
| 厂家： | 
Dialog Semiconductor |
| 描述： | Ultra-small 7.8 mΩ, 4 A Integrated Power Switch |
| 文件： | 总11页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLG7NT408V
Ultra-small 7.8 mΩ, 4 A
Integrated Power Switch
General Description
Pin Configuration
The SLG7NT408V is a 7.8 mΩ 4 A single-channel load switch
that is able to switch 0.85 to 5 V power rails. The product is
packaged in an ultra-small 1.5 x 2.0 mm package.
8
7
6
5
1
2
3
4
VDD
ON
D
GND
CAP
S
Features
•
1.5 x 2.0 mm FC-TDFN 8L package (2 fused pins for drain
and 2 fused pins for source)
•
Logic level ON pin capable of supporting 0.85 V CMOS
Logic
D
S
•
•
•
User selectable ramp rate with external capacitor
7.8 mΩ RDSONwhile supporting 4 A
Two Over Current Protection Modes
• Short Circuit Current Limit
8-pin FC-TDFN
(Top View)
• Active Current Limit
•
•
•
•
Over Temperature Protection
Pb-Free / Halogen-Free / RoHS compliant
Operating Temperature: -20 °C to 70°C
Operating Voltage: 2.5 V to 5.5 V
Applications
•
•
•
Notebook Power Rail Switching
Tablet Power Rail Switching
Smartphone Power Rail Switching
Block Diagram
4 A @ 7.8 mΩ
D
+2.5 to 5.5 V
CAP
S
Charge
Pump
Linear Ramp
Control
Over Current and
Over Temperature
Protection
ON
CMOS Input
Silego Technology, Inc.
000-007NT408-101
Rev1.01
Revised September 9, 2015
SLG7NT408V
Pin Description
Pin #
Pin Name
Type
Pin Description
1
VDD
PWR
VDD power for load switch control (2.5 V to 5.5 V)
Turns MOSFET ON (4 MΩ pull down resistor)
CMOS input with VIL < 0.3 V, VIH > 0.85 V
2
ON
Input
3
4
5
6
7
8
D
D
MOSFET
MOSFET
MOSFET
MOSFET
Input
Drain of Power MOSFET (fused with pin 4)
Drain of Power MOSFET (fused with pin 3)
Source of Power MOSFET (fused with pin 6)
Source of Power MOSFET (fused with pin 5)
Capacitor for controlling power rail ramp rate
Ground
S
S
CAP
GND
GND
Ordering Information
Part Number
SLG7NT408V
Type
Production Flow
FC-TDFN 8L
Commercial, -20 °C to 70 °C
Commercial, -20 °C to 70 °C
SLG7NT408VTR
FC-TDFN 8L (Tape and Reel)
000-007NT408-101
Page 2 of 11
SLG7NT408V
Absolute Maximum Ratings
Parameter Description
Conditions
Min.
--
Typ.
--
Max.
7
Unit
V
VDD
TS
Power Supply
Storage Temperature
ESD Protection
-65
2000
--
--
150
--
°C
V
ESDHBM
WDIS
Human Body Model
--
Package Power Dissipation
--
1
W
A
MOSFET IDSPK PeakCurrent fromDrainto Source For no more than 1 ms with 1% duty cycle
--
--
6
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Electrical Characteristics
TA = -20 to 70 °C (unless otherwise stated)
Parameter Description
Conditions
-20 to 70°C
Min.
2.5
--
Typ.
--
Max.
5.5
1
Unit
V
V
Power Supply Voltage
DD
when OFF
--
μA
μA
mΩ
mΩ
A
I
Power Supply Current (PIN 1)
DD
when ON, No load
--
70
7.8
8.5
--
100
8.5
9.6
4
T 25°C @ 100 mA
--
A
Static Drain to Source
ON Resistance
RDS
ON
T 70°C @ 100 mA
--
A
IDS
Operating Current
Drain Voltage
V = 1.0 V to 5.5 V
--
D
V
0.85
--
V
V
D
DD
50% ON to Ramp Begin,
T
ON pin Delay Time
0
300
500
μs
ON_Delay
R = 20 Ω, C = 10 μF
L
L
1
1
50% ON to 90% V
Configurable
ms
S
Example: CAP (PIN 7) = 4 nF, V
=
=
T
Total Turn On Time
DD
DD
Total_ON
V = 5 V, Source_Cap = 10 μF,
--
1.96
Configurable
3.0
--
ms
D
R = 20 Ω
L
10% V to 90% V
V/ms
V/ms
S
S
Example: CAP (PIN 7) = 4 nF, V
T
Slew Rate
SLEWRATE
V = 5 V, Source_Cap = 10 μF,
--
--
D
R = 20 Ω
L
CAP
Source Cap
Source to GND
--
--
--
0
500
μF
V
SOURCE
ON_V
High Input Voltage on ON pin
Low Input Voltage on ON pin
0.85
-0.3
V
DD
IH
ON_V
0.3
--
V
IL
MOSFET will automatically limit cur-
rent when VS > 250 mV
Active Current Limit
--
--
6.0
--
A
A
I
LIMIT
MOSFET will automatically limit cur-
rent when VS < 250 mV
Short Circuit Current Limit
0.5
THERM
Thermal shutoff turn-on temperature
Thermal shutoff turn-off temperature
Thermal shutoff time
--
--
--
125
100
--
--
--
1
°C
°C
ms
ON
OFF
TIME
THERM
THERM
T
50% ON to V Fall, V = V = 5 V,
S
DD
D
OFF Delay Time
--
--
--
15
--
μs
μs
OFF_Delay
R = 20 Ω, no C
L
L
90% V to 10% V , V = V = 5 V,
S
S
DD
D
T
V Fall Time
TBD
FALL
S
R = 20 Ω, no C
L
L
Notes:
1. Refer to table for configuration details.
000-007NT408-101
Page 3 of 11
SLG7NT408V
SLG7NT408V Turn ON
The normal power on sequence is first VDD, with VD only being applied after VDD is > 1 V, and then ON after VD is at least 90%
of final value. The normal power off sequence is the power on sequence in reverse.
If VDD and VD are turned on at the same time then it is possible that a voltage glitch will appear on VS before VDD achieves 1V
which is the VT of the main MOSFET. The size of the glitch is dependent on source and drain capacitance loading and the ramp
rate of VDD & VD.
SLG7NT408V Turn ON
The VS ramp follows a linear path, not an RC limitation provided the ramp is slow enough to not be current limited by load
capacitance.
SLG7NT408V Current Limiting
The SLG7NT408V has two forms of current limiting.
Standard Current Limiting Mode
Current is measured by mirroring the current through the main MOSFET. The mirrored current is then sent through a resistor
creating a voltage V(i) proportional to the MOSFET current. The V(i) is then compared with a Band Gap voltage V(BG). If V(i)
exceeds the Band Gap voltage then the voltage V(g) on the gate of the main MOSFET is reduced. The V(g) continues to drop
until V(i) < V(BG). This response is a closed loop response and is therefore very fast and current limits in less than a few
micro-seconds. There is no difference between peak or constant current limit.
Temperature Cutoff
However, as the V(g) drops the Rds(ON) of the main MOSFET will increase, thus limiting the current, but also increasing the
power dissipation of the IC. The IC is very small and cannot dissipate much power. Therefore, if a current limit condition is
sustained the IC will heat up. If the temperature exceeds approximately 120°C, then V(g) will be brought low completely shutting
off the main MOSFET. As the die cools the MOSFET will be turned back on at 100°C.
If the current limiting condition has not been mitigated then the die will again heat up to 120°C and the process will repeat.
Short Circuit Current Limiting Mode
When V(S) < 250 mV, which is the case if there is a solder bridge during the manufacturing process or a hard short on the power
rail, then the current is limited to approximately 500 mA. This current limit is accomplished in the same manner as the Standard
Current Limiting Mode with the exception that the current mirror is 15x greater. Because the current mirror is so much larger, a
15x smaller main MOSFET current is required to generate the same V(i). If V(S) rises above approximately 250 mV, then this
mode is automatically switched out.
000-007NT408-101
Page 4 of 11
SLG7NT408V
TTotal_ON vs. CAP @ VDD = 3.3 V
SLG7NT408V TTotal_ON: ON (50%) - VS (90%)
VDD = 3.3 V, TA = 25 °C. CL = 10 μF, IDS = 100 mA
6
5
4
3
2
1
0
VD = 1.5V
VD = 2.5V
VD = 3.3V
0
2000
4000
6000
8000
10000
12000
14000
16000
Cap (pf)
TTotal_ON vs. CAP @ VDD = 5.0 V
SLG7NT408V TTotal_ON: ON (50%) - VS (90%)
VDD = 5.0 V, TA = 25 °C. CL = 10 μF, IDS = 100 mA
6
5
4
3
2
1
0
VD = 1.50V
VD = 2.50V
VD = 3.30V
VD = 5.00V
0
2000
4000
6000
8000
10000
12000
14000
16000
Cap (pf)
000-007NT408-101
Page 5 of 11
SLG7NT408V
TSLEW vs. CAP @ VDD = 3.3 V
SLG7NT408V TSLEW: VS (10%) - VS (90%)
VDD = 3.3 V, TA = 25 °C. CL = 10 μF, IDS = 100 mA
15
14
13
12
11
10
9
VD = 1.50V
VD = 2.50V
VD = 3.30V
8
7
6
5
4
3
2
1
0
0
1000
2000
3000
4000
5000
6000
7000
8000
9000 10000 11000 12000 13000 14000 15000 16000
Cap (pf)
TSLEW vs. CAP @ VDD = 5.0 V
SLG7NT408V TSLEW: VS (10%) - VS (90%)
VDD = 5.0 V, TA = 25 °C. CL = 10 μF, IDS = 100 mA
15
14
13
12
11
10
9
VD = 1.50V
VD = 2.50V
VD = 3.30V
VD = 5.00V
8
7
6
5
4
3
2
1
0
0
1000
2000
3000
4000
5000
6000
7000
8000
9000 10000 11000 12000 13000 14000 15000 16000
Cap (pf)
000-007NT408-101
Page 6 of 11
SLG7NT408V
TTotal_ON, TON_Delay and Slew Rate Measurement
ON
50% ON
50% ON
T
OFF_DELAY
90% V
90% V
S
S
T
V
ON_DELAY
S
10% V
S
10% V
S
Slew Rate (V/ms)
T
FALL
TTotal_ON
000-007NT408-101
Page 7 of 11
SLG7NT408V
Package Top Marking System Definition
Part Code + Assembly Site
Lot Traceability
XXA
DDR
LL
Date Code + Revision
Pin 1 Identifier
000-007NT408-101
Page 8 of 11
SLG7NT408V
Package Drawing and Dimensions
8 Lead TDFN Package 1.5 x 2.0 mm (Fused Lead)
JEDEC MO-252, Variation W2015D
Index Area (D/2 x E/2)
L
A1
S
L1
L2
A2
E
Unit: mm
Symbol
Symbol
Min
0.70
0.005
0.15
0.15
1.95
1.45
Nom. Max
Min
0.35
Nom. Max
A
0.75
-
0.80
0.060
0.25
0.25
2.05
1.55
L
0.40
0.45
A1
A2
b
L1
L2
e
0.515 0.565 0.615
0.135 0.185 0.235
0.50 BSC
0.20
0.20
2.00
1.50
D
E
S
0.37 REF
000-007NT408-101
Page 9 of 11
SLG7NT408V
Tape and Reel Specifications
Max Units
Leader (min)
Length
Trailer (min)
Nominal
Package # of
Reel &
Hub Size
[mm]
Tape
Width Pitch
[mm]
Part
Package Size
Length
[mm]
Type
Pins
per Reel per Box
Pockets
Pockets
[mm]
[mm]
[mm]
TDFN 8L
FC Green
8
1.5 x 2.0 x 0.75 3000
3000
178 / 60
100
400
100
400
8
4
Carrier Tape Drawing and Dimensions
Index Hole Index Hole
PocketBTMPocketBTM Pocket Index Hole Pocket Index Hole
to Tape
Edge
to Pocket Tape Width
Center
Package
Type
Length
Width
Depth
Pitch
Pitch
Diameter
A0
B0
K0
P0
P1
D0
E
F
W
TDFN 8L
FC Green
1.68
2.18
0.9
4
4
1.5
1.75
3.5
8
P0
D0
E
Y
Section Y-Y
C
L
K0
Y
A0
P1
Refer to EIA-481 specification
Recommended Reflow Soldering Profile
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 2.25 mm3 (nominal). More
information can be found at www.jedec.org.
000-007NT408-101
Page 10 of 11
SLG7NT408V
Revision History
Date
Version
Change
Updated Vd min = 0.85 V
Updated Conditions in Electrical Characteristics Table
9/9/2015
1.01
000-007NT408-101
Page 11 of 11
相关型号：
©2020 ICPDF网 联系我们和版权申明