SLG7NT4229 [DIALOG]
PWROK GENERATOR AND STARTUP LATCHING CIRCUIT;
| 型号： | SLG7NT4229 |
| 厂家： | 
Dialog Semiconductor |
| 描述： | PWROK GENERATOR AND STARTUP LATCHING CIRCUIT |
| 文件： | 总9页 (文件大小：500K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLG7NT4229
PWROK GENERATOR AND STARTUP
LATCHING CIRCUIT
General Description
Pin Configuration
Silego SLG7NT4229 is a low power and small form
device. The SoC is housed in a 2.5mm x 2.5mm
TDFN package which is optimal for using with small
devices.
VDD
BC_ACOK_DSW
1
2
3
4
5
6
VR_ALW_ENABLE
12
11
10
9
SMC_SHUTDOWN
V3.3A_DSW_PWRGD
VBAT_MON_DPWROK
BC_ACOK
STARTUP_LATCH_SET
SMC_ONOFF_N
PS_ON_SW_N
GND
Features
8
• Low Power Consumption
• 3.3V Supply Voltage
• RoHS Compliant / Halogen-Free
• Pb-Free TDFN-12 Package
• MSL Level 1
PCH_DPWROK_R
7
Thermal Pad
connected to GND
TDFN-12
TOP VIEW
Output Summary
• 2 Outputs – Push Pull
• 2 Outputs – Open Drain
Silego Technology, Inc.
SLG7NT4229_DS_r100
SLG7NT4229_GP_r001
Rev 1.0
Revised October 3, 2013
SLG7NT4229
PWROK GENERATOR AND STARTUP
LATCHING CIRCUIT
Block Diagram
Typical Application Circuit
+V3.3A_DSW
+3.3A_KBC
C1
R1
100k
R2
100k
100nF
U1
data I/O
data I data I/O
data I/O data I/O
data I/O data I/O
data I/O data I/O
VR_ALW_ENABLE
1
2
3
4
5
6
12
11
10
9
8
7
OUT
OUT
VDD
BC_ACOK_DSW.
IN
IN
IN
V3.3A_DSW_PWRGD
VBAT_MON_DPWROK
SMC_ONOFF_N
data I/O
GND
SLG7NT4229
PCH_DPWROK_R
BC_ACOK
OUT
OUT
PS_ON_SW_N
IN
STARTUP_LATCH_SET
IN
IN
SMC_SHUTDOWN
SLG7NT4229_DS_r100
Page 2
SLG7NT4229
PWROK GENERATOR AND STARTUP
LATCHING CIRCUIT
Pin Configuration
Pin #
1
2
3
4
5
6
7
Pin Name
Type
PWR
Input
Input
Input
Output
Output
GND
Pin Description
Supply Voltage
Digital Input
Digital Input
Digital Input
Open Drain
Push Pull
VDD
BC_ACOK_DSW
V3.3A_DSW_PWRGD
VBAT_MON_DPWROK
BC_ACOK
PCH_DPWROK_R
GND
Ground
8
9
10
11
12
PS_ON_SW_N
Input
Output
Input
Input
Output
GND
Digital Input
Open Drain
Digital Input
Digital Input
Push Pull
SMC_ONOFF_N
STARTUP_LATCH_SET
SMC_SHUTDOWN
VR_ALW_ENABLE
Exposed Bottom Pad
Exposed
Bottom Pad
Ground
Ordering Information
Part Number
Package Type
SLG7NT4229V
V = TDFN-12
SLG7NT4229VTR
VTR = TDFN-12 - Tape and Reel (3k units)
SLG7NT4229_DS_r100
Page 3
SLG7NT4229
PWROK GENERATOR AND STARTUP
LATCHING CIRCUIT
Absolute Maximum Conditions
Parameter
Min.
-0.3
-0.3
-1.0
-65
--
Max.
7
Unit
V
VHIGH to GND
Voltage at input pins
Current at input pin
Storage temperature range
Junction temperature
7
V
1.0
150
150
mA
°C
°C
Electrical Characteristics
(@ 25°C, unless otherwise stated)
Symbol Parameter
Condition/Note
Min. Typ. Max. Unit
VDD
IQ
Supply Voltage
3.0
--
3.3
1
3.6
--
V
Quiescent Current
Operating Temperature
Static inputs and outputs
μA
°C
TA
-40
25
85
Leakage Current for Analog/Digital Inputs
or outputs in High impedance state
IL
Input Leakage Current
-100
--
100
nA
VOH
VOL
Output Voltage High
Output Voltage Low
Push Pull Logic Level Output, IOH=3mA
Push Pull Logic Level Output, IOL=3mA
2.1
--
--
--
--
V
V
0.81
Open Drain Logic Level Output,
IOL=10mA
VOL
VO
Output Voltage Low
--
--
--
--
0.605
VDD
V
V
Maximal Voltage Applied to any
PIN in High-Impedance State
VIH
VIL
HIGH-Level Input Voltage
LOW-Level Input Voltage
Logic Input
Logic Input
1.8
--
--
--
--
V
V
1.1
IOL
IOL
LOW-Level Output Current
LOW-Level Output Current
Push Pull Current at, VOL=0.4V
Open Drain Current at VOL=0.4V
--
--
1
7
--
--
mA
mA
TDLY1
TSU
Delay1 Time
Start up Time
10
--
--
7
14
--
ms
ms
After VDD reaches 1.6V
SLG7NT4229_DS_r100
Page 4
SLG7NT4229
PWROK GENERATOR AND STARTUP
LATCHING CIRCUIT
Timing Diagrams
SLG7NT4229_DS_r100
Page 5
SLG7NT4229
PWROK GENERATOR AND STARTUP
LATCHING CIRCUIT
Package Top Marking
Datasheet
Revision
1.0
Programming
Code Number
Part Code
Revision
Date
01
4229V
AA
10/03/2013
SLG7NT4229_DS_r100
Page 6
SLG7NT4229
PWROK GENERATOR AND STARTUP
LATCHING CIRCUIT
Package Drawing and Dimensions
12 Lead TDFN Package
JEDEC MO-229, Variation WDDE
SLG7NT4229_DS_r100
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SLG7NT4229
PWROK GENERATOR AND STARTUP
LATCHING CIRCUIT
Tape and Reel Specification
Max Units
Trailer A
Leader B
Pocket (mm)
Nominal
Package
Size (mm)
Reel &
Hub Size
(mm)
# of
Pins
Package Type
Length
Length
per reel per box
Pockets
Pockets
Width
Pitch
(mm)
(mm)
TDFN 12L
2.5x2.5mm
0.4P Green
12
2.5x2.5x0.75
3000
3000
178/60
42
168
42
168
8
4
Carrier Tape Drawing and Dimensions
Pocket
Index Hole Index Hole
Pocket
BTM Width
(mm)
Pocket
Depth
(mm)
Index Hole
Pocket
Pitch
(mm)
Index Hole
Diameter
(mm)
BTM
Length
(mm)
to Tape
Edge
to Pocket Tape Width
Center
(mm)
Pitch
(mm)
(mm)
Package
Type
(mm)
A0
B0
K0
P0
P1
D0
E
F
W
TDFN 12L
2.5x2.5mm
0.4P Green
2.75
2.75
1.05
4
4
1.55
1.75
3.5
8
Refer to EIA-481 Specifications
Recommended Reflow Soldering Profile
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 4.6875 mm3 (nominal).
More information can be found at www.jedec.org.
SLG7NT4229_DS_r100
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SLG7NT4229
PWROK GENERATOR AND STARTUP
LATCHING CIRCUIT
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THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR
USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. SILEGO
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RELIABILITY WITHOUT NOTICE.
SLG7NT4229_DS_r100
Page 9
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