PA7572FI-20L [DIODES]
EE PLD, 20ns, PLA-Type, CMOS, PQFP44, LEAD FREE, TQFP-44;
| 型号： | PA7572FI-20L |
| 厂家： | 
DIODES INCORPORATED |
| 描述： | EE PLD, 20ns, PLA-Type, CMOS, PQFP44, LEAD FREE, TQFP-44 时钟 输入元件 可编程逻辑 |
| 文件： | 总10页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PA7572 PEEL Array™
Programmable Electrically Erasable Logic Array
Versatile Logic Array Architecture
CMOS Electrically Erasable Technology
- Reprogrammable in 40-pin DIP, 44-pin PLCC and
TQFP packages
- 24 I/Os, 14 inputs, 60 registers/latches
- Up to 72 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
Flexible Logic Cell
- Up to 3 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
High-Speed Commercial and Industrial Versions
- As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (fMAX
)
- Industrial grade available for 4.5 to 5.5V VCC and -40
- Sum-of-products logic for output enables
to +85 °C temperatures
Development and Programmer Support
- ICT PLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, other wide-gate functions
General Description
The PA7572 is a member of the Programmable Electrically The PA7572’s logic and I/O cells (LCCs, IOCs) are
Erasable Logic (PEEL™) Array family based on Anachip’s extremely flexible with up to three output functions per cell
CMOS EEPROM technology. PEEL™ Arrays free (a total of 72 for all 24 logic cells). Cells are configurable as
designers from the limitations of ordinary PLDs by D, T, and JK registers with independent or global clocks,
providing the architectural flexibility and speed needed for resets, presets, clock polarity, and other features, making
today’s programmable logic designs. The PA7572 offers a the PA7572 suitable for a variety of combinatorial,
versatile logic array architecture with 24 I/O pins, 14 input synchronous and asynchronous logic applications. The
pins and 60 registers/latches (24 buried logic cells, 12 input PA7572 supports speeds as fast as 13ns/20ns (tpdi/tpdx)
registers/latches, 24 buried I/O registers/latches). Its logic and 66.6MHz (fMAX) at moderate power consumption
array implements 100 sum-of-products logic functions 140mA (100mA typical). Packaging includes 40-pin DIP
divided into two groups each serving 12 logic cells. Each and 44-pin PLCC (see Figure 1). Anachip and popular
group shares half (60) of the 120 product-terms available.
third-party development tool manufacturers provide
development and programming support for the PA7572.
Figure 1. Pin Configuration
Figure 2. Block Diagram
DIP (600 mil)
2 Input/
PLCC
Global Clock Pins
I/CLK1
I
VCC
I
I
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
6
5 4 3 2 1 44 43 42 41 40
Global
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
8
9
39
38
37
36
35
34
33
32
31
30
29
Cells
124 (62X2)
Array Inputs
true and
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
10
11
12
13
14
15
16
17
Input
Cells
(INC)
2
complement
12 Input Pins
I/O
Cells
(IOC)
9
24 I/O Pins
24
24
12
10
11
12
13
14
15
16
17
18
19
20
I/O
GND
Buried
logic
I/CLK
VCC
I
Global Cells
18 19 20 21 22 23 24 25 26 27 28
Logic
Array
I
Logic
Logic
A
B
C
D
I
I
I
I
functions
Control
Cells
I/O Cells
24
24
to I/O cells
Input Cells
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
(LCC)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/CLK2
4 sum terms
5 product terms
for Global Cells
24 Logic Control Cells
up to 3 output functions per cell
(72 total output functions
possible)
96 sum terms
(four per LCC)
44 43 42 41 4039 38 37 36 35 34
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
TQFP
9
10
11
GND
I
12 13 14 151617 18 19 20 21 22
I
I
I
I
Logic Control Cells
08-15-002A
PA7572
GND
I/CLK2
08-15-001A
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights
under any patent accompany the sale of the product.
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Inside the Logic Array
The heart of the PEEL™ Array architecture is based on a products functions provided to the logic cells can be used for
logic array structure similar to that of a PLA (programmable clocks, resets, presets and output enables instead of just
AND, programmable OR). The logic array implements all simple product-term control.
logic functions and provides interconnection and control of
The PEEL™ logic array can also implement logic functions
the cells. In the PA7572 PEEL™ Array, 62 inputs are
with many product terms within a single-level delay. For
available into the array from the I/O cells, inputs cells and
example a 16-bit comparator needs 32 shared product terms
input/global-clock pins.
to implement 16 exclusive-OR functions. The PEEL™ logic
All inputs provide both true and complement signals, which array easily handles this in a single level delay. Other
can be programmed to any product term in the array. The PLDs/CPLDs either run out of product-terms or require
PA7572 PEEL™ Arrays contains 124 product terms. All expanders or additional logic levels that often slow
product terms (with the exception of certain ones fed to the performance and skew timing.
global cells) can be programmably connected to any of the
sum-terms of the logic control cells (four sum-terms per
Logic Control Cell (LCC)
logic control cell). Product-terms and sum-terms are also
Logic Control Cells (LCC) are used to allocate and control the
routed to the global cells for control purposes. Figure 3
logic functions created in the logic array. Each LCC has four
shows a detailed view of the logic array structure.
primary inputs and three outputs. The inputs to each LCC are
complete sum-of-product logic functions from the array, which
can be used to implement combinatorial and sequential logic
functions, and to control LCC registers and I/O cell output
enables.
From
IO Cells
(IOC,INC,
I/CLK)
From Global Cell
Preset RegType Reset
System Clock
62 Array Inputs
On/Off
MUX
To
Array
P
D,T,J
Q
MUX
REG
R
From
Logic
K
Control
Cells
(LCC)
A
B
C
D
From
Array
To
Global
Cells
125 Product
Terms
To
I/O
Cell
MUX
08-15-004A
To
Logic Control
Cells
(LCC)
Figure 4. Logic Control Cell Block Diagram
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with synchronous
or asynchronous D, T, or JK registers (clocked-SR registers,
which are a subset of JK, are also possible). See Figure 5.
EEPROM memory cells are used for programming the
desired configuration. Four sum-of-product logic functions
(SUM terms A, B, C and D) are fed into each LCC from the
logic array. Each SUM term can be selectively used for
multiple functions as listed below.
08-15-003A
100 Sum Terms
PA7572 Logic Array
Figure 3. PA7572 Logic Array
True Product-Term Sharing
The PEEL™ logic array provides several advantages over
common PLD logic arrays. First, it allows for true product-
term sharing, not simply product-term steering, as com-
monly found in other CPLDs. Product term sharing ensures
that product-terms are used where they are needed and
not left unutilized or duplicated. Secondly, the sum-of-
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Sum-A = D, T, J or Sum-A
Sum A, B or C combinatorial paths. Thus, one LCC output
can be registered, one combinatorial and the third, an output
enable, or an additional buried logic function. The multi-
function PEEL™ Array logic cells are equivalent to two or
three macrocells of other PLDs, which have one output per
cell. They also allow registers to be truly buried from I/O pins
without limiting them to input-only (see Figure 8 & Figure 9).
Sum-B = Preset, K or Sum-B
Sum-C = Reset, Clock, Sum-C
Sum-D = Clock, Output Enable, Sum-D
D Register
Q = D after clocked
P
D
Q
Q
Q
Best for storage, simple counters,
shifters and state machines with
few hold (loop) conditions.
R
From Global Cell
Input Cell Clock
T Register
Q toggles when T = 1
Q holds when T = 0
P
R
T
REG/
Latch
Best for wide binary counters (saves
product terms) and state machines
with many hold (loop) conditions.
Q
To
Array
MUX
Input
JK Register
Q toggles when J/K = 1/1
Q holds when J/K = 0/0
Q = 1
Q = 0
Input
P
R
J
Input Cell (INC)
when J/K = 1/0
when J/K = 0/1
K
Combines features of both D and T
registers.
From Global Cell
08-15-005A
Input Cell Clock
Figure 5. LCC Register Types
REG/
Latch
SUM-A can serve as the D, T, or J input of the register or a
combinatorial path. SUM-B can serve as the K input, or the
preset to the register, or a combinatorial path. SUM-C can
be the clock, the reset to the register, or a combinatorial
path. SUM-D can be the clock to the register, the output
enable for the connected I/O cell, or an internal feedback
node. Note that the sums controlling clocks, resets, presets
and output enables are complete sum-of-product functions,
not just product terms as with most other PLDs. This also
means that any input or I/O pin can be used as a clock or
other control function.
Q
To
MUX
Input
Array
MUX
A,B,C
or
Q
MUX
I/O Pin
From
Logic
Control
Cell
MUX
D
0
1
08-15-006A
Several signals from the global cell are provided primarily
for synchronous (global) register control. The global cell
signals are routed to all LCCs. These signals include a
high-speed clock of positive or negative polarity, global
preset and reset, and a special register-type control that
selectively allows dynamic switching of register type. This
last feature is especially useful for saving product terms
when implementing loadable counters and state machines
by dynamically switching from D-type registers to load and
T-type registers to count (see Figure 9).
I/O Cell (IOC)
Figure 6. Input and I/O Cell Block Diagrams
IOC/INC Register
Q = D after rising edge of clock
holds until next rising edge
D
Q
IOC/INC Latch
Q = L when clock is high
holds value when clock is low
L
Q
Multiple Outputs Per Logic Cell
08-15-007A
An important feature of the logic control cell is its capability
to have multiple output functions per cell, each operating
independently. As shown in Figure 4, two of the three
outputs can select the Q output from the register or the
Figure 7. IOC/INC Register Configurations
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Input Cells (INC)
Global Cells
Input cells (INC) are included on dedicated input pins. The The global cells, shown in Figure 10, are used to direct global
block diagram of the INC is shown in Figure 6. Each INC clock signals and/or control terms to the LCCs, IOCs and
consists of a multiplexer and a register/transparent latch, INCs. The global cells allow a clock to be selected from the
which can be clocked from various sources selected by the CLK1 pin, CLK2 pin, or a product term from the logic array
global cell (see Figure 7). The register is rising edge (PCLK). They also provide polarity control for INC and IOC
clocked. The latch is transparent when the clock is high clocks enabling rising or falling clock edges for input
and latched on the clock’s falling edge. The register/ latch registers/latches. Note that each individual LCC clock has its
can also be bypassed for a non-registered input.
own polarity control. The global cell for LCCs includes sum-
of-products control terms for global reset and preset, and a
fast product term control for LCC register-type, used to save
product terms for loadable counters and state machines (see
Figure 11). The PA7572 provides two global cells that divide
the LCC and IOCs into groups, A and B. Half of the LCCs and
IOCs use global cell A, half use global cell B. This means that
two high-speed global clocks can be used among the LCCs.
I/O Cell (IOC)
All PEEL™ Arrays have I/O cells (IOC) as shown above in
Figure 6. Inputs to the IOCs can be fed from any of the
LCCs in the array. Each IOC consists of routing and control
multiplexers, an input register/transparent latch, a three-
state buffer and an output polarity control. The register/
latch can be clocked from a variety of sources determined
by the global cell. It can also be bypassed for a non-
registered input. The PA7572 allows the use of SUM-D as
a feedback to the array when the I/O pin is a dedicated
output. This allows for additional buried registers and logic
paths. (See Figure 8 and Figure 9).
CLK1
CLK2
MUX
INC Clocks
PCLK
Global Cell: INC
Group A & B
MUX
MUX
LCC Clocks
IOC Clocks
CLK1
CLK2
Q
D
PCLK
Input with optional
register/latch
I/O
Reg-Type
LCC Reg-Type
LCC Presets
LCC Resets
Preset
Reset
I/O with
independent
output enable
Global Cell: LCC & IOC
08-15-010A
1
D
Q
A
B
C
D
2
Figure 10. Global Cells
OE
Reg-Type from Global Cell
08-15-008A
Figure 8. LCC & IOC With Two Outputs
Register Type Change Feature
Global Cell can dynamically change user-
selected LCC registers from D to T or from D
to JK. This saves product terms for loadable
counters or state machines. Use as D register
to load, use as T or JK to count. Timing
allows dynamic operation.
P
R
D
Q
Q
D
Buried register or
logic paths
Output
Example:
1
D
Q
A
B
C
D
Product terms for 10 bit loadable binary counter
P
R
T
Q
2
3
D uses 57 product terms (47 count, 10 load)
T uses 30 product terms (10 count, 20 load)
D/T uses 20 product terms (10 count, 10 load)
08-15-009A
08-15-011A
Figure 9. LCC & IOC With Three Outputs
Figure 11. Register Type Change Feature
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unexpected changes to be made quickly and without waste.
PEEL™ Array Development Support
Programming of PEEL™ Arrays is supported by many
popular third party programmers.
Development support for PEEL™ Arrays is provided by
Anachip and manufacturers of popular development tools.
Anachip offers the powerful PLACE Development Software
(free to qualified PLD designers).
Design Security and Signature Word
The PEEL™ Arrays provide a special EEPROM security bit
that prevents unauthorized reading or copying of designs.
Once set, the programmed bits of the PEEL™ Arrays
cannot be accessed until the entire chip has been
electrically erased. Another programming feature,
signature word, allows a user-definable code to be
programmed into the PEEL™ Array. The code can be read
back even after the security bit has been set. The signature
word can be used to identify the pattern programmed in the
device or to record the design revision.
The PLACE software includes an architectural editor, logic
compiler, waveform simulator, documentation utility and a
programmer interface. The PLACE editor graphically
illustrates and controls the PEEL™ Array’s architecture,
making the overall design easy to understand, while
allowing the effectiveness of boolean logic equations, state
machine design and truth table entry. The PLACE compiler
performs logic transformation and reduction, making it
possible to specify equations in almost any fashion and fit
the most logic possible in every design. PLACE also
provides a multi-level logic simulator allowing external and
internal signals to be simulated and analyzed via a
waveform display.(See Figure 12, Figure 13, Figure 14)
Figure 13. PLACE LCC and IOC Screen
Figure 12. PLACE Architectural Editor
PEEL™ Array development is also supported by popular
development tools, such as ABEL and CUPL, via ICT’s
PEEL™ Array fitters. A special smart translator utility adds
the capability to directly convert JEDEC files for other
devices into equivalent JEDEC files for pin-compatible
PEEL™ Arrays.
Programming
PEEL™ Arrays are EE-reprogrammable in all package
types, plastic-DIP, PLCC and SOIC. This makes them an
ideal development vehicle for the lab. EE-
Figure 14. PLACE Simulator Screen
reprogrammability is also useful for production, allowing
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This device has been designed and tested for the specified
operating ranges. Improper operation outside of these levels
is not guaranteed. Exposure to absolute maximum
ratings may cause permanent damage.
Table 1. Absolute Maximum Ratings
Symbol
VCC
Parameter
Supply Voltage
Conditions
Relative to Ground
Relative to Ground1
Ratings
-0.5 to + 7.0
-0.5 to VCC + 0.6
±25
Unit
V
VI, VO
IO
Voltage Applied to Any Pin
Output Current
V
Per pin (IOL, IOH
)
mA
°C
TST
Storage Temperature
Lead Temperature
-65 to + 150
+300
TLT
Soldering 10 seconds
°C
Table 2. Operating Ranges
Symbol
Parameter
Conditions
Commercial
Industrial
Min
Max
Unit
4.75
5.25
VCC
Supply Voltage
V
4.5
0
5.5
+70
+85
20
Commercial
Industrial
TA
Ambient Temperature
°C
-40
TR
TF
Clock Rise Time
Clock Fall Time
VCC Rise Time
See Note 2
See Note 2
See Note 2
ns
ns
20
TRVCC
250
ms
Table 3. D.C. Electrical Characteristics
Over the Operating Range
Symbol
VOH
VOHC
VOL
Parameter
Conditions
Min
2.4
Max
Unit
V
Output HIGH Voltage - TTL VCC = Min, IOH = -4.0mA
Output HIGH Voltage -
VCC = Min, IOH = -10µA
CMOS
VCC - 0.3
V
Output LOW Voltage - TTL
VCC = Min, IOL = 16mA
0.5
0.15
VCC + 0.3
0.8
V
Output LOW Voltage -
CMOS
VOLC
VIH
VCC = Min, IOL = -10µA
V
Input HIGH Level
2.0
V
VIL
Input LOW Level
-0.3
V
IIL
Input Leakage Current
±10
±10
-120
75
µA
µA
mA
VCC = Max, GND ≤VIN ≤VCC
I/O = High-Z, GND ≤VO ≤VCC
IOZ
Output Leakage Current
Output Short Circuit
Current4
ISC
VCC = 5V, VO = 0.5V, TA= 25°C
-30
3,11
V
IN = 0V or VCC
-20
11
ICC
VCC Current
f = 25MHz
50 (typ.)18
I-20
mA
All outputs disabled4
85
7
CIN
Input Capacitance5
Output Capacitance5
6
pF
pF
TA = 25°C, VCC = 5.0V @ f = 1 MHz
7
COUT
12
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Table 4. A.C Electrical Characteristics Combinatorial
Over the Operating Range
-20/I-20
Min
Symbol
Parameter6,12
Unit
Max
Propagation delay Internal (tAL + tLC
)
Propagation delay External (tIA + tAL +tLC + tLO
Input or I/O pin to array input
13
20
2
ns
ns
ns
ns
ns
ns
ns
ns
t
PDI
)
t
PDX
t
IA
Array input to LCC
12
1
t
AL
LC
LO
LCC input to LCC output10
t
LCC output to output pin
5
t
Output Disable, Enable from LCC output7
Output Disable, Enable from input pin7
5
t
, t
OD OE
20
t
OX
This device has been designed and tested for the recommended operating conditions. Proper operation outside of these
levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage
Figure 15. Combinatorial Timing - Waveforms and Block Diagram
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Table 5. A.C. Electrical Characteristics Sequential
-20/I-20
Symbol
Parameter6,1
Unit
Min
8
Max
Internal set-up to system clock8 - LCC14
ns
t
SCI
(tAL + tSK + tLC - tCK
Input16 (EXT.) set-up to system clock, - LCC (tIA + tSCI
System-clock to Array Int. - LCC/IOC/INC14 (tCK +tLC
)
)
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
SCX
COI
COX
HX
SK
)
7
System-clock to Output Ext. - LCC (tCOI + tLO
Input hold time from system clock - LCC
LCC Input set-up to async. clock13 - LCC
Clock at LCC or IOC - LCC output
)
12
0
1
1
4
0
5
AK
LCC input hold time from system clock - LCC
Input set-up to system clock - IOC/INC14 (tSK - tCK
HK
SI
)
Input hold time from system clock - IOC/INC (tSK - tCK
)
HI
Array input to IOC PCLK clock
Input set-up to PCLK clock17 - IOC/INC (tSK-tPK-tIA)
9
PK
0
SPI
HPI
Input hold from PCLK clock17 - IOC/INC (tPK+tIA-tSK
Input set-up to system clock - IOC/INC Sum-D
)
10
10
0
ns
ns
ns
(tIA + tAL + tLC + tSK - tCK
)
t
t
t
SD
Input hold time from system clock - IOC Sum-D
HD
Input set-up to PCLK clock - IOC Sum-D15
7
SDP
(tIA + tAL + tLC + tSK - tPK
)
Input hold time from PCLK clock - IOC Sum-D
0
ns
ns
t
t
t
f
f
f
f
f
t
t
t
t
t
t
t
t
HDP
CK
System-clock delay to LCC/IOC/INC
6
System-clock low or high pulse width
7
ns
CW
Max. system-clock frequency Int/Int 1/(tSCI + tCOI
)
66.6
58.8
50.0
45.4
71.4
1
MHz
MHz
MHz
MHz
MHz
ns
MAX1
MAX2
MAX3
MAX4
TGL
PR
Max. system-clock frequency Ext/Int 1/(tSCX + tCOI
)
)
Max. system-clock frequency Int/Ext 1/(tSCI + tCOX
Max. system-clock frequency Ext/Ext 1/(tSCX + tCOX
)
9
Max. system-clock toggle frequency 1/(tCW + tCW
LCC presents/reset to LCC output
)
Input to Global Cell present/reset (tIA + tAL + tPR
Asynch. preset/reset pulse width
)
15
ns
ST
8
ns
AW
Input to LCC Reg-Type (RT)
8
1
9
ns
RT
LCC Reg-Type to LCC output register change
ns
RTV
RTC
RW
Input to Global Cell register-type change (tRT + tRTV
)
ns
Asynch. Reg-Type pulse width
Power-on reset time for registers in clear state2
10
ns
5
µs
RESET
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Figure 16. Sequential Timing – Waveforms and Block Diagram
Notes
1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V
for periods less than 20ns.
13. “Async. Clock” refers to the clock from the Sum term (OR gate).
14. The “LCC” term indicates that the timing parameter is applied to the
LCC register. The “LCC/IOC” term indicates that the timing
parameter is applied to both the LCC and IOC registers. The
“LCC/IOC/INC” term indicates that the timing parameter is applied to
the LCC, IOC, and INC registers.
2.Test points for Clock and VCC in tR,tF,tCL,tCH, and tRESET are referenced at
10% and 90% levels.
3. I/O pins are 0V or VCC.
4. Test one output at a time for a duration of less than 1 sec.
5. Capacitances are tested on a sample basis.
15. This refers to the Sum-D gate routed to the IOC register for an
additional buried register.
6. Test conditions assume: signal transition times of 5ns or less from the
10% and 90% points, timing reference levels of 1.5V (unless
otherwise specified).
16. The term “input” without any reference to another term refers to an
(external) input pin.
7. tOE is measured from input transition to VREF ±0.1V (See test loads at
end of Section 6 for VREF value). tOD is measured from input transition
to VOH -0.1V or VOL +0.1V.
17. The parameter t
indicates that the PCLK signal to the IOC register
SPI
is always slower than the data from the pin or input by the absolute
value of (t -t -t ). This means that no set-up time for the data
SK PK IA
8. DIP: “System-clock” refers to pin 1/21 high speed clocks. PLCC: “Sys-
tem-clock” refers to pin 2/24 high speed clocks.
from the pin or input is required, i.e. the external data and clock can
be sent to the device simultaneously. Additionally, the data from the
9. For T or JK registers in toggle (divide by 2) operation only.
10. For combinatorial and async-clock to LCC output delay.
11. ICC for a typical application: This parameter is tested with the device
programmed as a 10-bit D-type counter.
pin must remain stable for t
arrive at the IOC register.
time, i.e. to wait for the PCLK signal to
HPI
18. Typical (typ) ICC is measured at T = 25° C, freq = 25MHZ, V
=
CC
A
12. Test loads are specified in Section 5 of this Data Book.
5V
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Table 6. Ordering Information
Part Number
PA7572P-20 (L)
PA7572F-20 (L)
PA7572J-20 (L)
PA7572PI-20 (L)
PA7572FI-20 (L)
PA7572JI-20 (L)
Speed
Temperature
Package
P40
13/20ns
C
F44
J44
P40
F44
13/20ns
I
J44
Figure 17. Part Number
Device
Suffix
PA7572J-20X
Lead Free
L : Lead Free Package
Blank : Normal
Package
P = 600mil DIP
F = Thin Quad Flat Pack (TQFP)
Speed
J = Plastic (J) Leaded Chip Carrier (PLCC)
-20 = 13ns/20ns tpd/tpdx
Temperature Range
(Blank) = Commercial 0 to 70oC
I = Industrial -40 to +85oC
Anachip Corp.
Anachip USA
Head Office,
780 Montague Expressway, #201
2F, No. 24-2, Industry E. Rd. IV, Science-Based
Industrial Park, Hsinchu, 300, Taiwan
Tel: +886-3-5678234
San Jose, CA 95131
Tel: (408) 321-9600
Fax: (408) 321-9696
Fax: +886-3-5678368
Email: sales_usa@anachip.com
Website: http://www.anachip.com
©2004 Anachip Corp.
Anachip reserves the right to make changes in specifications at any time and without notice. The information furnished by
Anachip in this publication is believed to be accurate and reliable. However, there is no responsibility assumed by Anachip
for its use nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted
under any patents or patent rights of Anachip. Anachip’s products are not authorized for use as critical components in life
support devices or systems.
Marks bearing © or ™ are registered trademarks and trademarks of Anachip Corp.
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
10/10
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