PI3DPX1202A2 [DIODES]
Low power DisplayPort 1.2 Redriver with DDC/AUX CH Switch;
| 型号： | PI3DPX1202A2 |
| 厂家： | 
DIODES INCORPORATED |
| 描述： | Low power DisplayPort 1.2 Redriver with DDC/AUX CH Switch |
| 文件： | 总51页 (文件大小：3798K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A product Line of
Diodes Incorporated
PI3DPX1202A
Low power DisplayPort 1.2 Redriver with DDC/AUX CH Switch
Î ESD HBM protection 2kV
Î Package: 48-pin TQFN (7x7mm)
Description
PI3DPX1202A is DisplayPort 1.2 standard compliant, very
low power DP Redriver.
Typical Applications
e device can read the Aux-channel Link Training (LT)
Swing and Pre-emphasis data between Transmitter and
Receiver, configure the output swing / Pre-emphasis, and
automatically calculates EQ based on Swing/Pre-emphasis
LT values through the built-in Aux listener. EQ can pro-
gram by the I2C serial interface.
Î Notebook, AIO and Desktop PCs
Î Graphic Cards
DP ꢌꢍꢁnꢎꢁnꢏꢐꢑꢄnꢒ
DPꢂꢂ ꢈoꢉt
e device can reduce signal jitter caused by transmission
line effects, and compensate for the PCB-related frequency
and switching-related loss to provide optimum DP perfor-
mance between the link.
DP1.2 Reꢀrꢁver
ꢂ AuꢃꢄDDꢅ Sꢆꢁtcꢇ
ꢅPꢊ
ꢀꢋPꢊ
Auꢃ-cꢇꢐꢑꢄnꢒ
DisplayPort
Connector
ꢓoteꢔooꢏ Pꢅ DPꢂꢂ Reꢀrꢁver
Features
Î Dual mode DisplayPort Redriver, DP 1.2 Specification
compliant
Figure: NB Application Block Diagram
Î Support all 1.62 / 2.7 / 5.4 Gbps data rate with DDC/
Aux signal switching
Ordering Information
Î High speed inputs with internal 50 Ohm pull-down
Î Ultra Low-power design
Ordering
Code
Package
Code
Package Type
Î Dual mode DisplayPort Input/Output with TMDS clock
Frequencies up to 340 MHz
3.3V only power, Pb-free &
Green, 48-pin TQFN, Tray(Tape/
Reel)
PI3DPX1202A2
ZBE(X)
Î Aux Listener support link training and configure output
level, pre-emphasis setting during link initialization.
Aux Listener supports "sink Request test mode"
ZB
ZB
ZB
Industrial Temperature
3.3V only power, Pb-free &
Green, 48-pin TQFN, Tape/Reel
PI3DPX1202A2
ZBIEX
Î Pseudo-adaptive equalization based on signal level and
pre-emphasis setting in Aux register
3.3V only power, Pb-free &
Green, 48-pin TQFN, Tray(Tape/
Reel)
Î CNTRL provides pin control EQ, Output Voltage Swing
PI3DPX1202A1
ZBE(X)
and Pre-Emphasis
Î DP and TMDS output mode selection with Cable
Suffix: I = Industrial Temperature, E = Pb-free and Green, X = Tape/Reel.
Detection pins
Î Support Hot Plug Detect and Cable Detect function
Î Individual lane power down automatically when no DP
signal present
Î DP redriver enter power down state to reduce current
consumption when sink device deserted
Î Power Supply : 3.3V
PI3DPX1202A
Document number: DS40115 Rev.2-1
September 2017
© Diodes Incorporated
1 of 51
www.diodes.com
A product Line of
Diodes Incorporated
PI3DPX1202A
2. General Information
2.1 Revision History
Revision
Mar 2017
Apr 2017
Changes
Release. Always Automatic EQ control through Aux channel listener or I2C programmable control mode support
Ch3: Functional description to simplify.
Ch4: Min temp changed 0 to -40 deg C for I-temp support. ICC measurement data updated with different Pre-
emphasis and Voltage swing setting condition.
Ch5: Add Aux-listener redriver latency information & power mW comparison data
May 2017
Jun 2017
Ch3: Improved Functional description
Power-up / Reset timing added in functional session
Eye waveforms by Pre channel length added in application session
2.2 Similar Products Selection Guide
PI3DPX1202A2
PI3DPX1202A1
PI3EQXDP1201
PI3DPX1203B
Version
DP 1.2, DP++ 1.2
DP 1.2, DP++1.2
DP 1.2, DP++1.2
DP 1.4, DP++ 1.4
Recommenda- New DP 1.2 Design
PI3EQXDP1201 Pin-to- Not recommend
pin replacement
Variable Frame Rate ap-
plication, latency critical
system
tion
Power, BOM sensitive
system
DP1.4 Data Rate system
Redriver Type Limiting-type Redriver,
Depend Aux listener for
automatic Device setting
control
Same as PI3DPX1202A1 Same as PI3DPX1202A1
Linear-type Redriver
No need Aux listener for
Automatic Device setting
control
EQ mode
Auto, I2C and Fixed EQ
setting
Auto EQ, I2C setting
only
Auto, I2C and Fixed EQ
setting
EQ setting 4-bit with Pin or
I2C mode.
Auto_EQ pin Auto EQ pin: Tri-state
No Auto EQ pin control Internal 100kΩ pull up.
None
mode to control Auto EQ/ pin. Internally Pull-Up
0 = Fixed EQ
1 = Auto EQ
Fixed EQ and I2C mode
0: Disable
to VDD for always for
Pin-to-Pin with PI-
3EQXDP1201
1: Enable
M: Pin-control EQ mode
New Features Low-power design 136mA @ 400mV, 0dB setting.
Increase Aux Listener FIFO size.
300mA @ 400mV, 0dB
setting
Latency Free, Not blocking
linked channels and boost
Receiver DFE performance
Drop-in Pin out compatible with PI3EQXDP1201.
Availability
Production
Production
EOL
Production
PI3DPX1202A
Document number: DS40115 Rev.2-1
September 2017
© Diodes Incorporated
2 of 51
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A product Line of
Diodes Incorporated
PI3DPX1202A
2.3 Power Consumption Comparison
Power Consumption Comparison
x4 IDD
x4 Old
x4 New
Swing, Preemphsetting
Units
450
400
350
300
250
200
150
100
50
60%
50%
40%
30%
20%
10%
0%
Improve
DP1201
DPX1202
400mV_0dB
400mV_3.5dB
400mV_6dB
400mV_9.5dB
55%
38%
32%
26%
52%
34%
24%
40%
27%
36%
36%
36%
309
338
358
390
321
381
388
332
396
351
356
138
211
242
289
155
252
294
197
289
225
229
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
600mV_0dB
600mV_3.5dB
600mV_6dB
0
800mV_0dB
800mV_3.5dB
1200mV_0dB
x4 IDD Improve
x4 Old DP1201
x4 New DPX1202
Average Total Current
Average Total Power
1175
756
2.4 Output Eye Waveforms with different Pre-channel length
Output Eye Opening with Input Equalization, 5.4 Gbps, Vdd=3.3V, 25C with PRBS 2^7-1 pattern, Input/Output Swing=800mVd
No Trace, EQ=0101 (2.25dB)
PreCH =6”, EQ=0101 (3.5dB)
PreCH =12”, EQ=1001 (4.6dB)
PreCH=18”, EQ=0001 (4.6dB)
PreCH=24”, EQ=1011 (6.1dB)
PreCH=30”, EQ=1011 (6.1dB)
PreCH=36”, EQ=1101 (8.2dB)
PreCH=42”, EQ=1101 (8.2dB)
Figure 2-1: Pre-channel length/insertion loss and EQ compensation
PI3DPX1202A
Document number: DS40115 Rev.2-1
September 2017
© Diodes Incorporated
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www.diodes.com
A product Line of
Diodes Incorporated
PI3DPX1202A
2.5 Related Products
Part Numbers
Products Description
Retimers
PI3HDX2711B
PI3HDX711B
Redrivers
HDMI 2.0 and DP++ Retimer (Jitter Cleaner)
HDMI 1.4 and DP++ ReTimer (Jitter Cleaner)
PI3DPX1203B
PI3HDX1204B1
PI3HDX1204E
PI3DPX1207B
PI3DPX1202A
PI3HDX511F
Active Switches & Splitters
PI3DPX1205A
PI3HDX231
DisplayPort 1.4 Redriver for Source/Sink/Cable Application, Linear-type
HDMI 2.0 Redriver (DP++ Level Shiꢀer), High EQ, place near to the source-side, Limiting type
HDMI 2.0 Linear Redriver (DP++ Level Shiꢀer) , Link transparent, place near to the sink-side
DisplayPort 1.4 Alt Type-C Redriver, 8.1 Gbps and USB3.1 10 Gbps, Link Transparent
Low Power DisplayPort 1.2 Redriver with built-in AUX Listener, Limiting-type
High EQ HDMI 1.4b Redriver and DP++ Level Shiꢀer for Sink/Source Application, Limiting-type
DisplayPort 1.4 Alt Type-C Mux Redriver, 8.1 Gbps and USB3.1 10 Gbps, Link Transparent
HDMI 2.0 3:1 ports Mux Redriver, Linear-type
PI3HDX414
HDMI 1.4b 1:4 Demux Redriver & Splitter for 3.4 Gbps Application, Limiting-type
HDMI 1.4b 1:2 Demux Redriver & Splitter for 3.4 Gbps Application, Limiting-type
HDMI 1.4 Redriver 2:1 Active Switch with built-in ARC and Fast Switching support, Limiting-type
PI3HDX412BD
PI3HDX621
2.6 Product Status Definition
Product Status
Definition
(1) Advanced
Information
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
In Design
Datasheet contains preliminary data; supplementary data will be published at a later
date. Diodes Incorporated reserves the right to make changes at any time without no-
tice to improve design.
Engineering
(1) Preliminary
Samples
(2) No Identification
Full Production
Needed
Datasheet contains final specifications. Diodes Incorporated reserves the right to make
changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Diodes Incorpo-
rated. e datasheet is for reference information only.
(3) Obsolete
Not In Production
PI3DPX1202A
Document number: DS40115 Rev.2-1
September 2017
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A product Line of
Diodes Incorporated
PI3DPX1202A
Contents
1. Product Summary........................................................................................................................................................... 1
2. General Information...................................................................................................................................................... 2
2.1 Revision History.................................................................................................................................................... 2
2.2 Similar Products Selection Guide..................................................................................................................... 2
2.3 Power Consumption Comparison .................................................................................................................. 3
2.4 Output Eye Waveforms with different Pre-channel length ..................................................................... 3
2.5 Related Products ................................................................................................................................................... 4
2.6 Product Status Definition ................................................................................................................................... 4
3. Package Pin-out Information ..................................................................................................................................... 8
3.1 Package Pin-out..................................................................................................................................................... 8
3.2 Pin Description ................................................................................................................................................... 10
4. Functional Description............................................................................................................................................... 12
4.1 Block Diagram..................................................................................................................................................... 12
4.2 Function Description......................................................................................................................................... 13
4.3 SMBus Registers.................................................................................................................................................. 19
4.4 DisplayPort AUX Listener................................................................................................................................ 20
4.5 DPCD Aux Registers ......................................................................................................................................... 23
4.6 SMBus Programming ........................................................................................................................................ 28
5. Electrical Specification................................................................................................................................................ 29
5.1 Absolute Maximum Ratings ............................................................................................................................ 29
5.2 Recommended Operating Conditions.......................................................................................................... 29
5.3 Power Dissipation............................................................................................................................................... 30
5.4 Electrical Characteristic ................................................................................................................................... 31
6. Application...................................................................................................................................................................... 34
6.1 Application Circuit Diagrams ......................................................................................................................... 34
6.2 PCB Layout Guideline....................................................................................................................................... 36
6.3 DisplayPort 1.2 Test Report ............................................................................................................................. 43
7. Mechanical/Packaging ................................................................................................................................................ 45
7.1 Package Mechanical Outline............................................................................................................................ 45
7.2 Part Marking Information................................................................................................................................ 47
7.3 Tape & Reel Materials and Design................................................................................................................. 48
8. Important Notice .......................................................................................................................................................... 51
PI3DPX1202A
Document number: DS40115 Rev.2-1
September 2017
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A product Line of
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PI3DPX1202A
Figures
Figure 2-1: Pre-channel length/insertion loss and EQ compensation............................................................ 3
Figure 3-1: PI3DPX1202A1 Package Pin-out ....................................................................................................... 8
Figure 3-2: PI3DPX1202A2 Package Pin-out ........................................................................................................ 9
Figure 4-1: Functional Block Diagram................................................................................................................... 12
Figure 4-2: Power up timing Sequence.................................................................................................................. 13
Figure 4-3: Internal power up timing sequence .................................................................................................. 13
Figure 4-4: Reset control from External Capacitor or GPO pin..................................................................... 14
Figure 4-5: Power up sequence flow chart ............................................................................................................ 15
Figure 4-6: Sink Test Request Transaction in Aux Link Training ................................................................. 21
Figure 5-1: DisplayPort Main Link Test Circuit.................................................................................................. 32
Figure 5-2: DisplayPort Main Link Intra-Skew Measurement........................................................................ 33
Figure 5-3: Rising and Falling Time Definition................................................................................................... 33
Figure 6-1: DP++ Source Application with combined Aux/DDC Channels.............................................. 34
Figure 6-2: DP Source Application with separate Aux/DDC Channels....................................................... 35
Figure 6-3: Decoupling Capacitor Placement Diagram.................................................................................... 37
Figure 6-4: Trace Width and Clearance of Micro-strip and Strip-line ......................................................... 38
Figure 6-5: 4-Layer PCB Stack-up Example......................................................................................................... 39
Figure 6-6: 6-Layer PCB Stack-up Example......................................................................................................... 39
Figure 6-7: Stitching Capacitor Placement ........................................................................................................... 40
Figure 6-8: Layout Guidance of Matched Differential Pair.............................................................................. 40
Figure 6-9: Layout Guidance of Bends................................................................................................................... 41
Figure 6-10: Layout Guidance of Shunt Component......................................................................................... 41
Figure 6-11: Layout Guidance of Series Component......................................................................................... 41
Figure 6-12: Layout Guidance of Stitching Via.................................................................................................... 42
Figure 6-13: DisplayPort Test Set-up...................................................................................................................... 43
Figure 6-14: DisplayPort 1.2 Compliance Test Report...................................................................................... 44
Figure 7-1: Package TQFN-48 (ZB) Mechanical Outline Dimension .......................................................... 45
Figure 7-2: TQFN-48 (ZB) ermal Via Pad Area ........................................................................................... 46
Figure 7-3: General Part marketing information................................................................................................ 47
Figure 7-4: Tape & Reel label information............................................................................................................ 48
Figure 7-5: Tape leader and trailer pin 1 orientations ....................................................................................... 48
Figure 7-6: Standard embossed carrier tape dimensions.................................................................................. 49
PI3DPX1202A
Document number: DS40115 Rev.2-1
September 2017
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PI3DPX1202A
Tables
Table 4-1: DP Channel Power down State............................................................................................................. 16
Table 4-2: EQBAND and EQ[2:0] Setting............................................................................................................. 17
Table 4-3: EQ Setting ................................................................................................................................................. 17
Table 4-4: EQ Setting ................................................................................................................................................. 17
Table 4-5: EQ Setting ................................................................................................................................................. 18
Table 4-6: Output Swing Setting ............................................................................................................................. 18
Table 4-7: Output Swing Setting............................................................................................................................. 18
Table 4-8: Output Pre-emphasis Setting................................................................................................................ 18
Table 4-9: Output Pre-emphasis Setting............................................................................................................... 18
Table 4-10: SMBUS Register 0x00 & 0x01 Definition ....................................................................................... 19
Table 4-11: Sink Test Request Acknowledgement ............................................................................................. 20
Table 6-1: CTS Trace card insertion loss information....................................................................................... 43
Table 7-1: Constant Dimensions.............................................................................................................................. 49
Table 7-2: Variable Dimensions ............................................................................................................................... 49
Table 7-3: Reel dimensions by tape size................................................................................................................. 50
PI3DPX1202A
Document number: DS40115 Rev.2-1
September 2017
© Diodes Incorporated
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PI3DPX1202A
3. Package Pin-out Information
3.1 Package Pin-out
NC
IN0P
IN0N
ꢎꢐ
3ꢉ
3ꢊ
3ꢋ
40
41
42
43
44
45
46
4ꢉ
4ꢊ
24
23
22
21
20
1ꢋ
1ꢊ
1ꢉ
16
15
14
13
ꢌND
Oꢍꢁ0P
Oꢍꢁ0N
NC
IN1P
IN1N
NC
Oꢍꢁ1P
Oꢍꢁ1N
ꢌND
IN2P
IN2N
OCꢅ0
Oꢍꢁ2P
Oꢍꢁ2N
NC
PI3DPX1202A1
IN3P
IN3N
Oꢍꢁ3P
Oꢍꢁ3N
Figure 3-1: PI3DPX1202A1 Package Pin-out
PI3DPX1202A
Document number: DS40115 Rev.2-1
September 2017
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PI3DPX1202A
NC
IN0P
IN0N
ꢎꢐ
3ꢉ
3ꢊ
3ꢋ
40
41
42
43
44
45
46
4ꢉ
4ꢊ
24
23
22
21
20
1ꢋ
1ꢊ
1ꢉ
16
15
14
13
ꢌND
Oꢍꢁ0P
Oꢍꢁ0N
NC
IN1P
IN1N
NC
Oꢍꢁ1P
Oꢍꢁ1N
ꢌND
IN2P
IN2N
OCꢅ0
Oꢍꢁ2P
Oꢍꢁ2N
NC
PI3DPX1202A1
IN3P
IN3N
Oꢍꢁ3P
Oꢍꢁ3N
Figure 3-2: PI3DPX1202A2 Package Pin-out
PI3DPX1202A
Document number: DS40115 Rev.2-1
September 2017
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PI3DPX1202A
3.2 Pin Description
Pin # Pin Name
I/O
Description
Auto EQ Selection pin. Auto EQ has 3 modes. EQ (Pin 40) can select one of the
Auto EQ modes. is pin is internally biased to 50% of VDD33 (M = VDD/2).
AUTO_EQ
35
Input
"1": Enable
(PI3DPX1202A2)
"0": Disable
"M": Please refer to the Functional Truth table
NC
35
Non connection pin. Internally Pull-up tied to 3.3V VDD. is pin does not bond-
out to package.
NC
(PI3DPX1202A1)
1
2
VDD33
NC
Power
NC
3.3V power supply
Do Not Connect. Leave this pin floating.
Shared pin. Pulled-up internally with 100 kΩ
"I2C_ADDR": SMBus control address pin
"OC1": Voltage Swing control bit 1
Shared
3
4
OC1/I2C_ADDR
OP0/SCL_CTL
Shared pin. Internally pulled-up with 100 kΩ
"SCL_CTL": SMBus Clock
Shared
"OP0": Pre-emphasis control bit 1
Shared pin. Internally pulled-up with 100 kΩ
"SDA_CTL" : SMBus Data
5
6
OP1/SDA_CTL
VDD33
Shared
Power
"OP1" : Pre-emphasis control bit 0
3.3V power supply
Primary Control Pin for Auto-configuration or Fine-tuning boost mode
"0" : SMBus mode
"M" : Aux listener mode (Default)
"1" : Pin strap mode.
7
CNTRL
Input
Cable Adapter Detection pin from source side
"0": no cable adapter; enable DP redriver mode with AUX listening and link
8
CAD_SRC
Output
training active
"1": Installed cable adapter; enable TMDS redriver mode and disable AUX inter-
ception
9
HPD_SRC
CAD_SNK
Output
Input
Hot Plug detect pin to source-side. 3.3V CMOS output. Active High
Cable detect pin from sink-side. 1MΩ pull-down resister must be connected for
proper cable detection
10
Hot Plug Detect pin from the sink-side.
Internally 200 kΩ Pull-down.
11
HPD_SNK
Input
12
13
14
15
16
17
18
19
VDD33
OUT3N
OUT3P
NC
Power
Output
Output
NC
3.3V power supply
Main Link 3 data 100 Ω Differential negative output.
Main Link 3 data 100 Ω Differential positive output
Do Not Connect
OUT2N
OUT2P
GND
Output
Output
Ground
Output
Main Link 2 data 100 Ω Differential negative output
Main Link 2 data 100 Ω Differential positive output
Ground
OUT1N
Main Link 1 data 100 Ω Differential negative output
PI3DPX1202A
Document number: DS40115 Rev.2-1
September 2017
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PI3DPX1202A
Pin # Pin Name
I/O
Description
20
21
22
23
24
25
OUT1P
NC
Output
NC
Main Link 1 data 100 Ω Differential positive output
Do Not Connect
OUT0N
OUT0P
GND
Output
Output
Ground
Power
Main Link 0 data 100 Ω Differential negative output
Main Link 0 data 100 Ω Differential positive output
Ground
VDD33
3.3V power supply
Enable pin. Pulled-up internally with 100 kΩ
"0"= Power down
"1"= Enable. Normal operation
26
ENABLE
Input
27
28
29
30
31
32
33
34
36
37
38
39
AUX_SNKN
AUX_SNKP
AUX_SRCN
AUX_SRCP
GND
I/O
AUX negative channel connected to DP sink device
AUX positive channel connected to DP sink device
AUX negative channel connected to DP source device
AUX positive channel connected to DP source device
Ground
I/O
I/O
I/O
Ground
Power
I/O
VDD33
3.3V power supply
SCL_DDC
SDA_DDC
VDD33
DDC clock channel from source-side when CAD_SNK=1
DDC Data channel from source-side when CAD_SNK=1
3.3V power supply
I/O
Power
NC
NC
Do Not Connect
IN0P
Input
Input
Main Link 0 data 100 Ω Differential positive input
Main Link 0 data 100 Ω Differential negative input
IN0N
EQ selection pin. is pin is internally biased to 50% of VDD33.
When AUTO_EQ pin = 0, EQ pin can adjust EQ in the fixed pin mode
40
EQ
Input
41
42
43
44
45
IN1P
IN1N
NC
Input
Input
NC
Main Link 1 data 100 Ω differential positive input
Main Link 1 data 100 Ω differential negative input
NC
IN2P
IN2N
Input
Input
Main Link 2 data 100 Ω differentia positive input
Main Link 2 data 100 Ω differentia negative input
Output Voltage Swing Control pin.
Internally pull-up with 100 kΩ
46
OC0
Input
47
48
IN3P
IN3N
Input
Main Link 3 data 100 Ω differential positive input
Main Link 3 data 100 Ω differential negative input
Tied to Ground
Input
EPAD EPAD
Ground
PI3DPX1202A
Document number: DS40115 Rev.2-1
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4. Functional Description
4.1 Block Diagram
ꢄꢋIAS
1.5ꢄ
50Ω
50Ω
ꢊꢑꢂꢓ3:0ꢔP
ꢊꢑꢂꢓ3:0ꢔꢁ
Iꢁꢓ3:0ꢔP
Drꢗver
ꢏꢐ
Iꢁꢓ3:0ꢔꢁ
ꢊutꢎut Sꢜꢗnꢇ
Pre-ꢏmꢎꢝꢆꢘꢗꢘ
ꢏꢐꢋAꢁDꢓ0:2ꢔ
ꢄoꢅtꢆꢇe
ꢃeveꢅ
Detector
ꢀꢁꢂRꢃ
ꢕPDꢈSꢁꢒ
ꢀADꢈSꢁꢒ
ꢏꢁAꢋꢃꢏ
Aꢑꢂꢊꢏꢐ
Auto ꢉ ꢛꢗꢖeꢌ ꢏꢐ
ꢏꢐ ꢙoꢌe
ꢀontroꢅ
ꢏꢐ
ꢊꢀ0
ꢄoꢅtꢆꢇe Sꢜꢗnꢇ
Pre-ꢏmꢎ
ꢊꢀ1
ꢊP1
ꢊP0
SꢀꢃꢈꢀꢂꢃꢉꢊP0
SDAꢈꢀꢂꢃꢉꢊP1
ꢀꢁꢂꢃꢄꢁꢅ ꢆꢁꢇꢈꢉ
Sꢙꢋuꢘ
0ꢖ00:0ꢖ01
I2ꢀꢈADDRꢉꢊꢀ1
Reꢇꢗꢘterꢘ
AꢑXꢈSRꢀP
AꢑꢀꢈSRꢀꢁ
DPꢀD
Auꢖ ꢅꢗꢘtener
ꢀtrꢅ1
ꢀtrꢅ2
SꢀꢃꢈDDꢀ
SDAꢈDDꢀ
AꢑXꢈSꢁꢒP
AꢑXꢈSꢁꢒꢁ
1.5ꢄ
ꢊutꢎut
ꢋuꢚꢚer
1.2ꢄ
Inꢎut
ꢏꢐ
ꢕPDꢈSRꢀ
ꢀADꢈSRꢀ
Reꢇuꢅꢆtor
3.3ꢄ
1.5ꢄ
3.3ꢄ ꢋꢆnꢌꢍꢆꢎ
Figure 4-1: Functional Block Diagram
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4.2 Function Description
Power up operation Timing
Afer ENABLE signal is properly set, power up timing sequence complete. ENABLE signal ꢀrom controller
must be LOW until power supply become stable.
ꢍ10mS Rꢃmꢌ-uꢌ tꢅme
ꢓ0ꢒ
ꢀ100ꢁS Deꢂꢃꢄ tꢅme ꢆor PꢇRꢈꢉꢃnꢊꢋꢃꢌ cꢅrcuꢅt reꢃꢊꢄ
10ꢒ
Poꢎer Suꢌꢌꢂꢄ
ꢏꢐAꢉꢑꢏ
ꢀ400mS
ꢐormꢃꢂ ꢇꢌerꢃtꢅon
Sꢅꢋnꢃꢂ ꢇutꢌut
Figure 4-2: Power up timing Sequence
Power Supply
HPD_SINK
3.3V
POR
Reset Bandgap
3.3V
1.2V
Regulator
3.3V HPD Buꢀer
Level shifter
1.2V
POR
HPD_SRC
1.2V
State Machine
1.2V
Local oscillator
Figure 4-3: Internal power up timing sequence
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Reset Implementation
When ENABLE is Low, the device is power-down mode and output are high impedance. It is critical to transi-
tion the ENABLE afer the power supply VDD has reached the minimum recommended operation voltage. is
can be achieved by the control signal GPO or by an external capacitor connected to GND.
To insure properly Reset, the ENABLE pin must be de-asserted ꢀor at least 100μS beꢀore asserted, and must be
reprogrammed in I2C programming mode. When using external capacitor, the size oꢀ the cap value depends
on the power up VDD supply ramp. Larger value results in a slower ramp-up time. Consider 0.1uF capacitor as
a reasonable first estimate.
VDD
VDD
ENABLE
100k-Ohm
GPO
ENABLE
100k-Ohm
C
C
External Capacitor Controlled
GPO pin contolled from Controller IC
Figure 4-4: Reset control from External Capacitor or GPO pin
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Power-up/down and Hot Plug Detect (HPD)
Following power on, state machine enter Reset State. Chip is powered down. HPD startup oscillator and Bandgap and Digital VDD
regulator is on.
Afer Power-On-Reset (POR) de-asserted, state machine enter "Low Power Mode 1" and then 2-ms later enter "Low Power Mode 2"
and monitor HPD_SINK.
When HPD_SINK is asserted, the state will change ꢀrom "Low Power State 2" to "Active state". In Active stage, 1.2V regulator is
turned on. When 1.2V POR detects valid voltage, RX and TX section oꢀ the channel will power on.
In Active state, iꢀ HPD_SINK=0, then it will go to wait state and initiate debounce timer, iꢀ HPD_SINK is still=0 afer 300ms, this
signal a HPD reset and the state machine goes to the "Low Power mode 2" state. Iꢀ HPD_SINK reverts back to 1 (High) within
300ms, then the controller will return active state. All circuits blocks are active in both active and wait state.
Start
Power On Reset
ST_POR
Low Power Mode
ST_LPM1
Low Power Mode
ST_LPM2
HPD detect = ON
0
HPD_SNK=?
HPD=1
Active Mode
ST_ACT
HPD=1
HPD=0
Active Wait
ST_WAIT
= 300ms
HPD = 0
Figure 4-5: Power up sequence flow chart
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Intelligent Power Management
e device intelligent signal detection scheme allows portions, or all oꢀ the IC, to be disabled ꢀor power savings. In DP
mode, iꢀ only one or two lanes are active, the other lanes will be automatically powered off. Iꢀ there is no input video
signal the entire IC will be powered down. Iꢀ there is no monitor detected, it can also automatically power down the IC.
e power-down mode can also be entered using hard pin ENABLE, or through DPCD register (AUX link training).
Table 4-1: DP Channel Power down State
External Pins
CAD
Internal Signal
DPCD CS
3.3-1.2V active
channel regula-
tor(1)
State POR
State POR Description
HPD
_SNK decode
Active channel
ST_POR
ST_LPM1
ST_LPM2
ST_ACT
ST_ACT
ST_WAIT
ST_WAIT
ST_POR
ST_LPM1
ST_LPM2
ST_ACT
Power On Reset
Low Power Mode 1
Low Power Mode 2
Active Mode
X
X
X
1
X
X
X
0
0
0
0
1
1
1
1
1
0
0
0
1
0
1
0
X
X
X
1
1
Powered down
Powered down
Powered down
Active
Powered down
Powered down
Powered down
Active
Active Mode
1
Powered down
Active
Powered down
Active
Active Wait
1
Active Wait
1
Powered down
Powered down
Powered down
Powered down
Active
Powered down
Powered down
Powered down
Powered down
* Note (1)
Power On Reset
Low Power Mode 1
Low Power Mode 2
Active Mode
X
X
X
1
ST_WAIT
Active Wait
1
Active
* Note (1)
Note:
(1) Inactive channel are always powered down.
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Equalization/Swing/Pre-emphasis mode settings
Table 4-2: EQBAND and EQ[2:0] Setting
EQBAND, EQ[2:0]
BYTE0 bit4, bit[7:5]
Gain@1.6Gbps
Gain @2.7Gbps
dB
Gain@5.4Gbps
dB
dB
0000 (Deꢀault)
0001
-0.384
-0.3443
-0.2832
-0.1959
-0.1217
-0.0347
-0.0841
0.2295
0.3045
0.4452
0.6993
1.1651
1.67
-0.9281
-0.849
-2.0054
-1.8155
-1.5318
-1.1537
-0.8518
-0.5169
-0.0866
0.4153
0.8871
1.4147
2.2531
3.5315
4.6837
6.1106
8.2595
11.3532
0010
-0.7256
-0.5518
-0.4054
-0.2355
-0.00704
0.2698
0.5198
0.7885
1.2611
2.0748
2.8963
4.0103
5.8413
8.6898
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
2.4082
3.7438
6.0652
1110
1111
Table 4-3: EQ Setting
when Auto_EQ = 1 (Reꢀer to Table 4-2)
Auto EQ mode 0
EQ = 0
Byte1 bit[3:2] = 00
EQBAND, EQ[2:0]
Auto EQ mode 1
EQ = M
Byte1 bit[3:2] = 01
EQBAND, EQ[2:0]
Auto EQ mode 2
EQ = 1
Byte1 bit[3:2] = 11
EQBAND, EQ[2:0]
Pre-emphasis
OP[1:0]
Byte0 bit[3:2]
Pre-emphasis
0 0
0 1
1 0
1 1
3.5dB
6 dB
9 dB
0 dB
1010
0111
0011
0000
1101
1010
0111
0011
1111
1101
1011
1001
Table 4-4: EQ Setting
when Auto_EQ = 0 (Reꢀer to Table 4-2)
EQBAND, EQ[2:0]
EQ
1.62Gbps
2.7Gbps
0000
5.4Gbps
0000
0
M
1
0000
1100
1111
1100
1100
1111
1111
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Table 4-5: EQ Setting
when Auto_EQ = M and CNTRL = M
CNTRL
EQBAND = OC0
EQ0 = OC1
EQ1 = OP0
EQ2 = OP1
M
(Reꢀer to Table 4-2)
Table 4-6: Output Swing Setting
in Register Programming Mode when CNTRL = 0 or in Pin Control Mode when CNTRL = 1
OC[1:0]
Byte0 bit[1:0]
CNTRL
Output Swing
Comments
0/1
0/1
0/1
0/1
0 0
0 1
1 0
1 1
400mV
See Table 3.9: SMBUS Register 0x00 & 0x01 Definition
600mV
1200mV (Deꢀault)
800mV
Table 4-7: Output Swing Setting
when CNTRL = M
CNTRL CAD_SNK
Output Swing
Follow AUX listener
800mV
Comments
DP Mode
M
0
M
1
TMDS Mode
Table 4-8: Output Pre-emphasis Setting
in Register Programming Mode when CNTRL = 0 or in Pin Control Mode when CNTRL = 1
OP[1:0]
Byte0 bit[3:2]
CNTRL
Output Pre-emphasis
0 /1
0 /1
0 /1
0 /1
0 0
0 1
1 0
1 1
3.5dB
See Table 3-9: SMBUS Register 0x00 & 0x01 Definition
6dB (Deꢀault)
9dB
0dB
Table 4-9: Output Pre-emphasis Setting
when CNTRL = M
CNTRL CAD_SNK
Output Swing
Comments
M
0
Follow AUX listener
DP Mode
M
1
0 dB
TMDS Mode
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4.3 SMBus Registers
e AUX register can be read/write using the SMBus input. When in AUX mode, the control oꢀ the registers is passed to AUX, writ-
ing the SMBUS as the same time should be avoided.
In TMDS mode setting (CAD_DET) = 1, external source can use SMBus to set the Equalization settings. EQ table can also be set by
programming SMBus register 1.
SMBus is set to auto EQ mode 1 by deꢀault. ie. Reg0x01=00001101.
Table 4-10: SMBUS Register 0x00 & 0x01 Definition
SMBus Reg- Description
isters
Deꢀault value
06h
SMBus
Access
R/W
0x00
EQ Control Select, when CNTRL= 0 with SMBus_reg 0x01 bit [1:0]
bit[7]: EQ2
bit[6]: EQ1
bit[5]: EQ0
bit[4]: EQBAND is EQ group control register. Please reꢀer Gain(dB) Control table
Pre-emphasis control
bit[3]: Control OP1 pin
bit[2]: Control OP0 pin
Swing control
bit[1]: Control OC1 pin
bit[0]: Control OC0 pin
0x01
bit [7:4] Reserved
00h
R/W
bit [3:2] EQ control
00: EQ pin set Low
01: EQ pin set Middle
11: EQ pin set High
bit [1:0] AUTO_EQ control
00: AUTO_EQ pin set Low
01: AUTO_EQ pin set Middle
11: AUTO_EQ pin set High
0x02: 0x14
Reserved
00h
R/W
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4.4 DisplayPort AUX Listener
DP AUX listener supports Native AUX CH Syntax. Mapping oꢀ SMBus onto AUX CH Syntax is not supported.
AUX listener monitor AUX communication ꢀrom requester and replier ꢀor transactions and stored AUX communication ,
related to the link settings.
In AUX read/write request cycle, the AUX address compares with the ꢀollowing registers’ address. When the addresses
matches, data shall extract and store into the respective AUX Listener registers. Below registers will set during the link train-
ing sequence afer the hot plug detection.
00100h Data Rate Register
00101h LANE_COUNT_SET
00103h - 00106h TRAINING_LANE0/1/2/3_SET
00260h Sink Test request response
00600h Power Down
e AUX listener supports Sink request Test sequence. Afer HPD IRQ event and DP source read 00201h AUX register and
iꢀ bit 1 is high, the DP source will enter a Sink request test mode and initiate a sequence oꢀ AUX read request cycle. During
the read cycle, data matching the ꢀollowing registers address are stored in the listener.
00206h ADJUST_REQUEST_LANE0_1
00207h ADJUST_REQUEST_LANE2_3
00218h Test Request
00219h Test link rate
00220h Test Lane count
Afer the read request cycle, the DP source will write 1 to Bit 0 register 00260h iꢀ the DP source enters sink request mode,
or 1 to Bit 1 oꢀ register 00260h iꢀ the source declined the sink test request. e data stored in registers 002xx above will
override the value set in 00101h to 00106h registers when the sink entered the Sink Test mode.
Table 4-11: Sink Test Request Acknowledgement
Table 4-12:
00260h
Mode
Buffer configuration outputs
xxxxxx00b
xxxxxx01b
xxxxxx10b
xxxxxx11b
No action
Sink Test mode
00100 : 00106h
00206h,00207h,00219h,00220h Override 00100,1,3,4,5,6h register settings
Sink test mode declined 00100h : 00106h
Not Legal code 00100h : 00106h
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Source-side Aux
Sink-side Aux
Aux ACK 00201h:
Automated Test Request
AUX ACK 00201h
Aux reply 00201h
Aux read 00218h-0027F:
Test request
AUX ACK 00218h to 0027Fh
Aux reply 00218h
Aux reply 00260h
AUX write 00260h:
Sink Test request response
Enable Test registers (bit[0] = 1)
Do nothing (bit[1] = 1)
Figure 4-6: Sink Test Request Transaction in Aux Link Training
A complete two way AUX transaction is defined as one oꢀ the ꢀollowing
AUX write and Sink issue ACK reply:
From Source
Sync Start/Start Pattern
4-bit cmd 1000 20-bit address
From Sink ACK
Sync Start bit
00000000
Stop
AUX write and Sink issue NACK reply:
A data byte “M” must ꢀollow AUX NACK, “M” indicates the number oꢀ data bytes successꢀully written. When a Source Device is
writing a DPCD address not supported by the Sink Device, the Sink Device shall reply with AUX NACK and “M” equal to zero.
From Source
Sync Start bit
4-bit cmd 1000 20-bit adr
8-bit length Data Stop
From Sink NACK
Sync Start bit
00010000
8-bit data byte M Stop
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AUX Read and Sink issue ACK reply:
Ready to reply to Read request with data following. DisplayPort receiver may assert a STOP condition before transmit-
ting the total number of requested data bytes when not all the bytes are available.
From Source
Sync Start bit
4-bit cmd 1001 20-bit address
8-bit length
Stop
From sink ACK
Sync
Start bit 00000000 Data Stop
AUX Read and Sink issue NACK reply:
A Sink Device receiving a Native AUX CH read request for an unsupported DPCD address must reply with an AUX ACK
and read data set equal to zero instead of replying with AUX NACK.
From Source
Sync
Start bit
4-bit cmd 1001
20-bit address 8-bit length
Stop
From Sink NACK
Sync
Start bit
00001000 data = 0
Stop
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4.5 DPCD Aux Registers
DPCD Aux Register Definitions
SMBus
AUX
Deꢀault DP Ac-
Description
Registers Registers
value
cess
LINK_BW_SET : Main Link Bandwidth Setting=Value x 0.27Gbps per
lane
Bits 7:0 = LINK_BW_SET
For DisplayPort version 1, revision 1a, only three values are supported.
All other values are reserved.
Link initialization
field
0x02
AUX operation :
00100h
14h
R/W
06h = 1.62 Gbps per lane
0Ah = 2.7 Gbps per lane
14h = 5.4 Gbps per lane
e Source may choose any oꢀ the three link bandwidths as long as it
does not exceed the capability oꢀ DisplayPort receiver as indicated in the
receiver capability field.
LANE_COUNT_SET : Main Link Lane Count = Value
Bits 4:0 = LANE_COUNT_SET
For DisplayPort version 1 revision 1a, only the ꢀollowing three values are
supported. All other values are reserved.
1h = One lane
2h = Two lanes
4h = Four lanes
For one-lane configuration, Lane0 is used. For 2-lane configuration,
Lane0 and Lane1 are used. e source may choose any lane count as long
as it does not exceed the capability oꢀ the DisplayPort receiver as indi-
cated in the receiver capability field.
Link initialization
field
AUX operation :
00101h
0x03
04h
R/W
For DPCD Ver.1.0:
Bits 7:5 = RESERVED. Read all 0’s.
For DPCD Ver.1.1:
Bits 6:5 = RESERVED. Read all 0’s.
Bit 7 = ENHANCED_FRAME_EN
0 = Enhanced Framing symbol sequence is not enabled.
1 = Enhanced Framing symbol sequence ꢀor BS, SR, CPBS, and CPSR is
enabled. Applicable to SST mode only. A uPacket TX must set this bit to
1 when the uPacket RX has the ENHANCED_FRAME_CAP bit (Bit 7 oꢀ
DPCD 00002h) set to 1 (with the exception oꢀ eDP
operation).
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SMBus
AUX
Deꢀault DP Ac-
Description
Registers Registers
value
cess
TRAINING_LANE0_SET
Link Training Control_Lane0
Bits1:0 = DRIVE_CURRENT_SET
00 – Training Pattern 1 w/ drive current level 1
01 – Training Pattern 1 w/ drive current level 2
10 – Training Pattern 1 w/ drive current level 3
11 – Training Pattern 1 w/ drive current level 4
Bit2 = MAX_CURRENT_REACHED
DPCD Lane 0 status
Aux operation
00103h
Set to 1 when the maximum driven current setting is reached.
0x04
00h
R/W
Note: Support oꢀ programmable drive current is optional. For example iꢀ there is only 1
level, then program Bits2:0 to 100 to indicate to the receiver that Level 1 is the maximum
drive current. Support oꢀ independent drive current controlꢀor each lane is also optional.
Bit4:3 = PRE-EMPHASIS_SET
00 = Training Pattern 2 w/o pre-emphasis
01 = Training Pattern 2 w/ pre-emphasis level 1
10 = Training Pattern 2 w/ pre-emphasis level 2
11 = Training Pattern 2 w/ pre-emphasis level 3
Bit5 = MAX_PRE-EMPHASIS_REACHED
DPCD Lane 1 status
Aux operation
00104h
Lane setting ꢀor lane 1.
0x05
0x06
0x07
e definition is the same as lane 0
00h
00h
00h
R/W
R/W
R/W
DPCD Lane 2 status
Aux operation
00105h
Lane setting ꢀor lane 2.
e definition is the same as lane 0
DPCD Lane 3 status
Aux operation
00106h
Lane setting ꢀor lane 3.
e definition is the same as lane 0
DOWNSPREAD_CTRL : Down-spreading control
Bit 3:0 = RESERVED. Read all 0’s
Bits 4 = SPREAD_AMP Spreading amplitude
0 = No downspread
1 = Equal to or less than 0.5% down spread
0x08
00107h
00h
R/W
Bit 7:5 = RESERVED. Read all 0’s.
Note: Write 00h to declare to the receiver that there is no down-spreading. e modulation
ꢀrequency must be in the range oꢀ 30kHz ~ 33kHz
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SMBus
AUX
Deꢀault DP Ac-
Description
Registers Registers
value
cess
DEVICE_SERVICE_IRQ_VECTOR
Bit 0 = RESERVED ꢀor EMOTE_CONTROL_COMMAND_PENDING
When this bit is set to 1, the Source Device must read the Device Services
Field ꢀor REMOTE_CONTROL_COMMAND_PASS_THROUGH.
Clearable
read
only.
Bit 1 = AUTOMATED_TEST_REQUEST
When this bit is set to 1, the Source Device must read Addresses 00218h
-0027Fh ꢀor the requested link test.
Bit 2 = CP_IRQ
is bit is used by an optional content protection system.
(Bit is
cleared
when
‘1’ is
0x09
00201h
00h
written is
written
via an
AUX CH
write
Bit 3 = MCCS_IRQ
is bit is used by an optional MCCS system in the Sink
Bits 5:4 = RESERVED. Read all 0’s.
transac-
tion.
Bit 6 = SINK_SPECIFIC_IRQ
Usage is vendor-specific.
Bit 7 = RESERVED. Read 0.
ADJUST_REQUEST_LANE0_1 : Voltage Swing and Equalization Setting
Adjust Request ꢀor Lane0 and Lane1
Bits 1:0 = VOLTAGE_SWING_LANE0
00 = Level 0
01 = Level 1
10 = Level 2
11 = Level 3
0x0A
00206h
00h
R
Bits 3:2 = PRE-EMPHASIS_LANE0
00 = Level 0
01 = Level 1
10 = Level 2
11 = Level 3
Bits 5:4 = VOLTAGE_SWING_LANE1
00 = Level 0
01 = Level 1
10 = Level 2
11 = Level 3
0x0B
Bits 7:6 = PRE-EMPHASIS_LANE1
00 = Level 0
01 = Level 1
10 = Level 2
11 = Level 3
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SMBus
AUX
Deꢀault DP Ac-
Description
Registers Registers
value
cess
ADJUST_REQUEST_LANE2_3
(Bit definitions as in ADJUST_REQUEST_LANE0_1)
00207h
00h
R
TEST_REQUEST: Test requested by the Sink Device. All other values
reserved.
Bit 0 = TEST_LINK_TRAINING
0 = no link training test requested
1 = link training test requested.
See TEST_LINK_RATE and TEST_LANE_COUNT ꢀor link rate and
linkwidth requested respectively.
00h
Bit 1 = TEST_PATTERN
0 = no test pattern requested
1 = test pattern requested
Bit 2 = TEST_EDID_READ
0 = no EDID read test requested
1 = EDID read test requested.
0x0C
00218h
Checksum oꢀ the last EDID block read is written to TEST_EDID_
CHECKSUM. e source will also send a color square test pattern.
For DPCD version 1.0:
Bits 7:3 = RESERVED. Read all 0’s.
For DPCD version 1.1:
Bit 3 = PHY_TEST_PATTERN
Set = 1 to request the PHY test pattern as specified at address 00248h.
Bits 7:4 = Reserved. Read as zeros.
TEST_LINK_RATE
Bits 7:0 = TEST_LINK_RATE
06h = 1.62 Gbps
0x0D
0x0E
00219h
00220h
00h
00h
R
R
0Ah = 2.7 Gbps
14h = 5.4 Gbps
TEST_LANE_COUNT
Bits 4:0 = TEST_LANE_COUNT
1h = one lane
2h = two lanes
4h = ꢀour lanes
All other values reserved.
Bits 7:5 = RESERVED. Read all 0’s.
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SMBus
AUX
Deꢀault DP Ac-
Description
Registers Registers
value
cess
TEST_RESPONSE
Bit 0 = TEST_ACK
0 = writing zero has no effect on TEST_REQ state
1 = positive acknowledgement oꢀ TEST_REQ. Clears TEST_REQ inter-
rupt
flag and indicates to the sink that the source has started requested test
mode.
Bit 1 = TEST_NAK
0x0F
00260h
00h
R/W
0 = writing zero has no effect on TEST_REQ state
1 = negative acknowledgement oꢀ TEST_REQ. Clears TEST_REQ
interrupt flag and indicates to sink that source will not start requested test
mode.
Bit 2 = TEST_EDID_CHECKSUM_WRITE
0 = no write to TEST_EDID_CHECKSUM
1 = EDID checksum has been written to TEST_EDID_CHECKSUM
Bits 7:3 = RESERVED. Read all 0’s.
Bit 1, 0
0 1 - normal mode
1 0 - D3 power down state
0x10
00600h
01h
R/W
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4.6 SMBus Programming
SMBUS support Block Read, Block Write, Indexed Block Read and Indexed Block Write ꢀunction. No Byte write ꢀunction
is supported. SMBUS has 20 internal registers. Only two registers are accessible by users.
SMBUS address is set to 0xAA or 0xA8 depending on the SMBUS_ADDR pin setting.
SMBus Address:
Bit 7
1
Bit 6
0
Bit 5
1
Bit 4
0
Bit 3
1
Bit 2
0
Bit 1 (I2C_ADDR pin 1-bit)
1'b=0 : 0xA8 address
1'b=1 : 0xAA address
Bit 0
R/W
SMBus Write Byte
Block Write
s
slave address
Command Code
Date Byte 1
Date Byte 4
Date Byte 7
Byte Count = N
Date Byte 2
Date Byte 5
Date Byte 8
Date Byte 0
Date Byte 3
Date Byte 6
Wr
A
A
A
A
A
A
A
A
A
A
A
A
P
Index Block Write
s
slave address
Command Code
Date Byte 1
Date Byte 4
Date Byte 7
Byte Count = N
Date Byte 2
Date Byte 5
Date Byte 8
Date Byte 0
Date Byte 3
Date Byte 6
Wr
A
A
A
A
A
A
A
A
A
A
A
A
P
Byte Write
s
slave address
Command Code
Byte
Wr
A
A
A
P
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5. Electrical Specification
5.1 Absolute Maximum Ratings
Normal I/O supply voltage to ground potential.....................................................................................................-0.5V to 4.0V
Supply Voltage Range 3.3V .......................................................................................................................................-0.5V to 4.0V
DC Signal Voltage......................................................................................................................................-0.5V to VDD33 +0.5V
Output Current................................................................................................................................................... -25mA to +25mA
Storage Temperature .................................................................................................................................................-65 to +150°C
Junction Temperature .............................................................................................................................................................125°C
ESD HBM.............................................................................................................................................................................. 2000V
ESD CDM................................................................................................................................................................................ 500V
Note:
1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. is is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
5.2 Recommended Operating Conditions
Symbol
Parameters
Min.
Typ.
Max.
Units
VDD33
3.3V Power Supply
3.0
0
3.3
3.6
70
V
Commercial Part Number
Industrial Part Number
TA
Operating temperature
oC
-40
85
TCASE
Case temperature
103.1
5.5
oC
V
V
V
VIH(HPD)
High-level input voltage HPD_SNK
1.9
0
VIH
High-level input voltage for device control signals
Low-level input voltage for device control signals
0.75
100
VIL
0.8
Main Link
VID
Peak to Peak input differential voltage
Data Rate
0.3
1.4
5.4
200
120
2
Vpp
Gbps
nF
Ω
DR
CAC
AC Coupling Capacitance
75
75
0
RDIFF
Differential output termination resistor
Output Termination Voltage
Inter-pair Skew at the 5.4 Gbps Input
VO_TERM
V
tSKEW
20
ps
Aux Channel Data
VID
Input Differential Voltage
Data Rate Aux
300
0.8
1400
1.2
mVpp
Mbps
Mbps
nF
DRAUX
DRFAUX
CAC
1
Data rate Fast Aux
720
Aux AC Coupling Capacitance
75
0
200
Aux Source common mode voltage
CAD=VIL; measured on Aux source and sink before AC
coupling caps
VCM_SRC
2000
mV
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5.3 Power Dissipation
Symbol
Parameters
Condition
Min
Typ Max Units
400 mV Swing, 0 dB Pre-emphasis
400 mV Swing, 9.5 dB Pre-emphasis
600 mV Swing, 0 dB Pre-emphasis
600 mV Swing, 6 dB Pre-emphasis
800 mV Swing, 0 dB Pre-emphasis
800 mV Swing, 3.5 dB Pre-emphasis
1200 mV Swing, 0 dB Pre-emphasis
140
290
150
290
200
290
226
mA
mA
mA
mA
mA
mA
mA
3.3V Single supply
@5.4Gbps, CAD_SNK = 0,
HPD_SNK = 1
IDD33
ENABLE pin Low (Turn off all function includ-
ing band-gap)
ISB
3.3V Power down current
130
uA
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5.4 Electrical Characteristic
Control Pin ENABLE
Symbol
VIH
Parameters
Condition
Min.
2.4
Typ.
Typ.
Max.
VDD33
0.8
Units
V
LVTTL input high voltage
LVTTL input low voltage
Input High-level current
Input Low-level current
VIL
GND
-5
V
IIH
VIH = VDD33
VIL = GND
5
uA
uA
IIL
-50
-15
HPD_SRC and HPD_SNK Pins
Symbol
VIH
Parameters
Condition
Min.
2.4
Max.
VDD33
Units
V
LVTTL input high voltage
LVTTL input low voltage
Input High-level current
Input Low-level current
VIL
1/3*VDD33
2/3*VDD33 V
IIH
VIH = VDD33
VIL = GND
40
uA
IIL
GND
2.4
0.6
uA
V
VOH
VOL
LVTTL high level output voltage IOH=-8mA
LVTTL low level output voltage
IOL= 8mA
0.4
V
SCL/SDA and AUX Pins
Symbol
Parameters
Condition
Min.
Typ.
Max.
Units
When configure as SCL/SDA pins
VIH
LVTTL input high voltage
0.7*VDD
GND
-1
5.5
V
LVTTL input low voltage
Input High-level current
Input Low-level current
0.3*VDD
V
VIL
IIH
VIH = VDD33
VIL = 0
1
1
uA
uA
V
IIL
-1
LVTTL high level output voltage IOH=-8mA
2.4
VOH
LVTTL low level output voltage
IOL= 8mA
0.4
V
VOL
When configure as Aux channel pins
VCM
Common mode voltage
0
2.0
V
V
VAUX (diff-pp)
Peak to peak differential voltage
0.19
1.26
VIN = -0.3V to +0.4V
ION= -40mA
RON
On resistance
11
20
Ω
BW3dB
3dB Bandwidth
440
MHz
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DP Differential
Symbol
Parameters
Condition
Min.
Typ.
Max.
Units
DP differential Input
VID
Peak to peak differential input voltage
400
1200
15%*VDD33
25%*VDD33
10
mV
V
VODO
VODU
IOFF
Differential overshoot voltage
Differential undershoot voltage
Single end standby current
Output short current
V
uA
mA
ISC
60
DP differential Output
V
Differential pk-pk level 1
340
510
400
600
460
680
mV
mV
mV
mV
tx diff-lev1
V
Differential pk-pk level 2
Differential pk-pk level 3
Differential pk-pk level 4
tx diff-lev2
V
690
800
920
tx diff-lev3
V
1020
1200
1380
tx diff-lev4
Pre-emphasis level
0dB
V
tx diff = 1.2V
tx diff = 0.8V
tx diff = 0.6V
tx diff = 0.4V
0
0
0
dB
dB
dB
dB
3.5dB (1.5x)
6dB (2x)
V
2.8
4.8
7.6
3.5
6
4.2
7.2
11.4
V
9.5dB (3x)
V
9.5
DP differential output CML driver AC Switching Characteristics
T
rise / T
Rise and Fall Time
20% to 80 %
80
115
150
50
ps
ps
ps
fall
T
Intra-pair differential skew
Intra-pair differential skew
sk(D)
T
50
sk(O)
VBIAS
1.2V
50Ω
50Ω
50Ω
50Ω
Tx
Rx
VD+ VID
VD-
VZ
VY
VID = (VD+) - (VD-)
VICM = (VD+) + (VD-)
VID = VY - VZ
VOCM = VY + VZ
Figure 5-1: DisplayPort Main Link Test Circuit
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TSK_INTRA
TSK_INTRA
OUTxP
50%
OUTxN
OUTyP
TSK_INETER
50%
OUTyN
Figure 5-2: DisplayPort Main Link Intra-Skew Measurement
VIN
80%
0V
20%
VOUT
tR
tF
80%
VOD
0V
20%
tPHL
tPLH
Figure 5-3: Rising and Falling Time Definition
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6. Application
Note
Information in the following applications sections is not part of the component specification, and does not warrant its ac-
curacy or completeness. Customers are responsible for determining suitability of components for their purposes. Cus-
tomers should validate and test their design implementation to confirm system functionality.
6.1 Application Circuit Diagrams
•
SCL_DDC and SDA_DDC can be float, if unused.
5
4
3
2
1
Dual-mode DP Source
PI3DPX1202
INxP
INxN
OUTxP
OUTxN
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
D
D
C
B
A
DP Connector
AUX_SRCP
AUX_SRCN
SCL_DDC
SDA_DDC
0.1u_0402
0.1u_0402
Aux Listener & Switch
AUX_SNKP
AUX_SNKN
100K
100K
C
B
A
Separate AUX &
DDC Channels
+3V3
CAD_SRC
CAD_SNK
1M
HPD_SRC
HPD_SNK
200K
EQ
OC_[1:0]
OP_[1:0]
CNTRL
ENABLE
AUTO_EQ
Title
PI3DPX1202 DP Source App Diagram, Separate AUX & DDC
Size
Document Number
Rev
A
Date:
Sheet
of
Friday, November 04, 2016
2
1
2
5
4
3
1
Figure 6-1: DP++ Source Application with combined Aux/DDC Channels
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5
4
3
2
1
Dual-mode DP Source
PI3DPX1202
INxP
INxN
OUTxP
OUTxN
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
D
C
B
A
D
DP Connector
Combined AUX &
DDC Channels
AUX_SRCP
Aux Listener & Switch
AUX_SRCN
0.1u_0402
0.1u_0402
AUX_SNKP
AUX_SNKN
SCL_DDC
SDA_DDC
+3V3
100K
100K
C
B
A
2K
2K
47K
+3V3
CAD_SRC
CAD_SNK
1M
NDS0605
BSS138
0.1u_0402
+3V3
HPD_SRC
HPD_SNK
200K
EQ
OC_[1:0]
OP_[1:0]
CNTRL
ENABLE
AUTO_EQ
Title
PI3DPX1202 DM DP Source App Diagram, Combined AUX & DDC
Size
Document Number
Rev
A
Date:
Sheet
of
Friday, November 04, 2016
2
2
2
5
4
3
1
Figure 6-2: DP Source Application with separate Aux/DDC Channels
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6.2 PCB Layout Guideline
As transmission data rate increases rapidly, any flaws and/or mis-matches on PCB layout are amplified in terms of signal integrity.
Layout guideline for high-speed transmission is highlighted in this application note.
AC coupling Capacitor
Below is an example of placing AC coupling capacitors on high-speed channels.
Location
To wisely use the equalization selections offered by PI3DPX1202, it is recommended to place PI3DPX1202 at the end of the entire
path. In short, PI3DPX1202 should be located close to the output DP connector in a source application. Below is the PI3DPX1202
placement on its evaluation board.
Thermal Pad GND Via Recommendation
To wisely use the equalization selections offered by PI3DPX1202, it is recommended to place PI3DPX1202 at the end of the entire
path. In short, PI3DPX1202 should be located close to the output DP connector in a source application. Below is the PI3DPX1202
placement on its evaluation board .
Several GND vias are the “must” requirement in thermal pad. e recommended Via size is 12/24 mil.
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General Power and Ground Guideline
To provide a clean power supply for Diodes high-speed device, few recommendations are listed below:
•
Power (VDD) and ground (GND) pins should be connected to corresponding power planes of the printed circuit board directly
without passing through any resistor.
•
•
e thickness of the PCB dielectric layer should be minimized such that the VDD and GND planes create low inductance paths.
One low-ESR 0.1uF decoupling capacitor should be mounted at each VDD pin or should supply bypassing for at most two VDD
pins. Capacitors of smaller body size, i.e. 0402 package, is more preferable as the insertion loss is lower. e capacitor should be
placed next to the VDD pin.
•
•
•
One capacitor with capacitance in the range of 4.7uF to 10uF should be incorporated in the power supply decoupling design as
well. It can be either tantalum or an ultra-low ESR ceramic.
A ferrite bead for isolating the power supply for Diodes high-speed device from the power supplies for other parts on the printed
circuit board should be implemented.
Several thermal ground vias must be required on the thermal pad. 25-mil or less pad size and 14-mil or less finished hole are
recommended.
V DD P la ne
Bypass noise
Power Flow
10uF
Several Thermal GND Vias must
be required on the Thermal Pad area
1uF
VIN
Center Pad
0.1uF
GND Plane
VIN
0.1uF
G N D P la ne
VIN
0.1uF
Figure 6-3: Decoupling Capacitor Placement Diagram
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High-speed signal Routing
Well-designed layout is essential to prevent signal reflection:
•
•
For 90Ω differential impedance, width-spacing-width micro-strip of 6-7-6 mils is recommended; for 100Ω differential imped-
ance, width-spacing-width micro-strip of 5-7-5 mils is recommended.
Differential impedance tolerance is targeted at 15ꢀ.
Figure 6-4: Trace Width and Clearance of Micro-strip and Strip-line
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•
For micro-strip, using 1/2oz Cu is fine. For strip-line in 6+ PCB layers, 1oz Cu is more preferable.
Figure 6-5: 4-Layer PCB Stack-up Example
Figure 6-6: 6-Layer PCB Stack-up Example
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•
Ground referencing is highly recommended. If unavoidable, stitching capacitors of 0.1uF should be placed when reference plane
is changed.
Figure 6-7: Stitching Capacitor Placement
•
•
To keep the reference unchanged, stitching vias must be used when changing layers.
Differential pair should maintain symmetrical routing whenever possible. e intra-pair skew of micro-strip should be less than
5 mils.
•
•
To keep the reference unchanged, stitching vias must be used when changing layers.
Differential pair should maintain symmetrical routing whenever possible. e intra-pair skew of micro-strip should be less than
5 mils.
Figure 6-8: Layout Guidance of Matched Differential Pair
•
•
•
For minimal crosstalk, inter-pair spacing between two differential micro-strip pairs should be at least 20 mils or 4 times the
dielectric thickness of the PCB.
Wider trace width of each differential pair is recommended in order to minimize the loss, especially for long routing. More con-
sistent PCB impedance can be achieved by a PCB vendor if trace is wider.
Differential signals should be routed away from noise sources and other switching signals on the printed circuit board.
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•
To minimize signal loss and jitter, tight bend is not recommended. All angles α should be at least 135 degrees. e inner air gap
A should be at least 4 times the dielectric thickness of the PCB.
Figure 6-9: Layout Guidance of Bends
•
Stub creation should be avoided when placing shunt components on a differential pair.
Figure 6-10: Layout Guidance of Shunt Component
•
Placement of series components on a differential pair should be symmetrical.
Figure 6-11: Layout Guidance of Series Component
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•
Stitching vias or test points must be used sparingly and placed symmetrically on a differential pair.
Figure 6-12: Layout Guidance of Stitching Via
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6.3 DisplayPort 1.2 Test Report
Internal DisplayPort test setup is shown below for the reference.
Figure 6-13: DisplayPort Test Set-up
Table 6-1: CTS Trace card insertion loss information
DP FR4 trace
0 in
6 in
12 in
18 in
24 in
30 in
36 in
Insertion loss @
5.4Gbps
-5.27 dB
-7.24 dB
-9.21 dB
-11.75 dB
-13.28 dB
-15.27 dB
-19.08 dB
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Figure 6-14: DisplayPort 1.2 Compliance Test Report
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7. Mechanical/Packaging
7.1 Package Mechanical Outline
UNIT: mm
DATE: 0345/09/12
Notes:
1. All dimensions are in millimeters, angles are in degrees.
2. Coplanarity applies to the exposed thermal pad as well as the terminals.
3. Refer JEDEC MO-220
DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZB48
REVISION: B
DOCUMENT CONTROL #: PD-2080
12-0459
Figure 7-1: Package TQFN-48 (ZB) Mechanical Outline Dimension
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Figure 7-2: TQFN-48 (ZB) ermal Via Pad Area
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7.2 Part Marking Information
Our standard product mark follows our standard part number ordering information, except for those products with a speed letter
code. e speed letter code mark is placed aꢀer the package code letter, rather than aꢀer the device number as it is ordered. Aꢀer
electrical test screening and speed binning has been completed, we then perform an “add mark” operation which places the speed
code letter at the end of the complete part number.
PI 3 X1X2X3 X1X2X3X4X5 X1X2 XX I ꢀ X
Pꢇcꢗꢇꢆꢅnꢆ
ꢅ.eꢈ ꢘꢍꢇnꢗ ꢉ ꢌubeꢙ X ꢉ ꢌꢇꢊe ꢚ Reeꢍ
Pb-ꢏree
ꢅ.eꢈ ꢀ ꢉ Pb-ꢄree ꢚ ꢓreen
ꢌemꢊerꢇture Rꢇnꢆe
ꢅ.eꢈ ꢘꢍꢇnꢗꢉꢃommerꢅꢇꢍ temꢊꢋ IꢉInꢁuꢎtrꢅꢇꢍ temꢊ
Pꢇcꢗꢇꢆe ꢃoꢁe
X1:Proꢁuct Sꢗeꢛ ꢚ X2:ꢖerꢎꢅon
ꢅ.eꢈ ꢘꢍꢇnꢗ ꢉ 1ꢎt reꢍeꢇꢎeꢋ ꢘ1 ꢉ ꢌꢐꢊe ꢘ ꢇnꢁ ꢖerꢎꢅon 1
Proꢁuct Iꢂ ꢃonꢄꢅꢆurꢇtꢅon
ꢅ.eꢈ X1X2ꢉ Dꢇtꢇ Sꢊeeꢁꢋ X3ꢉꢌotꢇꢍ Iꢂ ꢊortꢎꢋ X4ꢉ Port ꢅnꢋ X5ꢉ Port out
Devꢅce ꢏꢇmꢅꢍꢐ ꢃoꢁe: X1X2: Protocoꢍꢋ X3:ꢌecꢑnoꢍoꢆꢐ
ꢅ.eꢈ DPX ꢉ DꢅꢎꢊꢍꢇꢐPort Reꢁrꢅverꢋ ꢀꢒX ꢉ ꢓenerꢅc Reꢁrꢅverꢋ ꢔDꢌꢉꢔDꢕI Retꢅmer
Iꢂ ꢖoꢍtꢇꢆe ꢃoꢁe
ꢅ.eꢈ 3 ꢉ 3.3ꢖ
PI ꢉ Perꢅcom
Figure 7-3: General Part marketing information
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7.3 Tape & Reel Materials and Design
Carrier Tape
e Pocketed Carrier Tape is made of Conductive Polystyrene plus Carbon material (or equivalent). e surface resistivity is 106
Ohm/sq. maximum. Pocket tapes are designed so that the component remains in position for automatic handling aꢀer cover tape is
removed. Each pocket has a hole in the center for automated sensing if the pocket is occupied or not, thus facilitating device removal.
Sprocket holes along the edge of the center tape enable direct feeding into automated board assembly equipment. See Figures 3 and 4
for carrier tape dimensions.
Cover Tape
Cover tape is made of Anti-static Transparent Polyester film. e surface resistivity is 107Ohm/Sq. Minimum to 1011Ohm sq. maxi-
mum. e cover tape is heat-sealed to the edges of the carrier tape to encase the devices in the pockets. e force to peel back the
cover tape from the carrier tape shall be a MEAN value of 20 to 80gm (2N to 0.8N).
Reel
e device loading orientation is in compliance with EIA-481, current version (Figure 2). e loaded carrier tape is wound onto ei-
ther a 13-inch reel, (Figure 4) or 7-inch reel. e reel is made of Anti-static High-Impact Polystyrene. e surface resistivity 107Ohm/
sq. minimum to 1011Ohm/sq. max.
NOTE: LABELS TO BE PLACED ON
THE REEL OPPOSITE PIN 1
BARCODE LABEL
TOP
COVER
TAPE
SPROCKET
HOLE (ROUND)
CARRIER TAPE
EMBOSSED CAVITY
Figure 7-4: Tape & Reel label information
Top Left
PIN 1
Top Right
PIN 1
ORIENTATION
ORIENTATION
CARRIER TAPE
COVER TAPE
START
END
TRAILER
COMPONENTS
LEADER
COVER
TAPE
Bottom Left
PIN 1
ORIENTATION
Figure 7-5: Tape leader and trailer pin 1 orientations
PI3DPX1202A
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September 2017
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Round Sprocket Holes
Cover
Tape
T
(10 pitches cumulative
tolerance on tape ±0.2mm
Po
Do
T1
E1
Ao
P2
F
Embossed
Cavity
Bo
So
B1
S1
Ko
W
R (min)
D1
P1
Center lines of Cavity
T2
Direction of Unreeling
Figure 7-6: Standard embossed carrier tape dimensions
Table 7-1: Constant Dimensions
Tape
Size
D0
D1 (Min)
E1
P0
P2
R(See Note 2)
25
S1 (Min)
0.6
T (Max)
0.6
T1 (Max)
8mm
1.0
2.0 0.05
12mm
16mm
24mm
32mm
44mm
1.5 +0.1
-0.0
1.5
2.0
30
50
1.75 0.1
4.0 0.1
0.1
2.0 0.1
N/A
(See Note 3)
2.0 0.15
Table 7-2: Variable Dimensions
Tape
Size
P1
B1 (Max)
E2 (Min)
F
So
T2 (Max.)
W (Max)
A0, B0, & K0
8mm
Specific per package
type. Refer to FR-0221
(Tape and Reel Packing
Information)
4.35
8.2
6.25
10.25
14.25
22.25
N/A
3.5 ± 0.05
5.5 ± 0.05
7.5 ± 0.1
2.5
6.5
8.0
8.3
12mm
16mm
24mm
32mm
44mm
12.3
16.3
24.3
32.3
44.3
N/A (see note 4)
12.1
20.1
23.0
35.0
See Note 1
11.5 ± 0.1
14.2 ± 0.1
20.2 ± 0.15
12.0
16.0
28.4± 0.1
40.4 ± 0.1
N/A
NOTES:
1. A0, B0, and K0 are determined by component size. e cavity must restrict lateral movement of component to 0.5mm maximum for 8mm and 12mm wide tape
and to 1.0mm maximum for 16,24,32, and 44mm wide carrier. e maximum component rotation within the cavity must be limited to 20o maximum for 8 and 12 mm
carrier tapes and 10o maximum for 16 through 44mm.
2. Tape and components will pass around reel with radius “R” without damage.
3. S1 does not apply to carrier width ≥32mm because carrier has sprocket holes on both sides of carrier where Do≥S1.
4. So does not exist for carrier ≤32mm because carrier does not have sprocket hole on both side of carrier.
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September 2017
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Access ꢃole at
Slot ꢄocation (40 mm min ꢀia)
ꢁ
ꢅ3
ꢅ2(measꢆred at ꢇꢆꢈ)
ꢀ
A
ꢂ
ꢅ1(measꢆred at ꢇꢆꢈ)
ꢅidtꢇꢉ2.5mm ꢊinꢋ
ꢀeptꢇꢉ10.0mm ꢊin
Table 7-3: Reel dimensions by tape size
Tape Size
A
N (Min)
See Note A
W1
W2(Max)
W3
B (Min)
C
D
(Min)
8mm
178
8.4 +1.5/-0.0 mm
12.4 +2.0/-0.0 mm
14.4 mm
18.4 mm
60 2.0mm or
100 2.0mm
2.0mm or
12mm
Shall Ac-
330 2.0mm
commodate
Tape Width
Without
13.0 +0.5/-
0.2 mm
16mm
24mm
32mm
44mm
16.4 +2.0/-0.0 mm
24.4 +2.0/-0.0 mm
32.4 +2.0/-0.0 mm
44.4 +2.0/-0.0 mm
22.4 mm
30.4 mm
38.4 mm
50.4 mm
1.5mm
20.2mm
330 2.0mm
100 2.0mm
Interference
NOTE:
A. If reel diameter A=178 2.0mm, then the corresponding hub diameter (N(min) will by 60 2.0mm. If reel diameter A=330 2.0mm, then the corresponding hub
diameter (N(min)) will by 100 2.0mm.
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8. Important Notice
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS
DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
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accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized applica-
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is document is written in English but may be translated into multiple languages for reference. Only the English version of this
document is the final and determinative format released by Diodes Incorporated.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without
the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the
labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or
systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concern-
ing their products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstand-
ing any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further, Customers must
fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated prod-
ucts in such safety-critical, life support devices or systems.
Copyright © 2016, Diodes Incorporated
www.diodes.com
--
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