PI6C49S1510ZDIE [DIODES]
Low Skew Clock Driver, 6C Series, 20 True Output(s), 0 Inverted Output(s), TQFN-48;
| 型号： | PI6C49S1510ZDIE |
| 厂家： | 
DIODES INCORPORATED |
| 描述： | Low Skew Clock Driver, 6C Series, 20 True Output(s), 0 Inverted Output(s), TQFN-48 驱动 逻辑集成电路 |
| 文件： | 总17页 (文件大小：3153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C49S1510
High Performance Differential Fanout Buffer
Features
Description
ꢀÎ10 differential outputs with 2 banks
e PI6C49S1510 is a high performance fanout buffer device-
which supports up to 1.5GHz frequency. It also integrates a
unique feature with user configurable output signaling stan-
dards on per bank basis which provide great flexibilities to
users. e device also uses Pericom's proprietary input detection
technique to make sure illegal input conditions will be detected
and reflected by output states. is device is ideal for systems
that need to distribute low jitter clock signals to multiple desti-
nations.
ꢀÎUser configurable output signaling standard for each bank:
LVDS or LVPECL or HCSL
ꢀÎLVCMOS reference output up to 200MHz
ꢀÎUp to 1.5GHz output frequency for differential outputs
ꢀÎUltra low additive phase jitter: < 0.03 ps (typ) (differential
156.25MHz, 12KHz to 20MHz integration range); < 0.02 ps
(typ) (differential 156.25MHz, 10kHz to 1MHz integration
range)
ꢀÎSelectable reference inputs support either single-ended
Applications
ꢀÎNetworking systems including switches and Routers
or differential or Xtal
ꢀÎLow skew between outputs within banks (<40ps)
ꢀÎLow delay from input to output (Tpd typ. < 1.7ns)
ꢀÎSeparate Input output supply voltage for level shiꢀing
ꢀÎ2.5V / 3.3V power supply
ꢀÎHigh frequency backplane based computing and telecom
platforms
ꢀÎIndustrial temperature support
ꢀÎTQFN-48 package
Block Diagram
Pin Configuration (48-Pin TQFN)
OPMODEA[1:0]
48 47 46 45 44 43 42 41 40 39 38 37
1
QA[0:4]
QAO+
QAO-
QA1+
QA1-
36
35
34
33
32
31
30
29
28
27
26
25
QBO+
QBO-
QB1+
QB1-
5
2
3
X1
OSC
X2
4
OPMODEB[1:0]
IN0+
IN0-
5
V
V
DDO
DDO
QB[0:4]
5
6
QA2+
QA2-
QB2+
QB2-
IN1+
IN1-
7
Ref_Out
8
V
V
DDO
DDO
9
QA3+
QA3-
QA4+
QA4-
QB3+
QB3-
QB4+
QB4-
IN_SEL[1:0]
10
11
12
Sync_OE
Iref
Sync
13 14 15 16 17 18 19 20 21 22 23 24
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Pinout Table
Pin #
Pin Name
Type
Description
QA0+
QA0-
QA1+
QA1-
VDDO
QA2+
QA2-
QA3+
QA3-
QA4+
QA4-
GND
Bank A differential output pair 0. Pin selectable
LVPECL/LVDS/HCSL interface levels.
1,2
Output
Bank A differential output pair 1. Pin selectable
LVPECL/LVDS/HCSL interface levels.
3,4
Output
Power
5,8,29,32,45
6,7
Power supply pins for IO
Bank A differential output pair 2. Pin selectable
LVPECL/LVDS/HCSL interface levels.
Output
Bank A differential output pair 3. Pin selectable
LVPECL/LVDS/HCSL interface levels.
9,10
Output
Output
Bank A differential output pair 4. Pin selectable
LVPECL/LVDS/HCSL interface levels.
11,12
13,18,24,37,43,48
Power
Input
Power
Input
Power supply ground
Output mode select for Bank A. See Table 2 for func-
tions, LVCMOS/LVTTL interface levels
14,47
15,42
16
OPMODEA
VDD
Pulldown
Power supply pins
XTAL input, can also be used as single ended input
pin
X1
XTAL output. If X1 is used as a single ended input
pin, X2 is to be leꢀ open
17
X2
Output
Input clock sele ct. See Table 1 for function. LVC-
MOS/LVTTL interface levels.
19,22
20
IN_SEL
IN0+
Input
Input
Input
Pulldown
Pulldown
Reference input 0
Pull-up/
Pulldown
21
IN0-
Inverted reference input 0, internal bias to VDD/2
Output mode select for Bank B. See Table 2for func-
tions, LVCMOS/LVTTL interface levels
23,39
26,25
OPMODEB
Input
Pulldown
QB4+
QB4-
QB3+
QB3-
QB2+
QB2-
QB1+
QB1-
Bank B differential output pair 4. Pin selectable
LVPECL/LVDS/HCSL interface levels.
Output
Bank B differential output pair 3. Pin selectable
LVPECL/LVDS/HCSL interface levels.
28,27
31,30
34,33
Output
Output
Output
Bank B differential output pair 2. Pin selectable
LVPECL/LVDS/HCSL interface levels.
Bank B differential output pair 1. Pin selectable
LVPECL/LVDS/HCSL interface levels.
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Pinout Table (Continued..)
Pin #
Pin Name
QB0+
Type
Description
Bank B differential output pair 0. Pin selectable
LVPECL/LVDS/HCSL interface levels.
36,35
Output
QB0-
A fixed precision resistor (475ohm) from this pin to
ground provides a reference current for HCSL mode.
If LVPECL or LVDS mode chosen, pin can be leꢀ
open
38
40
Iref
Output
Input
Pull-up/
Pulldown
IN1-
Inverted reference input, internal bias to VDD/2
41
44
IN1+
Input
Pulldown
Reference input 1
Ref_Out
Output
Reference output, CMOS
Synchronous output enable for Ref_Out, see Table 3
for functions
46
Sync_OE
Input
Pulldown
Function Table
Table 1: Input select function
IN_SEL [1]
IN_SEL [0]
Function
0
0
1
0
IN0 is the selected reference input
IN1 is the selected reference input
XTAL is the selected input
1
X
Table 2: Output Mode select function
OPMODEA/B [1]
OPMODEA/B [0]
Output Bank A / Bank B Mode
0
0
1
1
0
1
0
1
LVPECL
LVDS
HCSL
Hi-Z
Table 3: Reference output enable function
Sync_OE
Ref_Out
0
1
Hi-Z
Output enabled
Table 4: Illegal input level function
Input illegal status
Output status
Input open
Logic Low
Logic Low
Logic Low
Input both high
Input both low
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Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested)
Note:
Storage temperature...................................................-55 to +150ºC
Supply Voltage to Ground Potential (VDD)............. -0.5 to +4.6V
Inputs (Referenced to GND) ............................. -0.5 to VDD+0.5V
Clock Output (Referenced to GND)................. -0.5 to VDD+0.5V
Latch up..................................................................................200mA
ESD Protection (Input) ..................................2000 V min (HBM)
Junction Temperature ................................................. 125 °C max
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. is
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Power Supply Characteristics and Operating Conditions
Symbol
Parameter
Test Condition
Min.
2.375
2.375
Typ.
Max.
3.465
3.465
120
Units
Core Supply Voltage
Output Supply Voltage
Core Power Supply Current
V
V
VDD
VDDO
IDD
90
All LVPECL outputs unloaded
All LVDS outputs loaded
110
110
70
145
125
120
85
mA
°C
Output Power Supply Current
IDDO
All HCSL outputs unloaded
Ambient Operating Temperature
-40
TA
DC Electrical Specifications - Differential Inputs
Symbol
Parameter
Min.
Typ.
Max.
Units
uA
uA
PF
Input High current
Input Low current
Input capacitance
Input high voltage
Input low voltage
150
IIH
Input = VDD
Input = GND
-150
IIL
3
CIN
VIH
VIL
V
VDD+0.3
-0.3
V
Input Differential Amplitude
PK-PK
0.15
V
VID
VDD-0.85
VDD-0.85
Common model input voltage
MUX isolation
GND + 0.5
V
VCM
ISOMUX
-89
dBc
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DC Electrical Specifications - LVCMOS Inputs
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
Input High current
150
uA
IIH
Input = VDD
Input Low current
Input high voltage
Input low voltage
Input high voltage
Input low voltage
Input = GND
VDD=3.3V
VDD=3.3V
VDD=2.5V
VDD=2.5V
-150
2.0
uA
V
IIL
VIH
VIL
VIH
VIL
VDD+0.3
0.8
-0.3
1.7
V
V
VDD+0.3
0.7
-0.3
V
DC Electrical Specifications- LVPECL Outputs
Parameter
Description
Conditions
Min.
Typ.
Typ.
Max.
Units
Output High voltage
V
VOH
VDDO-1.4
VDDO-0.9
Output Low voltage
V
VOL
VDDO-2.1
VDDO-1.7
DC Electrical Specifications- LVDS Outputs
Parameter
Description
Conditions
Min.
Max.
Units
Output High voltage
Output Low voltage
1.433
1.064
1.25
V
V
V
VOH
VOL
Vocm
Output commode voltage
Change in Vocm between com-
pletely output states
DVocm
50
mV
W
Ro
Output impedance
85
140
DC Electrical Specifications – HCSL Outputs
Parameter
Description
Conditions
Min.
Typ.
Max.
900
Units
Output High voltage
Output Low voltage
520
mV
mV
VOH
VOL
-150
150
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DC Electrical Specifications – LVCMOS Output
Parameter Description
Conditions
Min.
2.3
Typ.
Max.
Units
V
V
V
V
V
V
V
V
Ω
Ω
VDDO=3.3V +/-5%, IOH = 8mA
Output High voltage
VOH
VOL
VOH
1.5
V
DDO=2.5V +/- 5%, IOH = 8mA
VDDO=3.3V +/-5%, IOL = -8mA
DDO=2.5V +/- 5%, IOL = -8mA
VDDO=3.3V +/-5%, IOH = 24mA
DDO=2.5V +/- 5%, IOH = 16mA
VDDO=3.3V +/-5%, IOL = -24mA
DDO=2.5V +/- 5%, IOL = -16mA
0.5
0.4
Output Low voltage
Output High voltage
V
2.1
1.5
V
1
Output Low voltage
Output Impedance
VOL
RIUT
0.8
V
VDDO = 3.3V 5%
17
22
VDDO = 2.5V 5%
AC Electrical Specifications – Differential Outputs
Parameter Description
Conditions
Min.
Typ.
Max. Units
LVPECL, LVDS
HCSL
1500
MHz
250
Clock output frequency
FOUT
LVPECL
LVDS
120
120
350
120
120
350
150
150
300
Output rise time
From 20% to 80%
300
550
300
300
550
ps
Tr
HCSL
LVPECL
LVDS
150
150
Output fall time
From 80% to 20%
ps
Tf
HCSL
LVPECL,
HCSL
48
52
Output duty cycle
Frequency<650MHz
%
TODC
LVDS
47
53
LVPECL outputs @ <1GHz
LVPECL outputs @ >1GHz
LVDS outputs
500
400
250
1000
Output swing Single-ended
mV
VPP
500
156.25MHz, 12kHz to 20MHz
156.25MHz, 10kHz to 1MHz
HCSL
0.03
0.02
460
ps
Buffer additive jitter RMS
Absolute crossing voltage
T
j
ps
mV
mV
VCROSS
Total variation of crossing voltage HCSL
10 outputs devices,
140
70
DVCROSS
outputs in same
tank, with same load,
at DUT.
Output Skew
40
ps
TSK
LVPECL, LVDS @ 3.3V, 100MHz
HCSL @ 3.3V, 100MHz
1650
2000
ps
ps
Propagation Delay
TPD
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Valid to HiZ
200
ns
ns
ps
TOD
TOE
HiZ to valid
Part to Part Skew1
200
200
TP2P Skew
Notes:
1. is parameter is guaranteed by design
AC Electrical Specifications – CMOS
Parameter Description
Conditions
Min.
Typ.
Max. Units
XTAL input
Reference input
XTAL input
Reference input
CL = 10pF
10
50
MHz
MHz
ps
Ref_Out frequency
FOUT
200
0.3
Buffer additive jitter RMS
T
j
0.03
1.5
ps
Rise time, Fall time
Output duty cycle
ns
tr/ tf
TODC
tPD
45
55
%
CL = 10pF
Propagation delay
3.3V, 25MHz
2700
ps
Setup time
300
2
ps
tS
Clock edge to output disable
Clock edge to output enable
Ref_Out
Ref_Out
4
4
cycles
cycles
tSOD
tSOE
2
Crystal Characteristics
Parameter
Min.
Typ.
Max.
Units
Mode of Oscillation
Frequency Range
Fundamental
10
50
70
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Load Capacitance
pF
10
18
500
pF
Drive Level
µW
Recommended Crystals
Pericom recommends:
a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf
b) FY2500091, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm
http://www.pericom.com/pdf/datasheets/se/FL.pdf
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Propagation Delay
Output Skew
Output Skew T
SK
Propagation Delay T
PD
V
OH
IN+/IN-
CLKn
V
OL
T
PLHx
T
PHLx
V
OH
IN+/IN-
QA/QB
tPD
t
PD
V
OL
V
OH
T
SK
TSK
V
OH
V
OL
CLKn+1
V
OL
t
R
tF
T
PLHy
TPHLy
T
SK = TPLHy - TPLHx or TSK = TPHLy - TPHLx
Part to Part Skew
Part-to-Part Skew
VOH
IN+/IN-
VOL
T
PLH1
T
PHL1
VOH
Part1 CLK
Part2 CLK
V
OL
TSK
T
SK
VOH
VOL
TPLH2
TPHL2
TSK = TPLH2 - TPLH1 or TSK = TPHL2 - TPHL1
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LVPECL/ LVDS Output Swing vs. Frequency
Propagation Delay vs. Temperature
1.5GHz LVEPCL/ LVDS Waveform
3.3V LVPECL Waveform
2.5V LVPECL Waveform
3.3V LVDS Waveform
2.5V LVDS Waveform
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Phase Noise and Additive Jitter
Output phase noise (Dark Blue) vs Input Phase noise (light blue)
Additive jitter is calculated at 156.25MHz~27fs RMS (12kHz to 20MHz). Additive jitter = √(Output jitter2 - Input jitter2)
Total phase jitter with 25MHz XTAL ~ 264fs RMS (12kHz ~20MHz)
Configuration Test Load Board Termination for LVPECL/ LVDS Outputs
LVPECL/ LVDS Buffer
VDDQx
Z = 50Ω
o
L = 0 ~ 10 in.
100Ω
Z = 50Ω
o
150Ω*
150Ω*
*Remove for LVDS
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Configuration Test Load Board Termination for HCSL Outputs
Rs
33Ω
5%
Clock
TLA
DUT
Rs
33Ω
5%
Clock#
TLB
2pF
5%
2pF
5%
Rp
49.9Ω
1%
Rp
49.9Ω
1%
475Ω
1%
Configuration Test Load Board Termination for LVCMOS Outputs
3.3V ±5%
V
V
DD
DDO
10pF
GND
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Application Information
Wiring the differential input to accept single ended levels
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is gener-
ated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and
R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is
only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609.
VDD
R1
1K
Single Ended
Clock Input
CLK
/CLK
C1
R2
0.1µ
1K
Figure 1. Single-ended input to Differential input device
Power Supply Filtering Techniques
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. All power pins should be individually connected to the power supply plane through vias,
and 0.1μF an 1μF bypass capacitors should be used for each pin.
VDD
VDD
0.1µF
1µF
VDDO
VDDO
0.1µF
1µF
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Single Ended Input, AC couple
Driving X1 with a Single Ended Input
0.1µF
0.1µF
Rs
0.1µF
Rs
0.1µF
X1
CMOS
Clock
CMOS
Clock
50Ω
50Ω
50Ω
Osc
50Ω
Differential
Clock
Input
Input
X2
0.1µF
Single Ended Input, DC couple
Single Ended Input, DC couple
VDD
100Ω
Rs
Rs
CMOS
Clock
CMOS
Clock
50Ω
50Ω
VDD
Differential
Clock
100Ω
Differential
Clock
Input
Input
0.1µF
0.1µF
LVPECL, DC Couple, Thevenin Equivalent
LVPECL, AC Couple, Thevenin Equivalent
VDDO
VDDO
RPU
RPD
RPU
0.1µF
QAn+/ QBn+
QAn+/ QBn+
VDDO
VDDO
RPD
RT
LVPECL
Driver
LVPECL
Driver
LVPECL
Receiver
LVPECL
Receiver
100Ω Differential
100Ω Differential
0.1µF
RPU
RPD
RPU
RPD
QAn-/ QBn-
QAn-/ QBn-
RT
VDDO RPU RPD
3.3V 120Ω 82Ω
2.5V 250Ω 62.5Ω
VDDO RT RPU RPD
3.3V 160Ω 120Ω 82Ω
2.5V 91Ω 250Ω 62.5Ω
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LVDS AC Couple at Load
LVDS DC Couple
0.1µF
QAn+/ QBn+
QAn+/ QBn+
kΩ
LVDS
Receiver
LVDS
Driver
LVDS
Driver
100Ω Differential
100Ω
Vbias
100Ω
100Ω Differential
kΩ
QAn-/ QBn-
QAn-/ QBn-
0.1µF
LVDS AC Couple with Internal Termination Single Ended LVPECL, DC Couple
VDDO - 2V
0.1µF
50Ω
QAn+/ QBn+
QAn+/ QBn+
50Ω
50Ω
LVDS
Driver
100Ω Differential
Vbias
50Ω
LVPECL
Driver
VDDO - 2V
QAn-/ QBn-
0.1µF
QAn-/ QBn-
50Ω
Single Ended LVPECL, DC Couple, Thevenin
Equivalent
Single Ended LVPECL, AC Couple, Thevenin
Equivalent
VDDO
0.1µF
RPU
Load
QAn+/ QBn+
QAn+/ QBn+
50Ω
50Ω
RT
50Ω
VDDO
LVPECL
Driver
RPD
LVPECL
Driver
VDDO RPU RPD
0.1µF
RPU
VDDO RT
3.3V 160Ω
2.5V 91Ω
3.3V 120Ω 82Ω
2.5V 250Ω 62.5Ω
QAn-/ QBn-
QAn-/ QBn-
RPD
RT
50Ω
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Clock IC crystal input guide
LVPECL/ LVDS AC and DC input
*Remove for LVDS
Clock IC
Rf
0.1uF
(For AC Couple Only)
IN+
C_in
XTL_IN
Cb
C_out
150Ω*
Input
Driver
100Ω Differential
XTL_OUT
100Ω
Cb
C2
IN-
Crystal (CL)
C1
0.1uF
(For AC Couple Only)
150Ω*
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Clock IC Crystal loading cap. design guide
Clock IC
Rf
CL =crystal spec. loading cap.
C_in/out = (3~5pF) of IC pin cap.
Cb = PCB trace (2~4pF)
C_in
XTL_IN
Cb
C_out
XTL_OUT
C1,C2 = load cap. of design
Cb
C2
Rd = 50 to 100ohm drive level limit
Crystal (CL)
C1
Design guide: C1=C2=2 *CL - (Cb +C_in/out) to meet target +/-ppm < 20 ppm
Example1: Select CL=18 pF crystal, C1=C2=2*(18pF) – (4pF+5pF)=27pF, check datasheet too
Example2: For higher frequency crystal (=>20MHz), can use formula C1=C2=2*(CL-6), can do fine tune of C1, C2 for more accurate
ppm if necessary
Thermal Information
Symbol
Description
Condition
ΘJA
ΘJC
23.65 °C/W
9.10 °C/W
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
Still air
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Packaging Mechanical: 48-Pin TQFN (ZD)
Ordering Information
Ordering Code
Package Code Package Type
Operating Temperature
PI6C49S1510ZDIE
PI6C49S1510ZDIEX
ZD
ZD
Pb-free & Green, 48-pin TQFN
Pb-free & Green, 48-pin TQFN, Tape & Reel
-40 °C to 85 °C
-40 °C to 85 °C
Notes:
1. ermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. “E” denotes Pb-free and Green
3. Adding an “X” at the end of the ordering code denotes tape and Reel packaging
Pericom Semiconductor Corporation • 1-800-435-2336
www.diodes.com
August 2016
© Diodes Incorporated
PI6C49S1510
Rev J
16-0147
17
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