PT7C4512WE [DIODES]

Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, GREEN, MS-012AA, SOIC-8;


型号：	PT7C4512WE
厂家：	DIODES INCORPORATED
描述：	Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, GREEN, MS-012AA, SOIC-8 时钟光电二极管外围集成电路晶体
文件：	总7页 (文件大小：483K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PT7C4512

PLL Clock Multiplier

Features

Description



Zero ppm multiplication error

This Clock Multiplier is the most cost-effective way to

generate a high quality, high frequency clock outputs from

lower frequency crystal or clock input. It is designed to

replace crystal oscillators in most electronic systems, clock

multipliers and frequency translation devices with low output

jitter. The device implements a standard fundamental mode

using PLL techniques and inexpensive crystal to produce

output clocks up to 200 MHz.

Input crystal frequency of 5 - 40 MHz

Input clock frequency of 4 - 50 MHz

Output clock frequencies up to 200 MHz

Low period jitter 80ps (100~200MHz)

Duty cycle of 45/55% of output clock up to 160MHz

9 selectable frequencies controlled by S0, S1 pins

Operating voltages of 3.0 to 5.5V

Lead free SOIC-8 package

The internal Logic divider is to generate nine different

popular multiplication factors, allowing one chip to output

many common frequencies.

Pin Configuration

Clock Output Table

Pin Description

Pin# Name

CLK

X4¹

Type Description

X1/ICLK

Crystal connection or clock input

Connect to +3.3V or +5V

M²

X(16/3)

VCC

GND

REF

CLK

Connect to ground

X2.5

Buffered crystal oscillator output clock

Clock output per Clock Output Table

Multiplier select pin 0, connect to GND

or V_CCor floating (no connection)

Multiplier select pin 1, connect to

GND or Vcc or floating (no

connection)

X(10/3)

Crystal connection. Leave unconnected

for clock input

Note:

1. CLK output frequency = ICLK X 4

2. M = Leave unconnected (self-biases to V^CC/2)

PT7C4512

www.diodes.com

February 2018

Document Number DS40692 Rev 2-2

PT7C4512

Block Diagram

External Components

Decoupling Capacitor

As with any high-performance mixed-signal IC, the PT7C4512 must be isolated from system power supply noise to perform

optimally. A decoupling capacitor of 0.01μF or 0.1uF must be connected between VCC and the GND. It must be connected close

to the PT7C4512 to minimize lead inductance. No external power supply filtering is required for the PT7C4512.

Series Termination Resistor

A 33Ω terminating resistor can be used next to the CLK pin for trace lengths over one inch.

Crystal Load Capacitors

There is no on-chip capacitance build-in chip. A parallel resonant, fundamental mode crystal should be used. The device crystal

connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to

adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can

only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces

(and no vias) between the crystal and device. Crystal capacitors, if needed, must be connected from each of the pins X1 and X2 to

ground. The value (in pF) of these crystal caps should equal CL*2. In this equation, CL= crystal load capacitance in pF. Example:

For a crystal with a 15 pF load capacitance, each crystal capacitor would be 30pF.

PT7C4512

www.diodes.com

February 2018

Document Number DS40692 Rev 2-2

PT7C4512

Maximum Rating

Note:

Storage Temperature………………………………….-60^oC to +150^oC

Junction Temperature………………………………...……+125^oC Max

Supply Voltage to Ground Potential (V_CC)……………..-0.3V to +7.0V

Inputs (Referenced to GND) ………………………-0.5V to V_CC+0.5V

Clock Output (Referenced to GND)… …………… -0.5V to V_CC+0.5V

Soldering Temperature (Max of 10 seconds)… …….260^oC (Max. 10s)

Stresses greater than those listed under MAXIMUM

RATINGS may cause permanent damage to the

device. This is a stress rating only and functional

operation of the device at these or any other

conditions above those indicated in the operational

sections of this specification is not implied.

Exposure to absolute maximum rating conditions

for extended periods may affect reliability.

Recommended Operating Conditions

Sym

V_CC

T_A

Parameter

Condition

Min

3.0

Typ

Max

5.5

Unit

Supply Voltage

Operating Temperature

-40

+85

^oC

DC Electrical Characteristics

(V_CC= 3.3±0.3V, T_A= -40~85^oC, unless otherwise noted)

Sym

V_CC

I_CC

Parameter

Test Condition

Min.

Typ.

3.3

Max.

Unit

Supply Voltage

Supply Current

VCC

3.6

No load, 20MHz crystal,

100MHz output

V_IH

V_IL

V_IH

V_IM

V_IL

V_OH

V_OL

I_S

Input Logic High

ICLK (V_CC/2)+1 V_CC/2

Input Logic Low

ICLK

S0, S1

CLK

V_CC/2 (V_CC/2)-1

Input Logic High

V_CC-0.5

Input Mid-level

V_CC/2

Input Logic Low

0.5

High-level Output Voltage

Low-level Output Voltage

Short Circuit Current

IOH = -12mA

IOL = 12 mA

2.4

CLK

0.4

CLK

±30

(V_CC= 5.0±0.5V, T_A= -40~85^oC, unless otherwise noted)

Sym

V_CC

I_CC

Parameter

Test Condition

Min.

Typ.

5.0

Max.

5.5

Unit

Supply Voltage

Supply Current

VCC

4.5

No load, 20MHz crystal,

100MHz output

V_IH

V_IL

V_IH

V_IM

V_IL

V_OH

V_OL

I_S

Input Logic High

ICLK (V_CC/2)+1 V_CC/2

Input Logic Low

ICLK

S0, S1

CLK

V_CC/2 (V_CC/2)-1

Input Logic High

V_CC-0.4

V_CC-0.5

Input Mid-level

V_CC/2

Input Logic Low

0.4

High-level Output Voltage

Low-level Output Voltage

Short Circuit Current

IOH = -12mA

IOL = 12 mA

CLK

0.4

CLK

±70

PT7C4512

www.diodes.com

February 2018

Document Number DS40692 Rev 2-2

PT7C4512

Test Circuits

1>Load circuit for output clock duty cycle, rise and fall time Measurement

2> Timing Definitions for output clock rise and fall time Measurement

PT7C4512

www.diodes.com

February 2018

Document Number DS40692 Rev 2-2

PT7C4512

AC Electrical Characteristics

(V_CC= 3.3±0.3V, T_A= -40~85^oC, unless otherwise noted)

Sym

Parameter

Test Condition

ICLK

CLK

Min.

Typ.

Max.

Unit

MHz

F_IN

Input Frequency

Crystal

Clock

Output Frequency ⁽²⁾

180

V_CC: 3.0 to 3.6V

F_OUT

t_R

Output Clock Rise Time

Output Clock Fall Time

Output Clock Duty Cycle

0.8 to 2.0V, with 15pF load

2.0 to 0.8V, with 15pF load

At V_CC/2, below 160MHz

t_F

Duty

At V_CC/2, 160MHz to

180MHz

PLL Bandwidth ⁽¹⁾

Period Jitter

kHz

70MHz~160MHz, 25C

CLK

120

Note:

1. Only reference for design

2. The phase relationship between input and output clocks can change at power up

(V_CC= 5.0±0.5V, T_A= -40~85^oC, unless otherwise noted)

Sym

Parameter

Test Condition

Crystal

Min.

Typ.

Max.

Unit

MHz

F_IN

Input Frequency

ICLK

CLK

Clock

F_OUT

t_R

Output Frequency ⁽²⁾

V_CC: 4.5 to 5.5V

200

20%V_CCto 80%V_CC, with

15pF load

80%V_CCto 20%V_CC, with

15pF load

Output Clock Rise Time

1.2

t_F

Output Clock Fall Time

Output Clock Duty Cycle

CLK

Duty

At V_CC/2, below 160MHz

CLK

At V_CC/2, 160MHz to

200MHz

PLL Bandwidth ⁽¹⁾

Period Jitter

kHz

70MHz~160MHz, 25C

CLK

120

Note:

1. Only reference for design

2. The phase relationship between input and output clocks can change at power up

Part Marking

W Package

PT7C4512

www.diodes.com

February 2018

Document Number DS40692 Rev 2-2

PT7C4512

Packaging Mechanical

8-SOIC (W)

For latest package info.

please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/

Ordering Information

Part Number

Package Code

Description

PT7C4512WEX

8-Pin, 150mil-Wide (SOIC)

Notes:

PT7C4512

www.diodes.com

February 2018

Document Number DS40692 Rev 2-2

PT7C4512

EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. All applicable RoHS exemptions applied.

See http://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, “Green” and

Lead-free.

Thermal characteristics can be found on the company web site at www.diodes.com/design/support/packaging/

E = Pb-free and Green

X suffix = Tape/Reel

IMPORTANT NOTICE

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TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY

JURISDICTION).

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any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or any product described herein; neither does

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released by Diodes Incorporated.

LIFE SUPPORT

Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of the Chief

Executive Officer of Diodes Incorporated. As used herein:

Life support devices or systems are devices or systems which:

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solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated products in such safety-critical, life support

devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify

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www.diodes.com

PT7C4512

www.diodes.com

February 2018

Document Number DS40692 Rev 2-2

PT7C4512WE [DIODES]

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