PT7V4050GACGB49.408/17.184 [DIODES]
PLL/Frequency Synthesis Circuit,;型号: | PT7V4050GACGB49.408/17.184 |
厂家: | DIODES INCORPORATED |
描述: | PLL/Frequency Synthesis Circuit, |
文件: | 总7页 (文件大小:127K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Features
Description
•
•
•
•
•
•
•
•
PLL with quartz stabilized VCXO
The device is composed of a phase-lock loop with an
integrated VCXO for use in clock recovery, data re-
timing, frequency translation and clock smoothing
applications in telecom and datacom systems.
Loss of signals alarm
Return to nominal clock upon LOS
Input data rates from 8 kb/s to 65 Mb/s
Tri-state output
Crystal Frequencies Supported: 12.000~50.000 MHz.
User defined PLL loop response
NRZ data compatible
Single +5.0V power supply
Block Diagram
RCLK
CLKIN
DATAIN
Phase Detector &
Loss Of Signal
Circuit
RDATA
LOS
HIZ
PHO
CLK1
VC
LOSIN
VCXO
Divider
CLK2
OPN
OPP
Op
Amp
OPOUT
Ordering Information
Frequencies using at CLK1 (MHz)
PT7V4050
T
B
C
G
A
49.408 / 12.352
CLK2 Frequency
12.000
12.288
16.384
18.936
24.576
30.720
38.880
47.457
12.624
16.777
20.000
24.704
32.000
40.000
49.152
19.440
13.00
16.896
20.480
25.000
32.768
41.2416
49.408
35.328
16.000
17.920
22.1184
27.000
33.330
41.943
50.000
40.960
16.128
18.432
22.579
28.000
34.368
44.736
DeviceType
CLK1 Frequency
16-pinclock recoverymodule
A: 5.0V supply voltage
B: 3.3V supply voltage
PackageLeads
T: Thru-Hole
G: Surface Mount
C: 20ppm
±
F: 32ppm
±
CLK2 Divider
±
G: 50ppm
H:
A: Divide by 2 E: Divide by 32
B: Divide by 4 F: Divide by 64
C: Divide by 8 G: Divide by 128
D: Divide by 16 H: Divide by 256
K: Disable
±
100ppm
Temperature Range
Note: CLK1 up to 40.960MHz for both 5V and
°
°
C
C: 0 C to 70
o
o
3.3V for temperature -40 Cto 85 C; CLK1 up to
°
°
C
T: -40 C to 85
o
o
50MHz for both 5V and 3.3V for temperature 0 C to 70 C.
PT0125(02/06)
Ver:2
1
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Pin Configuration
VC
1
16 V
CC
OPN 2
OPOUT 3
OPP 4
15 CLK1
14 HIZ
13 CLK2
12 RDATA
11 RCLK
10 LOS
LOSIN 5
PHO 6
DATAIN 7
GND 8
9 CLKIN
Pin Description
Pin No
Pin Name
Type
Description
VC
I
I
1
2
3
4
Control voltage input to internal voltage controlled crystal oscillator (VCXO).
Negative input terminal to internal operational amplifier.
Output terminal of internal operational amplifier.
OPN
OPOUT
OPP
O
I
Positive input terminal to internal operational amplifier.
TTL input. When LOSIN is set to HIGH, VC disabled, and when set to LOW, VC to
VCXO are enabled. (Internal pull-down resistor)
5
LOSIN
I
6
7
PHO
DATAIN
GND
O
I
Output signal of phase detector.
TTL input. Input data stream to phase detector.
Ground.
8
G
I
9
CLKIN
LOS
TTL input. Input clock to phase detector.
Signal loss indication for DATAIN, high active.
Output recovered clock.
10
11
12
13
O
O
O
O
RCLK
RDATA
CLK2
Output recovered data stream.
Output clock with divided function.
TTL input. When HIZ is set to LOW, the device is in standby state and the outputs are
set to high impedance. (Internal pull-up resistor)
14
15
HIZ
I
CLK1
VCC
O
P
Output clock of internal VCXO frequency.
5V power supply
16
Notes:
1. LOSIN input sets to HIGH, VC is disabled and the VCXO returns to its nominal center frequency. When sets to LOW, VC to
VCXO is enabled.
2. LOS output sets to HIGH, if no transitions are detected at DATAIN after 256 clock cycles. LOS output sets to LOW as soon
as a transition occurs at DATAIN.
3. HIZ input sets LOW, output pins CLK1, CLK2, RCLK, and RDATAbuffers are set to high-impedance state. When set to logic
high or no connection, the device functions and output pins CLK1, CLK2, RCLK, and RDATAetc. are active.
PT0125(02/06)
Ver:2
2
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested)
Note:
Stresses greater than those listed under MAXI-
Storage Temperature ........................................................ -55oCto+125oC
MUM RATINGS may cause permanent damage to
Power Supply Voltage ............................................................. -0.5to+7V
the device. This is a stress rating only and func-
Input High Voltage .................................................................... +7VMax.
tional operation of the device at these or any other
Input Low Voltage ....................................................................-0.5VMin.
conditions above those indicated in the operational
sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
DC Electrical Characteristics
Symbol
Parameters
Conditions
Min
Max
Units
VCC
ILEAK
VTIH
Supply Voltage
4.5
-10
2
5.5
10
V
µA
V
Input Leakage Current
TTL Input High Voltage
0~VDD
VTIL
TTL Input Low Voltage
0.8
0.4
V
V
VOH1
Output High Voltage for CLK1
& 2, RCLK&RDATA
Output Low Voltage for CLK1
& 2, RCLK&RDATA
Ioh = -8mA
Iol = 8mA
2.4
VOL1
V
VOH2
VOL2
Output High Voltage for LOS
Ioh = -3mA
Iol = 3mA
2.4
V
V
Output Low Voltage for LOS
Input Pull up Current for HIZ
0.4
50
IPULLUP
IPULLDOWN
-160
µA
µA
Input Pull down Current for
LOSIN
ICC
TA
Maximum Supply Current
Full Active
60
85
mA
oC
Ambient Temperature
-40
PT0125(02/06)
Ver:2
3
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
AC Electrical Characteristics
Parameter
Symbol
Min
Typical
Max
Unit
Input NRZ Data Rates
DATAIN
DATAIN
0.008
0.008
65.536
32.768
M b/s
M b/s
Input RZ Data and Clock Rates
Nominal Output Frequency
Clock Output 1
CLK1
CLK2
12.00
CLK1 /256
65.536
CLK1 /2
MHz
MHz
Clock Output 2
Transition Times:
Rise Time (0.5V to 2.5V)
Fall Time (2.5V to 0.5V)
tR
tF
0.5
0.5
5
5
ns
ns
Symmetry or Duty cycle (VS = 1.4V)
CLK1
CLK2
RCLK
SYM 1
SYM 2
RCLK
40
45
40
60
55
60
%
%
%
Control Voltage Bandwidth (-3 dB,VC =
0.5VCC)
BW
20
kHz
Sensitivity @ VC = VCC/2
100
ppm/V
∆F/∆VC
Nominal Output Frequency on Loss of Signal:
Clock Output 1 & 2
CLK1
CLK2
-75
-75
75
75
ppm from fo 1
ppm from fo 2
Phase Detector Gain
K D
0.53
V/rad
x Data
Density
PT0125(02/06)
Ver:2
4
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Packaging Information
16-pin Surface Mount (G)
20.32
10.16
2.54
1.2
20.32
PT0125(02/06)
Ver:2
5
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
16-pin Thru-Hole (T)
PT0125(02/06)
Ver:2
6
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Notes
Pericom Technology Inc.
Email: support@pti.com.cn
Web Site: www.pti.com.cn, www.pti-ic.com
China:
No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China
Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181
Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong
Tel: (852)-2243 3660 Fax: (852)- 2243 3667
U.S.A.:
2380 Bering Drive, San Jose, California 95131, USA
Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to
improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any
circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry
described herein is free from patent infringement or other rights, of Pericom Technology Incorporation.
PT0125(02/06)
Ver:2
7
相关型号:
©2020 ICPDF网 联系我们和版权申明