PT8R1202ND_技术文档

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

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Features

General Descriptions

y Compliant to Bluetooth Specification v1.2

The PT8R1202 is a part of the PTI Bluetooth product

y Seamless interface to PT8R1002 (BlueRF™ RF family. It is a DSP processor with the functionality of

transceiver) both baseband controller providing the Bluetooth™

y High speed UART, USB 1.1 interface with functionality for high data rate, short-distance wireless

hub/devices and host function, up to four channels communication in the free 2.4GHz ISM band and

8KHz PCM / CVSD codec, 16/18/20/24-bit I²S audio digital audio decoder such as MP3 or AC3. Together

input/output and SPDIF input/output interface, 2 with PT8R100X 2.4GHz radio transceiver IC and an

channel digital AMP interface

y Integrated 128MHz PTI own hybrid RISC and DSP Bluetooth system for data and voice communications.

PiCOII embedded processor with 24-bit PT8R1202 consists of BlueRF™ RXMODE2/3, 3-wires

external flash memory, it provides a fully compliant

multiplication and 48-bit accumulation and radio interface, Bluetooth™ baseband and bit processor,

128KByte on-chip SRAM enough to support several PTI proprietary 32-bit hybrid RISC/DSP embedded

digital audio and speech codecs

processor with 48bit resolution, and USB / UART /

y On-chip implementation of BT qualified Link PCM / DAC / I2S / SPDIF / SMC standard interfaces.

Controller, Link Manager, HCI, L2CAP, RFCOMM

and several profiles such as Headset, SPP, OBEX, The on-chip 32-bit hybrid RISC/DSP embedded

AV profiles, etc.

processor is powerful enough to support full rate

y Software development kit and source code licenses Bluetooth data communications as well as full rate

available for qualified embedded stacks and DSP digital audio decoding and includes large enough

firmware for popular digital audio and speech codecs

embedded SRAM up to 128KByte to support several

y Single reference clock for system, USB, audio sub applications without external memory, which results in

system

cost-effective and low-power consumption systems. In

combination with PTI own optimized Bluetooth™

baseband, embedded protocol stacks and audio decoder

firmware, it provides a complete cost-effective SOC

embedded solutions such as portable MP3 decoder,

wireless high quality speaker system or headset.

y 0.18um CMOS technology

Application

y Bluetooth portable audio players

y Stereo audio headset with HSP/HFP function

y Multi-functions USB dongle such as Bluetooth, USB

audio device, USB Flash storage, etc.

y Wireless high quality digital audio streaming system

for DVD/PC speaker

PT0137(08/04)

Ver:4

1

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

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Ordering Information

Device

Package

Order Number

Type

Size

Shipment Method

Tray

PT8R1202F

PT8R1202FX

PT8R1202FE

PT8R1202FEX

PT8R1202ND

PT8R1202NDX

PT8R1202NDE

PT8R1202NDEX

Normal

T&R

Tray

T&R

Tray

T&R

Tray

T&R

LQFP144

20 x 20 x 1.4mm

10 x 10 x 1.4mm

Pb(Lead) free

Normal

PT8R1202

fpBGA144

Pb(Lead) free

Block Diagram

MEM

IF

I-Cache

16KB

20bit address, 16bit data

Hybrid 32-bit RISC MCU &

24-bit DSP Core

I/O1

(2MB)

(IDE/

(V6@PiCOII-DSP,128MHz)

I/O0

(2MB)

(LCD)

SRAM

(2MB)

(option)

Flash

(2MB)

MMU &

DMA

YMEM2

16KB

Ethernet)

YMEM1

V6PB

Bridge

YMEM0 XMEM1

32KB

XMEM2

16KB

XMEM0

32KB

16KB

User Applications

PC

Phone

PDA

USB

(Multi-function

Devices or Host)

NAND

Flash

Controller

NAND

Flash

(2x2Gb)

System

registers

Interrupt /

Timer

DSP library

Network library

File System library

serial

NAND

GPIO

PTI

Stacks &

Profiles

Third party

Stacks &

Profiles

serial

GPIO (up to 56)

High speed UART

Bluetooth Controller

Bit Processor

(BT1.2 compliant)

Speech

Codec

HOST,

Off-chip

Debugger

HCI

Speech Codec

I/F

JTAG

OSC

serial

On chip debugger

-

BB/LM

Power

I2S Input,

SPDIF Input

Stereo

Audio

ADC

RTOS (VPOS ™, eCos ™)

PT8R1202 software

RTC

Mng

Multi-mode

RF transceiver I/F

(BlueRF RXMODE2/3

3-wires RF I/F)

32.768kHz

Serial

serial

.

Stereo

Audio

DAC

I2S Output,

SPDIF Output

SYSPLL AUDPLL

OSC

12/13/16/19.2MHz

Bluetooth

BlueRF

Radio

RXMODE2

PT8R1002

PT0137(08/04)

Ver:4

2

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

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Hybrid embedded RISC / DSP processor

Product Description

To satisfy multimedia data streaming through wireless

Bluetooth is an open specification for short-range data

connectivity like Bluetooth, the embedded processor used in

communications. It operates in the globally available 2.4

portable system must provide highly energy-efficient

GHz to 2.5 GHz ISM free band. Fast frequency hopping

operations, due to the importance of battery weight and size

(1600 hop/s), 79 available channels (2.402 to 2.480 GHz),

without compromising high performance when the user

and a maximum 1 Mbit/s GFSK modem are allowed.

requires it. The functions required in this application are

The PT8R1202 consists of a Bluetooth baseband hardware,

on-chip 128MHz hybrid embedded RISC / DSP processor

and peripheral interface block. The PT8R1202 focuses on

audio streaming to distribute audio content of high-quality

in mono or stereo on ACL channels of Bluetooth. Since

PT8R1202 is highly integrated SOC solution to support the

Advanced Audio Distribution Profile(A2DP) defined in

Bluetooth as audio streaming application with minimum

BOM, the minimum required external devices are just

PT8R100X 2.4GHz radio transceiver IC, external antenna,

crystal, and minimum 256KB flash memory for program

code.

classified into two computations such as MCU operation

and DSP operation. The former performs all functions

associated with user interface as well as real-time

communication protocols and the latter performs all signal-

processing and multimedia functions.

The on-chip embedded processor in the PT8R1202 is based

on PTI proprietary V6 processor(PiCOII-RISC/DSP), which

is optimized to accelerate both two computations for low

power and high performance embedded processing. Its

instruction set is optimized not only for general embedded

processing but also DSP signal processing specially used in

audio and speech code. This hybrid embedded RISC/DSP

processor supports 24-bit multiplication and 48-bit

accumulator with DSP functionality such as saturation and

rounding. Also, it supports SIMD features, which results in

high performance in 16-bit speech applications.

Bluetooth baseband hardware

Bluetooth baseband hardware consists of modem control,

packet processing hardware, and on-chip microcontroller

interface.

To support low power consumption, on-chip processor

adopts programmable dynamic clock control, reduces the

complexity of embedded RTOS optimizing for both

Bluetooth connectivity and audio streaming, and minimizes

external I/O access with several techniques. Default

operation frequency is 96MHz at boot and it can be

increased to 128MHz entering into turbo mode. There are

four global power states provided in PT8R1202 such as

active state, sleep state, deep sleep state and power-off state.

In active state, processor can change the processor clock

between normal operation clock, a half of one, and a third of

one. For example, if processor operates in turbo mode, it

can change processor clock between 128MHz, 64MHz and

42MHz. Also, during the execution of “idle” instruction, it

cuts down the processor clock without interrupting I/O

device operation. In sleep state, the clock of all processor

and I/O device except RTC is disabled. In sleep state,

processor can be waked up quickly by RTC time-out event

or external trigger signal since on-chip PLL is still working

in order to fast response. Deep sleep state is the same of

sleep state except on-chip PLL is off also. Since on-chip

PLL is off in deep sleep state, the power consumption is

reduced very much but requires more latency during wake-

up.

Modem control part generates the control signal for modem

and RF block and transmits or receives data with modem.

PT8R1202 supports BlueRF™ RXMODE2/3 Bluetooth

radio interface with uni/bi-directional and JTAG/DBUS

serial interface like PT8R1000 or PT8R1001 PTI Bluetooth

radio transceiver. In RXMODE3, SYNCWORD correlator

is located in radio transceiver, SYNCWORD detect signal

feeds from external radio transceiver. In RXMODE2,

SYNCWORD correlation is processed in PT8R1202,

SYNCWORD detect signal feed to external radio

transceiver to timing adjustment of modem. In additional to

BlueRF™ interface, PT8R1202 supports BlueQ™ interface

with SBI serial interface.

Packet processing for Bluetooth is implemented by a

dedicated hardware for a low power solution whilst

providing the required data throughput. The function

implemented in hardware include : forward error correction,

header error control, cyclic redundancy check, encryption,

and data whitening. On-chip microcontroller interface

generates interrupt signal to on-chip interrupt handler and

processes DMA operation with 16KB internal

memory(XMEM2) which is shared with on-chip

microcontroller. During radio transmission this block

constructs a packet from header information and payload

data/voice taken from a ring buffer in XMEM2 which is

previously loaded by software. For radio reception, this

block stores the packet header and the payload data in the

appropriate ring buffer in XMEM2, which is indicated by

software. After the completion of reception, this block

generates interrupt signal to on-chip interrupt handler. This

architecture minimizes the interventions required by the

processor during packet transmission and reception.

To minimize the access of external flash memory for code,

PT8R1202 includes on-chip 16KB instruction cache. In

addition to instruction cache, frequent access code or time

critical code is dynamically located on scratch-pad memory

of internal X/YMEM region. It is possible to allocate up to

96KB as scratch-pad memory in order to reduce external

memory access for low power and high performance

Bluetooth digital audio streaming system.

Total 128KB internal SRAM is integrated large enough to

support both on-chip Bluetooth stack and audio application

without external memory, which results in cost-effective

and low-power consumption systems. Internal SRAM

PT0137(08/04)

Ver:4

3

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

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consists of six types memories : XMEM0, XMEM1,

XMEM2, YMEM0, YMEM1, and YMEM2. All memories

can be byte accessible as general purpose data memory.

Some memories such as XMEM2 and YMEM2 have special

usage. XMEM2 is used as 16KB memory for

communication with Bluetooth baseband hardware or USB,

and YMEM2 is used as 16KB memory for communication

with audio data buffer for stereo PCM output.

Peripheral Interface block

PT8R1202 has several peripheral interface such as off-chip

memory interface, USB interface, UART interface, PCM

interface, I2S and SPDIF interface, JTAG interface, Flash

Memory/Card interface, and up-to 59-general purpose

programmable I/O(GPIO) interface. All peripheral devices

are connected to on-chip microcontroller via internal

peripheral bus(V6PB), which is compatible with Advanced

Peripheral Bus(APB) from ARM™

PT8R1202 can boot from NOR type flash and NAND type

flash memory. With NOR type flash memory, code can be

cached into internal instruction cache in order to execute

code at high frequency and reduce power consumption of

frequent memory fetch. With NAND type flash memory,

both code and data are stored same memory, which results

in the reduction of system BOM and form factor. If

PT8R1202 boots from NAND flash, the configuration of the

internal instruction cache is optimized to support NAND

flash efficiently.

Off-chip memory interface supports 4 devices concurrently

such as flash memory, SRAM, and I/O for code and data. It

supports 2MB address space and 16bit data with byte access

functionality. The access timing for each device can be

programmable by software. Also, PT8R1202 supports

external I/O with explicit wait signal such as PCMCIA card.

USB interface supports both 12Mbps and 1.5Mbps serial

data communication conforming to universal serial bus

standard version 1.1. It supports both device and host side

operation and all operation modes such as bulk, interrupt,

control and isochronous mode. It consists of one control

end-point, four receiver end-points and four transmit end-

points, each of which has dual 64bytes FIFO except control

end-point and supports bulk, interrupt, and control, and two

pair of end-points which supports isochronous mode up to

1023bytes.

Software development environment

The PT8R1202 supports high-level programming

development with our optimized C compiler based on GCC

and intrinsic library functions to maximize the software

development productivity. The system software to support

application software development includes C-compiler,

multi-level instruction set simulator, performance analyzing

profiler, memory configuration optimizer and power

monitor. Specially, our C compiler supports automatically

collaboration mechanism between compiled general code

and hand-written DSP libraries to maximize the utilization

of V6 advanced features.

On-chip UART supports programmable baud rate up to

maximum 1.84MBaud serial communication and fully

programmable serial interface such as flow control and bit

format. It includes separate 16-byte transmit and receiver

FIFOs to reduce CPU interrupts.

To reduce the system developing cost, PTI provides

performance optimized DSP library for enabling several

multimedia standards with our own developing skill for

multimedia application. This library supports several

standards such as MPEG-1/2 layer I, II, III audio

decompression, Dolby Digital decompression, WMA, SBC

codec, G.723.1/G.728 speech codec, etc.

PCM interface supports the external PCM codec with

CVSD Bluetooth codec functionality. For the external PCM

codec, it support 8-bit A/u-law PCM and 13- or 14-bit

8KHz linear PCM in both master or slave mode. For 8-bit

A/u-law format, it supports one, two and four channels

simultaneously.

Audio output interface supports I2S digital audio interface,

SPDIF digital audio interface. For external DAC, it supports

32, 44.1, or 48KHz sampling frequencies with the

programmable bit resolution up to 24bit. All sampling

frequency can be generated both from on-chip audio PLL or

external clock source.

Advanced audio streaming on Bluetooth

PT8R1202 supports advanced audio streaming using the

advanced audio distribution profile(A2DP) defined in

Bluetooth. This profile is used by devices to distribute audio

content of high-quality in mono or stereo on ACL channels,

as well as Bluetooth audio which indicates distribution of

narrow band voice on SCO channel. PT8R1202 support

several codecs in A2DP such as low complexity subband

codec(SBC), MPEG-1,2 audio, or WMA. This advanced

audio streaming feature of PT8R1202 can be used several

audio system with Bluetooth connectivity between portable

audio player and headphone, high-quality audio system and

surround speaker, or portable speech recorder and

microphone.

Audio input interface supports both I2S interface and SPDIF

interface with 32, 44.1, or 48kHz sampling frequencies. For

slave mode in which all control signals come from external,

I2S interface can support up to 192kHz sampling frequency.

PT8R1202 supports the dedicated hardware interface to

SmartMedia™ flash memory(NAND type) or card. Without

the occupation of the CPU resource, it supports DMA

transfer for SmartMedia™ interface to achieve fast

read/write operation. At SMC boot mode, PT8R1202 can

boot from SMC without normal parallel flash of NOR type.

For supporting A2DP, PT8R1202 embeds all Bluetooth

stack such as baseband, LMP, L2CAP, SDP, AVDTP(A/V

Distribution Transport Protocol) and AVCTP(A/V Control

Transport Protocol). As well as A2DP, PT8R1202 supports

cordless phone or dial-up networking using RFCOMM,

TCS/BIN protocol and profiles.

PT8R1202 provides 59-bit programmable, bi-directional

IO(GPIO) which are shared with dedicated pins in order to

reduce pins. GPIO signal can be used as key-pad input,

MMC/SDCard/Memory Stick™ interface, or LCD interface.

PT0137(08/04)

Ver:4

4

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

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PT8R1202 supports standard JTAG interface for both

boundary scan and communication channel with PTI

enhanced on-chip hardware debugger controller. Using on-

chip debugger controller, off-chip debug handler or external

host can access internal peripheral device registers, external

memory interface, and executes real-timing hardware

debugging and monitoring of on-chip embedded RISC

processor. Also, external host can communicate on-chip

processor through JTAG with on-chip hardware managed

channel buffer.

PT0137(08/04)

Ver:4

5

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

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Pin Descriptions

Pin Name

I/O

TYPE

Description

DI(Digital Input, 3.3V), DO(Digital Output, 3.3V), DB(Digital Bidirectional, 3.3V), DP(Digital Programmable, 3.3V)

DCP(Digital Core Power, 1.8V), DPP(Digital Peripheral Power, 3.3V)

DCG(Digital Core Ground), DPG(Digital Peripheral Ground)

AAI(Analog Audio Input, 3.3V), AAO(Analog Audio Output, 3.3V), AAB(Analog Audio Bidirectional, 3.3V)

ACI(Analog Core Input, 1.8V), ACO(Analog Core Output, 1.8V), ACB(Analog Core Bidirectional, 1.8V)

AAP(Analog Audio Power, 3.3V), AAG(Analog Audio Ground)

ACP(Analog Core Power, 1.8V), ACG(Analog Core Ground)

BLUETOOTH INTERFACE : 12

TXACTIVE / GPA[0]

RXACTIVE / GPA[1]

TXDATA_EN / GPA[2]

TXDATA / GPA[3]

D4

C1

E2

D1

E3

E1

F1

F3

F2

G3

G1

G2

DO/ DP

DO / DP active high

DB / DP

DI / DP

DB / DP

DI / DP

DO / DP active high

DO / DP clock

active high

transmitter enable

receiver enable

timing reference of valid data

transmit data

receive data

serial data

active high

clock

RXDATA / GPA[4]

SYNCDECTECT / GPA[5]

DATACLK / GPA[6]

RFRESET / GPA[7]

BLUERF_TCK / GPA[8]

BLUERF_TMS / GPA[9]

BLUERF_TDI / GPA[10]

BLUERF_TDO / GPA[11]

indication of SYNC word detection

Phy reference data clock

Reset signal for external radio transceiver

a serial register interface clock

control signal of Phy’s TAP controller

Phy control register serial data output

Phy control register serial data input

DO / DP serial data

DB / DP

DI / DP

serial data

CLOCK SIGNAL INTERFACE : 6

XTALIN

XTALOUT

J8

L9

DI

DO

clock

Crystal input for on-chip PLL (see note1)

Crystal output

PLL mode control (see note1)

External, test clock input (see note1, 2)

PLL mode control (see note1)

Manufacturing test mode (see note2)

External clock source select signal (see note1,2)

clock out divided by a third of internal system clock (see note1)

PLL_MD1

PLL_MD0

M10

M11

DI

control

DI / DO

DI

control

PLLSEL

CLKOUT / GPB[0]

L10

L7

control pin

DO / DP clock

TEST & DEBUG INTERFACE : 9

RESET

K8

DI

active low

reset signal

BTMD[1:0]

SCAN_EN

M7, J7

C5

M8

K7

L8

K9

DI / DP

DI

DI / DP

control pin

clock

serial data

active low

serial data

boot mode (see note2)

manufacturing test (see note3)

JTAG clock signal

JTAG test mode signal

JTAG reset signal

JTAG_TCK / GPC[4]

JTAG_TMS / GPC[5]

JTAG_RST / GPC[6]

JTAG_TDI / GPC[7]

JTAG_TDO / GPC[8]

JTAG serial input data

JTAG serial output data

M9

DO / DP serial data

EXTERNAL MEMORY INTERFACE : 45

(see note4)

(see note5)

C10

MEMA[19:0]

MEMD[15:0]

WEB

REB

UBE / GPB[1]

LBE / GPB[2]

DO

DB

DO

bus

active low

address bus for external memory

data bus for external memory

write enable signal for external memory

read enable signal for external memory

upper byte enable (see note6)

C12

D11

D10

DO / DP active low

lower byte enable (see note6)

FLASHCSB / GPB[3]

SRAMCSB / GPB[4]

IOCSB0 / GPB[5]

IOCSB1 / SM_CSB1 / GPB[6]

IOWAIT / GPB[7]

UART & USB INTERFACE : 6

D12

E10

E11

E12

DO

active low

chip select for external flash memory

chip select for external SRAM memory

chip select for external I/O device0

chip select for external I/O device1 (see note7)

IO wait cycle extension indication signal

DO / DP active low

F10

DI / DP

control pin

UARTTX / GPC[0]

UARTRX / GPC[1]

H3

H1

DO / DP serial data

DI / DP serial data

UART serial transmit data / USBOE

UART serial receive data / USBSPEED

UART RTS(Ready To Send) signal / USBVPO

AUDISCLK / DIGAMP_L (see note8)

UART CTS(Clear To Send) signal / USBVMO

AUDILRCLK / DIGAMP_R(see note8)

USB D+

DIGAMP_L

AUDISCLK / GPC[2]

DIGAMP_R UARTCTS

/

UARTRTS

/

H2

J4

DO / DP active low

/

AUDILRCLK / GPC[3]

D+

D-

B4

A4

DB

serial data

USB D-

PT0137(08/04)

Ver:4

6

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

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Pin Name

I/O

TYPE

Description

DIGITAL AUDIO INTERFACE : 9

PCMOUT / GPD[0]

PCMIN / GPD[1]

J3

J1

J2

K1

K2

L1

L2

M1

K3

DO / DP serial data

PCM 8kbps data out

PCM 8kbps data input

DI / DP

DP

serial data

clock

PCMSYNC / GPD[2]

PCMCLK / GPD[3]

AUDSCLK / GPD[4]

AUDLRCLK / GPD[5]

AUDOUT / GPD[6]

AUDMCLK / GPD[7]

AUDIN / SPDIFIN/GPD[8]

PCM 8KHz frame synchronization signal

PCM bit data clock (128/256)

audio serial data bit clock(64*fs)

audio left/right sync clock(fs)

audio serial data output

DP

clock

DP

clock

DP

clock/

DO / DP serial data

DP

clock

audio oversampled clock(256/384*fs)

audio serial data input

DI / DP

serial data

ANALOG AUDIO INTERFACE : 6 (see note9)

MIC_IN

MICGS

VMID

VREF

EARA

EARB

B2

A1

C3

C2

C4

B1

AAI

analog

Reserved

AAO

Sleep crystal(32.768kHz) XTALIN

Sleep crystal(32.768kHz) XTALOUT

SMARTMEDIA INTERFACE : 14

SM_CSB / GPE[0]

SM_CLE / GPE[1]

SM_ALE / GPE[2]

SM_WE / GPE[3]

SM_OE / GPE[4]

SM_RB / GPE[5]

L3

M2

M3

K4

M4

L4

DO / DP active low

Smartmedia chip select

Smartmedia command latch enable

Smartmedia address latch enable

Smartmedia write enable

Smartmedia read enable

Smartmedia ready signal

DI / DP

DB

control pin

bus

(see note10)

SM_DATA[7:0] /GPF[7:0]

Smartmedia data/address bus

GPIO INTERFACE : 7

GPG[0] / IRQ0 / SSM1

GPG[1] / IRQ1

GPG[2] / WAKEUP

GPG[3] / SSM0

GPG[4] / CLK32K

SPDIFO / GPG[5]

D6

B6

C6

A5

D5

B5

DI / DP

DO / DP clock

DB / DP signal

DO / DP signal

active high

external interrupt request0 (see note11)

external interrupt request1 / USBVPI

external wake up signal (see note12) / USBRCV

Size indicator at Smartmedia boot (see note11) / USBVMI

External RTC clock(32kHz) input (see note13)

SPDIF output / USBSUSPND (see note14)

POWER SUPPLIES : 31

SPLL_VCC(1)

SPLL_GND(1)

APLL_VCC(1)

APLL_GND(1)

ACODEC_VCC(1)

ACODEC_GND(2)

VCC(6)

VCC_GND(6)

VPP(6)

VPP_GND(6)

L11

M12

D3

D2

A2

ACP

ACG

ACP

ACG

AAP

AAG

DCP

DCG

DPP

DPG

power

ground

power

ground

power

ground

power

ground

power

ground

supply for system PLL (1.8V)

ground for system PLL

supply for audio PLL (1.8V)

ground for audio PLL

supply for combo audio codec (3.0V)

ground for combo audio codec

power for digital core block (1.8V)

ground for digital core block

supply for digital peripheral blocks (3.3V)

ground for digital peripheral blocks

A3, B3

(see note15)

(see note16)

(see note17)

(see note18)

Note :

1. PT8R1202 use two main clocks for core operation and peripheral operation. Both clocks can be generated from on-chip PLL or

individually pumped from external clock source. The clock for processor operation, named CLKSYS, can be variable by application

requirement or dynamic power management, but the clock for peripheral operation must be fixed as 48MHz for USB and audio interface

and 32MHz for others. The PLL in the PT8R1202 supports 12MHz, 13MHz, 16MHz, or 19.2MHz as reference clock. Following table

shows the configuration of PT8R1202 clock generation block. For using internal clock from on-chip PLL, PLLSEL must be set “0”.

When using internal clock from on-chip PLL, PT8R1202 can change the operating frequency of on-chip processor up to 128MHz turbo

mode. The default operation mode is normal execution at 96MHz operating frequency and it can be changed into turbo mode by software.

However, in the case of using external clock source, it does not support turbo mode.

PT0137(08/04)

Ver:4

7

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

Table 1. PLL mode set value for setting core frequency

XTALIN

PLL_MD1

PLL_MD0

PLLSEL

CLKOUT

32MHz

42.7MHz

32MHz

42.7MHz

32MHz

42.7MHz

32MHz

CLKSYS

96MHz

128MHz

96MHz

128MHz

96MHz

128MHz

96MHz

Comment

Normal mode

Turbo mode

Normal mode

Turbo mode

Normal mode

Turbo mode

Normal mode

Turbo mode

Normal mode

TEST mode

12MHz

Low

13MHz

16MHz

19.2MHz

Low

High

Low

High

Low

42.7MHz

32MHz

TESTCLK

128MHz

96MHz

TESTCLK

Don’t use

96MHz

TESTCLK

Low

High

2. If both PLL_MD0 and PLLSEL are high, the operation mode of PT8R1202 changes into TEST mode. This mode is used only for

manufacturing test purpose. In TEST mode, the boot mode will be used as indication of specific test mode. In normal mode, the boot

mode indicates the source of boot code to be fetched first PC.

Table 2. Boot mode set value for indicating the source of boot code fetch in normal mode

BTMD[1:0]

Name

Comment

0

1

2

3

Flash

Debug

reserved

NandFlash

Boot from external memory using FLASHCSB[0] signal

Wait for debug command through JTAG

Bood from NandFlash using smart media interface

The size of NandFlash is indicated by SSM pin. See note7 for more information.

Table 3. Boot mode set value for indicating the source of boot code fetch in test mode

BTMD[1:0]

Name

Comment

0

1

2

3

SCAN test

Codec test

Codec0 test

Codec1 test

Full scan test mode (manufacturing test purpose)

Analog audio external test mode (debugging purpose)

Audio left DAC and ADC test mode (manufacturing test purpose)

Audio right DAC and ADC test mode (manufacturing test purpose)

3. This pin should be low for normal operation. It is used only in manufacturing test.

4. PIN of MEMA[19:0] : A6, B7, A7, C7, D7, B8, A8, D8, A9, C8, D9, A10, B9, C9, B10, A11, A12, B11, B12, C11

5. PIN of MEMD[15:0] : F11, F12, G11, G12, H12, G10, H11, H10, J12, K12, J9, J11, J10, L12, K11, K10

6. In non byte access device such as flash memory(x16), these pin will be not connected.

7. This pin can be programmed to access the second NAND flash chip in addition to SM_CSB signal. With this pin, PT8R1202 can support

up to 4 Gb(512MB) NAND flash directly.

8. These pins can be used as multiple purposes by programming such as digital AMP output, UART flow control signal and alternative I2S

input. From R2.4, the default direction and signal usage is changed. The default configuration is the output of internal digital amplifier.

For the case of alternative I2S input mode, the sampling frequency of I2S input can be different to that of I2S output.

9. Internal audio codec is not recommended to use for both voice and audio. Instead of internal stereo sigma-delta DAC, we recommend to

use external voice and audio codec. From R2.6, EARA and EARB PAD are only dedicated to oscillator PAD for external sleep crystal.

10. PIN of SM_DATA[7:0] : K5, J5, M5, L5, K6, M6, J6, L6

11. These pins is only used at NandFlash boot mode. If BTMD is “11” which means on-chip processor boots from NandFlash, these pins are

used as size indication of external NandFlash. After the completion of boot, it is used as GPIO. Otherwise, it is always used as GPIO.

12. This signal can be programmed for embedded processor to be waked up from sleep or deep sleep power state.

13. Instead of dividing clock from XTALIN, this pin can be used as the low oscillator clock source as programming for extremely low

power consumption in stand-by state.

14. From R2.4, the default direction of this pin is output as SPDIF output signal.

15. PIN of VCC : G4, H4, H5, H6, H7, H8

16. PIN of VPP : F5, F6, F7, F8, G9, H9

17. PIN of VCC_GND : E4, F4, G5, G6, G7, G8

18. PIN of VPP_GND : E5, E6, E7, E8, E9, F9

PT0137(08/04)

Ver:4

8

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

Package Diagram

The circuits is packaged with 144pin FPBGA and LQFP package. The body size of FPBGA is 10x10mm and the body size of

LQFP is 20x20mm. Following figure shows the top view of the package.

10mm

1

2

3

4

5

6

7

8

9

10 11 12

CODECCODEC

MICGS

D-

GPG3 MA19 MA17 MA13 MA11 MA8

MA4

MA3

MA1

REB

A

B

C

D

VCC

GND

CODEC

GND

EARB MICIN

D+

GPG5 GPG1 MA18 MA14 MA7

MA5

MA2

SCAN

GPA1 VREF VMID EARA

GPG2 MA16 MA10 MA6

EN

WEB MA0

APLL APLL

GPA3

GPA0 GPG4 GPG0 MA15 MA12 MA9 GPB2 GPB1 GPB3

GND

VCC

GND

VPP

GND

VPP

GND

VPP

GND

VPP

GND

VPP

GND

GPA5 GPA2 GPA4

GPA6 GPA8 GPA7

GPB4 GPB5 GPB6

GPB7 MD15 MD14

E

F

VCC

GND

VPP

GND

VPP

10mm

VCC

GND

VCC

GND

VCC

GND

VCC

GND

GPA11 GPA9 VCC

VPP MD10 MD13 MD12

G ^GPA10

GPC1 GPC2 GPC0 VCC

VCC

VPP

MD5

MD8

MD3

MD9 MD11

H

J

XTAL

IN

GPD1 GPD2 GPD0 GPC3 GPF6 GPF1 BTMD0

MD4

MD1

MD7

MD6

MD2

GPD3 GPD4 GPD8 GPE3 GPF7 GPF3 GPC5 RST GPC7 MD0

K

L

XTAL PLL SPLL

OUT

GPD5 GPD6 GPE0 GPE5 GPF4 GPF0 GPB0 GPC6

SEL

VCC

PLL

MD1

PLL

MD0

SPLL

GND

GPD7 GPE1 GPE2 GPE4 GPF5 GPF2 BTMD1 GPC4 GPC8

M

MICGS

AGNDC

VREF

EARA

EARB

APLL VCC

APLL GND

1

2

3

4

5

6

7

8

¹⁰⁸ꢀ ^MEMA2

¹⁰⁷ꢀ ^MEMA1

¹⁰⁶ꢀ ^MEMA0

¹⁰⁵ꢀ ^WEB

ꢀ

¹⁰⁴ꢀ ^REB

¹⁰³ꢀ ^UBE(GPB[1])

¹⁰²ꢀ ^LBE(GPB[2])

¹⁰¹ꢀ ^{FLASHCSB(GPB[3])}

¹⁰⁰ꢀ ^{SRAMCSB(GPB[4])}

⁹⁹ꢀ ^{IOCSB0(GPB[5])}

⁹⁸ꢀ ^{IOCSB1(GPB[6])}

⁹⁷ꢀ ^{IOWAIT(GPB[7])}

⁹⁶ꢀ ^{DIG GNDC}

⁹⁵ꢀ ^{DIG VCC}

⁹⁴ꢀ ^MEMD15

⁹³ꢀ ^MEMD14

⁹²ꢀ ^MEMD13

⁹¹ꢀ ^{DIG GNDP}

⁹⁰ꢀ ^{DIG VPP}

TXACTIVE(GPA[0])

RXACTIVE(GPA[1])

TXDATA_EN(GPA[2])

TXDATA(GPA[3])

RXDATA(GPA[4])

SYNCDETECT(GPA[5])

DIG GNDC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

DIG VCC

DATACLK(GPA[6])

RFRESET(GPA[7])

BLUERF_TCK(GPA[8])

BLUERF_TMS(GPA[9])

BLUERF_TDI(GPA[10])

BLUERF_TDO(GPA[11])

DIG VPP

PT8R1202-QFP144

⁸⁹ꢀ ^MEMD12

⁸⁸ꢀ ^MEMD11

⁸⁷ꢀ ^MEMD10

⁸⁶ꢀ ^MEMD9

DIG GNDP

UARTTX(GPC[0])

UARTRX(GPC[1])

UARTRTS(GPC[2])

UARTCTS(GPC[3])

PCMOUT(GPD[0])

PCMIN(GPD[1])

PCMSYNC(GPD[2])

PCMCLK(GPD[3])

DIG VCC

⁸⁵ꢀ ^{DIG GNDC}

⁸⁴ꢀ ^{DIG VCC}

⁸³ꢀ ^MEMD8

⁸²ꢀ ^MEMD7

⁸¹ꢀ ^MEMD6

⁸⁰ꢀ ^MEMD5

⁷⁹ꢀ ^MEMD4

⁷⁸ꢀ ^MEMD3

⁷⁷ꢀ ^MEMD2

DIG GNDC

⁷⁶ꢀ ^MEMD1

AUDSCLK(GPD[4])

AUDLRCLK(GPD[5])

AUDOUT(GPD[6])

⁷⁵ꢀ ^MEMD0

⁷⁴ꢀ ^SPLL_GND

⁷³ꢀ ^SPLL_VCC

PT0137(08/04)

Ver:4

9

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

Package Diagram of FPBGA

Notes :

1. All dimension are in millimeters.

2.

3.

‘e’ represents the basic solder ball grid pitch.

‘M’ represents the basic solder ball matrix size.

And, symbol ‘N’ is the number of balls after depopulating.

‘b’ is measurable at the maximum solder ball diameter after

reflow parallel to primary datum -c-.

4.

5.

6.

Dimension ‘aaa’ is measured parallel to primary datum –c-.

Primary datum –c- and seating plane are defined by the spherical

crowns of the solder balls.

7.

8.

Package surface shall be matte finish charmilles 24 to 27.

Package centering to substrate shall be 0.0760 mm maximum

for both X and Y direction respectively.

9.

Package warp shall be 0.050mm maximum.

10. Substrate material base is bt resin.

11. The overall package thickness “A” already considers collapse balls.

12. Dimension and tolerancing per ASME Y14.5-1994.

PT0137(08/04)

Ver:4

10

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

Package Diagram for TQFP

Notes :

1.

2.

All dimension are in millimeters.

Dimention shown are nominal with TOL.

As indicated.

3.

4.

L/F : EFTEC 64T copper or equivalent

0.127mm (.005”) thick

Foot length “L” is measured at gage plane.

At 0.25mm, above the seating plane.

PT0137(08/04)

Ver:4

11

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

I/O Description

Off-chip memory interface

The external memory port comprises a 16bit data bus(MEMD[15:0]) and an 20bit address bus(MEMA[19:0]), thus addressing up to 2Mbytes

of off-chip code or data. Control signal WEB, REB, and multiple CSB(FLAHSCSB, SRAMCSB, IOCSB0 and IOCSB1) are provided, which

make it possible to use a variety of different memories, including flash memory, SRAM and ROM. For SRAM access, UBE and LBE signal

support byte access and memory interface block automatically handles control signals for 32bit word, 16bit half-word and 8bit byte access of

on-chip microcontroller memory operations. In standard Bluetooth application, only external 256KB flash memory is required in PT8R1202.

For additional Bluetooth application including several Bluetooth protocol stack which requires more data memory than internal SRAM of

PT8R1202, external SRAM is used for extended data memory of PT8R1202 on-chip microcontroller. The access time of each device can be

programmed and the wait cycle ranges 0 to 63 based on system clock, which is normally processor clock, that is CLKSYS. External flash can

be programmed via host interface by external host or self update by PT8R1202 on-chip RISC/DSP processor.

Because PT8R1202 on-chip RISC/DSP processor is based on harvard architecture, the address map of instruction and data access is difference.

Following table 1. shows the instruction address map and table 2. shows the data address map.

Table 4. Instruction address map

Address(24bit)*

Device

FLASH

-

SRAM

IO0

Attribute

read only

-

read only

Description

cacheable, scratch-pad memory or non-cacheable

reserved

cacheable, scratch-pad memory or non-cacheable

0x000000~0x1FFFFF

0x200000~0x3FFFFF

0x400000~0x5FFFFF

0x600000~0x7FFFFF

0x800000~0x9FFFFF

IO1

* This address space is based on byte addressing. There are addition extended two bits in the most significant bits(25th and 24th), and they are

used for the indication of section attribute. All instructions are checked whether they are cached in the scratch-pad memory first. Then, those

two bits are used to check the source of that instruction fetch. “00” indicates those section can be loaded only through on-chip instruction cache

with conventional two-way set associate policy. “01” indicates those section can be loaded only set0 region of on-chip instruction cache. “10”

indicates those section can be loaded only set1 region of on-chip instruction cache. “11” indicates those section can be loaded directly from

external memory without passing instruction cache. The address space of this internal scratch-pad memory is 0xA00000~0xA0BFFF for

XMEM and 0xC00000~0xC0BFFF for YMEM. The scratch memory is divided into four pages each size of which is 32KB with 9-bit

instruction tag which consists of 3-bit section attribute and the most significant 6-bit section address. On-chip RISC processor will check the

match by full associative comparison with four tag registers of internal scratch-pad memory first. Then, if that tag comparison is matched,

instruction will be fetched from internal scratch-pad memory. Otherwise, instruction will be fetch through on-chip instruction cache from

external flash memory region.

Table 5. Data address map

Address(23bit)*

Device

Attribute

Description

FLASH

z

instruction code memory

constant data memory

accessible by on-chip DMA

0x000000~0x1FFFFF

read/write

half-word, word

-

reserved

0x200000~0x3FFFFF

0x400000~0x5FFFFF

-

SRAM

z

data memory

read/write

byte, half-word, word

fast fetch instruction code memory

accessible by on-chip DMA

I/O access

IO0

IO1

0x600000~0x7FFFFF

0x800000~0x9FFFFF

0xA00000~0xA07FFF

read/write

byte, half-word, word

read/write

byte, half-word, word

read/write

byte, half-word, word

DSP memory (14M)

accessible by on-chip DMA

z

I/O access

accessible by on-chip DMA

XMEM0

(32KB)

z

data memory

scratch-pad instruction memory

SmartMedia™ FIFO

accessible by DMA

data memory

scratch-pad instruction memory

SmartMedia™ FIFO

accessible by on-chip DMA

XMEM1

(16KB)

0xA08000~0xA0BFFF

0xA0C000~0xA0FFFF

read/wrtie

byte, half-word, word

DSP memory (14M)

XMEM2

(16KB)

data memory

read/write

byte, half-word, word

Bluetooth baseband FIFO,

USB FIFO(0x20C000~0x20FFFF)

accessible by on-chip DMA

data memory

YMEM0

(32KB)

0xC00000~0xC07FFF

PT0137(08/04)

read/write

byte, half-word, word

scratch-pad instruction memory

Ver:4

12

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

DSP memory (14M)

z

SmartMedia™ FIFO

accessible by on-chip DMA

data memory

scatch-pad instruction memory

SmartMedia™ FIFO

accessible by on-chip DMA

data memory

digital stereo audio output FIFO

accessible by on-chip DMA

YMEM1

(16KB)

0xC08000~0xC0BFFF

read/write

byte, half-word, word

DSP memory (14M)

YMEM2

(16KB)

0xC0C000~0xC0FFFF

read/write

byte, half-word, word

DSP memory(14M)

* This address space is based on byte addressing.

Off-chip memory interface waveform diagram

Internal Core Clock

(CLKSYS)

0 MEM Wait Cycles

8bit-L

16bit

8bit-H

Write2

16bit

Write3

32bit

32bit

Write5

IDLE

Operation Mode

CS (Flash, SRAM, I/O)

WEB

REB

UBE

LBE

MEMA[19:0]

MEMD[15:0]

unknown ADDR0 ADDR1

DATA0 DATA1

ADDR2

DATA2

ADDR3

DATA3

ADDR4 ADDR4+1

DATA4 DATA4

ADDR5

DATA5 MSB

ADDR5+1

DATA5 LSB

MSB

LSB

1 MEM Wait Cycles

8bit-L

IDLE

16bit

8bit-H

Write2

16bit

Write3

32bit

IDLE

Operation Mode

CS (Flash, SRAM, I/O)

WEB

REB

UBE

LBE

MEMA[19:0]

MEMD[15:0]

unknown

ADDR0

DATA0

ADDR1

DATA1

ADDR2

DATA2

ADDR3

DATA3

ADDR4

DATA4 MSB

ADDR4+1

DATA4 LSB

PT0137(08/04)

Ver:4

13

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

Off-chip memory interface read access timing without wait signal

t_RC

MEMA[19:0]

Address

CSB, REB, U/LBE

MEMD[15:0]

t_RSC

Valid Read Data

t_RDS

t_RDH

RSCYC

(0~3)

RACYC

(1~64)

Off-chip memory interface read access timing with wait signal

t_RC

Address

MEMA[19:0]

CSB, REB, U/LBE

WAIT

t_RSC

Valid Read Data

MEMD[15:0]

t_RDS

t_RDH

RSCYC

(0~3)

RWCYC

(0~7)

RECYC

(0~7)

Table 6. Read access timing

Parameter

Symbol

Min

Max

Unit

Read cycle time

Read data setup time

Read data hold time

t_RC

t_RDS

t_RDH

1 (7.8ns)

3

1

64 (500ns)

CLKSYS clock cycles (128MHz)

ns

* RSCYC, RACYC, RWCYC, RECYC based on cycle number of CLKSYS

PT0137(08/04)

Ver:4

14

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

Off-chip memory interface write access timing without wait signal

t_WC

MEMA[19:0]

Address

t_CPW

CSB, WEB, U/LBE

MEMD[15:0]

t_WSC

t_WAH

Valid Write Data

t_WDS

t_WDE

t_WDH

t_WDD

WSCYC

(0~3)

WACYC

(1~64)

WHCYC

(0~3)

Off-chip memory interface write access timing with wait signal

t_WC

MEMA[19:0]

Address

t_CPW

CSB, WEB, U/LBE

WAIT

t_WSC

t_WAH

Valid Write Data

MEMD[15:0]

t_WDS

t_WDE

t_WDH

t_WDD

WSCYC

(0~3)

WWCYC

(0~7)

WECYC

(0~7)

WHCYC

(0~3)

Table 7. Write access timing

Parameter

Symbol

Min

Max

Unit

Write cycle time

t_WC

2 (15.6ns)

1 (7.8ns)

0

65 (507.8ns)

64 (500ns)

1 (7.8ns)

CLKSYS clock cycles (128MHz)

ns

ns (CLKSYS=128MHz)

CLKSYS clock cycles (128MHz)

ns

Write control signal pulse width

Write address hold time from control signal

Write data output enable time

Write data setup time to control signal

Write data hold time from control signal

Write data output disable time

t_CPW

t_WAH

t_WDE

t_WDS

t_WDH

t_WDD

4

1 (7.8ns)

0

1 (7.8ns)

PT0137(08/04)

Ver:4

15

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

Bluetooth radio interface

PT8R1202 supports BlueRF™ RXMODE2/3 Bluetooth radio interface with uni/bi-directional and JTAG/DBUS serial

interface .PTI Bluetooth radio transceiver. In RXMODE3, SYNCWORD correlator is located in radio transceiver, SYNCWORD

detect signal feeds from external radio transceiver. In RXMODE2, SYNCWORD correlation is processed in PT8R1202,

SYNCWORD detect signal feed to external radio transceiver to timing adjustment of modem. In additional to BlueRF™

interface, PT8R1202 supports BlueQ™ interface with SBI serial interface.

RXDATA(GPA4)

RXACTIVE(GPA1)

TXACTIVE(GPA0)

SYNCDETECT(GPA5)

GPIO(optional)

BRXD

RXDATA(GPA4)

RXACTIVE(GPA1)

TXACTIVE(GPA0)

SYNCDETECT(GPA5)

GPIO(optional)

BRXD

BRXEN

BTXEN

BPKTCTL

BSEN

BRXEN

BTXEN

BPKTCTL

BSEN

GPIO(optional)

TXDATA(GPA3)

BXTLEN

BTXD

GPIO(optional)

TXDATA(GPA3)

BXTLEN

BTXD

TXDATA_EN(GPA2)

RFRESET(GPA7)

DATACLK(GPA6)

BPAEN

BnPWR

BRCLK

TXDATA_EN(GPA2)

RFRESET(GPA7)

DATACLK(GPA6)

BPAEN

BnPWR

BRCLK

PT8R1202

BLUERF_TCK(GPA8)

BLUERF_TMS(GPA9)

BLUERF_TDI(GPA10)

BLUERF_TDO(GPA11)

BDCLK

BnDEN

BLUERF_TCK(GPA8)

BLUERF_TMS(GPA9)

BDCLK

BnDEN

BMOSI

BMISO

BMOSI

BMISO

BLUERF_TDI(GPA10)

BLUERF_TDO(GPA11)

–

-

– -

BlueRF RXMODE2 Uni directional I/F

BlueRF RXMODE3 Uni directional I/F

SYNCDETECT(GPA5)

BPKTCTL

GPIO(optional)

TXDATA(GPA3)

GPIO(optional)

TXDATA(GPA3)

BXTLEN

BTXD

BXTLEN

BTXD

PT8R1202

RFRESET(GPA7)

DATACLK(GPA6)

RFRESET(GPA7)

DATACLK(GPA6)

BnPWR

BRCLK

BnPWR

BRCLK

BLUERF_TCK(GPA8)

BLUERF_TMS(GPA9)

BLUERF_TCK(GPA8)

BLUERF_TMS(GPA9)

BDCLK

BnDEN

BDCLK

BnDEN

BLUERF_TDO(GPA11)

BDDATA

–

-

– -

BlueRF RXMODE2 Bi directional I/F

BlueRF RXMODE3 Bi directional I/F

SYNCDETECT(GPA5)

TXDATA(GPA3)

SYNC_DET

RX_TX_DATA

CLK_REF

PGTD8MR11220022

DATACLK(GPA6)

BLUERF_TCK(GPA8)

BLUERF_TMS(GPA9)

SBCK

SBST

BlueQ

BLUERF_TDO(GPA11)

SBDT

BlueQ

PT0137(08/04)

Ver:4

16

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

External PCM interface

PCMIN, PCMOUT, PCMCLK, PCMSYNC carry one channel of voice data using 8-bit A/u-law, 13-bit /14-bit/16-bit linear

PCM at 8kbps. PT8R1202 generates PCMCLK and PCMSYNC as both outputs or input, which can be programmed, and

interfaces directly to PCM audio devices. PCMSYNC operates at fixed clock frequency of 8KHz. PCMCLK operates at one of

two fixed clock frequencies such as 128 and 256kHz. PCM interface supports both long frame sync signal and short frame sync

signal. Additionally, PT8R1202 supports two or four channels of 8-bit A/u-law PCM interfacing with external multi-channel

codec.

Table 8. Configuration of external PCM interface

Configuration

Supporting device

PCM type

Frame

type

L

S/L

L

S/L

Bit length

PCMCLK

clock

128kHz

128/256kHz

256KHz

Channel

number

1

Qualcomm MSM

Motorola MC145481

Oki MSM7717

Oki MSM7704

Oki MSM7705

A, u-law

A, U-law

Linear

8bit

13bit

8bit A/u-law codec

13bit linear PCM

1

2(dual)

4(quad)

1,

Motorola MC145483

128/256kHz

2(volume)

14bit linear PCM

16bit linear PCM

Oki MSM7716

TBD

Linear

L

S/L

14bit

16bit

128/256kHz

1

PCM_CLK

(128, 256, 512, 1024kHz)

PCM_SYNC(8kHz)

(Short Frame)

PCM_SYNC(8kHz)

(Long Frame)

8bit

13bit 14bit

16bit

MSB

8bit A/u-law

LSB

PCM_IN

(sample int at falling edge)

PCM_OUT

13bit linear PCM

14bit linear PCM

16bit linear PCM

LSB

3bit Vol

LSB

(sample out at rising edge)

PCM_SYNC(8kHz)

(Dual-channel)

MSB

8bit A/u-law -1Ch

LSB

MSB

8bit A/u-law -2Ch

LSB

PCM_SYNC(8kHz)

(Quad-channel)

MSB

LSB

8bit-3Ch

8bit-4Ch

PT0137(08/04)

Ver:4

17

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

External Audio ADC/DAC, SPDIF input interface

Audio ADC/DAC interface provides a high quality multi resolution(16/18/20/24-bit) digital audio connection to external audio

devices. ADI interface supports I2S audio format as well as optional left-justified or right-justified audio format. ADI interface

produces one 64-bit frame at the audio sample frequency using a bit clock and frame sync signal in master mode. In slave mode,

ADI accepts one 64-bit frame in audio DAC or one 64/48-bit frame at the audio sample frequency using external generated

control signal. ADI interface supports several audio sampling frequency up to 96-kHz such as 32, 44.1, 48, 64, 88.2, or 96-kHz,

of which 256 or 384 times main clock can be generated from on-chip audio PLL or external clock signal by interface mode

programming. ADI interface contains dual on-chip FIFO which size contains maximally 2048 samples with 16-bit or 1024

samples with above 16-bit stereo audio data through YMEM2 shared with RISC/DSP processor.

Table 9. Audio interface pin description

Pin Name

I/O

Type

Description

AUDMCLK

programmable clock

audio oversampled clock

This clock can be programmed 256 or 384 times AUDLRCLK

audio serial data bit clock

AUDSCLK

programmable clock

This clock is fixed at 64 times AUDLRCLK in output, but can be programmed at 64 or 48

times AUDLRCLK or UARTRTS in input

audio frame synchronization clock

AUDLRCLK programmable clock

This clock can be programmed up to 96kHz

AUDOUT

AUDIN

output

input

serial data audio serial data used for sending playback data to DAC

serial data audio serial data used for receiving recording data from ADC

SPDIF serial data input

UARTRTS

UARTCTS

programmable clock

audio input serial data bit clock

This pin can be programmed as alternative audio serial data bit clock for audio input interface

audio input frame synchronization clock

programmable clock

This pin can be programmed as alternative audio frame synchronization for audio input

interface

• I²S interface

AUDSCLK

Left

AUDLRCLK

Right

MS-1 MS-2

MS

2

1

LS

MS

2

1

LS

AUDOUT

Audio Output : 32 AUDBCLK

Audio Input : Any(24, 32) AUDBCLK

• Left-justified interface

AUDSCLK

Left

AUDLRCLK

Right

MS-1 MS-2

MS

2

1

LS

MS

2

1

LS

AUDOUT

Audio Output : 32 AUDBCLK

Audio Input : Any(24, 32) AUDBCLK

• Right-justified interface

AUSCLK

AUDLRCLK

Left

Right

MS-1 MS-2

MS

2

1

LS

MS

2

1

LS

AUDOUT

MS

Audio Output : 32 AUDBCLK

Audio Input : 24, 32 AUDBCLK

PT0137(08/04)

Ver:4

18

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

SPDIF interface

The PT8R1202 supports IEC-958 or SPDIF serial digital input or output data directly. Through SPDIF interface, uncompressed

audio PCM or compressed PCM can be transferred into or from the PT8R1202 in order to do wireless audio streaming solution.

The function of SPDIF and I2S input shall be executed in the time share way. The function of SPDIF and I2S output can be

executed in the same time. Following figure shows the supported data format in the PT8R1202.

0

3 4

7 8

27

31

P

Preamble Aux Data LSB

Audio Data

Sub-frame

MSB V U C

Validity

User Data

Channel Status Data

Parity Bit

Sub-frame

Channel A

Sub-frame

X

Channel A

Y

Channel B

Z

Y

Channel B

X

Channel A

Y

Channel B

Frame 191

Frame 0

Frame 1

Start of Channel Status Block

USB interface

USB controller in PT8R1202 is compliant USB 1.1 version. The USB functionality is executed by an USB hardware block and

firmware running on V6 RISC processor. This configuration allows acceleration of the intensive function processing while

allowing flexibility in the implementation of higher level protocols over USB. USB controller in PT8R1202 supports both

12Mbps high speed mode and 1.5Mbps low speed mode and host and device mode programmed by firmware.

The USB hardware block consists of a serial interface engine(SIE), a serial bus controller(SBC) and a V6PB bus interface. The

SIE performs the clock/data separation, NRZI encoding and decoding, bit stuffing and unstuffing, CRC generation and checking

and the serial-parallel data conversion. The SBC consists of protocol engine and a USB device with nine endpoints including

endpoint0 for control, each with single or double buffered scheme. Control endpoint consists of single 16-byte FIFO for transmit

and receive, and eight endpoints consist of dual 64-byte FIFOs in each side, which is shared through XMEM2 with on-chip

RISC processor. Four of eight endpoints are for transmit and others for receiving. Additionally, there are four endpoints

dedicated to isochronous operation with 1023-byte FIFO located in XMEM2. The SBC manages the device address, monitors

the status of the transactions, manage the FIFOs and communicates to the processor through a set of status and control registers.

The V6PB bus interface connects the serial bus controller to the processor.

z

Endpoint 0 (EP0) : Control Endpoint equipped with 16bytes single-buffered FIFO

Endpoint 1 (EP1) : OUT Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

Endpoint 2 (EP2) : IN Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

Endpoint 3 (EP3) : OUT Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

Endpoint 4 (EP4) : IN Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

Endpoint 5 (EP5) : OUT Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

Endpoint 6 (EP6) : IN Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

Endpoint 7 (EP7) : OUT Endpoint (isochronous) with 1023bytes single-buffered FIFO

Endpoint 8 (EP8) : IN Endpoint (isochronous) with 1023bytes single-buffered FIFO

Endpoint 9 (EP9) : OUT Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

Endpoint 10 (EP10) : IN Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO

Endpoint 11 (EP11) : OUT Endpoint (isochronous) with 1023bytes single-buffered FIFO

Endpoint 12 (EP12) : IN Endpoint (isochronous) with 1023bytes single-buffered FIFO

PT0137(08/04)

Ver:4

19

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

PT8R1202 supports device function, Hub function and host function in USB 1.1 version. Specially, PT8R1202 emulates the

multiple device operations simultaneously with supporting Hub function. Together with on-chip Nand flash controller and audio

DSP, PT8R1202 supports multiple function in USB dongle which integrates Bluetooth, USB storage device and USB sound card.

Following list is possible configuration for multiple USB device system on a chip.

Table 10. Recommend Endpoint mapping in USB

End point

Bluetooth USB dongle

Bluetooth USB dongle +

USB storage device

Bluetooth USB dongle +

USB storage device +

USB sound device

Common control

BT Event (interrupt)

BT Command (control)

BT ACL data (Bulk)

HUB

USB audio control

BT SCO data (Isoch)

USB storage (Bulk)

USB audio stream (Isoch)

EP0

Common control

BT Event (interrupt)

BT Command (control)

BT ACL data (Bulk)

reserved

BT SCO data (Isoch)

Common control

BT Event (interrupt)

BT Command (control)

BT ACL data (Bulk)

HUB

EP1(Out)

EP2(In)

EP3(Out)

EP4(In)

EP5(Out)

EP6(In)

EP7(Out)

EP8(In)

EP9(Out)

EP10(In)

EP11(Out)

EP12(In)

reserved

BT SCO data (Isoch)

USB storage (Bulk)

reserved

Wireless Stereo Headset

Bluetooth

over Bluetooth

Bulk, ISO device

USB Hub

USB Bus

Bluetooth

Device Driver

Bulk, ISO device

Bulk device

PT8R1202

(Multiple USB

devices over

Portable Storage

Device Driver

single USB bus)

Audio

Device Driver

ISO device

NAND

PT0137(08/04)

Ver:4

20

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

UART interface

UARTTX, UARTRX, UARTRTS, and UARTCTS form a conventional asynchronous data serial port. The interface is designed

to operate correctly when connected to other UART devices such as NS16550A. The signaling levels are 0V and 3.3V. The

interface is programmable over a variety of bit rates. It supports many configurations such as no, even or odd parity, one or two

stop bit, number of bit in a frame, break conditions, and hardware flow control on or off. The maximum UART data rates is

1.8Mb/s. Two-way hardware control is implemented by UARTRTS and UARTCTS. If input UARTCTS signal becomes high,

transmission will be stopped, else it will be continued. If internal UART FIFO will be full, output UARTRTS signal becomes

high, else becomes low.

Flash Card interface

PT8R1202 supports two types of flash card such as SmartMedia™ flash devices and MMC or SDCard flash devices. This flash

card devices are small removable cards that contain one or two NAND Flash devices. Alternatively, the system designer can use

non-removable NAND flash chips. PT8R1202 supports hardware interface logic for SmartMedia™ devices, but only supports

software firmware using GPIO for MMC or SDCard. The SmartMedia™ electrical interface uses an 8-bit data/address bus and

6-bit control lines. PT8R1202 supports up to 4GB SmartMedia™ devices.

PT0137(08/04)

Ver:4

21

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

JTAG interface

PT8R1202 supports IEEE1149.1 standard specification compliant interface. This interface supports basic test commands such as

EXTEST, SMAPLE, BYPASS, and IDCODE. Beside of this, JTAG interface can be used communication channel with PTI

enhanced on-chip hardware debugger controller. Using on-chip debugger controller, off-chip debug handler or external host can

access internal peripheral device registers, external memory interface, and executes real-timing hardware debugging and

monitoring of on-chip embedded RISC processor. Also, external host can communicate on-chip RISC processor through JTAG

with on-chip hardware managed channel buffer. There are sixteen debug registers specified and these will be used in PTI own

development chip manager software, named as V6EMU™. The length of instruction register in JTAG interface is 6bit and that

of debug data register is 32bit. Table 11. shows the summary of TAP instructions supported in PT8R1202 and Table 12. shows

the summary of debugger registers in JTAG interface.

Table 11. TAP instructions

Instruction

Opcode

Description

EXTEST

0x000000

EXTEST initiates testing of external circuitry, typically board-level interconnects and off chip

circuitry. EXTEST connects the Boundary-Scan register between TDI and TDO in the SHIFT_DR

state only. When EXTEXT is selected, all output signal pin values are driven by values shifted into

the Boundary-Scan register and may change only on the falling-edge of TCK in the Update_DR

state. Also, when EXTEST is selected, all system input pin states must be loaded into the

Boundary-Scan register on the rising-edge of TCK in the Capture_DR state. Values shifted into

input latches in the Boundary-Scan register are never used by the processor’s internal logic.

SAMPLE / PRELOAD performs two functions:

SAMPLE

0x000001

• When the TAP controller is in the Capture-DR state, the SAMPLE instruction occurs on the

rising edge of TCK and provides a snapshot of the component’s normal operation without

interfering with that normal operation. The instruction causes Boundary-Scan register cells

associated with outputs to SAMPLE the value being driven by or to the processor.

• When the TAP controller is in the Update-DR state, the PRELOAD instruction occurs on the

falling edge of TCK. This instruction causes the transfer of data held in the Boundary-Scan cells to

the slave register cells. Typically the slave latched data is then applied to the system outputs by

means of the EXTEST instruction.

IDCODE is used in conjunction with the device identification register. It connects the

identification register between TDI and TDO in the Shift_DR state. When selected, IDCODE

parallel-loads the hard-wired identification code (32 bits) on TDO into the identification register on

the rising edge of TCK in the Capture_DR state.

NOTE: The device identification register is not altered by data being shifted in on TDI.

DEBUG instruction select the DEBUGReg with address indicator SSSS.

IDCODE

0x011111

0x10SSSS

DEBUG

• When the TAP controller is in the Capture-DR state, the DEBUG instruction occurs on the rising

edge of TCK and executes a snapshot of DEBUG register addressed SSSS into DEBUGReg.

• When the TAP controller is in the Update-DR state, the DEBUG instruction occurs on the falling

edge of TCK. This instruction causes the transfer of data held in DEBUGReg to DEBUG register

addressed SSSS.

(Private Instruction)

BYPASS

0x111111

BYPASS instruction selects the Bypass register between TDI and TDO pins while in SHIFT_DR

state, effectively bypassing the processor’s test logic. 0 is captured in the CAPTURE_DR state.

While this instruction is in effect, all other test data registers have no effect on the operation of the

system. Test data registers with both test and system functionality perform their system functions

when this instruction is selected

Table 12. Debug interface register address map

Address

0x0

0x1

0x2

0x3

Name

Attribute

Write

Read

Description

DEBUG_CMD

DEBUG_CTRL

DEBUG_TX

DEBUG_RX

debugger control register

debug handler control register

debug handler transmit register

debug handler receive register

Read

Write

DEBUG_ADDR

debugger address register

0x4

0x5

DEBUG_WDATA0

(DEBUG_CYC_CNT)

DEBUG_RDATA0

DEBUG_INST_ACNT

DEBUG_INST_SCNT

DEBUG_BREAK_PC

debugger write data register0(31:0)

debugger instruction step count

debugger read data register0(31:0)

debugger instruction cycle accumulator

debugger instruction step cycle count

debugger breakpoint PC register

0x7

0x9

0xA

0xB

Read

Write

PT0137(08/04)

Ver:4

22

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

Electrical specifications

Absolute Maximum Rating

Symbol

Parameter

Condition

Min

Typ

Max

Unit

TA

Storage Temperature

-40

150

°C

Supply Voltages : SPLL_VCC, APLL_VCC, VCC

-0.4

2.1

V

TA= +25°C

Supply Voltage : ACODEC_VCC

Supply Voltage : VPP

-0.4

3.6

V

Other Terminal Voltage

Recommended Operating Conditions

Symbol

TA

Parameter

Condition

Min

-40

Typ

25

Max

105

Unit

°C

Ambient Temperature

Supply Voltage VCC (to VCC_GND)*

VCC

1.62

1.8

1.98

V

TA= +25°C

TA=+25°C

VPP

Supply Voltage VPP (to VPP_GND)*

2.7

3.0

1.8

3.6**

1.98

V

SPVCC

APVCC

Supply Voltage SPLL_VCC (to SPLL_GND)*

Supply Voltage APLL_VCC (to APLL_GND)*

1.62

Supply Voltage ACODEC_VCC(to

ACODEC_GND)*

ACVCC

2.7

3.0

3.6

0.3

V

TA=+25°C

Difference between any two VCC, SPLL_VCC,

APLL_VCC terminals

* An external regulator is required for reliability

PT0137(08/04)

Ver:4

23

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

DC/AC Specification

Unless otherwise noted, the specification applies for: TA=+25°C, Typical conditions

Sym

Parameter

Condition

Min

Typ

Max

Unit

Digital Inputs

VIH

Logical input High

2.0

-0.3

-1

VPP

0.8

1

V

VIL

Logical input Low

V

ILEAK

Input leakage current

0.5 < VIN < V_CC-0.5

µA

Digital Outputs

VOH

VOL

Logical output High

2.4

-1

V

Logical output Low

0.4

1

V

Tri-state output leakage current

µA

Low level max output current for MEMA,

MEMD, REB, WEB

High level max output current for MEMA,

MEMD, REB, WEB

13.2

24.8

mA

Low level max output current for others

High level max output current for others

6.6

mA

12.4

USB Signals (D+, D-)

VDI

Differential input sensitivity

(D+) – (D-)

-0.2

0.8

0.7

0.2

2.5

1.7

0.3

V

VCM

VSE

Differential common mode range

Single ended receiver threshold

Output low voltage

V

VUOL

VUOH

IUOZ

RL=1.5K

V

Output high voltage

RL=1.5K

2.8

-10

V

Tri-state date line leakage

O < VIN < 3.3

10

µA

Current Consumption

Operating supply current of VCC

under 96MHz operation

under IDLE operation

100

3.5

mA

Low power mode supply current of VCC

Sleep mode supply current of VCC

0.55

10

Operating supply current of VPP

Sleep mode supply current of VPP

under oscillator operation

0.5

Operating supply current of SPLL_VCC

Sleep mode supply current of SPLL_VCC

Operating supply current of APLL_VCC

Sleep mode supply current of APLL_VCC

Operating supply current of ACODEC_VCC

Sleep mode supply current of ACODEC_VCC

3.5

0.35

1.6

0.2

11.8

0.12

System Power Consumption

Deep sleep with RTC timer operation

Sleep with RTC timer operation

BT data transfer (DM5)*

VPP, ACODEC_VCC =3.0V, others all 1.8V

4.7

18.2

41

mW

BT voice connection (HV1)*

MP3 decoding from NAND flash*

45

111

139

91

MP3(128kbps) streaming from Bluetooth link* VPP, ACODEC_VCC =3.0V, others all 1.8V

SBC(384kbps) streaming from Bluetooth link*

VOIP(G.723.1) call with Bluetooth link*

VPP, ACODEC_VCC =3.0V, others all 1.8V

136

* The actual power consumption depends on real situation.

PT0137(08/04)

Ver:4

24

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

Application Note

PT8R1202 reference configuration

13MHz

16MHz

1.8V

LDO

3.3V

LDO

FLASHCSB

SRAMCSB

IOCSB0/1

IOWAIT

LCD

Compact

Flash

Ethernet

IDE

NOR Flash

SRAM

RESET

MEMA[19:0]

WEB,REB,UBE,LBE

TXACTIVE

RXACTIVE

TXDATAEN

TXDATA

RXDATA

SYNCDETECT

DATACLK

TCK

TXACTIVE(GPA0)

RXACTIVE(GPA1)

TXDATAEN(GPA2)

TXDATA(GPA3)

RXDATA(GPA4)

SYNCDETECT(GPA5)

MEMD[15:0]

PCMCLK,

PCMSYNC,

PCMIN,

PCM

Codec

(MC145483)

DATACLK(GPA6)

PCMOUT

BLUERF_TCK(GPA8)

BLUERF_TMS(GPA9)

BLUERF_TDI(GPA10)

BLUERF_TDO(GPA11)

TMS

TDI

TDO

EARA

EARB

32.768kHz

AUDSCLK,

AUDLRCLK,

AUDOUT,

Audio DAC

(CS42L50)

GDM1002

PT8R1002

AUDMCLK,

AUDIN,

GPIO(SCL), GPIO(SDA)

D+

D-

USB

SM_CSB,CLE,ALE

SM_WE,OE,RB

SM_DATA[7:0]

GPIOs

MMC/SD

card

PC serial

port

Nand Flash

RS232

driver

UARTTX,UARTRX,

UARTRTS,UARTCTS

JTAG_TCK,JTAG_TMS,

JTAG_TDI,JTAG_TDO,

JTAG_RST

GPG0(KEY0),

GPG1(KEY1),

GPG2(KEY2)

PC Parallel

port

Applications

Wireless speaker for DVD / PC surround speaker with CD quality, low-latency audio transmission

Portable digital audio player with Bluetooth streaming and storage function

Bluetooth stereo headset with combining A/V profile and headset profile

3-in-one multi-functions(Bluetooth, USB audio, USB flash storage) USB dongle

Bluetooth USB printer adaptor with USB host function

Bluetooth handsfree with on-chip echo cancellation function

Bluetooth VOIP phone with on-chip speech compression function

PT0137(08/04)

Ver:4

25

Data Sheet

PT8R1202

PTPericom Technology Inc.

Bluetooth Digital Audio Streaming IC

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

Notes

Pericom Technology Inc.

Email: support@pti.com.cn

No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China

Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181

Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong

Tel: (852)-2243 3660 Fax: (852)- 2243 3667

3545 North First Street, San Jose, California 95134, USA

Tel: (1)-408-435 0800 Fax: (1)-408-435 1100

Web Site: www.pti.com.cn, www.pti-ic.com

China:

U.S.A.:

Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design

or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than

the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement

or other rights, of Pericom Technology Incorporation.

PT0137(08/04)

Ver:4

26


型号：	PT8R1202ND
厂家：	DIODES INCORPORATED
描述：	Digital Signal Processor, 32-Bit Size, CMOS, PBGA144
文件：	总26页 (文件大小：656K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PT8R1202ND [DIODES]

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