ST1500ACAK-FREQ3(T) [DIODES]

HCMOS/TTL Output Clock Oscillator, 70MHz Min, 100MHz Max,;
ST1500ACAK-FREQ3(T)
型号: ST1500ACAK-FREQ3(T)
厂家: DIODES INCORPORATED    DIODES INCORPORATED
描述:

HCMOS/TTL Output Clock Oscillator, 70MHz Min, 100MHz Max,

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中文:  中文翻译
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SaRonix  
Voltage Controlled Crystal Oscillator  
5V, HCMOS  
S150x / ST150x Series  
Technical Data  
Frequency Range:  
1.5 MHz to 100 MHz ( Full Size )  
1.5 MHz to 28.6363 MHz ( Half Size )  
Frequency Stability:  
20ꢀ 25 or 50 ppm over all conditionsꢁ operating  
temperatureꢀ voltage changeꢀ load changeꢀ calibration  
toleranceꢀ shock and vibrationꢀ with V = 2.5V  
C
Aging @ 25°C:  
3ppm max per yearꢀ 10ppm max for 10 years  
Temperature Range:  
Operatingꢁ  
Storageꢁ  
0 to +70°C or -40 to +85°C  
-55 to +125°C  
Supply Voltage:  
Recommended Operatingꢁ  
5V 10ꢃ  
ACTUAL SIZE  
Supply Current:  
Full Size Packageꢁ  
1.5 to 11.9MHzꢁ  
12 to 70MHzꢁ  
70+ to 100MHzꢁ  
20mA max with 30pF load  
65mA max with 30pF load  
60mA max with 15pF load  
Description  
A voltage controlled crystal oscillator  
designed with excellent Jitter character-  
istics - ideal for telecom applications.  
TheHCMOSoutputcandrivehighspeed  
CMOS & TTL loads. Devices are in  
standard 14-pin DIP metal packages. Pin  
7(4 on 1/2 size) is grounded to reduce  
EMI. SMD DIL 14 version is available  
utilizing adaptor technology (see sepa-  
rate data sheet for dimensions).  
Half Size Packageꢁ  
1.5 to 28.6363MHzꢁ 25mA max with 30pF load  
Output Drive:  
Symmetryꢁ  
45/55ꢃ max @ 50ꢃ V  
40/60ꢃ max @ 50ꢃ V  
1.5 to 70 MHz  
70+ to 100 MHz  
DD  
DD  
Rise & Fall Timesꢁ  
1.5 to 25 MHzꢁ  
25+ to 70 MHzꢁ  
70+ to 100 MHzꢁ  
1.5 to 28.6363 MHzꢁ  
20ꢃ to 80ꢃ V  
DD  
8ns max riseꢀ 6ns max fallꢀ full size package  
5ns max rise & fallꢀ full size package  
3ns max rise & fallꢀ full size package  
6ns max rise & fallꢀ half size package  
Logic 0ꢁ  
Logic 1ꢁ  
10ꢃ V  
90ꢃ V  
max  
min  
DD  
DD  
Applications & Features  
Loadꢁ  
Period Jitter RMSꢁ  
30pF to 70 MHzꢀ 15pF from 70+ to 100 MHz  
3.5ps max  
Phase Locked Loop (PLL) Clock &  
DataRecoveryFrequencyTranslationꢀ  
Frequency Synthesis in Videoꢀ Video  
Compressionꢀ Telephonyꢀ and LAN/  
WAN Data Communication and other  
Telecommunication applications.  
HCMOS / TTL compatible  
Pull Characteristics:  
Input Impedance (pin 1)ꢁ  
Frequency Response (-3dB)ꢁ  
Pullabilityꢁ  
50Kmin  
10 kHz min  
50ꢀ 100ꢀ 200ppm APRꢂ minꢀ See Part Numbering ꢄuide  
0.5 to 4.5V  
Frequency increases when Control Voltage increases  
5 or 10ꢃ max  
2.5V  
Control Voltageꢁ  
Transfer Functionꢁ  
Linearityꢁ  
3.5ps max RMS period jitter  
50ꢀ 100 or 200 ppm APRꢂ  
20ꢀ 25 or 50 ppm Stability  
Center Control Voltageꢁ  
Tri-State option available  
Mechanical:  
SMD versions for IR reflow available  
Shockꢁ  
Solderabilityꢁ  
Terminal Strengthꢁ  
Vibrationꢁ  
MIL-STD-883ꢀ Method 2002ꢀ Condition B  
MIL-STD-883ꢀ Method 2003  
MIL-STD-883ꢀ Method 2004ꢀ Conditions B2  
MIL-STD-883ꢀ Method 2007ꢀ Condition A  
MIL-STD-202ꢀ Method 215  
Output Waveform  
CMOS  
Solvent Resistanceꢁ  
Resistance to Soldering Heatꢁ  
T
r
T
f
MIL-STD-202ꢀ Method 210ꢀ Conditions Aꢀ B or C  
( I or J for ꢄull Wing or SMD)  
Logic 1  
80%V  
50%V  
20%V  
DD  
DD  
DD  
Environmental:  
ꢄross Leak Testꢁ  
Fine Leak Testꢁ  
Thermal Shockꢁ  
MIL-STD-883Cꢀ Method 1014ꢀ Condition C  
MIL-STD-883Cꢀ Method 1014ꢀ Condition A2  
MIL-STD-883Cꢀ Method 1011ꢀ Condition A  
MIL-STD-883Cꢀ Method 1004  
Moisture Resistanceꢁ  
Logic 0  
APR = (VCXO Pull relative to specified Output Frequency) (VCXO Frequency Stability) – (Aging)  
SYMMETRY  
10 years aging is inclusive on 1/2 size version  
DS-197 REV E  
SaRonix  
www.pericom.com/saronix  
SaRonix  
Voltage Controlled Crystal Oscillator  
5V, HCMOS  
S150x / ST150x Series  
Technical Data  
Package Details  
Part Numbering Guide  
S T 1509 A A A K - 19.4400 (T)  
SaRonix  
0.2" HIGH, FULL SIZE PACKAGE  
ꢃ.2ꢅ  
.±22  
±1.2  
pax  
Packing Method  
pax  
2.91  
.ꢅ±ꢃ  
(T) = Ta0e & Reelm SMD versitns  
full reel increpenꢀs tnly (±220cs)  
Blank = Bulk  
.2ꢆ6  
pax  
Blank = Ntn TriꢄSꢀaꢀe  
T = TriꢄSꢀaꢀe  
6.ꢆꢃ±2.ꢃ1  
2.±ꢃ±2.2±  
ꢆ.9-±.±ꢃ  
.1ꢃꢃ±.212  
Frequency (MHz)  
.-6±.2ꢅ  
.21ꢅ±.22ꢆ  
Package Size  
1ꢃ22 = Full Size  
1ꢃ29 = 1/± Size ꢀt ±ꢅ.6ꢆ6ꢆ MHz  
Package Options  
*
If Full Size Package (S1500)  
Blank = Sꢀandard 2.ꢆ" highm Thruꢄhtle(ntꢀ shtwn)  
L = 2.±" highm Thruꢄhtle  
1ꢃ.±-±.1ꢆ  
.622±.22ꢃ  
Pin 3  
Pin 1  
Pin 7  
Stability Tolerance  
J = 2.±" highm Gull Wing (ntꢀ shtwn)  
K = 2.ꢆ" highm Gull Wing (ntꢀ shtwn)  
S = 2.±" highm wiꢀh True SMD Ada0ꢀtr (ntꢀ shtwn)  
U = 2.ꢆ" highm wiꢀh True SMD Ada0ꢀtr (ntꢀ shtwn)  
If Half Size Package (S1509)  
Blank = Sꢀandard 2.±" highm Thruꢄhtle  
J = 2.±" highm Gull Wing (ntꢀ shtwn)  
Linearity  
AA = ±±200pm 2 ꢀt ꢁ+2ꢂ°  
A = ±±ꢃ00pm 2 ꢀt ꢁ+2ꢂ°  
B = ±ꢃ200pm 2 ꢀt ꢁ+2ꢂ°  
E = ±ꢃ200pm ꢄ-2 ꢀt ꢁꢅꢃꢂ°  
1ꢆ.2  
.ꢃ12  
pax  
+.+ꢃ  
pax  
.ꢆ2ꢃ  
Pullability (min APR)**  
A = ±ꢃ200p  
B = ±12200p  
° = ±±2200p  
Pin 12  
Pin 14  
Pin 8  
*
*
*
(-) Glass Insulaꢀtrs  
Pin Function:  
A = ꢃ%  
B = 12%  
( ctnꢀacꢀ SaRtnix ftr  
available frequencies)  
Pin ꢅ: OUTPUT  
Pin 1±: N/° (t0ꢀitnal)  
Pin 1: °tnꢀrtl Vtlꢀage  
Pin ꢆ: TriꢄSꢀaꢀe °tnꢀrtl (t0ꢀitnal)  
Pin 1-: VD° (V  
)
Pin +: GND/°ase (V  
)
DD  
SS  
*
Prtducꢀs are available wiꢀh ꢀhe ftlltwing ctpbinaꢀitn tf Frequencym Pull and Package  
Marking Format**  
Includes Daꢀe °tdem Frequencym Parꢀ Nupber  
Frequency  
1.ꢃ ꢀt ±ꢅ.6ꢆ6ꢆMHz  
Pullability  
Full Size (S1500)  
Lm Jm S  
Half Size (S1509)  
Am B  
Sꢀandardm J  
°
Sꢀandardm Km U  
Sꢀandardm Km U  
SARONIX  
V°XO  
±ꢅ.6ꢆ6ꢆꢁ ꢀt 122MHz Am Bm °  
** APR = (V°XO Pull relaꢀive ꢀt s0ecified Ouꢀ0uꢀ Frequency) (V°XO Frequency Sꢀabiliꢀy) – (Aging)  
10 years aging is inclusive on 1/2 size version  
Dentꢀes Pin 1  
HALF SIZE PACKAGE  
Tri-State Logic Table  
1ꢆ.2  
pax  
.ꢃ12  
2.91  
.2ꢆ6  
Pin ꢆ(±) In0uꢀ  
Pin ꢅ(ꢃ) Ouꢀ0uꢀ  
Oscillaꢀitn  
Required In0uꢀ Levels tn Pin ꢆ(±):  
Ltgic 1 = ꢆ.2V pin  
pax  
ꢃ.2ꢅ  
.±22  
pax  
Ltgic 1 tr N°  
6.ꢆꢃ±2.ꢃ1  
2.±ꢃ±2.2±  
Ltgic 2 tr GND  
High Ip0edance  
Ltgic 2 = 2.ꢃV pax  
.-6±.2ꢅ  
.21ꢅ±.22ꢆ  
±.ꢃ-  
.122  
Test Circuit  
Pin 2  
O0ꢀitnal  
TriꢄSꢀaꢀe °tnꢀrtl  
+.6±±.±2  
.ꢆ22±.22ꢅ  
Pin 4  
GND °ase (V  
)
SS  
TEST  
Pin 1  
°tnꢀrtl  
Vtlꢀage  
POINT  
pA  
M
1ꢆ.2  
.ꢃ12  
pax  
+.6±±.±2  
.ꢆ22±.22ꢅ  
Pin 1-(ꢅ)  
Pin ꢅ(ꢃ)  
Pin +(-)  
VDD  
OUT  
Pin 8  
Pin 5  
Ouꢀ0uꢀ  
OS°ILLATOR  
GND  
°
(Ntꢀe A) = ꢆ20F  
(1ꢃ0F > +2 MHz)  
L
POWER  
SUPPLY  
V
DD  
V M  
Marking Format**  
Includes Daꢀe °tdem Frequencym Parꢀ Nupber  
Pin ꢆ(±)  
Pin 1(1)  
*
SARONIX  
°ONTROL  
VOLTAGE  
OPTIONAL  
TRIꢄSTATE  
NOTE A: ° includes 0rtbe and fixꢀure ca0aciꢀance.  
L
*
Iꢀeps in brackeꢀs( ) re0resenꢀ Half Size ptdel  
Dentꢀes Pin 1  
All specifications are subject to change without notice.  
**Exacꢀ ltcaꢀitn tf iꢀeps pay vary  
pp  
Scale: Ntne (Dipensitns in  
)
DS-197 REV E  
inches  
SaRonix  
www.pericom.com/saronix  
SaRonix  
True SMDAdaptor - 7.57mm High  
Technical Data  
REV A  
SaRonix  
www.pericom.com/saronix  
SaRonix  
True SMDAdaptor - 9.85mm High  
Technical Data  
REV A  
SaRonix  
www.pericom.com/saronix  

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