ZABG6004 [DIODES]
6 STAGE FET LNA BIAS CONTROLLER;
| 型号： | ZABG6004 |
| 厂家： | 
DIODES INCORPORATED |
| 描述： | 6 STAGE FET LNA BIAS CONTROLLER |
| 文件： | 总11页 (文件大小：447K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZABG6004
6 STAGE FET LNA BIAS CONTROLLER
Summary
The ZABG6004 is an advanced GaAs and HEMT FETs bias controller designed to operate from minimal supply rails and intended primarily for
satellite Low Noise Blocks (LNBs). With the addition of one capacitor and two resistors, the ZABG6004 provides drain voltage and current control
for up to 6 external grounded source FETs. Generating the regulated negative rail required for FET gate biasing whilst operating from a single
supply of 2.1V to 5V. The -2V negative bias can also be used to supply other external circuits. Setting drain currents on the ZABG6004 uses two
resistors and drain current control is split between the six FETs in a group of two and a group of four. This allows the operating current of input
FETs to be adjusted to minimize noise, whilst the following FET stages can be adjusted for maximum gain.
Features
Applications
Provides Bias for up to 6 GaAs and HEMT FETs
Low Power LNB’s
Digital LNB’s
Operating Range of 2.1V to 5V
Ultra-low Operating Current of 1.1mA
IP LNB’s
Dynamic FET Protection
Twin LNB’s and Quad LNB’s
General Purpose LNA Bias
Amplifier FET Drain Current Selectable (4mA to 15mA)
Regulated Negative Rail Generator Requires only 1 External
Capacitor
Expended Temperature Range of -40°C to +105°C
U-QFN3030-16 (Type B) and QSOP-20 Surface Mount Package
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
Twin LNB System Diagrams
IF Switching,
gain and
control
Gain Stages
GaAs FETs
Down
Conversion
MUX
IF Gain
ZABG
6004
Controller
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ZABG6004
Document number: DS38917 Rev. 2 - 2
ZABG6004
Device Description
The ZABG series of devices are designed to meet the bias requirements of GaAs and HEMT FETs commonly used in satellite receiver LNBs
with a minimum of external components whilst operating from a minimal voltage supply and using minimal current.
The ZABG6004 has six FET bias stages that can be programmed to provide a constant drain current. Programming of the FET bias stage
arrangement and the operating currents of each FET group is achieved by resistors connected to the RCAL1 and RCAL2 pins, allowing input FETs
to be biased for optimum noise and the later stages for optimum gain. All FET groups can be operated at currents in the range 4mA to 15mA,
RCAL1 sets the drain current for D1 and D4 and RCAL2 sets the drain current for D2, D3, D5 and D6. It is not recommended to connect RCAL1 and
RCAL2 together.
Drain voltages of amplifier stages are set at 2.0V and are current limited to approximately current set by their associated RCAL resistors.
Depletion mode FETs require a negative voltage bias supply when operated in grounded source circuits. The ZABG6004 includes an integrated
switched capacitor DC-DC converter generating a regulated output of -2V to allow single supply operation. The ZABG6004 has been designed to
be used with supply rails of 2.1V to 5.0V and the VDD range has been extended to 5.5V to allow for 10% supply variation.
It is possible to use less than the full complement of FET bias controls, unused drain and gate connections can be left open circuit without
affecting operation of the remaining bias circuits.
To protect the external FETs the circuits have been designed to ensure that, under any conditions including power up/down transients, the gate
drive from the bias circuits cannot exceed -2.5V. Additionally each stage has its own individual current limiter. Furthermore if the negative rail
experiences a fault condition, such as overload or short circuit, the drain supply to the FETs will be limited, avoiding excessive current flow.
The ZABG6004 is available in the U-QFN3030-16 (Type B) and the QSOP-20 packages.
Device operating temperature is -40°C to +105°C to suit a wide range of environmental conditions.
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ZABG6004
Document number: DS38917 Rev. 2 - 2
ZABG6004
Pin Assignments and Descriptions
(Top View)
(Top View)
20
1
2
3
D1
G1
D2
VDD
G1 D1 VDD D4
19 D4
13
16
15 14
18
17
16
15
14
G4
D5
G5
D6
G6
1
2
3
4
12
11
10
9
D2
G2
D3
G3
G4
D5
G5
D6
G2
D3
4
5
Gnd
G3
Gnd
NC
6
7
5
6
7
8
8
13 RCAL1
CSUB
RCAL1 G6
RCAL2
NC
RCAL2
CSUB
9
12
11
10
NC
U-QFN3030-16 (Type B)
QSOP-20
Pin Number
U-QFN3030-16
Pin Name
Description
QSOP-20
(Type B)
3
D2
G2
Drain GaAs FET 2
4
Gate GaAs FET 2
2
3
5
D3
Drain GaAs FET 3
6
G3
Gate GaAs FET 3
4
11
12
13
14
15
16
17
18
19
20
1
Negative rail reservoir capacitor
CSUB
RCAL2
RCAL1
G6
5
Drain current setting for D1 and D4
Drain current setting for D2, D3, D5 and D6
Gate GaAs FET 6
6
7
8
D6
Drain GaAs FET 6
9
G5
Gate GaAs FET 5
10
11
12
13
14
15
D5
Drain GaAs FET 5
G4
Gate GaAs FET 4
D4
Drain GaAs FET 4
Supply voltage
VDD
D1
Drain GaAs FET 1
2
G1
Gate GaAs FET 1
16
Pad
—
Gnd
Must be connected to Ground
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ZABG6004
Document number: DS38917 Rev. 2 - 2
ZABG6004
Maximum Ratings
Symbol
Parameter
Rating
-0.6 to +6
100
Unit
V
Supply Voltage
Supply Current
VDD
IDD
—
mA
mW
mW
°C
Power Dissipation U-QFN3030-16 (Type B)
Power Dissipation QSOP-20
Junction Temperature
650
—
600
+135
TJ
Storage Temperature Range
-40 to +150
°C
TSTG
Recommended Operating Conditions (Note 8)
Symbol
VDD
Parameter
Operating Voltage Range
Operating Temperature Range
Min
2.1
-40
Max
5.5
Unit
V
TA
+105
°C
Electrical Characteristics (@TA = +25°C, VDD = 2.3V, RCAL1 = RCAL2 = 33kΩ, setting ID1 to ID4 set to 10mA.)
Symbol
IDD
Parameter
Supply Current
Conditions
Min
—
Typ
1.1
—
Max
Unit
mA
mA
V
ID1-6 = 0
2.5
65
IDD(L)
ID1-6 = 10mA
ICSUB = 0
—
VCSUB
VCSUB(L)
fOSC
-2.5
—
-2.0
—
-1.5
-1.5
—
Substrate Voltage (Note 5)
Oscillator Frequency
ICSUB = -20µA
V
—
—
7.5
MHz
CGATE-GND = 10nF
CDRAIN-GND = 10nF
VD(NOISE)
Drain Voltage (Note 6)
—
—
—
—
0.02
VPK-PK
CGATE-GND = 10nF
CDRAIN-GND = 10nF
VG(NOISE)
Gate Voltage (Note 6)
0.005
VPK-PK
Gate Characteristics
Gate (G1 to G6)
IG
Current Range
—
-50
-2.5
0
—
-2.0
0.7
60
-1.5
1.0
µA
V
VG(L)
VG(H)
Voltage Low
Voltage High
ID = 12mA, IG = -10µA
ID = 8mA, IG = 0
V
Drain Characteristics
Drain (D1 to D6)
ID
Current Range
D1 and D6
4
8
—
10
15
12
2.2
—
mA
mA
V
ID(OP)
Current Operating (Note 4)
Voltage Operating (Note 7)
delta VD vs VDD
Standard Application Circuit
ID = 10mA
VD(OP)
1.8
—
—
—
2.0
dVD/dVDD
dID/dVDD
dVD/dTA
VDD = 2.3V to 5.5V
VDD = 2.3V to 5.5V
TA = -40°C to +105°C
0.075
0.7
%/V
%/V
ppm
delta ID vs VDD
—
delta VD vs TA
150
—
Notes:
4. Characteristics are measured using up to two external reference resistors, RCAL1 and RCAL2
.
5. The negative bias voltages are generated on-chip using an internal oscillator. An external 47nF capacitor is required for this purpose.
6. Noise voltage measurements are made with FETs and gate and drain capacitors of value 10nF in place. Noise voltages are not measured in production.
7. The maximum operating drain voltage is equal to VDD or VD(OP) max whichever is lower.
8. ESD sensitive, handling precautions are recommended.
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ZABG6004
Document number: DS38917 Rev. 2 - 2
ZABG6004
Typical Characteristics (@TA = +25°C, VDD = 2.3V, RCAL1 = RCAL2 = 33kΩ (setting ID to 10mA), unless otherwise stated.)
Drain Voltage vs Temperature Drain Current vs Temperature
12
11.5
11
2.2
2.15
2.1
10.5
10
2.05
2
9.5
9
1.95
1.9
8.5
8
1.85
1.8
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
Drain Voltage vs Drain Current
CSUB Voltage vs Temperature
2.1
2.08
2.06
2.04
2.02
2
-1.5
-1.6
-1.7
-1.8
-1.9
-2
1.98
1.96
1.94
1.92
1.9
-2.1
-2.2
-2.3
-2.4
-2.5
Vdd = 2.3V
Vdd > 2.6V
4
5
6
7
8
9
10 11 12 13 14 15
-40
-20
0
20
40
60
80
100
Temperature (°C)
Drain Current (mA)
Drain Current vs RCAL
15
14
13
12
11
10
9
8
7
6
5
4
3
20
30
40
50
60
70
80
90
RCAL (k)
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ZABG6004
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ZABG6004
Application Information
Below are partial applications circuits for the ZABG6004 showing all external components needed for biasing one of the six FET stages available
as a typical LNA (Low Noise Amplifier). Each bias stage is provided with a gate and drain pin. The drain pin provides a regulated 2.0V supply that
includes a drain current monitor. The drain current taken by the external FET is compared with a user selected level, generating a signal that
adjusts the gate voltage of the FET to obtain the required drain current. If for any reason, an attempt is made to draw more than the user set drain
current from the drain pin, the drain voltage will be reduced to ensure excess current is not taken. The gate pin drivers are also current limited.
The bias stages are split up into two groups, with the drain current of each group set by an external RCAL resistor. RCAL1 sets the drain currents of
stages 1 and 4, whilst RCAL2 sets the drain currents of stages 2, 3, 5 and 6.
This allows the optimization of drain currents for differing tasks such as input stages where noise can be critical and later amplifier stages where
gain may be more important. A graph showing the relationship between the value of RCAL and ID is provided in the Typical Characteristics section
of this datasheet.
ZABG6004JA16TC
L*
C1
10nF
C*
*Stripline Elements
VDD
L*
C2
C*
10nF
13
16
15 14
1
2
3
4
12
11
10
9
D2
G2
D3
G3
G4
D5
G5
D6
Gnd
5
6
7
8
CSUB
47nF
The Gnd flag on the underside ZABG6004JA16 must be connected to ground.
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ZABG6004
Document number: DS38917 Rev. 2 - 2
ZABG6004
Application Information (Cont.)
ZABG6004Q20TC
VDD
VDD
RCAL1
RCAL2
CSUB
NC
NC
NC
CSUB
47nF
RCAL2
RCAL1
The ZABG6004 includes a switched capacitor DC-DC converter that is used to generate the negative supply required to bias depletion mode FETs
used in common source circuit configuration as shown above. This converter uses an external capacitor CSUB as the output reservoir capacitor.
The circuit provides a regulated -2V supply both for gate driver use and for external use if required (for extra discrete bias stages, mixer bias, local
oscillator bias etc.). The -2V supply is available from the CSUB pin.
If any bias stages are not required, their gate and drain pins may be left open circuit. If all bias stages associated with an RCAL resistor are not
required, then this resistor may be omitted.
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ZABG6004
Ordering Information
Part Number
Package
Reel Size (inches)
Tape Width (mm)
Quantity Per Reel
3,000
ZABG6004JA16TC
ZABG6004Q20TC
U-QFN3030-16 (Type B)
QSOP-20
13
13
12
16
2,500
Marking Information
(1) U-QFN3030-16 (Type B)
(Top View)
Pin 1
ZABG
6004
YYWW
Part Name
Date Code
Year/Week
(2) QSOP-20
(Top View)
Part Name
ZABG6004
Date Code
Year/Week
YYWW
Pin 1
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ZABG6004
Document number: DS38917 Rev. 2 - 2
ZABG6004
Package Outline Dimensions
Please see http://www.diodes.com/package-outlines.html for the latest version.
(1) U-QFN3030-16 (Type B)
A3
A1
A
U-QFN3030-16
Type B
Dim
A
A1
A3
b
D
D2
E
Min
0.55
0
Max
0.65
0.05
-
0.28
3.05
1.60
3.05
1.60
-
Typ
0.60
0.02
0.15
0.23
3.00
1.50
3.00
1.50
0.50
0.40
0.625
Side View
D
e
-
0.18
2.95
1.40
2.95
1.40
-
(Pin #1 ID)
0.450
0
0
2
.
0
R
E2
e
L
E
E2
D2
0.35
-
0.45
-
Z
L (16x)
All Dimensions in mm
Z (8x)
b (16x)
Bottom View
(2) QSOP-20
QSOP-20
D
Dim
A
A1
A2
b
c
D
E
E1
e
Min
1.55
0.10
1.40
0.20
0.18
8.56
5.79
3.81
Max
1.73
0.25
1.50
0.30
0.25
8.74
6.20
3.99
Typ
ZD
-
-
-
-
-
-
-
-
E/2
E1/2
E1
SEE DETAIL 'A'
E
h
0.635 BSC
PIN 1
h
e
h
L
0.254
0.41
0.508
1.27
-
-
c
b
L1
L2
R
R1
ZD
θ
1.03 REF
0.254 BSC
1 ( 4x)
0.0762
0.0762
-
-
-
-
2
R1
R
A2
1.47 REF
A
0°
5°
0°
8°
15°
-
-
-
-
GAUGE PLANE
SEATING PLANE
θ1
θ2
A1
L
1( 4x)
L2
All Dimensions in mm
L1
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ZABG6004
Suggested Pad Layout
Please see http://www.diodes.com/package-outlines.html for the latest version.
(1) U-QFN3030-16 (Type B)
C
G
G1
Value
(in mm)
0.500
0.150
0.150
0.350
1.800
0.600
1.800
Dimensions
C
G
G1
X
X1
Y
Y1
Y1
X1
Y (16x)
X (16x)
(2) QSOP-20
X1
Y
Value
(in mm)
0.635
Dimensions
C
X
0.350
X1
Y
6.065
1.450
Y1
Y1
6.400
C
1
X
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ZABG6004
IMPORTANT NOTICE
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes
without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the
application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or
trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume
all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated
website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and
hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such unintended or unauthorized application.
Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings
noted herein may also be covered by one or more United States, international or foreign trademarks.
This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the
final and determinative format released by Diodes Incorporated.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express
written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the
labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any
use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related
information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its
representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2017, Diodes Incorporated
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