HMN328DLF-85 [DLGHANBIT]

Non-Volatile SRAM MODULE 256Kbit (32K x 8-Bit),28Pin DIP, 5V;


型号：	HMN328DLF-85
厂家：	DLG HANBIT
描述：	Non-Volatile SRAM MODULE 256Kbit (32K x 8-Bit),28Pin DIP, 5V 静态存储器
文件：	总7页 (文件大小：476K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLGHANBIT

DLGHANBIT Confidential

HMN328D

Non-Volatile SRAM MODULE 256Kbit (32K x 8-Bit),28Pin DIP, 5V

Part No. HMN328D

GENERAL DESCRIPTION

The HMN328D nonvolatile SRAM is a 262,144-bit static RAM organized as 32,768 bytes by 8 bits.

The HMN328D has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write

cycles of standard SRAM and integral control circuitry which constantly monitors the single 5V supply for an out-of-

tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the

memory until after V_CCreturns valid and write protection is unconditionally enabled to prevent garbled data. In addition the

SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is

switched on to sustain the memory until after V_CCreturns valid.

The HMN328D uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide non-

volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.

FEATURES

 Access time : 70 ns

PIN ASSIGNMENT

 High-density design : 256Kbit Design

 Battery internally isolated until power is applied

 Industry-standard 28-pin 32K x 8 pinout

A₁₄

A₁₂

A₇

A₆

A₅

A₄

A₃

V_CC

/WE

A₁₃

 Unlimited write cycles

 Data retention in the absence of V_CC

 5-years typical data retention in absence of power

 Automatic write-protection during power-up/power-down

cycles

A₈

A₉

A₁₁

 Data is automatically protected during power loss

 Industrial temperature operation

/OE

A₁₀

A₂

A₁

A₀

/CE

DQ₇

DQ₆

DQ₅

DQ₄

DQ₃

DQ₀

DQ₁

DQ₂

V_SS

OPTIONS

 Timing

70 ns

MARKING

- 70

- 85

85 ns

28-pin Encapsulated Package

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

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HMN328D

FUNCTIONAL DESCRIPTION

The HMN328D executes a read cycle whenever /WE is inactive(high) and /CE /OE are active(low). The address specified

by the address inputs(A₀-A₁₄) defines which of the 32,768 bytes of data is accessed. Valid data will be available to the

eight data output drivers within t_ACC(access time) after the last address input signal is stable.

When power is valid, the HMN328D operates as a standard CMOS SRAM. During power-down and power-up cycles, the

HMN328D acts as a nonvolatile memory, automatically protecting and preserving the memory contents.

The HMN328D is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs are

stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is

terminated by the rising edge of /WE. All address inputs must be kept valid throughout the write cycle. /WE must return

to the high state for a minimum recovery time (t_WR) before another cycle can be initiated. The /OE control signal should be

kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled (/CE and /OE

active) then WE will disable the outputs in t_ODWfrom its falling edge.

The HMN328D provides full functional capability for Vcc greater than 4.5 V and write protects by 4.37 V nominal. Power-

down/power-up control circuitry constantly monitors the V_CCsupply for a power-fail-detect threshold V_PFD. When V_CCfalls

below the V_PFDthreshold, the SRAM automatically write-protects the data. All inputs to the RAM become “don’t care” and

all outputs are high impedance. As Vcc falls below approximately 3 V, the power switching circuit connects the lithium

energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 3.0 volts, the power switching

circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume

after Vcc exceeds 4.5 volts.

BLOCK DIAGRAM

PIN DESCRIPTION

A₀-A₁₄

/OE

32K x 8

SRAM

Block

A₀-A₁₄: Address Input

/CE : Chip Enable

DQ₀-DQ₇

/WE

V_SS: Ground

Power

/CE _CON

DQ₀-DQ₇: Data In / Data Out

/WE : Write Enable

/OE : Output Enable

V_CC: Power (+5V)

V_CC

Power – Fail

/CE

Control

Lithium

Cell

NC : No Connection

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

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HMN328D

TRUTH TABLE

MODE

Not selected

Output disable

Read

/OE

/CE

/WE

I/O OPERATION

High Z

POWER

Standby

Active

High Z

D_OUT

Active

Write

D_IN

Active

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

RATING

CONDITIONS

DC voltage applied on V_CCrelative to V_SS

DC Voltage applied on any pin excluding V_CC

relative to V_SS

V_CC

-0.3V to 7.0V

V_T≤V_CC+0.3

V_T

-0.3V to 7.0V

0 to 70C

-40 to 85C

-40C to 85C

Commercial

Industrial

Operating temperature

T_OPR

Storage temperature

T_STG

NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.

Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Not recommend direct soldering by soldering machine, recommend by manual soldering or using socket.

RECOMMENDED DC OPERATING CONDITIONS ( T_A= T_OPR

)

PARAMETER

SYMBOL

MIN

4.5V

TYPICAL

MAX

5.5V

Supply Voltage

V_CC

5.0V

Ground

V_SS

Input high voltage

Input low voltage

V_IH

2.2

V_CC+0.3V

V_IL

-0.3

0.8V

NOTE: Typical values indicate operation at T_A= 25℃

URL : www.dlghb.co.kr

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HMN328D

DC ELECTRICAL CHARACTERISTICS (T_A= T_OPR, V_CCmin V_CC≤ V_CCmax

)

PARAMETER

CONDITIONS

V_IN=V_SSto V_CC

SYMBOL

MIN

TYP.

MAX

UNIT

±1

Input Leakage Current

I_LI

A

/CE=V_IHor /OE=V_IH

or /WE=V_IL

±1

Output Leakage Current

I_LO

A

Output high voltage

Output low voltage

Standby supply current

I_OH=-1.0mA

V_OH

V_OL

I_SB

2.4

0.4

I_OL= 2.1mA

㎃

/CE=V_IH

/CE≥V_CC-0.2V,

0V≤V_IN≤0.2V,

or V_IN≥V_CC-0.2V

Standby supply current

Operating supply current

I_SB1

2.5

100

A

Min.cycle,duty=100%,

㎃

I_CC

/CE=V_IL, I_I/O=0㎃

V_PFD

V_SO

Power-fail-detect voltage

Supply switch-over voltage

4.30

4.37

4.50

READ CYCLE (T_A= T_OPR, V_CCmin V_CC≤ V_CCmax

)

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNIT

Read Cycle Time

Address access Time

t_RC

t_ACC

t_ACE

t_OE

Chip enable access time

Output enable to output valid

Chip enable to output in high Z

Output enable to output high Z

Output hold from address change

Output enable end to chip select end

t_CHZ

t_OHZ

t_OH

t_OETCE

WRITE CYCLE (T_A= T_OPR, V_ccmin V_cc≤ V_ccmax

)

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNIT

Write Cycle Time

Chip enable to end of write

Address setup time

t_WC

t_CW

t_AS

Address valid to end of write

Write pulse width

t_AW

t_WP

Write recovery time

t_WR

t_DW

Data valid to end of write

Data hold from write time

Output active from end of write

Write end to chip enable end

t_DH

t_OW

t_WETCE

NOTE: 1. A write ends at the transition of /WE low to high.

URL : www.dlghb.co.kr

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HMN328D

CAPACITANCE (T_A=25℃, f=1MHz, V_CC=5.0V)

DESCRIPTION

Input Capacitance

Input/Output Capacitance

CONDITIONS

Input voltage = 0V

Output voltage = 0V

SYMBOL

C_IN

MAX

MIN

UNIT

C_I/O

POWER-DOWN/POWER-UP CYCLE (T_A= T_OPR,V_CC=5V)

PARAMETER

V_CCslew, 4.75 to 4.25V

V_CCslew, 4.75 to V_SO

SYMBOL

CONDITIONS

MIN

TYP.

MAX

UNIT

㎲

t_PF

t_FS

300

㎲

V_CCslew, V_SOto V_PFD(max)

t_PU

Time during which SRAM

is write-protected after V_CC

passes V_PFDon power-up.

Chip enable recovery time

t_CER

120

Data-retention time in

Absence of V_CC

T_A= 25℃

t_DR

years

Delay after V_CCslews down

past V_PFDbefore SRAM is

Write-protected.

㎲

Write-protect time

t_WPT

100

150

TIMING WAVEFORM

- Read Cycle

t_RC

Address

t_OD

t_ACC

t_OETCE

/CE

/OE

t_ACE

t_OE

t_OHZ

Data Valid

t_OH

_OUT

High-Z

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HMN328D

- Write Cycle

t_WC

Address

t_WR

t_WETCE

t_AW

t_CW

/CE

t_AS

t_WP

/WE

t_DW

t_DH

D_IN

Data-in Valid

t_OW

High-Z

D_OUT

Data Undefined (1)

- POWER-DOWN/POWER-UP TIMING

V_CC

4.75

V_PFD

4.25

V_SO

t_FS

t_PU

t_CER

t_DR

t_WPT

/CE

URL : www.dlghb.co.kr

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HMN328D

PACKAGE DIMENSION

Dimension

Min

Max

1.450

0.700

0.365

0.012

0.008

0.590

0.017

0.090

0.075

0.150

1.525

0.760

0.380

0.013

0.630

0.023

0.110

0.190

All dimensions are in inches.

ORDERING INFORMATION

H M N 32 8 D LF- 70

Speed options : 70 = 70 ns

85 = 85 ns

LF : Lead Free

Dip type package

Device : 32K x 8 bit

Nonvolatile Timekeeping SRAM

HANBit Memory Module

7F(#712), 274, Samsung-ro, Suwon-si, Gyeonggi-do, South Korea

TEL : (+82) 31-211-2523 , FAX : (+82) 31-211-2524

EMAIL : dlghbinfo@dlghb.co.kr

http://www.dlghb.co.kr

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

DLG HANBIT Co.,Ltd

HMN328DLF-85 [DLGHANBIT]

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