HMNR28DV [DLGHANBIT]
5.0 or 3.3V, 16K bit (2 Kbit x 8) TIMEKEEPER NVSRAM;
| 型号： | HMNR28DV |
| 厂家： | 
DLG HANBIT |
| 描述： | 5.0 or 3.3V, 16K bit (2 Kbit x 8) TIMEKEEPER NVSRAM 静态存储器 |
| 文件： | 总11页 (文件大小：836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DLGHANBIT
DLGHANBIT Confidential
HMNR28D(V)
5.0 or 3.3V, 16K bit (2 Kbit x 8) TIMEKEEPER NVSRAM
Part No. HMNR28D(V)
GENERAL DESCRIPTION
The HMNR28D(V) TIMEKEEPER SRAM is a 2Kb x 8 non-volatile static RAM and real time clock organized as 2,048
words by 8 bits. The special DIP package provides a fully integrated battery back-up memory and real time clock solution.
The HMNR28D(V) directly replaces industry standard 2Kbit x 8 SRAMs. It also provides the non-volatility of Flash without
any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
FEATURES
■ INTEGRATED LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY and
CRYSTAL
■ BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS
■ AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION VOLTAGES :
(VPFD = Power-fail Deselect Voltage)
– HMNR28D : VCC = 4.5 to 5.5V
4.1V ≤ VPFD ≤ 4.5V
– HMNR28DV: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V
■ CONVENTIONAL SRAM OPERATION : UNLIMITED WRITE CYCLES
■ SOFTWARE CONTROLLED CLOCK CALIBRATION FOR HIGH ACCURACY APPLICATIONS
■ 5 YEARS OF DATA RETENTION and CLOCK OPERATION IN THE ABSENCE OF POWER PIN and FUNCTION
COMPATIBLE WITH INDUSTRY STANDARD 2K x 8 SRAMS
■ SELF-CONTAINED BATTERY and CRYSTAL IN DIP PACKAGE
OPTIONS
Timing
70 ns
MARKING
PIN ASSIGNMENT
-70
-85
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
Vcc
A8
A9
1
2
3
4
24
23
22
21
85 ns
/WE
/OE
A10
/CE
DQ7
DQ6
DQ5
DQ4
DQ3
5
6
7
8
20
19
18
17
16
15
14
13
9
10
11
12
24-pin Encapsulated Package
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HMNR28D(V)
FUNCTIONAL DESCRIPTION
The HMNR28D(V) is a full function, year 2000 compliant (Y2KC), real–time clock/calendar (RTC) and 2k x 8 non-volatile
static RAM. User access to all registers within the HMNR28D(V) is accomplished with a bytewide interface . The Real-
time clock (RTC) information and control bits reside in the sixteen upper most RAM locations. The RTC registers contain
century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the date of
each month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of
incorrect data that can occur during clock update cycles. The double buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data.
The HMNR28D(V) also contains its own power-fail circuitry which deselects the device when the VCC supply is in an out of
tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as
errant access and update cycles are avoided.
BLOCK DIAGRAM
16 x 8
OSCILLATOR AND
TIMEKEEPER
CLOCK CHAIN
REGISTER
32.768KHz
CRYSTAL
A0 ~ A10
POWER
2,032 x 8
SRAM ARRAY
DQ0 ~ DQ7
LITHIUM
CELL
VPFD
/CE
/WE
/OE
VOLTAGE SENSE
AND
SWITCHING
CIRCURITY
Vcc
Vss
A0-A10 : Address Input
/CE : Chip Enable
/WE : Write Enable
/OE : Output Enable
VCC : Power (+5V or +3.3V)
NC : No Connection
Vss : Ground
DQ0-DQ7 : Data In / Data Out
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HMNR28D(V)
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
°C
°C
V
TA
AmbientOperatingTemperature
Storage Temperature(Vcc Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
Input or Output Voltage
0 to 70
-30 to 70
260
TSTG
(1)
TSLD
VIO
-0.3 to Vcc+0.3
4.5 to 5.5
3.0 to 3.6
20
HMNR28D
Supply Voltage
V
VCC
HMNR28DV
V
IO
Output Current
mA
W
PD
Power Dissipation
1
Note : Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Not recommend direct soldering by soldering machine, and recommend manual soldering or using socket.
Caution : Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Operating and AC Measurement Conditions
Parameter
HMNR28D
4.5 to 5.5
0 to 70
100
HMNR28DV
3.0 to 3.6
0 to 70
50
Unit
V
VCC Supply Voltage
Ambient Operating Temperature
Load Capacitance (CL )
°C
pS
nS
V
Input Rise and Fall Times
Input Pulse Voltages
≤ 5
≤ 5
0 to 3
1.5
0 to 3
1.5
Input and Output Timing Ref. Voltages
V
DC Characteristics
HMNR28D
Typ
HMNR28DV
Symbol
Parameter
Test Condition (1)
Unit
Min
Max
Min
Typ
Max
±1
±1
15
±1
±1
10
ILI
Input Leakage Current
Output Leakage Current
Supply Current
0V ≤ VIN ≤ VCC
0V ≤VOUT ≤ VCC
Outputs open
uA
uA
(2)
ILO
ICC
8
4
mA
Supply Current (Standby)
TTL
ICC1
/CE=VIH
5
3
mA
Supply Current (Standby)
CMOS
ICC2
/CE=VCC-0.2
3
2
mA
nA
nA
V
Battery Current OSC ON
Battery Current OSC
OFF
575
100
800
575
800
100
IBAT
VIL
VIH
Input Low Voltage
-0.3
2.2
0.8
-0.3
2.0
0.8
VCC
+0.3
VCC
+0.3
Input High Voltage
V
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HMNR28D(V)
Output Low Voltage
IOL=2.1mA
IOL=10mA
0.4
0.4
0.4
0.4
V
V
VOL
Output Low Voltage
(open drain) (4)
VOH
VOHB
IOUT1
Output High Voltage
VOH Battery Back-up
VOUT Current (Active)
VOUT Current (Battery
Back-up)
IOH=-1.0mA
IOUT2=-1.0uA
VOUT1 > VCC-0.3
2.4
2.0
2.4
2.0
V
V
3.6
3.6
70
100
mA
IOUT2
VOUT2>VBAT-0.3
100
4.5
100
3.0
uA
V
Power-fail Deselect
Voltage
VPFD
4.1
4.35
2.7
2.9
VPFD
100
mV
3.0
-
Battery Back-up
VSO
3.0
3.0
V
V
Switchover Voltage
VBAT
Battery Voltage
Note: 1. Valid for Ambient Operating Temperature: TA =0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. Outputs deselected.
OPERATING MODES
The 24-pin, 600mil DIP Hybrid houses a controller chip, SRAM, quartz crystal, and a long life lithium button cell in a single
package. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year-compliant until the year 2100), 30, and 31 day months are made automatically. Byte
7F8h is the clock control register. This byte controls user access to the clock information and also stores the clock
calibration setting. The seven clock bytes (7FFh-7F9h) are not the actual clock counters, they are memory locations
consisting of READ/WRITE memory cells within the static RAM array. The HMNR28D includes a clock control circuit which
updates the clock bytes with current information once per second. The information can be accessed by the user in the
same manner as any other location in the static memory array. The HMNR28D(V) also has its own Power-Fail Detect
circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition.
When VCC is out of tolerance, the circuit write protects the TIMEKEEPER register data and SRAM, providing data security
in the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery,
maintaining data and clock operation until valid power is restored.
Operating Modes
Mode
Deselect
WRITE
READ
VCC
/CE
VIH
VIL
VIL
VIL
/OE
X
/WE
X
DQ7 – DQ0
High-Z
DIN
Power
Standby
Active
4.5V to 5.5V
or
X
VIL
VIH
VIH
VIL
VIH
DOUT
High
Active
3.0V to 3.6V
READ
Active
CMOS
Deselect
Deselect
VSO to VPFD (min)
X
X
X
X
X
X
High
High
Standby
Battery Back-
up
≤ VSO (1)
Note : X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
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HMNR28D(V)
READ Mode
The HMNR28D(V) is in the READ Mode whenever /WE (WRITE Enable) is high and /CE /OE are low. The unique
address specified by the 11 Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data will
be available at the Data I/O pins within Address Access Time (tAVQV) after the last address input signal is stable, providing
the /CE and /OE access times are also satisfied. If the /CE and /OE access times are not met, valid data will be available
after the latter of the Chip Enable Access Times (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-
state Data I/O signals is controlled by /CE and /OE. If the outputs are activated before tAVQV, the data lines will be driven to
an indeterminate state until tAVQV. If the Address Inputs are changed while /CE and /OE remain active, output data will
remain valid for Output Data Hold Time (tAXQX) but will go indeterminate until the next Address Access.
READ Mode AC Waveforms
A0-A10
/CE
/OE
Note : /WE = High.
READ Mode AC Characteristics
HMNR28D
-70
HMNR28DV
-85
Symbol
Parameter
Unit
Min
Max
Min
85
Max
tAVAV
tAVQV
tELQV
tGLQV
tELQX
tGLQX
tEHQZ
tGHQZ
tAXQX
READ Cycle Time
70
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Valid to Output Valid
70
70
40
85
85
40
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
5
0
5
0
10
10
10
10
5
5
Note: 1.Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
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HMNR28D(V)
WRITE Mode
The HMNR28D(V) is in the WRITE Mode whenever /WE (WRITE Enable) and /CE (Chip Enable) are low state after the
address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge of /WE or /CE. A
WRITE is terminated by the rising edge of /WE. The addresses must be held valid throughout the cycle. /CE must
return high for a minimum of tEHAX and /WE must return high for a minimum of tWHAX from write cycle enable prior to the
initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for
tWHDX afterward. /OE should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has
been activated by a low on /CE and /OE a low on /WE will disable the outputs tWLQZ after /WE falls.
WRITE AC Waveforms, WRITE Enable Controlled
A0-A10
WRITE Mode AC Characteristics
HMNR28D
-70
HMNR28DV
-85
Symbol
Parameter(1)
Unit
Min
Max
Min
85
0
Max
tAVAV
tAVWL
tAVEL
WRITE Cycle Time
70
0
nS
nS
nS
nS
nS
nS
nS
nS
Address Valid to WRITE Enable Low
Address Valid to Chip Enable Low
WRITE Enable Pulse Width
0
0
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
50
70
0
50
75
0
Chip Enable Low to Chip Enable High
WRITE Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to WRITE Enable High
0
0
25
25
tWHDX
WRITE Enable High to Input Transition
WRITE Enable Low to Output High-Z
Address Valid to WRITE Enable High
0
0
nS
nS
nS
(2)
tWLQZ
25
25
tAVWH
60
65
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HMNR28D(V)
(2)
tWHQX
WRITE Enable High to Output Transition
5
0
0
5
0
0
nS
nS
nS
tEHAX
tWHAX
Chip Enable High to Address Transition
Write Enable High to Address Transition
Note : 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
3. If /CE goes low simultaneously with /WE going low, the outputs remain in the high impedance state.
Data Retention Mode
With valid VCC applied, the HMNR28D(V) operates as a conventional Bytewide static RAM. Should the supply voltage
decay, the RAM will automatically deselect, write protecting itself when VCC falls between VPFD (max), VPFD (min) window.
All outputs become high impedance and all inputs are treated as “Don't care.”
Note : A power failure during a WRITE cycle may corrupt data at the current addressed location, but does not jeopardize
the rest of the RAM's content. At voltages below VPFD (min), the memory will be in a write protected state, provided the VCC
fall time is not less than tF. The HMNR28D(V) may respond to transient noise spikes on VCC that cross into the deselect
window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery, preserving data and powering the
clock. The internal energy source will maintain data in the HMNR28D(V) for an accumulated period of at least 10 years at
room temperature. As system power rises above VSO, the battery is disconnected, and the power supply is switched to
external VCC . Write protection continues until VCC reaches VPFD (min) plus tREC (min). Normal RAM operation can resume
tREC after VCC exceeds VPFD (max).
Power Down/Up Mode AC Waveforms
Power Down/Up AC Characteristics
Symbol
Parameter
Min
300
10
Max
Unit
uS
(2)
tF
VPFD (max) to VPFD (min) VCC Fall Time
HMNR28D
HMNR28DV
VPFD (min) to VPFD (max) VCC Rise Time
uS
(3)
tFB
VPFD (min) to VSS VCC Fall Time
150
10
uS
tR
uS
tREC
tRB
VPFD (max) to RST High
40
200
mS
uS
VSS to VPFD (min) VCC Rise Time
5
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HMNR28D(V)
Note :
1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after
VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Power Down/Up Trip Points DC Characteristics
Symbol
Parameter(1,2)
Min
4.1
2.7
Typ
Max
4.5
Unit
HMNR28D
HMNR28DV
HMNR28D
HMNR28DV
4.35
V
VPFD
Power-fail Deselect Voltage
2.9
3.0
V
3.0
VPFD-100mV
5
V
V
Battery Back-up Switchover
Voltage
VSO
(3)
TDR
Expected Data Retention Time
YEARS
Note: 1. All voltages referenced to VSS
.
2. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
3. At 25°C.
Register Map
Data
Funtion /
Address
Range BCD Format
D7
D6
D5
D4
D3
D2
D1
D0
7FF
7FE
7FD
7FC
7FB
7FA
7F9
7F8
7F7
7F6
7F5
7F4
7F3
7F2
7F1
7F0
10Years
Year
Year
00-99
01-12
01-31
01-07
00-23
00-59
00-59
0
0
0
0
0
10M
0
Month
Date : Day of Month
Day
Month
Date
10 Date
0
FT
0
0
0
Day
0
10 Hours
10 Minutes
Hours(24 Hour Format)
Minutes
Hours
Minutes
Seconds
Control
0
ST
W
0
10 Seconds
Seconds
R
0
0
0
0
0
0
S
0
0
0
0
0
0
Calibration
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1000 Years
100 Years
Century
Flag
00-99
0
0
0
BL
0
0
0
0
Keys :
R = READ Bit
W = WRITE Bit
ST = Stop Bit
0 = Must be set to ’0’
BL = Battery Low Flag
S = Sign Bit
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HMNR28D(V)
CLOCK OPERATIONS
The HMNR28D(V) offers 16 internal registers which contain TIMEKEEPER, and Control data. These registers are memory
locations which contain external (user accessible) and internal copies of the data. The external copies are independent of
internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy.
TIMEKEEPER Registers store data in BCD. Control Registers store data in Binary Format.
Reading the Clock
Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition.
The TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the
registers can be halted without disturbing the clock itself. Updating is halted when a ’1’ is written to the READ Bit, D6 in the
Control Register (7F8h). As long as a ’1’ remains in that position, updating is halted. After a halt is issued, the registers
reflect the count; that is, the day, date, and time that were current at the moment the halt command was is-sued. All of the
TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs
approximately 1 second after the READ Bit is reset to a ’0.’
Setting the Clock
Bit D7 of the Control Register (7F8h) is the WRITE Bit. Setting the WRITE Bit to a ’1,’ like the READ Bit, halts updates to
the TIMEKEEPER reg-isters. The user can then load them with the correct day, date, and time data in 24-hour BCD
format. Resetting the WRITE Bit to a ’0’ then transfers the
values of all time registers (7Fh-7F9h, 7F1h) to the actual TIMEKEEPER counters and allows normal operation to resume.
After the WRITE Bit is reset, the next clock update will occur approximately one second later.
Note: Upon power-up following a power failure, both the WRITE Bit and the READ Bit will be reset to ’0.’
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the
oscillator can be turned off to minimize current drain on the battery. The STOP Bit is located at Bit D7 within the Seconds
Register (7F9h). Setting it to a ’1’ stops the oscillator. When reset to a ’0,’ the HMNR28D oscillator starts within one
second.
Note : It is not necessary to set the WRITE Bit when setting or resetting the STOP Bit (ST).
Calibrating the Clock
The HMNR28D(V) is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are
factory calibrated at 25°C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator
frequency error at 25°C, which equates to about ±1.53 minutes per month. When the Calibration circuit is properly
employed, accuracy improves to better than +1/-2 ppm at 25°C. The oscillation rate of crystals changes with temperature.
The HMNR28D design employs periodic counter correction. The calibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage. The number of times pulses are blanked (subtracted, negative
calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the
Control Register.
Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower
order bits (D4-D0) in the Control Register 7F8h. These bits can be set to represent any value between 0 and 31 in binary
form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64
minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle
will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles; that is, +4.068 or -
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HMNR28D(V)
2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly
32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which
corresponds to a total range of +5.5 or -2.75 minutes per month. One method for ascertaining how much calibration a
given HMNR28D(V) may require involves setting the clock, letting it run for a month and comparing it to a known accurate
reference and recording deviation over a fixed period of time. This allows the designer to give the end user the ability to
calibrate the clock as the environment requires, even if the final product is packaged in a nonuser serviceable enclosure.
The designer could provide a simple utility that accesses the Calibration bits.
Battery Low Warning
The HMNR28D(V) automatically performs battery voltage monitoring upon power-up and at factory-programmed time
intervals of approximately 24 hours. The Battery Low (BL) Bit, Bit D4 of Flags Register 7F0h, will be asserted if the battery
voltage is found to be less than approximately 2.5V. The BL Bit will remain asserted until completion of battery
replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next
scheduled 24hour interval. If a battery low is generated during a power-up sequence,
this indicates that the battery is below approximately 2.5V and may not be able to maintain
data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life.
However, data is not compromised
due to the fact that a nominal VCC is supplied. In order to insure data integrity during
Power Supply Decoupling and Undershoot Protection
Note: ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes
on the VCC bus. These transients can be reduced if capacitors
are used to store energy which stabilizes the VCC bus. The
energy stored in the bypass capacitors will be released as low
going spikes are generated or energy will be absorbed when
overshoots occur. A ceramic bypass capacitor value of 0.1uF
is recommended in order to provide the needed filtering. In
addition to transients that are caused by normal
SRAM operation, power cycling can generate negative
voltage spikes on VCC that drive it to values below VSS by as
much as one volt. These negative spikes can cause data
corruption in the SRAM while in battery backup mode. To
protect from these voltage spikes, ST recommends
connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is
recommended for through hole and MBRS120T3 is recommended for surface mount).
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HMNR28D(V)
PACKAGE DIMENSION
Dimension
Min
Max
A
B
C
D
E
F
G
H
I
1.450
0.700
0.365
0.012
0.008
0.590
0.017
0.090
0.175
0.150
1.525
0.760
0.380
-
J
A
0.013
0.630
0.023
0.110
0.210
0.190
H
I
G
B
C
J
D
All dimensions are in inches.
E
F
ORDERING INFORMATION
H M N R 2 8 D V LF – 70
Speed options : 70 = 70 ns
85 = 85 ns
LF: Lead-Free
Operating Voltage : Blank = 5V
V = 3.3V
Dip type package
Device : 2K x 8
Nonvolatile Timekeeping SRAM
HANBit Memory Module
7F(#712), 274, Samsung-ro, Suwon-si, Gyeonggi-do, South Korea
TEL : (+82) 31-211-2523 , FAX : (+82) 31-211-2524
EMAIL : dlghbinfo@dlghb.co.kr
http://www.dlghb.co.kr
URL : www.dlghb.co.kr
Rev. 1.3 (Apr, 2009)
11
DLG HANBIT Co.,Ltd
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