HSD32M64B8W [DLGHANBIT]

Synchronous DRAM Module 256Mbyte(32Mx64-Bit), 144pin SODIMM, 4Banks, 8K Ref., 3.3V;


型号：	HSD32M64B8W
厂家：	DLG HANBIT
描述：	Synchronous DRAM Module 256Mbyte(32Mx64-Bit), 144pin SODIMM, 4Banks, 8K Ref., 3.3V 动态存储器
文件：	总9页 (文件大小：539K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLGHANBIT

DLGHANBIT Confidential

HSD32M64B8W

Synchronous DRAM Module 256Mbyte(32Mx64-Bit), 144pin SO-

DIMM, 4Banks, 8K Ref., 3.3V Part No.

GENERAL DESCRIPTION

The HSD32M64B8W is a 32M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists

of eight CMOS 4M x 16 bit x 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 144-pin glass-epoxy

substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The

HSD32M64B8W is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting into 144-pin edge

connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are

possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be

useful for a variety of high bandwidth, high performance memory system applications All module components may be

powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES

• Part Identification

HSD32M64B8W-13 : 133MHz (CL=3)

HSD32M64B8WLF-13 : 133MHz (CL=3) Pb-Free

• Burst mode operation

• Auto & self refresh capability (8192 Cycles/64ms)

• LVTTL compatible inputs and outputs

• Single 3.3V 0.3V power supply

• MRS cycle with address key programs

- Latency (Access from column address)

- Burst length (1, 2, 4, 8 & Full page)

- Data scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock

• The used device is 4M x 16bit x 4Banks SDRAM

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HSD32M64B8W

PIN ASSIGNMENT

Front

Vss

Back

Vss

Frontl

DQ13

DQ14

DQ15

Vss

Back

DQ45

DQ46

DQ47

Vss

Front

DQ22

DQ23

VCC

Back

DQ54

DQ55

VCC

DQ0

DQ1

DQ2

DQ3

VCC

DQ4

DQ5

DQ6

DQ7

Vss

DQ32

DQ33

DQ34

DQ35

VCC

DQ36

DQ37

DQ38

DQ39

Vss

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

101

103

105

107

109

BA0

Vss

CLK0

VCC

/RAS

/WE

CKE0

VCC

/CAS

CKE1

A12

BA1

111 A10_AP

A11

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

VCC

DQM2

DQM3

Vss

VCC

DQM6

DQM7

Vss

/CS0

/CS1

DQM0

DQM1

VCC

DQM4

DQM5

VCC

CLK1

Vss

DQ24

DQ25

DQ26

DQ27

VCC

DQ56

DQ57

DQ58

DQ59

VCC

DQ60

DQ61

DQ62

DQ63

Vss

VCC

DQ16

DQ17

DQ18

DQ19

Vss

VCC

DQ48

DQ49

DQ50

DQ51

Vss

DQ28

DQ29

DQ30

DQ31

Vss

DQ8

DQ9

DQ10

DQ11

VCC

DQ12

DQ40

DQ41

DQ42

DQ43

VCC

DQ44

DQ20

DQ21

DQ52

DQ53

SDA

SCL

VCC

*Pin Names

Pin Name

Function

Pin Name

Function

A0 ~ A12

DQ0 ~ DQ63

CKE0, CKE1

/RAS

Address input (Multiplexed)

Data input/output

BA0 ~ BA1

CLK0,CLK1

/CS0, /CS1

/CAS

Select bank

Clock input

Clock enable input

Chip select input

Row address strobe

Column address strobe

DQM

/WE

Write enable

DQM0 ~ 7

Vcc

SDA

Power supply (3.3V)

Serial data I/O

Vss

Ground

SCL

Serial clock

No connection

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HSD32M64B8W

FUNCTIONAL BLOCK DIAGRAM

DQ0-63

CKE

CLK

CKE0

/CAS

CLK0

CAS

RAS

DQ0-7,DQ32-39

DQM0

/RAS

/CS0

DQM0

DQM4

WE A0-A12 BA0-1

DQM4

CKE

CAS

CLK

DQ8-15,DQ40-47

RAS

DQM1

DQM5

WE A0-A12 BA0-1

DQM5

CKE

CAS

CLK

DQ16-23,DQ48-55

DQM2

RAS

DQM2

DQM6

WE A0-A12 BA0-1

DQM6

CKE

CAS

CLK

DQ24-31,DQ56-63

RAS

DQM3

DQM7

WE A0-A12 BA0-1

DQM7

CKE

CAS

CLK

CKE1

/CS1

CLK1

DQ0-7,DQ32-39

DQM0

RAS

DQM0

DQM4

WE A0-A12 BA0-1

DQM4

CKE

CAS

CLK

DQ8-15,DQ40-47

RAS

DQM1

DQM5

WE A0-A12 BA0-1

DQM5

CKE

CAS

CLK

DQ16-23,DQ48-55

DQM2

RAS

DQM2

DQM6

WE A0-A12 BA0-1

DQM6

CKE

CAS

CLK

DQ24-31,DQ56-63

RAS

DQM3

DQM7

WE A0-A12 BA0-1

DQM7

/WE

A0 – A12

BA0-1

Vcc

Vss

Two 0.1uF Capacitors

per each SDRAM

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HSD32M64B8W

PIN FUNCTION DESCRIPTION

NAME

System clock

Chip enable

INPUT FUNCTION

Active on the positive going edge to sample all inputs.

CLK

/CS

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

CKE

Clock enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE should be enabled 1CLK+tSS prior to valid command.

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12, Column address : CA0 ~ CA8

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

A0 ~ A12

BA0 ~ BA1

/RAS

Address

Bank select address

Row address strobe

/CAS

Column

address Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

strobe

/WE

Write enable

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

DQM0 ~ 7

Data

input/output Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

mask

DQ0 ~DQ 63

VCC/VSS

Data input/output

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Power supply/ground

ABSOLUTE MAXIMUM RATINGS

PARAMETER

Voltage on Any Pin Relative to Vss

Voltage on Vcc Supply Relative to Vss

Power Dissipation

SYMBOL

V_{IN ,OUT}

Vcc

RATING

-1V to 4.6V

P_D

Storage Temperature

T_STG

-55 C to 150 C

Short Circuit Output Current

I_OS

400mA

Notes:

Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be

restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

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HSD32M64B8W

DC OPERATING CONDITIONS

(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) )

PARAMETER

Supply Voltage

SYMBOL

Vcc

V_IH

MIN

3.0

2.0

-0.3

2.4

TYP.

MAX

3.6

UNIT

NOTE

3.3

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

3.0

Vcc+0.3

0.8

V_IL

V_OH

V_OL

I_OH= -2mA

I_OL= 2mA

0.4

Input leakage current

I _LI

-12

Notes :

1. V_IH(max) = 5.6V AC. The overshoot voltage duration is  3ns.

2. V_IL(min) = -2.0V AC. The undershoot voltage duration is  3ns.

3. Any input 0V  V_IN V_DDQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

VERSION

TEST

PARAMETER

SYMBOL

UNIT NOTE

CONDITION

-13

-12

-10

-10L

Burst length = 1

Operating current

I_CC1

t_RC t_RC(min)

1200

1200 1120

1120

(One bank active)

I_O= 0mA

CKE  V_IL(max)

I_CC2

t_CC=10ns

Precharge standby current in

power-down mode

CKE & CLK  V_IL(max)

t_CC=

I_CC2PS

CKE  V_IH(min)

CS*  V_IH(min), t_CC=10ns

Input signals are changed

one time during 20ns

CKE  V_IH(min)

I_CC2

128

Precharge standby current in

non power-down mode

I_CC2NS

CLK  V_IL(max), t_CC=

Input signals are stable

CKE  V_IL(max), t_CC=10ns

CKE&CLK  V_IL(max)

t_CC=

112

I_CC3

Active standby current in

power-down mode

I_CC3PS

CKEV_IH(min),

Active standby current in

non power-down mode

(One bank active)

CS*V_IH(min), t_CC=10ns

Input signals are changed

one time during 20ns

I_CC3

280

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CKEVIH(min)

CLK VIL(max), t_CC=

Input signals are stable

I_O= 0 mA

I_CC3NS

240

Operating current

(Burst mode)

Page burst

I_CC4

1440

1680

1440 1160

1160

1600

4Banks Activated

t_CCD= 2CLKs

Refresh current

I_CC5

t_RC t_RC(min)

1680 1600

Self refresh current

I_CC6

CKE  0.2V

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Unless otherwise noticed, input swing level is CMOS(V_IH/V_IL=V_DDQ/V_SSQ).

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

VERSION

PARAMETER

SYMBOL

UNIT

NOTE

-13

-12

-10

-10L

Row active to row active delay

RAS to CAS delay

t_RRD(min)

t_RP(min)

Row precharge time

t_RP(min)

t_RAS(min)

t_RAS(max)

Row active time

100

Row cycle time

_tRC(min)

t_RDL(min)

t_DAL(min)

t_CDL(min)

t_BDL(min)

t_CCD(min)

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

CLK

2.5

2 CLK + 20 ns

CLK

Col. address to col. address delay

CAS latency=3

CAS latency=2

Number of valid output data

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

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HSD32M64B8W

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

-13

-12

MAX MIN

-10

MAX MIN

-10L

SYMBO

PARAMETER

UNIT

NOTE

MIN

MAX MIN

MAX

CLK cycle time CAS

7.5

latency=3

t_CC

t_SAC

t_OH

1000

1,2

CAS

latency=2

CAS

CLK to valid

output delay

5.4

latency=3

CAS

latency=2

CAS

Output data

hold time

2.7

latency=3

CAS

latency=2

CLK high pulse width

CLK low pulse width

Input setup time

t_CH

t_CL

2.5

1.5

0.8

t_SS

t_SH

t_SLZ

Input hold time

CLK to output in Low-Z

CLK to output

in Hi-Z

CAS

5.4

latency=3

CAS

t_SHZ

latency=2

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to

the parameter.

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HSD32M64B8W

SIMPLIFIED TRUTH TABLE

CKE

n-1

CKE

0,1

A10/

A11

A9~A0

COMMAND

NOTE

Refresh

Mode register set

Auto refresh

OP code

1,2

Entry

Self

refres

Exit

Bank active & row addr.

Row address

Auto

Read &

precharge

Column

disable

Address

column

(A0 ~

Auto

address

disable

4,5

A8)

Column

Auto

Write &

precharge

Address

disable

(A0 ~

column

A8)

address

Auto

4,5

disable

Burst Stop

Bank selection

All banks

Precharg

Entry

Exit

Clock suspend or

active power down

Entry

Precharge power

down mode

Exit

DQM

No operation command

(V=Valid, X=Don't care, H=Logic high, L=Logic low)

Notes :

1. OP Code : Operand code

A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

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HSD32M64B8W

TIMING DIAGRAMS

Please refer to attached timing diagram chart (II)

PACKAGING INFORMATION

Unit : Inch [mm]

PCB Thickness: 1.0mm (0.9t - 1.1t)

Immersion Gold PCB Pattern

ORDERING INFORMATION

Part Number

Density

Org.

Package

Ref.

Vcc

MAX.frq

Mark

144 Pin-

SODIMM

144 Pin-

SODIMM

CL 3

133MHz

CL3

HSD32M64B8W-13

256MByte

32M x 64

3.3V

HSD32M64B8WLF-13

Pb-Free

133MHz

7F(#712), 274, Samsung-ro, Suwon-si, Gyeonggi-do, South Korea

TEL : (+82) 31-211-2523 , FAX : (+82) 31-211-2524

EMAIL : dlghbinfo@dlghb.co.kr

http://www.dlghb.co.kr

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DLG HANBIT Co.,Ltd

REV.1.0 (August.2002)

HSD32M64B8W [DLGHANBIT]

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HSD32M64D16A-10

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